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1 ? fn7488.0 preliminary EL5625 programmable 18-channel gamma with 1-channel v com with reference the EL5625 represents a high integration programmable buffer solution from intersil. the device integrates 18- channels of programmable buffers, with a single programmable v com , a reference output, and a supply side ldo. the 18-channel programmable buffers have 11-bit resolution and rail-to-rail outputs. each output is capable of driving 15ma continuous. the v com output also features 11-bits of resolution. the generated voltage is connected to the non-inverting input of the integrated v com amplifier. this amplifier has a short- circuit current of 1a, 100ma continuous. the integrated low drop-out regulat or is used, in conjunction with an external transistor, to provide a solid supply voltage to the device. it features 200mv minimum drop-out and has very good load regulation for the cleanest gamma and v com outputs. the EL5625 also includes over-temperature protection and is available in a 38-pin qfn package. pinout EL5625 (38-pin qfn) top view features ? 18-channel programmable gamma - rail-to-rail ?single v com amplifier - 1a peak output ? 11-bit resolution per output ? accuracy 0.5% ? integrated supply ldo - low drop out - 200mv ? integrated reference - very accurate - 0.75% ? +7v to +16v supply ? thermal protection ? 38-pin qfn ? pb-free plus anneal available (rohs compliant) applications ?lcd-tvs ? flat panel monitors ? tft-lcd displays outi vs gnd cap ldo_out refh refl inncom gnd outcom vs outj 1 2 3 4 5 6 7 8 9 10 11 12 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 13 14 15 16 17 18 19 thermal pad outa ldo_comp ldo_in vsd sdi sclk ena sdo rd_wrbar ext_osc reset outr outb outc outd oute outf outg outh outq outp outo outn outm outl outk ordering information part number (see note) package (pb-free) tape & reel pkg. dwg. # EL5625ilz 38-pin qfn - mdp0046 EL5625ilz-t13 38-pin qfn 13? mdp0046 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet february 28, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn7488.0 february 28, 2006 absolute maxi mum ratings (t a = 25c) supply voltage between v s and gnd. . . . . . 4.5v(min) to 18v(max) supply voltage between v sd and gnd 3v(min) to v s and +7(max) maximum continuous output current (gamma) . . . . . . . . . . . 15ma maximum continuous output current (v com ) . . . . . . . . . . . 100ma ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v s = 15v, v sd = 5v, v refh = 13v, v refl = 2v, r l = 1.5k ? and c l = 200pf to 0v, t a = 25c, unless otherwise specified. parameter description conditions min typ max unit supply i s supply current no load 11 15 ma i sd digital supply current 1.1 1.35 ma analog v ol output swing low (chan 1-16) sinking 5ma (v refh = 15v, v refl = 0) 100 200 mv output swing low (chan 17, 18) 50 150 mv v oh output swing high (chan 1, 2) sourcing 5ma (v refh = 15v, v refl = 0) 14.85 14.95 v output swing high (chan 3-18) 14.8 14.9 v i sc short circuit current r l = 10 ? 100 130 ma psrr power supply rejection ratio v s + is moved from 14v to 16v 50 70 db v com 45 60 db t d program to out delay 4ms v ac accuracy referred to the ideal value code = 512 20 mv ? v mis channel to channel mismatch code = 512 2 mv v droop droop voltage 12mv/ms r inh input resistance @ v refh , v refl 25 32 k ? reg load regulation i out = 5ma step 1 3 mv/ma bg band gap 1.227 1.242 1.257 v digital v ih logic 1 input voltage 2 v v il logic 0 input voltage 1v f clk clock frequency 5mhz t s setup time 20 ns t h hold time 20 ns t lc load to clock time 20 ns t ce clock to load line 20 ns t dco clock to out delay time negative edge of sclk 10 ns r sdin s din input resistance 1g ? t pulse minimum pulse width for ext_osc signal 5s duty cycle duty cycle for ext_osc signal 50 % EL5625
3 fn7488.0 february 28, 2006 f_osc internal refresh oscillat or frequency osc_select = 0 21 khz inl integral nonlinearity error 1.3 lsb dnl differential nonlinearity error 0.5 lsb v com characteristics bw bandwidth of v com 10 mhz sr slew rate 59 v/s i sc short-circuit current 1000 ma electrical specifications v s = 15v, v sd = 5v, v refh = 13v, v refl = 2v, r l = 1.5k ? and c l = 200pf to 0v, t a = 25c, unless otherwise specified. (continued) parameter description conditions min typ max unit EL5625
4 fn7488.0 february 28, 2006 typical application diagram - + + + - voltage sources 19 channel registers control if reset sdi sclk ena rd_wrbar sdo ext_osc cap refl inncom outcom outr outq outb outa refh ldo_comp ldo_out ldo_in v=1.242 microcontroller horizontal rate lcd timing controller column (source) driver lcd panel v com 0.1f +2v r f high reference voltage +13v 0.1f vs vsd 0.1f 0.1f +15v +5v EL5625
5 fn7488.0 february 28, 2006 pin descriptions pin number pin name pin type pin description 1 outa analog output channel a output voltage 2 ldo_comp analog input ldo compensation capacitor 3 ldo_in analog input ldo inverting input 4 vsd power positive power supply fo r digital circuits (3.3v - 5v) 5 sdi logic input serial data input 6 sclk logic input serial data clock 7ena logic input chip select, low enables data input to logic 8 sdo logic output serial data output 9 rd_wrbar analog input read, write select: ?0? = write, ?1? = read 10 ext_osc input/output oscillator pin for synchronizing 11 reset analog input reset all registers: ?0? = reset 12 outr analog output channel r output voltage 13 outq analog output channel q output voltage 14 outp analog output channel p output voltage 15 outo analog output channel o output voltage 16 outn analog output channel n output voltage 17 outm analog output channel m output voltage 18 outl analog output channel l output voltage 19 outk analog output channel k output voltage 20 outj analog output channel j output voltage 21, 30 vs power positive supply voltag e for analog circuits (4.5v - 16.5v) 22 outcom analog output v com output 23, 29 gnd power ground 24 inncom analog input v com inverting input 25 refl analog input low reference voltage 26 refh analog input high reference voltage 27 ldo_out analog output ldo output 28 cap analog decoupling capacito r for internal reference 31 outi analog output channel i output voltage 32 outh analog output channel h output voltage 33 outg analog output channel g output voltage 34 outf analog output channel f output voltage 35 oute analog output channel e output voltage 36 outd analog output channel d output voltage 37 outc analog output channel c output voltage 38 outb analog output channel b output voltage EL5625
6 fn7488.0 february 28, 2006 typical performance curves figure 1. transient load regulation (sourcing) figure 2. transient load regulation (sinking) figure 3. large signal response (rising from 0v to 8v) figure 4. small signal response (falling from 200mv to 100mv) figure 5. package power dissipation vs ambient temperature figure 6. package power dissipation vs ambient temperature 0ma 200mv/div 5ma v s =v refh =15v c l =180pf c l =1nf c l =4.7nf m=400ns/div v s =v refh =15v 5ma 0ma c l =4.7nf c l =1nf 200mv/div m=400ns/div c l =180pf sclk sdi ena outa m=400s/div sclk sdi ena outa m=400s/div jedec jesd51-7 high effective thermal conductivity test board - lpp exposed diepad soldered to pcb per jesd51-5 3.5 3 2 1 0 0 255075100 150 ambient temperature (c) power dissipation (w) 3.33w ja =30c/w qfn38 125 85 2.5 1.5 0.5 jedec jesd51-3 low effective thermal conductivity test board 1 0.8 0.6 0.4 0.2 0 0 255075100 150 ambient temperature (c) power dissipation (w) 0.80w ja =125c/w qfn38 125 85 EL5625
7 fn7488.0 february 28, 2006 general description the EL5625 is designed to produce the reference voltages required in tft-lcd applications. each output is programmed to the required voltage with 11 bits of resolution. ref-high and ref-low pins determine the high and low voltages of the output range. these outputs can be driven to within 50mv of t he power rails of the EL5625. programming of each output, 18 buffers and 1 vcom, is performed using the usb interface. usb interface the EL5625 uses usb interface to control the 18 gamma channels and vcom channel (figure 7). software is available for download on intersil?s website. serial interface the EL5625 is programmed through a three-wire serial interface. the start and stop conditions are defined by the ena signal. while the ena is low, the data on the sdi (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the sclk (serial clock) signal. the msb (bit 15) is loaded first and the lsb (bit 0) is loaded last (see table 1). after the full 16-bit data has been loaded, the ena is pulled high and the addressed output channel is updated. the sclk is disabled internally when the ena is high. the sclk must be low before the ena is pulled low. the serial timing diagram and parameters table show the timing requirements for three-wire signals. the serial data has a minimum length of 16 bits, the msb (most significant bit) is the firs t bit in the signal. the bits are allocated to the following functions (also refer to the control bits logic table). ? bits 15 through 11 select the channel to be written to, these are binary coded with channel a = 0, and channel r = 17 ? the 11-bit data is on bits 10 through 0. some examples of data words are shown in the table of serial programming examples figure 7. usb interface table 1. control bits logic table bit name description b15 a4 channel address b14 a3 channel address b13 a2 channel address b12 a1 channel address b11 a0 channel address b10 d10 data b9 d9 data b8 d8 data b7 d7 data b6 d6 data b5 d5 data b4 d4 data b3 d3 data b2 d2 data b1 d1 data b0 d0 data EL5625
8 fn7488.0 february 28, 2006 serial timing diagram v com amplifier the v com amplifier is designed to control the voltage on the back plate of an lcd display. this plate is capacitively coupled to the pixel drive vo ltage which alternately cycles positive and negative at the line rates for the display. thus the amplifier must be capable of sourcing and sinking capacitive pulse of current, which can be quite large (100ma for typical applications). analog section transfer function the transfer function is: where data is the decimal value of the 11-bit data binary input code. the output voltages from the EL5625 will be derived from the reference voltages present at the v refl and v refh pins. the impedance between t hose two pins is about 32k ? . care should be taken that th e system design holds these two reference voltages within the lim its of the power rails of the EL5625. gnd < v refh v s and gnd v refl v refh . clock oscillator the EL5625 requires an internal clock or external clock to refresh its outputs. the outputs are refreshed at the falling osc clock edges. the output refreshed switches open at the rising edges of the osc clock. the driving load shouldn?t be changed at the rising edges of the osc cl ock. otherwise, it will generate a voltage error at the outputs. this clock may be input or output via the clock pin labelled ext_osc. the internal clock is provided by an internal oscill ator running at approximately 21khz and can be output to the ext_osc pin. in a 2 chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the osc pin will output the clock from the internal oscillator. the second chip may have the osc pin connected to this clock source. for transient load application, the external clock mode should be used to ensure all functions are synchronized together. the positive edge of the external clock to the osc pin should be timed to avoid the transient load effect. the application drawing shows the lcd h rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. after power on, the chip will start with the internal oscillator mode. at this time, the ext_osc pin will be in a high impedance condition to prevent contention. by setting pin 10 to high, the chip is on external clock mode. setting pin 10 to low, the chip is on internal clock mode. table 2. serial timing parameters parameter recommended operating range description t 200ns clock period t r /t f 0.05 * t clock rise/fall time t he 10ns ena hold time t se 10ns ena setup time t hd 10ns data hold time t sd 10ns data setup time t w 0.50 * t clock pulse width b15 b14 b13 b12-b2 b1 b0 ena sclk sdi msb lsb t t he t se t sd t hd tt r t w t he t se load msb first, lsb last t f v out ideal ) ( v refl = data 2048 ------------ - v refh - v refl () + EL5625
9 fn7488.0 february 28, 2006 channel outputs each of the channel outputs has a rail-to-rail buffer. this enables all channels to have the capability to drive to within 50mv of the power rails, (see electrical characteristics for details). when driving large capacitive loads, a series resistor should be placed in series with the output (usually between 5 ? and 50 ? ). each of the channels is updat ed on a conti nuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. the best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 48s. in the worst-case scenario, this will be 860s for EL5625, when the data has just missed the cycl e at f_osc = 21khz. when a large change in output voltage is required, the change will occur in 2v steps, thus the requisite number of timing cycles will be added to the overall updat e time. this means that a large change of 16v can take between 6.8ms and 7.2ms depending on the absolute timing relative to the update cycle. output stage and the use of external oscillator simplified output sample and hold amp stage for one channel. the output voltage is generated from the dac, which is v in in the above circuit. the refreshed switches are controlled by the internal or external oscillator signal. when the osc clock signal is low, switches s 1 and s 2 are closed. the output v out = v in and at the same time the sample and hold cap ch is being charged. when the osc clock signal is high, the refreshed switches s 1 and s 2 are opened and the output voltage is maintained by ch. this refreshed process will repeat every 18 clock cycles for each channel. the time takes to update the output depends on the timing at the v in and the state of the switches. it can take 1 to 19 clock cycles to update each output. for the sample and hold capacitor ch to maintain the correct output voltage, the driving load shouldn?t be changed at the rising edge of the osc signal. since at the rising edge of the osc clock, the refres hed switches are being opened, if the load changes at that time, it will generate an error output voltage. for a fixed load condition, the internal oscillator can be used. for the transient load condition, the external osc mode should be used to avoid the conflict between the rising edge of the osc signal and the changing load. so a timing delay circuit will be needed to delay the osc signal and avoid the rising edge of the osc signal and changing the load at the same time. transient load response channel 3 --- sinking and sourcing 5ma current channel 2 --- ext_osc signal channel 1 --- v out here, the osc signal is synchronized to the load signal. the rising edge of the osc signal is then delayed by some amount of time and gives enough time for ch to be charged to a new voltage before the switches are opened. channel to channel refresh ch1 --- output1 ch3 --- output2 ch2 --- ext_osc - + v out 1.3v figure 8. s 1 - + v in s 2 - + ch osc 1.3v figure 9. figure 10. EL5625
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7488.0 february 28, 2006 at the falling edge of the osc, output 1 is being refreshed and one clock cycle later, output 2 is being refreshed. the spike you see here is the response of the output amplifier when the refreshed switches are closed. when driving a big capacitor load, there will be ringing at the spikes because the phase margin of the amplifier is decreased. the speed of the external osc signal shouldn?t be greater than 70khz because for the worst condition, it will take at least 4s to charge the sample and hold capacitor ch. the pulse width has to be at least 4s long. from our lab test, the duty cycle of the osc signal must be greater than 30%. power dissipation with the 100ma maximum continues output drive capability for v com channel, it is possible to exceed the 125c absolute maximum junction tem perature. therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. the maximum power dissipation allowed in a package is determined according to: where: ?t jmax = maximum junction temperature ?t amax = maximum ambi ent temperature ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package the maximum power dissipation actually produced by the ic is the total quiescent supply current times the total power supply voltage and plus the power in the ic due to the loads. when sourcing, and: when sinking. where: ?i = 18 ?v s = supply voltage ?i s = quiescent current ?v out i = output voltage of the i channel ?i load i = load current of the i channel by setting the two p dmax equations equal to each other, we can solve for the r load s to avoid the device overheat. the package power dissipation curves provide a convenient way to see if the device will overheat. thermal shutdown the EL5625 has an internal the rmal shutdown circuitry that prevents overheating of t he part. when the junction temperature goes up to a bout 150c, the part will be disabled. when the junction temperature drops down to about 120c, the part will be ena bled. with this feature, any short circuit at the outputs will enable the thermal shutdown circuitry to disable the part. power supply bypassing and printed circuit board layout good printed circuit board layo ut is necessary for optimum performance. a low impedance and clean analog ground plane should be used for the EL5625. the traces from the two ground pins to the ground plane must be very short. the thermal pad of the EL5625 should be connected to the analog ground plane. lead length should be as short as possible and all power supply pins must be well bypassed. a 0.1f ceramic capacitor must be place very close to the v s , v refh , v refl , and cap pins. a 4.7f local bypass tantalum capacitor should be placed to the v s , v refh , and v refl pins. p dmax t jmax - t amax ja -------------------------------------------- - = p dmax v s i s v s ( - v out i ) i load i [] + = p dmax v s i s v out ii load i () + = EL5625
11 fn7488.0 february 28, 2006 qfn package outline drawing EL5625

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