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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary* 256mb - 32mx72 ddr sdram registered, w/pll description the w3eg7234s is a 32mx72 double data rate sdram memory module based on 128mb ddr sdram component. the module consists of eighteen 32mx4 ddr sdrams in 66 pin tsop package mounted on a 184 pin fr4 substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * this product is under development, is not quali? ed or characterized and is subject to change without notice. features double-data-rate architecture clock speeds: 100mhz and 133mhz bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2,5 (clock) programmable burst length (2,4,8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input auto and self refresh serial presence detect power supply: 2.5v 0.20v jedec standard 184 pin dimm package ? package height options: jd3: 30.48mm (1.20") ajd3: 28.70mm (1.13") operating frequencies ddr266 @cl=2 ddr266 @cl=2.5 ddr200 @cl=2 clock speed 133mhz 133mhz 100mhz cl-t rcd -t rp 2-2-2 2.5-3-3 2-2-2
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary pin configurations pin names a0 C a12 address input (multiplexed) ba0-ba1 bank select address dq0-dq63 data input/output cb0-cb7 check bits dqs0-dqs17 data strobe input/output ck0 clock input ck0# clock input cke0 clock enable input cs0# chip select input ras# row address strobe cas# column address strobe we# write enable v cc power supply v ccq power supply for dqs v ss ground v ref power supply for reference v ccspd serial eeprom power supply sda serial data i/o scl serial clock sa0-sa2 address in eeprom v ccid v cc identi? cation flag nc no connect reset# reset enable pin symbol pin symbol pin symbol pin symbol 1v ref 47 dqs8 93 v ss 139 v ss 2 dq0 48 a0 94 dq4 140 dqs17 3v ss 49 cb2 95 dq5 141 a10 4 dq1 50 v ss 96 v ccq 142 cb6 5 dqs0 51 cb3 97 dqs9 143 v ccq 6 dq2 52 ba1 98 dq6 144 cb7 7v cc 53 dq32 99 dq7 145 v ss 8dq354v ccq 100 v ss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 reset# 56 dqs4 102 nc 148 v cc 11 v ss 57 dq34 103 nc 149 dqs13 12 dq8 58 v ss 104 v ccq 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 v ss 15 v ccq 61 dq40 107 dqs10 153 dq44 16 *ck1 62 v ccq 108 v cc 154 ras# 17 *ck1# 63 we# 109 dq14 155 dq45 18 v ss 64 dq41 110 dq15 156 v ccq 19 dq10 65 cas# 111 *cke1 157 cs0# 20 dq11 66 v ss 112 v ccq 158 *cs1# 21 cke0 67 dqs5 113 *ba2 159 dqs14 22 v ccq 68 dq42 114 dq20 160 v ss 23 dq16 69 dq43 115 a12 161 dq46 24 dq17 70 v cc 116 v ss 162 dq47 25 dqs2 71 *ck2# 117 dq21 163 *cs3# 26 v ss 72 dq48 118 a11 164 v ccq 27 a9 73 dq49 119 dqs11 165 dq52 28 dq18 74 v ss 120 v cc 166 dq53 29 a7 75 *ck2# 121 dq22 167 a13* 30 v ccq 76 *ck2 122 a8 168 v cc 31 dq19 77 v ccq 123 dq23 169 dqs15 32 a5 78 dqs6 124 v ss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 v ss 80 dq51 126 dq28 172 v ccq 35 dq25 81 v ss 127 dq29 173 nc 36 dqs3 82 v ccid 128 v ccq 174 dq60 37 a4 83 dq56 129 dqs12 175 dq61 38 v cc 84 dq57 130 a3 176 v ss 39 dq26 85 v cc 131 dq30 177 dqs16 40 dq27 86 dqs7 132 v ss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 v ss 88 dq59 134 cb4 180 v ccq 43 a1 89 v ss 135 cb5 181 sa0 44 cb0 90 nc 136 v ccq 182 sa1 45 cb1 91 sda 137 ck0 183 sa2 46 v cc 92 scl 138 ck0# 184 v ccspd * not used
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary functional block diagram dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqs16 rcs0# dqs4 dqs1 dqs5 dqs2 dqs3 dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqs8 dqs17 ras# cas# cke0 ba0-ba1 a0-a12 cs0# rcs0# rba0 - rba1 ra0 - ra12 rras# rcas# rcke0 rwe# ba0-ba1: ddr sdrams a0-a12: ddr sdrams ras#: ddr sdrams cas#: ddr sdrams cke: ddr sdrams we#: ddr sdrams r e g i s t e r dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm v ss dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs i/o 3 i/o 2 i/o 1 i/o 0 cs# dm dqs10 reset# pck pck# we# a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp pll ck0 ck0# sdram register v ss ddr sdram v cc /v ccq ddr sdram ddr sdram v ref v ccspd spd note: all resistor values are 22 ohms unless otherwise speci? ed
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary parameter symbol value units voltage on any pin relative to v ss v in , v out -0.5 to 3.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 to 3.6 v storage temperature t stg -55 to +150 c power dissipation p d 27 w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability absolute maximum ratings dc characteristics 0c t a 70c, v cc = 2.5v 0.2v parameter symbol min max unit supply voltage v cc 2.3 2.7 v supply voltage v ccq 2.3 2.7 v reference voltage v ref 1.15 1.35 v termination voltage v tt 1.15 1.35 v input high voltage v ih v ref + 0.15 v ccq + 0.3 v input low voltage v il -0.3 v ref -0.15 v output high voltage v oh v tt + 0.76 v output low voltage v ol v tt -0.76 v capacitance t a = 25c. f = 1mhz, v cc = 2.5v parameter symbol max unit input capacitance (a0-a12) c in1 6.25 pf input capacitance (ras#,cas#,we#) c in2 6.25 pf input capacitance (cke0) c in3 6.25 pf input capacitance (ck0#,ck0) c in4 5.5 pf input capacitance (cs0#) c in5 6.25 pf input capacitance (dqs0-dqs17) c in6 13 pf input capacitance (ba0-ba1) c in7 6.25 pf data input/output capacitance (dq0-dq63)(dqs) c out 13 pf data input/output capacitance (cb0-cb7) c out 13 pf
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary i dd specifications and test conditions 0c t a 70c, v ccq = 2.5v 0.2v, v cc = 2.5v 0.2v includes pll and register power parameter symbol rank 1 conditions ddr266@cl=2 max ddr266@cl=2.5 max ddr200@cl=2 max units operating current i dd0 one device bank; active - precharge; t rc = t rc (min); t ck = t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two cycles. 2520 2385 2385 ma operating current i dd1 one device bank; active-read-precharge burst = 2; t rc = t rc (min); t ck = t ck (min); l out = 0ma; address and control inputs changing once per clock cycle. 2700 2520 2520 ma precharge power- down standby current i dd2p all device banks idle; power-down mode; t ck = t ck (min); cke = (low) 54 54 54 ma idle standby current i dd2f cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs and dm. 1120 1030 1030 ma active power-down standby current i dd3p one device bank active; power-down mode; t ck (min); cke = (low) 450 360 360 ma active standby current i dd3n cs# = high; cke = high; one device bank; active-precharge;t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. 1210 1120 1120 ma operating current i dd4r burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); l out = 0ma. 2745 2610 2610 ma operating current i dd4w burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq,dm and dqs inputs changing once per clock cycle. 2700 2565 2565 ma auto refresh current i dd5 t rc = t rc (min) 3770 3680 3645 ma self refresh current i dd6 cke 0.2v 329 311 346 ma operating current i dd7a four bank interleaving reads (bl=4) with auto precharge with t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active read or write commands. 4860 4770 4770 ma
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary i dd specifications and test conditions 0c t a 70c, v ccq = 2.5v 0.2v, v cc = 2.5v 0.2v includes ddr sdram components only parameter symbol rank 1 conditions ddr266@cl=2 max ddr266@cl=2.5 max ddr200@cl=2 max units operating current i dd0 one device bank; active - precharge; t rc = t rc (min); t ck = t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two cycles. 1935 1800 1800 ma operating current i dd1 one device bank; active-read-precharge burst = 2; t rc = t rc (min); t ck = t ck (min); l out = 0ma; address and control inputs changing once per clock cycle. 2115 1935 1935 ma precharge power- down standby current i dd2p all device banks idle; power-down mode; t ck = t ck (min); cke = (low) 54 54 54 ma idle standby current i dd2f cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs and dm. 810 720 720 ma active power-down standby current i dd3p one device bank active; power-down mode; t ck (min); cke = (low) 450 360 360 ma active standby current i dd3n cs# = high; cke = high; one device bank; active-precharge;t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. 900 810 810 ma operating current i dd4r burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); l out = 0ma. 2160 2025 2025 ma operating current i dd4w burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq,dm and dqs inputs changing once per clock cycle. 2115 1980 1980 ma auto refresh current i dd5 t rc = t rc (min) 3150 3060 3060 ma self refresh current i dd6 cke 0.2v 54 36 36 ma operating current i dd7a four bank interleaving reads (bl=4) with auto precharge with t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active read or write commands. 4275 4185 4185 ma
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary i dd1 : operating current: one bank 1. typical case: v cc = 2.5v, t = 25c 2. worst case: v cc = 2.7v, t = 10c 3. only one bank is accessed with t rc (min), burst mode, address and control inputs on nop edge are changing once per clock cycle. l out = 0ma 4. timing patterns ? ddr200 (100mhz, cl = 2) : t ck = 10ns, cl2, bl = 4, t rcd = 2*t ck , t rag = 5*t ck read: a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl = 2.5) : t ck = 7.5ns, cl = 2.5, bl = 4, t rcd = 3*t ck , t rc = 9*t ck , t rag = 5*t ck read: a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl = 2) : t ck = 7.5ns, cl = 2, bl = 4, t rcd = 3*t ck , t rc = 9*t ck , t rag = 5*t ck read: a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst i dd7a : operating current: four banks 1. typical case: v cc = 2.5v, t = 25c 2. worst case: v cc = 2.7v, t = 10c 3. four banks are being interleaved with t rc (min), burst mode, address and control inputs on nop edge are not changing. lout = 0ma 4. timing patterns ? ddr200 (100mhz, cl = 2) : t ck = 10ns, cl2, bl = 4, t rrd = 2*t ck , t rcd = 3*t ck , read with autoprecharge read: a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl = 2.5) : t ck = 7.5ns, cl = 2.5, bl = 4, t rrd = 3*t ck , t rcd = 3*t ck read with autoprecharge read: a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl = 2): t ck = 7.5ns, cl2 = 2, bl = 4, t rrd = 2*t ck , t rcd = 3*t ck read: a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst detailed test conditions for ddr sdram i dd1 & i dd7a legend: a = activate, r = read, w = write, p = precharge, n = nop a (0-3) = activate bank 0-3 r (0-3) = read bank 0-3
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary ddr sdram component electrical characteristics and recommended ac operating conditions 0c t a +70c; v cc = +2.5v 0.2v, v ccq = +2.5v 0.2v ac characteristics 262/265 202 parameter symbol min max min max units notes access window of dqs from ck, ck# t ac -0.75 +0.75 -0.8 +0.8 ns ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 16 ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 16 clock cycle time cl=2.5 t ck (2.5) 7.5 13 8 13 ns 22 cl=2 t ck (2) 7.5/10 13 10 13 ns 22 dq and dm input hold time relative to dqs t dh 0.5 0.6 ns 14,17 dq and dm input setup time relative to dqs t ds 0.5 0.6 ns 14,17 dq and dm input pulse width (for each input) t dipw 1.75 2 ns 17 access window of dqs from ck, ck# t dqsck -0.75 +0.75 -0.8 +0.8 ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.5 0.6 ns 13,14 write command to ? rst dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck half clock period t hp t ch , t cl t ch , t cl ns 18 data-out high-impedance window from ck, ck# t hz +0.75 +0.8 ns 8,19 data-out low-impedance window from ck, ck# t lz -0.75 -0.8 ns 8,20 address and control input hold time (fast slew rate) t ihf 0.90 1.1 ns 6 address and control input set-up time (fast slew rate) t isf 0.90 1.1 ns 6 address and control input hold time (slow slew rate) t ihs 1 1.1 ns 6 address and control input setup time (slow slew rate) t iss 1 1.1 ns 6 address and control input pulse width (for each input) t ipw 2.2 2.2 ns load mode register command cycle time t mrd 15 16 ns dq-dqs hold, dqs to ? rst dq to go non-valid, per access t qh t hp -t qhs t hp -t qhs ns 13,14 data hold skew factor t qhs 0.75 1 ns active to precharge command t ras 40 120,000 40 120,000 ns 15 active to read with auto precharge command t rap 15 20 ns active to active/auto refresh command period t rc 60 70 ns auto refresh command period t rfc 75 80 ns 21
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary ddr sdram component electrical characteristics and recommended ac operating conditions (continued) 0c t a +70c; v cc = +2.5v 0.2v, v ccq = +2.5v 0.2v ac characteristics 262/265 202 parameter symbol min max min max units notes active to read or write delay t rcd 15 20 ns precharge command period t rp 15 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck 19 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 12 15 ns dqs write preamble t wpre 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 ns 10,11 dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 9 write recovery time t wr 15 15 ns internal write to read command delay t wtr 11t ck data valid output window na t qh -t dqsq t qh -t dqsq ns 13 refresh to refresh command interval t refc 140.6 140.6 s 12 average periodic refresh interval t refi 15.6 15.6 s 12 terminating voltage delay to v cc t vtd 00ns exit self refresh to non-read command t xsnr 75 80 ns exit self refresh to read command t xsrd 200 200 t ck
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary 11. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss . 12. the refresh period is 64ms. this equates to an average refresh rate of 15.625s. however, an auto refresh command must be asserted at least once every 140.6s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 13. the valid data window is derived by achieving other speci? cations - t hp (t ck/2 ), t dqsq , and t qh (t qh = t hp - t qhs ). the data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycled variation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. the data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 14. referenced to each output group: x4 = dqs with dq0-dq3. 15. r eads and writes with auto precharge are not allowed to be issued until t ras (min) can be satis? ed prior to the internal precharge command being issued. 16. jedec speci? es ck and ck# input slew rate must be > 1v/ns (2v/ns differentially). 17. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rates exceed 4v/ns, functionality is uncertain. 18. t hp min is the lesser of t cl min and t ch min actually applied to the device ck and ck# inputs, collectively during bank active. 19. t hz (max) will prevail over the t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + pre (max) condition. 20. for slew rates greater than 1v/ns the (lz) transition will start about 310ps earlier. 21. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t rfc has been satis? ed. 22. w henever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles (before read commands). notes 1. all voltages referenced to v ss 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at normal reference / supply voltage levels, but the related speci? cations and device operations are guaranteed for the full voltage range speci? ed. 3. outputs are measured with equivalent load: output o u t p u t (v ( v out o u t ) reference r e f e r e n c e point p o i n t 50? 5 0 ? v tt t t 30pf 3 0 p f 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci? cations are guaranteed for the speci? ed ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level speci? cations are de? ned in the sstl_ 2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. for slew rates less than 1v/ns and greater than or equal to 0.5v/ ns. if the slew rate is less than 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100mv/ns reduction in slew rate from the 500mv/ns. t ih has 0ps added, that is, it remains constant. if the slew rate exceeds 4.5v/ns, functionality is uncertain. for 403 and 335, slew rates must be greater than or equal to 0.5v/ns. 7. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.3 x v ccq is recognized as low. 8. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a speci? c voltage level, but specify when the device output is no longer driving (hz) and begins driving (lz). 9. the intent of the dont care state after completion of the postamble is the dqs-driven signal should either be high, low, or high-z, and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high (above v ihdc (min) then it must not transition low (below v ihdc ) prior to t dqsh (min). 10. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround.
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary ordering information for jd3 part number speed cas latency t rcd t rp height* w3eg7234s262jd3 133mhz/266mb/s 2 2 2 30.48 (1.20") w3eg7234s265jd3 133mhz/266mb/s 2.5 3 3 30.48 (1.20") w3eg7234s202jd3 100mhz/200mb/s 2 2 2 30.48 (1.20") 2.31 (0.091) (2x) 133.48 (5.255" max.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 30.48 (1.20 max) 1.27 (0.050 typ.) 6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 4.06 (0.160 max) 3.99 (0.157) (min) 1.27 0.10 (0.050 0.004) package dimensions for jd3 * all dimensions are in millimeters and (inches).
12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary ordering information for ajd3 part number speed cas latency t rcd t rp height* w3eg7234s262ajd3 133mhz/266mb/s 2 2 2 28.70 (1.13") w3eg7234s265ajd3 133mhz/266mb/s 2.5 3 3 28.70 (1.13") w3eg7234s202ajd3 100mhz/200mb/s 2 2 2 28.70 (1.13") 133.48 (5.255" max.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 28.70 (1.13 max) 2.31 (0.091) (2x) 1.27 (0.050 typ.) 6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 4.06 (0.160 max) 3.99 (0.157) (min) 1.27 0.10 (0.050 0.004) package dimensions for ajd3 * all dimensions are in millimeters and (inches).
13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary ordering information for d3 part number speed cas latency t rcd t rp height* w3eg7234s262d3 133mhz/266mb/s 2 2 2 28.58 (1.125") W3EG7234S265D3 133mhz/266mb/s 2.5 3 3 28.58 (1.125") w3eg7234s202d3 100mhz/200mb/s 2 2 2 28.58 (1.125") 133.48 (5.255" max.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 28.58 (1.125 max) 2.31 (0.091) (2x) 1.27 (0.050 typ.) 6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 4.06 (0.160 max) 3.99 (0.157) (min) 1.27 0.10 (0.050 0.004) package dimensions for d3 * all dimensions are in millimeters and (inches). not recommended for new designs
14 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg7234s-d3 -jd3 -ajd3 december 2004 rev. 2 preliminary document title 256mb - 32mx72 ddr sdram registered, w/pll revision history rev # history release date status rev a created 5-21-02 advanced rev 0 0.1 updated cap and i dd specs 0.2 removed "ed" from part marking 0.3 added jd3 and ajd3 package height options 0.4 moved datasheet from advanced to preliminary 0.5 added new document title page 7-04 preliminary rev 1 1.1 added ac specs 11-04 preliminary rev 2 2.1 updated i dd specs 12-04 preliminary

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