View SAA2032GP_5162077.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet february 1995 integrated circuits philips semiconductors saa2032 digital equalization for the tape drive processing of the dcc system product speci?cation supersedes data of february 1993 file under integrated circuits, miscellaneous
philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 february 1995 2 features analog-to-digital conversion, demultiplexing, equalization and zero crossing of time multiplexed analog read amplifier signal microcontroller interface search mode envelope, label and virgin detection of the aux channel search mode tape speed measurement simplified external biassing reduced power consumption analog eye output 4 v nominal operating voltage capability. general description performing the digital equalizing function in the digital compact cassette (dcc) system, the saa2032 is intended for use in conjunction with the saa2022, read amplifier tda1317 or tda1318. ordering information note 1. when using reflow soldering it is recommended that the dry packing instructions in the quality reference pocketbook are followed. the pocketbook can be ordered using the code 9398 510 34011. extended type number package pins pin position material code SAA2032GP 44 qfp 1 plastic sot205ag
february 1995 3 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 fig.1 block diagram. clock generation slicer filter demux adc virgin label detector lt interface 22 23 24 25 26 27 28 29 30 31 3 2 43 5 32 33 34 35 rdclk rdsync label virgin aenv ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 aux ltdata v dd v ddad saa2032 v ss 11 12 13, 17, 39 vin ltendeq ltcnt1 ltcnt0 ltclk mea663 v ssad 10 24 f 37 36 38 v ssa 8, 14 val digeye 1 44 dac aneye 15
february 1995 4 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 pinning symbol pin description digeye 1 serial data output for eye pattern rdsync 2 sync data for read ampli?er (push-pull output) rdclk 3 data clock for read ampli?er (push-pull output) test1 4 test 1; to be connected to v ss vin 5 analog time multiplexed input from read ampli?er refn 6 lower reference voltage (+1 v) for adc refp 7 upper reference voltage (+3.1 v) for adc v ssa 8 analog ground (0 v) biasa 9 bias current for adc (sinks current from v ddad via 33 k w ) v ssad 10 supply ground (0 v) for adc v ddad 11 supply voltage (+5 v) for adc v dd 12 supply voltage (+5 v) v ss 13 supply ground (0 v) v ssa 14 supply ground (0 v) aneye 15 analog eye voltage output n.c. 16 not connected v ss 17 supply ground (0 v) test4 18 test 4; do not connect test5 19 test 5; do not connect test6 20 test 6; do not connect test7 21 test 7; do not connect ch0 22 channel 0 output for saa2022 (dcc drive signal processing) (push-pull output) ch1 23 channel 1 output for saa2022 (push-pull output) ch2 24 channel 2 output for saa2022 (push-pull output) ch3 25 channel 3 output for saa2022 (push-pull output) ch4 26 channel 4 output for saa2022 (push-pull output) ch5 27 channel 5 output for saa2022 (push-pull output) ch6 28 channel 6 output for saa2022 (push-pull output) ch7 29 channel 7 output for saa2022 (push-pull output) aux 30 aux channel output for saa2022 (push-pull output) ltdata 31 microcontroller i/o data interface (3-state push-pull output and input; cmos levels) ltendeq 32 microcontroller interface enabling (cmos input levels) ltcnt1 33 microcontroller interface; mode control 1 (cmos input levels) ltcnt0 34 microcontroller interface; mode control 0 (cmos input levels) ltclk 35 microcontroller bit-clock interface (cmos input levels) virgin 36 search mode virgin detection output label 37 search mode label detection output aenv 38 search mode auxiliary detection output v ss 39 supply ground (0 v)
february 1995 5 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 test8 40 test 8 input; to be connected to v ss test9 41 test 9 input; to be connected to v ss test10 42 test 10 input; to be connected to v ss f24 43 clock input; typical frequency 24.576 mhz (cmos input) val 44 synchronization output for digeye symbol pin description dd v 12 13 14 15 16 17 18 19 20 21 22 test7 ch0 test6 test5 test4 n.c. aneye ss v ssa v ss v 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 digeye rdsync rdclk test1 vin refn refp biasa v ssad v ddad ltcnt1 ltendeq ltdata aux ch7 ch6 ch5 ch4 ch3 ch2 ch1 f24 test10 ltclk 44 43 42 41 40 39 38 37 36 35 34 val test9 test8 aenv label virgin ltcnt0 ss v saa2032 mea661 v ssa fig.2 pin configuration.
february 1995 6 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 heads and tape mea695 - 2 saa2022 ram 256 kbits saa2032 digital equalizer write read tda1317 or tda1318 tda1316 or tda1319 tape drive processing adc saa7360 dac saa7323 analog input daio tda1315 digital input analog output audio input/output pasc processing saa2012 saa2002 adaptive allocation and scale factors stereo filter codec recording + play back i s (sub-band) 2 microcontroller i s 2 speed control capstan drive digital output fig.3 dcc data flow diagram.
philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 february 1995 7 functional description operating modes deq operating modes are programmed via the lt interface: n ormal a/d conversion demultiplexing equalization zero crossing. in this mode the saa2032 performs the equalization and slicing of the eight data channels and the auxiliary channel. the eight data channels have a bit-rate of 96 kbits/s while the auxiliary channel has a bit-rate of 12 kbits/s. the saa2032 input is a time-multiplexed analog signal from the read amplifier. the signal contains ten time slots, of which nine are used. the read amplifier and the saa2032 synchronize with the rdclk and rdsync signals generated by the saa2032. following a/d conversion and demultiplexing the nine channels are equalized. the encoding of the equalizing coefficients (12 per channel) are not fixed and must be loaded via the lt interface before operation. the nine equalized output signals are up-sampled by a factor of 10 with the resulting signals fed to the slicer. the slicer output is applied to the saa2022. t est a/d conversion demultiplexing equalization zero crossing eye-pattern. same as normal mode. in addition the digital and analog eye-pattern outputs are enabled. the eye-pattern output corresponds to one of the equalized channel outputs. s earch a/d conversion envelope detection tape search and speed measurement. in the search mode the analog input signal from the read amplifier is not the multiplexed signal but only the auxiliary channel signal. following a/d conversion the envelope of this signal is filtered and sliced. this forms the alternating envelope aenv output. the label and virgin outputs are detected from this and the tape search speed measured. o ff in the off mode the rdsync and rdclk signals are high, the eye outputs are disabled and the channel and auxiliary outputs (ch0 to ch7 and aux) are 3-stated. read ampli?er interface the interface between the read amplifier and the saa2032 consists of three signals: 1. vin from read amplifier to saa2032; time multiplexed data. 2. rdsync from saa2032 to read amplifier; synchronization between read amplifier multiplexer and saa2032 demultiplexer. 3. rdclk from saa2032 to read amplifier; data clock for read amplifier multiplexer. the multiplexed vin output of the read amplifier changes to another channel at the rising edge of rdclk. rdsync synchronizes the read amplifier vin output: if rdsync is high, the rising edge of the rdclk will select the aux channel. figures 4 and 5 show the relationship between the saa2032 and the read amplifier. saa2022 interface the interface with the saa2022 consists of the 9 data output signals ch0 to ch7, aux. table 1 dependency of read ampli?er on operational mode. label and virgin detection interface when the dcc player is in its search mode, the tape is fast-wound while the head retains tape contact. the saa2032 can be made to operate in the search mode and the information will be read from the auxiliary tape track. operational mode rdsync rdclk normal yes yes test yes yes search high yes off high high
february 1995 8 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 the following three signals are generated: 1. label: label detection (high if label is detected). 2. virgin: virgin tape detection (high if virgin tape is detected). 3. aenv: alternating envelope (sliced envelope). aenv, label and virgin are disabled in normal or off modes. label, virgin and aenv are low. aenv, label and virgin are enabled when the saa2032 is in search mode. the device detects the envelope aenv of the auxiliary track at search speeds between 3 and 50 times normal speed. if aenv is continuously high (label detection), label will be high. when aenv is continuously low (virgin tape detection) virgin will be high. figures 6, 7 and 8 show the relationship between aenv, virgin and label. labelled tape-speed calculation when the dcc player is in its search mode, the tape speed increases. label information is encoded throughout its length. to examine the length of a label, the tape speed must be known. in search mode the saa2032 assesses the speed of labelled tapes. the microcontroller obtains this information via the lt-interface. the speed information is encoded in 3 variables: 1. svf speed validation flag (high if invalid). 2. sc (4..0) speed counter. 3. sr (1..0) speed range. if sc = 0 then search speed > 51.2. with sr = 0, 1, 2 or 3 and sc = 0 to 31. if svf = 1 then sr and sc values are invalid. appendix 1 gives a table of the search mode speed control. microcontroller (lt) interface the saa2032 is able to exchange information with the microcontroller via the lt-interface. the microcontroller performs as master, the saa2032 as slave. figure 9 gives the operation of the lt-interface. search speed 2 sr 51.2 sc ----------- = x normal speed. ? ? fig.4 signals on interface between read amplifier and saa2032. rdclk rdsync vin mcd477 ch7 aux *** ch0 ch3 ch4 ch5 ch6 ch7 aux *** ch0 ch2 ch1 ch1
february 1995 9 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 t su > 80 ns; set-up time vin before rdclock high. typical frequency for rdclk = 3.072 mhz. typical frequency for rdsync = 307.2 khz. fig.5 timing. t su vin stable rdclk vin mcd478 t d1 = t d2 = between 0.5 and 1.0 auxiliary block lengths. fig.6 diagram of aenv signal. t d2 t d1 mcd488 - 1 signal from tape aenv
february 1995 10 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 t d3 aenv label mla635 - 2 t d4 t d3 = between 4 and 12 auxiliary blocks. t d4 = between 4 and 12 auxiliary blocks. fig.7 aenv and label signals. t d5 = t d6 = between 4 and 12 auxiliary blocks. fig.8 aenv and virgin signals. t d5 aenv virgin mla634 - 2 t d6
february 1995 11 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 ltcnt speci?cation table 2 four types of data exchange performed on the interface. ltcnt1 ltcnt0 lt data exchange mode from to 0 0 data write m c deq 0 1 data read deq m c 1 0 address write m c deq 1 1 mode settings write m c deq fig.9 typical operation of the lt-interface. ltendeq ltcnt 0/1 ltclk ltdata 01234567 lsb msb mcd479
philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 february 1995 12 mode settings load (ltcnt = 11) (see fig.10) the 8-bits transmitted under mode settings load control both the operation mode and the data exchange type. table 3 mode settings; operation mode. table 4 mode settings; data exchange type. remark post condition: after every communication sequence the data exchange type must be set to read coefficient data. a1 a0 operation mode 0 0 normal 0 1 test 1 0 search 1 1 off b1 b0 data exchange type 0 0 write coef?cient data 0 1 read coef?cient data 1 1 read envelope data fig.10 mode settings load (ltcnt = 11). **** b1 b0 a1 a0 msb lsb mcd480 data exchange type operation mode address information load (ltcnt = 10) (see fig.11) a channel/tap combination can be selected through this type of data exchange. co-ef?cient data load (ltcnt = 00) (see fig.12) this type of data exchange will overwrite the equalizer tap coefficient of the current selected channel/tap combination. the coefficient data for tap <0000> of the auxiliary channel should always be zero. data read (ltcnt = 01) (see fig.13) this type of data exchange will send information from the ltdata register in the saa2032 to the microcontroller. data in the ltdata register depends upon the current data exchange type. ltdata interpretation: coefficient data: twos complement coefficient data tape speed data C d7 = svf flag C d6 to d2 = sc4 to sc0 C d1, d0 = sr1, sr0. tape speed data format is shown in fig.14.
february 1995 13 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 c3 to c0 --> channel number <0000 to 0111> + auxiliary channel <1000> t3 to t0 --> tap number <0000 .. 1011> fig.11 address information load (ltcnt = 10). c3 c2 c1 c0 t3 t2 t1 t0 msb lsb mcd481 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb mcd482 fig.12 coefficient data load (ltcnt = 00). fig.13 read data (ltcnt = 01). d7 d6 d5 d4 d3 d2 d1 d0 msb lsb mcd483 fig.14 tape speed data format. mbc381 svf sc (h. . .0) d0 sr (1. . .0) d7
february 1995 14 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 fig.15 microcontroller to saa2032 timing. mcd485 - 1 ltclk ltcnt0/1 ltendeq 0 1 ltdata bit t h2 t hc t lc t h1 t su1 t su4 t su2 t le t su3 t h3 t le > 120 ns; minimum low time ltendeq before transfer. t su1 > 20 ns; set-up time ltcnt0/1 before ltendeq high. t h1 > 100 ns; hold time ltcnt0/1 after ltendeq high. t su2 3 0 ns; set-up time ltcnt0/1 before ltclk low. t h2 > 20 ns; hold time ltendeq after ltclk high. t lc > 120 ns; minimum low time ltclk. t hc > 120 ns; minimum high time ltclk. t su4 > 200 ns; set-up time ltclk before ltendeq high. t su3 > 100 ns; set-up time ltdata before ltclk high. t h3 > 20 ns; hold time ltdata after ltclk high.
february 1995 15 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 fig.16 saa2032 to microcontroller timing. mcd486 - 1 ltclk ltcnt0/1 ltendeq 0 1 ltdata bit t d1 t d2 t h6 t h2 t hc t lc t h1 t su1 t su4 t su2 t le t h5 t le > 120 ns; minimum low time ltendeq before transfer. t su1 > 20 ns; set-up time ltcnt0/1 before ltendeq high. t h1 > 100 ns; hold time ltcnt0/1 after ltendeq high. t su2 3 0 ns; set-up time ltcnt0/1 before ltclk low. t h2 > 20 ns; hold time ltendeq after ltclk high. t lc > 120 ns; minimum low time ltclk. t hc > 120 ns; minimum high time ltclk. t su4 > 200 ns; set-up time ltclk before ltendeq high. t d1 > 300 ns; maximum delay ltdata after ltendeq high. t d2 > 400 ns; maximum delay ltdata after ltclk high. t h5 > 160 ns; hold time ltdata after ltclk high. t h6 > 0 ns; hold time ltda after ltendeq low.
february 1995 16 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 eye pattern output to test equalization performance it is possible to output the equalized channels. for this purpose one analog and two digital output signals are provided. selection of the eye pattern output is determined by the last channel address sent to the saa2032. digeye: serial data line for 8-bits output value val: validation signal for data bits aneye: analog eye voltage output. the eye outputs are enabled in test mode. table 5 eye outputs. the internal number representation in the saa2032 is in two's complement. the format of the selected 8-bits will be converted to the off-set-binary format. this means that the msb of the two's complement number has been inverted. this 8-bit number is shifted out via the digeye output. figure 17 gives the eye pattern output timing. operation mode digeye aneye normal low high test enabled enabled search low high off low high fig.17 timing diagram. mea662 - 1 stable data t h t su t clk rdclk digeye lsb msb (inverted) lsb digeye rdclk val t val t eye t val = 1/4 clock period; pulse width high. t su > 60 ns; minimum set-up time data before clock. t h > 5 ns; minimum hold time data after clock. t clk = 1/f clk . f clk = 3.072 mhz; nominal digeye clock frequency. t eye = 1/f eye . f eye = 307.2 khz; nominal digeye clock frequency.
february 1995 17 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. input voltage should not exceed 6.5 v unless otherwise specified. 2. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 3. equivalent to discharging a 200 pf capacitor through a 0 w series resistor. dc characteristics v dd = 3.8 to 5.5 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +6.5 v v i input voltage note 1 - 0.5 v dd + 0.5 v i ss supply current in v ss -- 100 ma i dd supply current in v dd - 100 ma i i input current - 10 10 ma i o output current - 20 20 ma p tot total power dissipation - 550 mw t stg storage temperature - 55 +150 c t amb operating ambient temperature - 40 +85 c v es1 electrostatic handling note 2 - 1500 +1500 v v es2 electrostatic handling note 3 - 70 +70 v symbol parameter conditions min. typ. max. unit supply v dd supply voltage 3.8 5.0 5.5 v v ddad supply voltage for adc note 1 3.8 5.0 5.5 v i dd supply current v dd = 5 v; note 2 - 22 26 ma v dd = 3.8 v; note 2 - 12 14 ma i ddad supply current for adc v ddad = 5 v - 11 13 ma v ddad = 3.8 v - 57ma i op operating current note 3 1.3 1.9 3.4 ma inputs f24, ltclk, ltcnt0, ltcnt1 and ltendeq v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i i input current v i = 0 v; t amb = 25 c --- 10 m a v i = v dd ; t amb = 25 c -- 10 m a input refp v refp reference voltage 2.7 3.1 3.4 v input refn v refn reference voltage 0.7 1.0 1.4 v
february 1995 18 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 notes 1. v ddad should never be lower than v dd - 0.2 v. 2. for load impedances in a typical application circuit. 3. operating reference current for the specified range of v refp allowing for the tolerance on the internal resistor. 4. for outputs digeye, rdsync, rdclk, ch0 to ch7, aux and val the maximum load current is 1 ma. for aneye output the maximum load current is 10 m a. for virgin, label and aenv the maximum load current is 2 ma. inputs refp and refn d v ref reference voltage difference between refp and refn 2 2.1 2.7 v input vin v i(p-p) input voltage (peak-to-peak) v refn - v refp v i i input current -- 100 m a digital outputs v ol low level output voltage note 4 -- 0.4 v v oh high level output voltage note 4 v dd - 0.5 -- v output aneye v o output voltage note 4 -- v ddad v v o output voltage range note 4 - 1.1 - v input/output ltdata v ol low level output voltage i o = - 3ma -- 0.4 v v oh high level output voltage i o = 2 ma v dd - 0.5 -- v i oz leakage current with outputs in 3-state v i = 0 v; t amb = 25 c -- 10 m a v i = v dd ; t amb = 25 c -- 10 m a v il low level input voltage -- 0.3v dd v v ih high level input voltage 0.7v dd -- v symbol parameter conditions min. typ. max. unit
february 1995 19 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 ac characteristics v dd = 3.8 to 5.5 v; t amb = - 40 to 85 c; unless otherwise speci?ed. note 1. low-to-high transition. symbol parameter conditions min. typ. max. unit vin c i input capacitance -- 15 pf all digital inputs c i input capacitance -- 10 pf clock input f24 f clock frequency 23 24.576 26 mhz t p pulse width low or high 10 -- ns inputs ltclk, ltendeq, ltcnt0 and ltcnt1 t su set-up time to f24 note 1 10 -- ns t h hold time from f24 note 1 30 -- ns all outputs c i input capacitance -- 10 pf c l load capacitance -- 50 pf t d propagation delay time from f24 note 1 -- 80 ns input/output ltdata c i input capacitance -- 10 pf c l load capacitance -- 50 pf t d propagation delay time from f24 -- 80 ns t su set-up time to f24 note 1 10 -- ns t h hold time from f24 note 1 30 -- ns
february 1995 20 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 converter characteristics v dd = 3.8 to 5.5 v; t amb = - 40 to 85 c; unless otherwise speci?ed. notes 1. v refp is supplied externally. v refn is derived internally and set to 1 / 3 v refp . v refn must be decoupled externally at pin 6 via a 100 nf capacitor. 2. signal level (f s ) - 20 db, at any dc level within the input voltage range. 3. the output impedance of the analog input signal source must be <150 w . 4. load impedance 3 1m w . symbol parameter conditions min. typ. max. unit analog-to-digital converter; vin resolution - 7 - bits conversation data available after - 2 t cy - effective input bandwidth 6-bit resolution at f s = 3.1 mhz 0.5 -- mhz differential non-linearity -- 0.99 lsb v refn reference voltage at vrefn note 1 0.7 1.0 1.4 v v refp reference voltage at vrefp 2.7 3.1 3.4 v d v ref reference voltage difference between refp and refn 2 2.1 2.7 v v i input voltage v refn - v refp v s+thd/n signal-to-total harmonic distortion and noise ratio note 2 21 -- db c i input capacitance -- 15 pf i i input current (dc) note 3 -- 100 m a digital-to-analog converter; output aneye resolution - 6 - bits v o output voltage note 4 -- v ddad v v o output voltage range note 4 - 1.1 - v
february 1995 21 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 appendix 1 search mode speed control interface in search mode the saa2032 measures the tape speed. the tape speed is encapsulated in the variables: svf speed validation flag; is high if not valid sc speed counter sr speed range. the values in table 6 represent the speed in multiples of the nominal tape speed of 4.76 cm/s. table 6 speed in multiples of nominal tape speed. sc[4 .. 0] sr[1 .. 0] remarks 0123 0 >51.20 >102.40 >204.80 >409.60 shift to higher speed range 1 51.20 102.40 204.80 409.60 2 25.60 51.20 102.40 204.80 3 17.07 34.13 68.27 136.53 4 12.80 25.60 51.20 102.40 5 10.24 20.48 40.96 81.92 6 8.53 17.07 34.13 68.27 7 7.31 14.63 29.26 58.51 8 6.40 12.80 25.60 51.20 normal working area 9 5.69 11.38 22.76 45.51 10 5.12 10.24 20.48 40.96 11 4.65 9.31 18.62 37.24 12 4.27 8.53 17.07 34.13 13 3.94 7.88 15.75 31.51 14 3.66 7.31 14.63 29.26 15 3.41 6.83 13.65 27.31 16 3.20 6.40 12.80 25.60 17 3.01 6.02 12.05 24.09
february 1995 22 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 18 2.84 5.69 11.38 22.76 shift to lower speed range 19 2.69 5.39 10.78 21.56 20 2.56 5.12 10.24 20.48 21 2.44 4.88 9.75 19.50 22 2.33 4.65 9.31 18.62 23 2.23 4.45 8.90 17.81 24 2.13 4.27 8.53 17.07 25 2.05 4.10 8.19 16.38 26 1.97 3.94 7.88 15.75 27 1.90 3.79 7.59 15.17 28 1.83 3.66 7.31 14.63 29 1.77 3.53 7.06 14.12 30 1.71 4.41 6.83 13.65 31 1.65 3.30 6.61 13.21 sc[4 .. 0] sr[1 .. 0] remarks 0123
february 1995 23 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 package outline dimensions in mm. 2.0 1.2 mbc659 - 1 detail x 1.2 0.9 0.25 0.14 2.60 2.15 0 to 7 o 2.3 2.1 0.25 0.05 s 0.15 s seating plane x a b 19.2 18.2 2.4 1.8 (4x) 14.1 13.9 19.2 18.2 0.15 m b 0.50 0.35 2.4 1.8 (4x) 14.1 13.9 pin 1 index 1 44 34 33 23 22 12 11 0.50 0.35 0.15 m a 1.0 1.0 fig.18 44-lead quad flat-pack; plastic (sot205ag).
february 1995 24 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 soldering quad ?at-packs b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two waves (dual-wave), in which, in a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour- phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. r epairing soldered joints ( by hand - held soldering iron or pulse - heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
february 1995 25 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress rating only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. the digital compact cassette logo is a registered trade mark of philips electronics n.v.
february 1995 26 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 notes
february 1995 27 philips semiconductors product speci?cation digital equalization for the tape drive processing of the dcc system saa2032 notes
philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970). tel. (011)829-1166, fax. (011)829-1849 canada: integrated circuits: tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 601 milner ave, scarborough, ontario, m1b 1m8, tel. (0416)292 5161 ext. 2336, fax. (0416)292 4477 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: carrera 21 no. 56-17, bogota, d.e., p.o. box 77621, tel. (571)217 4609, fax. (01)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. (031)57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (9)0-50261, fax. (9)0-520971 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: p.o. box 10 63 23, 20095 hamburg , tel. (040)3296-0, fax. (040)3296 213 greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 hong kong: 15/f philips ind. bldg., 24-28 kung yip st., kwai chung, tel. (0)4245 121, fax. (0)4806 960 india: peico electronics & electricals ltd., components dept., shivsagar estate, block 'a', dr. annie besant rd., worli, bombay 400 018, tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)640 000, fax. (01)640 200 italy: viale f. testi, 327, 20162 milano, tel. (02)6752.1, fax. (02)6752.3350 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, kokio 108, tel. (03)3740 5101, fax. (03)3740 0570 korea: (republic of) philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)794-5011, fax. (02)798-8022 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)757 5511, fax. (03)757 4880 mexico: philips components, 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, tel. (040)78 37 49, fax. (040)78 83 99 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (22)74 8000, fax. (22)74 8341 pakistan: philips markaz, m.a. jinnah rd., karachi 3, tel. (021)577 039, fax. (021)569 1832 philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 911, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: av. eng. duarte pacheco 6, 1009 lisboa codex, tel. (01)683 121, fax. (01)658 013 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: 195-215 main road, martindale, p.o. box 7430,johannesburg 2000, tel. (011)470-5433, fax. (011)470-5494 spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 7730 taiwan: 69, min sheng east road, sec 3, p.o. box 22978, taipei 10446, tel. (2)509 7666, fax. (2)500 5899 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna - trad road km. 3 prakanong, bangkok 10260, tel. (2)399-3280 to 9, (2)398-2083, fax. (2)398-2080 turkey: talatpasa cad. no. 5, 80640 levent/istanbul, tel. (0212)279 2770, fax. (0212)269 3094 united kingdom: philips semiconductors limited, p.o. box 65, philips house, torrington place, london, wc1e 7hd, tel. (071)436 41 44, fax. (071)323 03 42 united states: integrated circuits: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 2001 west blue heron blvd., p.o. box 10330, riviera beach, florida 33404, tel. (800)447-3762 and (407)881-3200, fax. (407)881-3300 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 for all other countries apply to: philips semiconductors, international marketing and sales, building baf-1, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd28 ? philips electronics n.v. 1994 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors

▲Up To Search▲

Price & Availability of SAA2032GP

	To Download SAA2032GP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .