View MSM548332_5071374.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor MSM548332 1/23 ? semiconductor MSM548332 278,400-word 12-bit field memory description the MSM548332 is a 3.3-mbit, 960 bits 290 lines, field memory. access is done line by line. the line address must be set each time a line is changed. more than two MSM548332s can be cascaded directly without any delay devices between them. cascading MSM548332s provides larger capacity and longer delay. x serial address input enables random initial address setting of serial access in a page. other than the random address setting, MSM548332 has several types of address set modes such as line hold, address jump to initial address and line increment. self refresh function releases the MSM548332 from being applied external refresh control clocks even though it contains dynamic type memory cells. MSM548332 has write mask function or input enable function (ie), and read-data skipping function or output enable function (oe). the MSM548332 is especially designed for digital tvs and vtrs for consumer use and video cameras. the MSM548332 is not designed for high end use in such applications as medical systems, professional graphics systems which require long term picture storage, data storage systems and others. features ? 960 290 12-bit configuration ? line by line access ? x serial address inputs for random serial initial bit address ? asynchronous operation ? serial read and write cycle times read cycle: 30 ns/50 ns write cycle: 30 ns/50 ns ? low operating supply voltage: 3.3 v 0.3 v ? self-refresh ? various address reset mode for picture processing ? write mask function (input enable control) ? data skipping function (output enable control) ? package: 44-pin 400 mil plastic tsop (type ii) (tsopii44-p-400-0.80-k) (product : MSM548332-xxts-k) xx indicates speed rank. this version: jan. 1998 previous version: dec. 1996 e2l0036-17-y1
? semiconductor MSM548332 2/23 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 21 22 44-pin plastic tsop ( ii ) (k type) 20 v ss din5 din4 din3 din2 din1 din0 rclk rxad rade/rx re oe do0 do1 v cc do2 do3 do4 do5 v ss 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 24 23 25 din6 din7 din8 din9 din10 din11 wclk wxad wade/rx wr/tr ie do11 do10 v cc do9 do8 v ss do6 v cc do7 11 rr 34 we 12 rxinc 33 wxinc
? semiconductor MSM548332 3/23 note: same power supply voltage level must be provided to every v cc pin. same ground voltage level must be provided to every v ss pin. pin name serial read/write cycle address setting cycle function rclk read port, serial read clock read port, x serial address strobes re read port, read enable do0 - 11 read port, data output rr read port, address reset mode enable rxinc read port, x address increment rade/rx read port, x address input enable read port, x address reset rxad read port, x serial address data oe output enable wclk write port, serial write clock write port, x serial address strobes we write port, write enable din0 - 11 write port, input data wr/tr write port, write data transfer write port, address reset mode enable wxinc write port, x address increment wade/rx write port, x address input enable write port, x address reset wxad write port, x serial address data ie input enable v cc power supply voltage (3.3 v) v ss ground (0 v)
? semiconductor MSM548332 4/23 block diagram wclk refresh counter write buffer write register memory cell array 960 290 12 bits read register d out buffer rclk re oe 12 din0 to din11 do0 to do11 12 we wclk ie memory controller read address control write address control rclk wade/rx rade/rx wxad rxad wr/tr rr wxinc rxinc v bb generator x-address decoder
? semiconductor MSM548332 5/23 pin function read related rclk : read clock rclk is the read control clock input. synchronized with rclk's rising edge, serial read access from read ports is executed when both re and oe are high. the internal counter for the serial read address is incremented automatically on the rising edge of rclk. in a read address set cycle, all the read address bits which were input from rxad pin are stored into internal address registers synchronized with rclk. in this address set cycle, rade/rx must be held high and rr must be held low. in the read address reset cycle, various read address reset modes can be set synchronously with rclk. these reset cycles work to replace complicated serial address control which requires many rclk clocks with a simple reset cycle control requiring only a single rclk cycle. it greatly facilitates memory access. re : read enable re is a read enable clock input. re enables or disables both internal read address pointers and data- out buffers. when re is high, the internal read address pointer is incremented synchronously with rclk. when re is low, even if the rclk is input, the internal read address pointer is not incremented. oe : output enable oe is an output enable clock input. oe enables or disables data-outs. oe high level enables the outputs. the internal read address pointer is always incremented by cycling rclk regardless of oe level. do0-11 : data-outs do0-11 are serial data-outs. data is output synchronously with rclk when oe is high. the output enable/disable operation through oe input is performed synchronously with oe and asynchronously with rclk. rr : read reset rr is a read reset control input. read address reset modes are defined when rr level is high according to the "function table for read". rxinc : read x address increment rxinc is a read x address (or line address) increment control input. in the read address reset cycle, defined by rr high, the x address (or line address) is incremented by 1 when rxinc is pulled high with rade/rx low. rade/rx : read address enable/read x address reset logic function rade/rx is a dual function control input. rade, one of the two functions of rade/rx, is a read address enable input. in the read address set cycle, defined by rr high, x address (or line address) input from the rxad pin are latched into internal read x address register synchronously with rclk. rx, the second function of rade/rx, works as an element to set read x address (or line address) reset mode. in an address reset mode cycle, defined by rr high, read x address is reset to 0 when rade/rx is pulled high with rxinc low. rxad : read x address rxad is a read x address (or line address) input. rxad specifies the line address. 9 bits of read x address data are input serially from rxad.
? semiconductor MSM548332 6/23 write related wclk : write clock wclk is a write control clock input. synchronized with wclk's rising edge, serial write access into write ports is executed when we is high and ie is high. according to wclk clocks, the internal counter for the serial address is incremented automatically. in a write address set cycle, all the write addresses which were input from wxad are stored into internal address registers synchronously with wclk. in this address set cycle, wade/rx must be held high and wr/tr must be held low. in the write address reset cycle, various write address reset modes can be set synchronously with wclk. these reset cycles replace complicated serial address control with simple reset cycle control which requires only one wclk cycle. it greatly facilitates memory access. we : write enable we is a write enable clock input. we enables or disables both internal write address pointers and data-in buffers. when we is high, the internal write address pointer is incremented synchronously with wclk. when we is low, even if wclk is input, the internal write address pointer is not incremented. din0-11 : data-ins din0-11 are serial data-ins. corresponding data-in-buffers are masked by ie. wr/tr : write reset/write transfer wr/tr is a write reset control input. write address reset modes are defined when wr/tr level is high according to the "function table for write". when the write operation on a line is terminated, be sure to perform a write transfer operation by wr/tr in order to store the written data in the write register to corresponding memory cells. wxinc : write x address increment wxinc is a write x address (or line address) increment control input. in the write address reset cycle, defined by wr/tr high, the write x address (or line address) is incremented when wxinc and wade/rx are high. wade/rx : write address enable/write x address reset logic function wade/rx is a dual functional control input. wade, one of the two functions of wade/rx, is a write address enable input. in the write address reset cycle, defined by wr/tr high, x address (or line address) input from wxad is latched into internal write x address register synchronously with wclk. wxad : write x address wxad is a write x address (or line address) input. wxad specifies line address. 9 bits of write x address data are input serially from wxad. ie : input enable ie is an input enable which controls the write operation. when ie is high, the input operation is enabled. when ie is low, the write operation is masked. when we signal is high, and ie low, the internal serial write address pointer is incremented on the rising edge of wclk without actual write operations. this function facilitates picture in picture function in a tv system.
? semiconductor MSM548332 7/23 operation mode write 1. write operation before the write operation begins, x address (or line address) must be input to set the initial bit address for the following serial write access. when we and ie are high, a set of serial 12- bit -width write data on din0-11 is written into write registers attached to the dram memory arrays temporarily on the rising edge of wclk. following 12-bit-width serial input data is written into the memory locations in the write register designated by an internal write address pointer which is advanced by wclk. this enables continuous serial write on a line. when write clock wclk and read clock rclk are tied together and are controlled by a common clock or clk, more than two MSM548332s can be cascaded directly without any delay devices between the MSM548332s because the read timing is delayed by one clk cycle to the write timing. when the write operation on a line is terminated, be sure to perform a write transfer operation by wr/tr in order to store the written data in the write registers to the corresponding memory cells in the dram memory arrays. 2. write address pointer increment operation the write address pointer is incremented synchronously with wclk when we is high. we h h l ie h l wclk rise internal write address pointer data input incremented inputted not inputted stopped relationship between the we and ie input levels, write address pointer, and data input status when we and ie are high, the write operation is enabled. if ie level goes low while wclk is active, the write operation is halted but the write address pointer will continue to advance. that is, ie enables a write mask function. when we goes low, the write address pointer stops without wclk. read 1. read operation before the read operation begins, the x address (or line address) must be input for setting initial bit address for the following serial read access. when both re and oe are high, a set of serial 12-bit-width read data on do0-11 pins is read from read registers attached to dram memory arrays on the rising edge of rclk. each access time is specified by the rising edges of rclk.
? semiconductor MSM548332 8/23 2. read address pointer increment operation the read address pointer is incremented synchronized with rclk when oe level is high. re h h l oe h l h rclk rise internal read address pointer data output incremented outputted outputted stopped relationship between the re and oe input levels, read address pointer, and data output status l l hi-z hi-z when each read address pointer reaches the last address of a line, it stops at the last address and no address increment occurs. initial address setting (write/read independent) any read operations are prohibited in the read initial address set period. similarly, any write operations are prohibited in the write initial address set period. note that read initial address set and write initial address set can occur independently. similarly, read access can be achieved independently from write initial address set period and write access can be achieved independently from read initial address set cycles. 1. write address setting wade/rx enables initial read address inputs. when wade/rx is high, 9 bits of serial x address (or line address) are input from wxad. the operations above enable selection of specific lines randomly and enables the start of serial write access synchronized with write clock wclk. address for each line must be input between each line access. in other words, MSM548332's write is achieved in a "line by line" manner. any write operations are prohibited in the initial write address set periods. serial write input enable time t swe must be kept for starting a serial write just after the initial write address set period. 2. read address setting rade/rx enables initial read address inputs. when rade/rx is high, 9 bits of serial x address (or line address) are input from rxad. the operations above enable selection of specific lines randomly and enables the start of serial read access synchronized with read clocks, rclk. address for each line must be input between each line access. in other words, MSM548332's read operation is achieved in "line by line" manner. any read operations are prohibited in the initial read address set periods. serial read operations are prohibited while rade/rx is high. serial read port enable time t sre must be kept for starting a serial read just after the initial read address set period. initial address reset modes (write/read independent) the initial address reset modes replace complicated read or write initial address settings with simple reset cycles. initial address reset modes are selected by rr high during read and wr/tr high during write. as in normal read or write address settings, any read operations are prohibited in the read address reset cycles. similarly, any write operations are prohibited in the initial write address reset cycles. note that read initial address reset and write initial address reset can occur independently. similarly, read access can be achieved independently from write initial address reset cycles and write
? semiconductor MSM548332 9/23 access can be achieved independently from read initial address reset cycles. input addresses are stored into address registers which are connected with address counter which controls address pointer operation. in the serial access operation, the input address into the address registers are kept. serial write data input enable time t swe and serial read port read enable time t sre must be kept for starting serial read or write just after the initial read or write address reset cycles. refer to the "function table" shown later. 1. line hold operation (read only) by the "line hold operation" logic which is composed by a combination of control inputs' level, access is executed starting from the first word on the current line. 2. original address reset operation by the "original address reset" logic, the address counter is reset to (0,0). after the reset mode, serial access starts from the address (0,0) . the address counter is reset by this reset mode but the address register, which stored input address in the previous address reset cycle or address set cycle, is not reset. the non-initialized address can be used as a preset address in "address jump reset" mode. 3. line increment operation by the "line increment operation" logic, the x address counter is incremented by one from the current x address. that is, serial access from the y = (0) on the next line is enabled. 4. address jump operation by the "address jump operation" logic, a jump may be caused to the initialized line address. note : during one reset setting cycle, a plurality of resets cannot be set. power on power must be applied to rclk, re, oe, wclk, we and ie input signals to pull them "low" before or when the v cc supply is turned on. after power-up, the device is designed to begin proper operation in at least 200 m s after v cc has reached the specified voltage. after 200 m s, a minimum of one line dummy write operation and read operation is required according to the address setting mode, because the read and write address pointers are not valid after power-up. new data read access in order to read out "new data', the delay between the beginning of a write address setting cycle and read address setting cycle must be at least two lines. old data read access in order to read out "old data", the delay between the beginning of a write address setting cycle and read address setting cycle must be more than 0 but less than a half line.
? semiconductor MSM548332 10/23 function table 1. write mode no. description of operation wr/tr wxinc wade/rx internal address pointer 1 write transfer h l l 2 reset h l h 4 address jump h h h first address setting l l h x address cleared to (0, 0) x address jump to (xi, 0) 3 line increment h h l x address increment to (xn + 1, 0) address reset mode address setting mode x address set note : for write, line hold is not provided. 2. read mode no. description of operation rr rxinc rade/rx internal address pointer 1 line hold h l l 2 reset h l h 3 line increment h h l 4 adress jump h h h first address setting l l h x address cleared to (0, 0) x address increment to (xn + 1, 0) address reset mode x address jump to (xi, 0) address setting mode x address set x address holde to (xn, 0)
? semiconductor MSM548332 11/23 electrical characteristics absolute maximum ratings recommended operating conditions dc characteristics capacitance parameter symbol condition rating pin voltage v t ta = 25c, with respect to v ss C0.5 to 4.6 v short circuit output current i os ta = 25c 50 ma power dissipation p d ta = 25c 1 w operating temperature t opr 0 to 70c storage temperature t stg C55 to 150c parameter symbol min. power supply voltage v cc 3.0 power supply voltage v ss 0 "h" input voltage v ih 2.1 "l" input voltage v il C0.5 typ. 3.3 0 v cc 0 max. 3.6 0 v cc + 0.3 0.8 unit v v v v (ta = 0 to 70c) parameter symbol condition "h" output voltage v oh i oh = C0.1 ma "l" output voltage v ol i ol = 0.1 ma input leakage current i li 0 < v i < v cc output leakage current i lo 0 < v o < v cc min. 2.2 C10 C10 unit v v m a m a power supply current i cc1 min. cycle ma power supply voltage i cc2 input pin = v il /v ih ma max. 0.6 10 10 50 10 (v cc = 3.0 to 3.6 v, ta = 0 to 70c) other input voltage 0 v (during operation) (during standby) 75 -50 -30 parameter symbol input capacitance c i output capacitance c o max. 7 7 unit pf pf (ta = 25c, f = 1 mhz)
? semiconductor MSM548332 12/23 ac characteristics (1/2) unit ns symbol t wclk parameter wclk cycle time ns t wwclh wclk "h" pulse width ns t wwcll wclk "l" pulse width ns t was serial write address input active setup time ns t wah serial write address input active hold time ns t wadh serial write address input inactive hold time ns t wads serial write address input inactive setup time ns t wtrs write transfer instruction setup time ns t wtrh write transfer instruction hold time ns t wtdh write transfer instruction inactive hold time ns t wtds write transfer instruction inactive setup time ns t wxas serial write x address setup time ns t wxah serial write x address hold time ns t swe serial write data input enable time ns t wes write instruction setup time ns t weh write instruction hold time ns t wedh write instruction inactive hold time ns t weds write instruction inactive setup time ns t ds input data setup time ns t dh input data hold time ns t wrs wr/tr-wclk active setup time ns t wrh wr/tr-wclk active hold time ns t wrdh wr/tr-wclk inactive hold time ns t wrds wr/tr-wclk inactive setup time ns t wins wxinc-wclk active setup time ns t winh wxinc-wclk active hold time ns t windh wxinc-wclk inactive hold time ns t winds wxinc-wclk inactive setup time ns t wrxs wade/rx-wclk active setup time ns t wrxh wade/rx-wclk active hold time ns t wrxdh wade/rx-wclk inactive hold time ns t wrxds wade/rx-wclk inactive setup time measurement conditions: (v cc = 3.3 v 0.3 v, ta = 0 to 70c) ns t ies ie enable setup time ns t ieh ie enable hold time ns t ieds ie disable setup time ns max. min. 30 13 13 5 7 7 7 5 7 7 7 5 7 3000 5 7 7 7 5 12 5 7 7 7 5 7 7 7 5 7 7 7 5 7 7 7 t iedh ie disable hold time MSM548332-30 MSM548332-50 max. min. 50 23 23 5 7 7 7 5 7 7 7 5 7 3000 5 7 7 7 5 12 5 7 7 7 5 7 7 7 5 7 7 7 5 7 7 7
? semiconductor MSM548332 13/23 ac characteristics (2/2) rclk cycle time rclk "h" pulse width rclk "l" pulse width ns t rclk rr-rclk active setup time ns t wrclh rr-rclk active hold time ns t wrcll rr-rclk inactive hold time ns t rrs rr-rclk inactive setup time ns t rrh rxinc-rclk active setup time ns t rrdh rxinc-rclk active hold time ns t rrds rxinc-rclk inactive hold time ns t rins rxinc-rclk inactive setup time ns t rinh rade/rx-rclk active setup time ns t rindh rade/rx-rclk active hold time ns t rinds rade/rx-rclk inactive setup time ns t rrxs rade/rx-rclk inactive hold time ns t rrxh ns t rrxds re enable setup time ns t rrxdh re enable hold time re disable hold time re disable setup time read port read enable time read port read data hold time ns t res access time from rclk ns t reh ns t redh ns t reds ns t sre ns t oh ns t ac read data hold time from oe access time from oe ns t ddoe ns t deoe transition time (rise and fall) ns t t unit symbol parameter measurement conditions: (v cc = 3.3 v 0.3 v, ta = 0 to 70c) MSM548332-30 MSM548332-50 t ras ns t rah ns t radh ns ns t rads ns t rxas ns 30 20 30 max. 30 13 13 5 7 7 7 5 7 7 7 5 7 7 7 5 7 7 7 3000 12 2 2 min. 5 7 7 7 5 7 t rxah serial read address input active setup time serial read address input active hold time serial read address input inactive hold time serial read address input inactive setup time serial read x address setup time serial read x address hold time max. 40 30 30 min. 50 23 23 5 7 7 7 5 7 7 7 5 7 7 7 5 7 7 7 3000 12 2 2 5 7 7 7 5 7 note : measurement conditions input pulse level : v ih = 2.1 v, v il = 0.8 v input timing reference level : v ih = 2.1 v, v il = 0.8 v output timing reference level : v oh = 2.2 v, v ol = 0.6 v input rise/fall time : 2 ns load condition : cl = 30 pf (oscilloscope and tool capacity included)
? semiconductor MSM548332 14/23 timing waveform write cycle (address setting cycle) wclk t wclk t wwcll t wwclh t wadh t was t wah t wads valid a7 valid a1 valid a0 valid a8 valid valid low low t wxas t wxah t wedh t wes t iedh t ies wade/rx wxad we ie wr/tr wxinc din0 - 11 t ds t dh t ds t dh t swe \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ t wxah t wxas t wxah t wxas t wxah t wxas
? semiconductor MSM548332 15/23 write cycle (we control) write cycle (ie control) note : in the we =" l" cycle, the write address pointer is not incremented and no din data is written. wclk t wclk n cycle (n-1)cycle (n-2)cycle (n+2) cycle (n+1) cycle low wade/rx \ \ ie t weh t wedh t weds t wes \ \ \ \ wxinc \ \ we \ \ din0 - 11 \ \ high low wr/tr \ \ low valid d(n+2) valid d(n+1) valid d(n) valid d(n-1) valid d(n-2) valid d(n-3) wclk low wade/rx \ \ we t ieh t ieds t iedh t ies \ \ \ \ wxinc \ \ ie \ \ din0 - 11 \ \ high low wr/tr \ \ low valid d(n+3) valid d(n+2) valid d(n) valid d(n-1) valid d(n-2) valid d(n-3) t wclk n cycle (n-1)cycle (n-2)cycle (n+3) cycle (n+2) cycle note : in the ie = "l" cycle, the write address pointer is incremented, though no din data is written and the memory data is held.
? semiconductor MSM548332 16/23 write cycle (write transfer) wclk t wclk n cycle (n-1)cycle (n-2)cycle t wtdh t wtrs t wtrh t wtds low wade/rx \ \ wr/tr t weh t weds \ \ \ \ wxinc \ \ we \ \ din0 - 11 \ \ low valid d(n) valid d(n-1) valid d(n-2) valid d(n-3) note : when finishing the write operation on a line, be sure to perform a write transfer operation because the write data on the line is stored in the memory cell.
? semiconductor MSM548332 17/23 read cycle (address setting cycle) rclk t rclk t wrcll t wrclh t radh t ras t rah t rads valid b7 valid b1 valid b0 valid b8 valid valid low low high-z t rxas t rxah t redh t res rade/rx rxad re rr rxinc do0 - 11 t ac t oh t sre \ \ \ \ \ \ \ \ \ \ \ \ \ \ t rxah t rxas t rxah t rxas t rxah t rxas
? semiconductor MSM548332 18/23 read cycle (re control) note : in the cycle of oe = "l", the read address pointer is incremented and the output enters the high impedance state. \ \ \ \ \ \ \ \ \ \ t oh valid d(n+2) high-z t deoe t ac valid d(n+3) valid d(n-1) valid d(n) valid d(n-3) valid d(n-2) t ddoe \ \ \ \ t rclk n cycle (n-1)cycle (n-2)cycle (n+3) cycle (n+2) cycle low low low high rclk rade/rx rr rxinc oe do0 - 11 re rclk t rclk n cycle (n-1)cycle (n-2)cycle (n+2) cycle (n+1) cycle low rade/rx \ \ rr t reh t reds t redh t res valid d(n+1) t ac \ \ \ \ rxinc \ \ re \ \ do0 - 11 \ \ oe \ \ low low valid d(n+2) valid d(n-1) valid d(n) valid d(n-3) valid d(n-2) t oh high note : in the cycle of re = "l", the read address pointer is not incremented and the data at the address is output continuously. read cycle (oe control)
? semiconductor MSM548332 19/23 write reset mode write line increment mode note : both the line address and word address are reset to 0. wclk t wclk t wwcll t wwclh \ \ wxinc \ \ din0 - 11 \ \ valid valid t ds t dh t ds t dh low we \ \ wade/rx t wrxs t wrxh t wrdh t wrs t wrh t wrds \ \ wr/tr \ \ t wrxdh t wrxds t swe t wedh t wes wclk t wclk t wwcll t wwclh \ \ wade/rx \ \ din0 - 11 \ \ valid valid t ds t dh we \ \ wr/tr t wrs t wrh t wins t winh \ \ wxinc \ \ t wrdh t wrds t swe t wedh t wes t windh t winds t ds t dh note : the line address is incremented by 1 and the word address is reset to 0.
? semiconductor MSM548332 20/23 write address jump mode note : the line address is reset to the initialized addresses and the word address is reset to 0. wclk t wclk t wwcll t wwclh \ \ din0 - 11 \ \ valid valid t ds t dh we \ \ wade/rx t wrxs t wrxh t wins t winh \ \ wxinc \ \ t wrxdh t wrxds wr/tr t wrs t wrh \ \ t wrdh t wrds t windh t winds t swe t wedh t wes t ds t dh
? semiconductor MSM548332 21/23 read line hold mode rclk t rclk t wrcll t wrclh \ \ rxinc \ \ do0 - 11 \ \ valid valid t ac t oh low re \ \ t rrdh t rrs t rrh t rrds rr \ \ t sre t redh t res oe \ \ high rade/rx \ \ low note : the line address is held and the word address is reset to 0. rclk t rclk t wrcll t wrclh \ \ rxinc \ \ do0 - 11 \ \ valid valid t ac t oh low re \ \ rade/rx t rrxs t rrxh t rrdh t rrs t rrh t rrds \ \ rr \ \ t rrxdh t rrxds t sre t redh t res oe \ \ high read reset mode note : both the line address and word address are reset to 0.
? semiconductor MSM548332 22/23 read line increment mode rclk t rclk t wrcll t wrclh \ \ rxinc \ \ do0 - 11 \ \ valid valid t ac t oh low re \ \ rade/rx t rrs t rrh t rindh t rins t rinh t rinds \ \ rr \ \ t rrdh t rrds t sre t redh t res oe \ \ high note : the line address is incremented by 1 and the word address is reset to 0. note : the line address is reset to the initialized addresses and the word address is reset to 0. rclk t rclk t wrcll t wrclh \ \ rxinc \ \ do0 - 11 \ \ valid valid t ac t oh re \ \ rade/rx t rrs t rrh t rindh t rins t rinh t rinds \ \ rr \ \ t rrdh t sre t redh t res oe \ \ high t rrds t rrxs t rrxh t rrxdh t rrxds read address jump mode
? semiconductor MSM548332 23/23 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.54 typ. tsop ii 44-p-400-0.80-k mirror finish

▲Up To Search▲

Price & Availability of MSM548332

	To Download MSM548332 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .