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www.irf.com 1 03/11/04 IRF3704ZCSPBF irf3704zclpbf hexfet power mosfet notes through are on page 11 applications benefits low r ds(on) at 4.5v v gs ultra-low gate impedance fully characterized avalanche voltage and current high frequency synchronous buck converters for computer processor power lead-free d 2 pak IRF3704ZCSPBF to-262 irf3704zclpbf v dss r ds(on) max qg 20v 7.9m 8.7nc absolute maximum ratings parameter units v ds drain-to-source voltage v v gs gate-to-source voltage i d @ t c = 25c continuous drain current, v gs @ 10v a i d @ t c = 100c continuous drain current, v gs @ 10v i dm pulsed drain current p d @t c = 25c maximum power dissipation w p d @t c = 100c maximum power dissipation linear derating factor w/c t j operating junction and c t stg storage temperature range soldering temperature, for 10 seconds thermal resistance parameter typ. max. units r jc junction-to-case ??? 2.65 c/w r ja junction-to-ambient (pcb mount) ??? 40 57 0.38 28 max. 67 47 260 20 20 300 (1.6mm from case) -55 to + 175

2 www.irf.com s d g static @ t j = 25c (unless otherwise specified) parameter min. typ. max. units bv dss drain-to-source breakdown voltage 20 ??? ??? v ? v dss / ? t j breakdown voltage temp. coefficient ??? 0.014 ??? v/c r ds(on) static drain-to-source on-resistance ??? 6.3 7.9 m ? ??? 8.9 11.1 v gs(th) gate threshold voltage 1.65 2.1 2.55 v ? v gs(th) / ? t j gate threshold voltage coefficient ??? -5.6 ??? mv/c i dss drain-to-source leakage current ??? ??? 1.0 a ??? ??? 150 i gss gate-to-source forward leakage ??? ??? 100 na gate-to-source reverse leakage ??? ??? -100 gfs forward transconductance 48 ??? ??? s q g total gate charge ??? 8.7 13 q gs1 pre-vth gate-to-source charge ??? 2.9 ??? q gs2 post-vth gate-to-source charge ??? 1.1 ??? nc q gd gate-to-drain charge ??? 2.3 ??? q godr gate charge overdrive ??? 2.4 ??? see fig. 16 q sw switch charge (q gs2 + q gd ) ??? 3.4 ??? q oss output charge ??? 5.6 ??? nc t d(on) turn-on delay time ??? 8.9 ??? t r rise time ??? 38 ??? t d(off) turn-off delay time ??? 11 ??? ns t f fall time ??? 4.2 ??? c iss input capacitance ??? 1220 ??? c oss output capacitance ??? 390 ??? pf c rss reverse transfer capacitance ??? 190 ??? avalanche characteristics parameter units e as single pulse avalanche energy mj i ar avalanche current a e ar repetitive avalanche energy mj diode characteristics parameter min. typ. max. units i s continuous source current ??? ??? 67 (body diode) a i sm pulsed source current ??? ??? 260 (body diode) v sd diode forward voltage ??? ??? 1.0 v t rr reverse recovery time ??? 11 17 ns q rr reverse recovery charge ??? 2.3 3.5 nc mosfet symbol v gs = 4.5v, i d = 17a ??? v gs = 4.5v typ. ??? ??? i d = 17a v gs = 0v v ds = 10v t j = 25c, i f = 17a, v dd = 10v di/dt = 100a/s t j = 25c, i s = 17a, v gs = 0v showing the integral reverse p-n junction diode. v ds = v gs , i d = 250a v ds = 16v, v gs = 0v v ds = 16v, v gs = 0v, t j = 125c clamped inductive load v ds = 10v, i d = 17a v ds = 10v, v gs = 0v v dd = 10v, v gs = 4.5v i d = 17a v ds = 10v conditions v gs = 0v, i d = 250a reference to 25c, i d = 1ma v gs = 10v, i d = 21a v gs = 20v v gs = -20v conditions 5.7 max. 36 17 ? = 1.0mhz

www.irf.com 3 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 0.1 1 10 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 60s pulse width tj = 25c 3.0v vgs top 10v 9.0v 7.0v 5.0v 4.5v 4.0v 3.5v bottom 3.0v 0.1 1 10 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 60s pulse width tj = 175c 3.0v vgs top 10v 9.0v 7.0v 5.0v 4.5v 4.0v 3.5v bottom 3.0v 3.0 4.0 5.0 6.0 7.0 8.0 v gs , gate-to-source voltage (v) 10.0 100.0 1000.0 i d , d r a i n - t o - s o u r c e c u r r e n t ( ) v ds = 10v 60s pulse width t j = 25c t j = 175c -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.5 1.0 1.5 2.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 42a v gs = 10v

4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 v ds , drain-to-source voltage (v) 100 1000 10000 c , c a p a c i t a n c e ( p f ) coss crss ciss v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 0 5 10 15 20 25 q g total gate charge (nc) 0 2 4 6 8 10 12 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 16v vds= 10v i d = 17a 0.0 0.5 1.0 1.5 2.0 v sd , source-todrain voltage (v) 0.1 1.0 10.0 100.0 1000.0 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v 0 1 10 100 v ds , drain-tosource voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) tc = 25c tj = 175c single pulse 1msec 10msec operation in this area limited by r ds (on) 100sec

www.irf.com 5 fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature fig 10. threshold voltage vs. temperature 25 50 75 100 125 150 175 t c , case temperature (c) 0 10 20 30 40 50 60 70 i d , d r a i n c u r r e n t ( a ) limited by package -75 -50 -25 0 25 50 75 100 125 150 175 200 t j , temperature ( c ) 0.6 1.0 1.4 1.8 2.2 2.6 v g s ( t h ) g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250a 1e-006 1e-005 0.0001 0.001 0.01 t 1 , rectangular pulse duration (sec) 0.001 0.01 0.1 1 10 t h e r m a l r e s p o n s e ( z t h j c ) 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc ri (c/w) i (sec) 0.920 0.000139 0.194 0.000602 0.538 0.001567 j j 1 1 2 2 3 3 r 1 r 1 r 2 r 2 r 3 r 3 c ci= i / ri ci= i / ri

6 www.irf.com d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13. gate charge test circuit fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as fig 12c. maximum avalanche energy vs. drain current r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v v gs fig 14a. switching time test circuit fig 14b. switching time waveforms v gs v ds 90% 10% t d(on) t d(off) t r t f v gs pulse width < 1s duty factor < 0.1% v dd v ds l d d.u.t + - 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 20 40 60 80 100 120 140 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 5.6a 8.5a bottom 17a

www.irf.com 7 fig 15.

for n-channel hexfet power mosfets
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? ? p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period

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8 www.irf.com control fet

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#' p loss = p conduction + p switching + p drive + p output this can be expanded and approximated by; p loss = i rms 2 r ds(on ) () + i q gd i g v in f ? ? ? ? ? ? + i q gs 2 i g v in f ? ? ? ? ? ? + q g v g f () + q oss 2 v in f ? ? ? ? " (

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synchronous fet the power loss equation for q2 is approximated by; p loss = p conduction + p drive + p output * p loss = i rms 2 r ds(on) () + q g v g f () + q oss 2 v in f ? ? ? ? ? + q rr v in f ( ) *dissipated primarily in q1. for the synchronous mosfet q2, r ds(on) is an im- portant characteristic; however, once again the im- portance of gate charge must not be overlooked since it impacts three critical areas. under light load the mosfet must still be turned on and off by the con- trol ic so the gate drive losses become much more significant. secondly, the output charge q oss and re- verse recovery charge q rr both generate losses that are transfered to q1 and increase the dissipation in that device. thirdly, gate charge will impact the mosfets? susceptibility to cdv/dt turn on. the drain of q2 is connected to the switching node of the converter and therefore sees transitions be- tween ground and v in . as q1 turns on and off there is a rate of change of drain voltage dv/dt which is ca- pacitively coupled to the gate of q2 and can induce a voltage spike on the gate that is sufficient to turn the mosfet on, resulting in shoot-through current . the ratio of q gd /q gs1 must be minimized to reduce the potential for cdv/dt turn on. power mosfet selection for non-isolated dc/dc converters figure a: q oss characteristic

www.irf.com 9 n ote: "p " in as s embly line pos ition indicates "l ead-f ree" f 530s t h is is an ir f 530s wit h lot code 8024 as s e mb le d on ww 02, 2000 in t h e as s e mb l y l ine "l " as s e mb l y lot code in t e r nat ional r e ct if ie r logo part number date code ye ar 0 = 2000 we ek 02 line l f 530s a = as s e mb l y s it e code week 02 p = de s ign at e s l e ad -f r e e product (optional) rectifier in t e r n at ion al logo lot code as s e mb l y ye ar 0 = 2000 dat e code part number

dimensions are shown in millimeters (inches)

10 www.irf.com as s e mb l y lot code rectifier international as s e mb l e d on ww 19, 1997 note: "p" in as s embly line position indicates "lead-free" in the assembly line "c" logo t his is an irl3103l l ot code 1789 example: line c dat e code week 19 ye ar 7 = 1997 part number part number logo lot code as s e mb l y international rectifier product (optional) p = designates lead-free a = assembly site code week 19 ye ar 7 = 1997 dat e code or to-262 part marking information to-262 package outline igbt 1- gate 2- collector 3- emitter

www.irf.com 11 data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 03/04
repetitive rating; pulse width limited by max. junction temperature. starting t j = 25c, l = 0.25mh, r g = 25 ? , i as = 17a. pulse width 400s; duty cycle 2%. this is applied to d 2 pak, when mounted on 1" square pcb (fr- 4 or g-10 material). for recommended footprint and soldering techniques refer to application note #an-994. calculated continuous current based on maximum allowable junction temperature. package limitation current is 42a. 3 4 4 trr feed direction 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) trl feed direction 10.90 (.429) 10.70 (.421) 16.10 (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 4.72 (.136) 4.52 (.178) 24.30 (.957) 23.90 (.941) 0.368 (.0145) 0.342 (.0135) 1.60 (.063) 1.50 (.059) 13.50 (.532) 12.80 (.504) 330.00 (14.173) max. 27.40 (1.079) 23.90 (.941) 60.00 (2.362) min. 30.40 (1.197) max. 26.40 (1.039) 24.40 (.961) notes : 1. comforms to eia-418. 2. controlling dimension: millimeter. 3. dimension measured @ hub. 4. includes flange distortion @ outer edge. d 2 pak tape & reel infomation dimensions are shown in millimeters (inches)

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