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mosel vitelic 1 v53c16258h high performance 256k x 16 edo page mode cmos dynamic ram optional self refresh preliminary v53c16258h rev. 3.8 november 1999 high performance 25 30 35 40 45 50 max. ras access time, (t rac ) 25 ns 30 ns 35 ns 40 ns 45 ns 50 ns max. column address access time, (t caa ) 13 ns 16 ns 18 ns 20 ns 22 ns 24 ns min. extended data out mode cycle time, (t pc ) 10 ns 12 ns 14 ns 15 ns 17 ns 19 ns min. read/write cycle time, (t rc ) 45 ns 60 ns 70 ns 75 ns 80 ns 90 ns features n 256k x 16-bit organization n edo page mode for a sustained data rate of 100 mhz n ras access time: 25, 30, 35, 40, 45, 50 ns n dual cas inputs n low power dissipation n read-modify-write, ras -only refresh, cas -before-ras refresh n optional self refresh (v53c16258sh) n refresh interval: 512 cycles/8 ms n available in 40-pin 400 mil soj and 40/44l-pin 400 mil tsop-ii packages n single +5v 10% power supply n ttl interface description the v53c16258h is a high speed 262,144 x 16 bit high performance cmos dynamic random access memory. the v53c16258h offers a combination of unique features including: edo page mode operation for higher sustained bandwidth with page mode cycle times as short as 10ns. all inputs are ttl compatible. input and output capicatance is significantly lowered to increase performance and minimize loading. these features make the v53c16258h ideally suited for a wide variety of high performance computer systems and peripheral applications. device usage chart operating temperature range package outline access time (ns) power temperature mark k t 25 30 35 40 45 50 std. 0 c to 70 c blank ?0 c to +85 c i
2 v53c16258h re v . 3.8 no v ember 1999 mosel vitelic v53c16258h family device pkg ( t rac ) speed pwr. v 5 3 c 2 5 8 25 (25 ns) 30 (30 ns) 35 (35 ns) 40 (40 ns) 45 (45 ns) 50 (50 ns) temp. blank (0 c to 70 c) i ( 40 c to +85 c) blank (normal) k (soj) h (5v) t (tsop-ii) h 16 16258h-01 s (optional standard self refresh) s pin names a 0 ? 8 address inputs ras row address strobe ucas column address strobe/upper byte control lcas column address strobe/lower byte control we write enable oe output enable i/o 1 ?/o 16 data input, output v cc +5v supply v ss 0v supply nc no connect 40-pin soj pin configuration top view 5 6 7 8 9 10 11 12 vcc i/o1 i/o2 i/o3 i/o4 vcc i/o5 i/o6 i/o7 i/o8 nc nc we ras nc a0 a1 a2 a3 vcc 1 2 3 4 16258h-02 39 40 38 37 36 35 34 33 32 31 30 29 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 vss i/o16 i/o15 i/o14 i/o13 vss i/o12 i/o11 i/o10 i/o9 nc lcas ucas oe a8 a7 a6 a5 a4 vss part name self refresh supply voltage package speed v53c16258hkxx no self refresh 5v soj 25/30/35/40/45/50 v53c16258htxx no self refresh 5v tsop 25/30/35/40/45/50 v53c16258shkxx optional standard self refresh (8ms) 5v soj 25/30/35/40/45/50 v53c16258shtxx optional standard self refresh (8ms) 5v tsop 25/30/35/40/45/50 40/44 pin plastic tsop-ii pin configuration top view 5 6 7 8 9 10 vcc i/o1 i/o2 i/o3 i/o4 vcc i/o5 i/o6 i/o7 i/o8 nc nc we ras nc a0 a1 a2 a3 vcc 1 2 3 4 16258h-03 43 44 42 41 40 39 38 37 36 35 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 vss i/o16 i/o15 i/o14 i/o13 vss i/o12 i/o11 i/o10 i/o9 nc lcas ucas oe a8 a7 a6 a5 a4 vss
3 mosel vitelic v53c16258h v53c16258h re v . 3.8 no v ember 1999 absolute maximum ratings* ambient temperature under bias ..................................... ?0 c to +80 c storage temperature (plastic) ..... ?5 c to +125 c voltage relative to v ss ................. ?.0 v to +7.0 v data output current ..................................... 50 ma power dissipation .......................................... 1.0 w *note: operation above absolute maximum ratings can adversely affect device reliability. capacitance* t a = 25 c, v cc = 5 v 10%, v ss = 0 v * note: capacitance is sampled and not 100% tested symbol parameter typ. max. unit c in1 address input 3 4 pf c in2 ras , cas , we , oe 4 5 pf c out data input/output 5 7 pf block diagram a 0 a 1 a 7 a 8 sense amplifiers refresh counter v cc v ss 9 i/o 1 address buffers and predecoders x 0 -x row decoders 512 memory array 256k x 16 column decoders data i/o bus y 0 -y 8 512 x 16 i/o buffer i/o 2 i/o 3 i/o 4 oe clock generator we clock generator cas clock generator ras clock generator oe we lcas ras 8 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 ucas 256k x 16 16258h-04
4 v53c16258h re v . 3.8 no v ember 1999 mosel vitelic v53c16258h dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0 v, unless otherwise specified. symbol parameter access time v53c16258h unit test conditions notes min. typ. max. i li input leakage current (any input pin) ?0 10 m a v ss v in v cc i lo output leakage current (for high-z state) ?0 10 m a v ss v out v cc ras , cas at v ih i cc1 v cc supply current, operating 25 260 ma t rc = t rc (min.) 1, 2 30 200 35 190 40 180 45 100 50 90 i cc2 v cc supply current, ttl standby 2 ma ras , cas at v ih other inputs 3 v ss i cc3 v cc supply current, ras -only refresh 25 260 ma t rc = t rc (min.) 2 30 200 35 190 40 180 45 100 50 90 i cc4 v cc supply current, edo page mode operation 25 200 ma minimum cycle 1, 2 30 140 35 130 40 120 45 90 50 80 i cc5 v cc supply current, standby, output enabled other inputs 3 v ss 2 ma ras = v ih , cas = v il 1 i cc6 v cc supply current, cmos standby 1 ma ras 3 v cc ?0.2 v, cas 3 v cc ?0.2 v, all other inputs 3 v ss i cc7 self refresh current 400 m a cbr cycle with t ras 3 t rass (min.) and cas = v il ; we = v cc ?.2v; a 0 ? 8 and d in = v cc ?.2v v cc supply voltage 4.5 5.0 5.5 v v il input low voltage ? 0.8 v 3 v ih input high voltage 2.4 v cc + 1 v 3 v ol output low voltage 0.4 v i ol = 2 ma v oh output high voltage 2.4 v i oh = ? ma
5 mosel vitelic v53c16258h v53c16258h re v . 3.8 no v ember 1999 ac characteristics t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0v unless otherwise noted ac test conditions, input pulse levels 0 to 3v # symbol parameter 25 (100 mhz) 30 35 40 45 50 unit notes min. max. min. max. min. max. min. max. min. max. min. max. 1 t ras ras pulse width 25 75k 30 75k 35 75k 40 75k 45 75k 50 75k ns 2 t rc read or write cycle time 45 60 70 75 80 90 ns 3 t rp ras precharge time 15 20 25 25 25 30 ns 4 t csh cas hold time 25 30 35 40 45 50 ns 5 t cas cas pulse width 4 5 6 7 8 9 ns 6 t rcd ras to cas delay 10 17 12 20 13 24 15 28 18 32 19 36 ns 4 7 t rcs read command setup time 0 0 0 0 0 0 ns 8 t asr row address setup time 0 0 0 0 0 0 ns 9 t rah row address hold time 4 5 6 7 8 9 ns 10 t asc column address setup time 0 0 0 0 0 0 ns 11 t cah column address hold time 4 5 5 5 6 7 ns 12 t rsh (r) ras hold time (read cycle) 7 9 10 10 10 10 ns 13 t crp cas to ras precharge time 5 5 5 5 5 5 ns 14 t rch read command hold time referenced to cas 0 0 0 0 0 0 ns 5 15 t rrh read command hold time referenced to ras 0 0 0 0 0 0 ns 5 16 t roh ras hold time referenced to oe 4 6 7 8 9 10 ns 17 t oac access time from oe 8 10 11 12 13 14 ns 12 18 t cac access time from cas 8 10 11 12 13 14 ns 6, 7, 14 19 t rac access time from ras 25 30 35 40 45 50 ns 6, 8, 9 20 t caa access time from column address 13 16 18 20 22 24 ns 6, 7, 10 21 t lz oe or cas to low-z output 0 0 0 0 0 0 ns 16 22 t hz oe or cas to high-z output 0 5 0 5 0 6 0 6 0 7 0 8 ns 16 23 t ar column address hold time from ras 19 23 25 30 35 40 ns 24 t rad ras to column address delay time 8 13 9 14 10 17 12 20 13 23 14 26 ns 11 25 t rsh (w) ras or cas hold time in write cycle 7 9 10 10 10 10 ns 26 t cwl write command to cas lead time 5 7 8 10 13 14 ns 27 t wcs write command setup time 0 0 0 0 0 0 ns 12, 13 28 t wch write command hold time 4 5 5 5 6 7 ns
6 v53c16258h re v . 3.8 no v ember 1999 mosel vitelic v53c16258h 29 t wp write pulse width 4 5 5 5 6 7 ns 30 t wcr write command hold time from ras 19 23 25 30 35 40 ns 31 t rwl write command to ras lead time 7 9 10 10 13 14 ns 32 t ds data in setup time 0 0 0 0 0 0 ns 14 33 t dh data in hold time 4 5 5 5 6 7 ns 14 34 t woh write to oe hold time 5 5 5 6 7 8 ns 14 35 t oed oe to data delay time 5 5 5 6 7 8 ns 14 36 t rwc read-modify-write cycle time 67 79 90 95 115 130 ns 37 t rrw read-modify-write cycle ras pulse width 46 53 59 64 80 87 ns 38 t cwd cas to we delay 19 21 23 25 32 34 ns 12 39 t rwd ras to we delay in read- modify-write cycle 36 41 46 51 62 68 ns 12 40 t crw cas pulse width (rmw) 27 31 34 38 50 52 ns 41 t awd col. address to we delay 24 27 29 31 41 42 ns 12 42 t pc edo fast page mode read or write cycle time 10 12 14 15 17 19 ns 43 t cp cas precharge time 3 3 4 5 6 7 ns 44 t car column address to ras setup time 13 16 18 20 22 24 ns 45 t cap access time from column precharge 15 18 20 22 25 27 ns 7 46 t dhr data in hold time referenced to ras 19 23 25 30 35 40 ns 47 t csr cas setup time cas -before- ras refresh 5 7 8 10 10 10 ns 48 t rpc ras to cas precharge time 0 0 0 0 0 0 ns 49 t chr cas hold time cas -before- ras refresh 6 7 8 8 10 10 ns 50 t pcm edo page mode read-modify-write cycle time 35 40 43 47 65 70 ns 51 t coh output hold after cas low 4 5 5 5 5 5 ns 52 t oes oe low to cas high setup time 3 3 3 3 5 5 ns 53 t oeh oe hold time from we during read-modify write cycle 5 5 5 5 10 10 ns # symbol parameter 25 (100 mhz) 30 35 40 45 50 unit notes min. max. min. max. min. max. min. max. min. max. min. max. ac characteristics (cont?)
7 mosel vitelic v53c16258h v53c16258h re v . 3.8 no v ember 1999 notes: 1. i cc is dependent on output loading when the device output is selected. specified i cc (max.) is measured with the output open. 2. i cc is dependent upon the number of address transitions. specified i cc (max.) is measured with a maximum of two transitions per address cycle in edo page mode. 3. specified v il (min.) is steady state operating. during transitions, v il (min.) may undershoot to ?.0 v for a period not to exceed 20 ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v cc . 4. t rcd (max.) is specified for reference only. operation within t rcd (max.) limits insures that t rac (max.) and t caa (max.) can be met. if t rcd is greater than the specified t rcd (max.), the access time is controlled by t caa and t cac . 5. either t rrh or t rch must be satisified for a read cycle to occur. 6. measured with a load equivalent to one ttl input and 50 pf. 7. access time is determined by the longest of t caa , t cac and t cap . 8. assumes that t rad t rad (max.). if t rad is greater than t rad (max.), t rac will increase by the amount that t rad exceeds t rad (max.). 9. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), t rac will increase by the amount that t rcd exceeds t rcd (max.). 10. assumes that t rad 3 t rad (max.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t caa and t cac . 12. t wcs , t rwd , t awd and t cwd are not restrictive operating parameters. 13. t wcs (min.) must be satisfied in an early write cycle. 14. t ds and t dh are referenced to the latter occurrence of cas or we . 15. t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 3 ns. 16. assumes a three-state test load (5 pf and a 500 ohm thevenin equivalent). 17. an initial 200 m s pause and 8 ras -containing cycles are required when exiting an extended period of bias without clocks. an extended period of time without clocks is defined as one that exceeds the specified refresh interval. 18. one cbr refresh or complete set of row refreah cycles must be completed upon exiting self refreah mode. 54 t oep oe high pulse width 4 5 8 10 10 10 ns 55 t t transition time (rise and fall) 1.5 50 1.5 50 1.5 50 1.5 50 1.5 50 1.5 50 ns 15 56 t ref refresh interval (512 cycles) 8 8 8 8 8 8 ms 17 optional self refresh 57 t rass ras pulse width during self refresh 100 100 100 100 100 100 m s 18 58 t rps ras precharge time during self refresh 100 100 100 100 100 100 ns 18 59 t chs cas hold time width during self refresh 100 100 100 100 100 100 ns 18 60 t chd cas low time during self refresh 100 100 100 100 100 100 m s 18 # symbol parameter 25 (100 mhz) 30 35 40 45 50 unit notes min. max. min. max. min. max. min. max. min. max. min. max. ac characteristics (cont?)
8 v53c16258h re v . 3.8 no v ember 1999 mosel vitelic v53c16258h truth table notes: 1. byte write cycles lcas or ucas active. 2. byte read cycles lcas or ucas active. 3. only one of the two cas must be active ( lcas or ucas ). function ras lcas ucas we oe address i/o notes standby h h h x x x high-z read: word l l l h l row/col data out read: lower byte l l h h l row/col lower byte, data-out upper byte, high-z read: upper byte l h l h l row/col lower byte, high-z upper byte, data-out write: word (early-write) l l l l x row/col data-in write: lower byte (early) l l h l x row/col lower byte, data-in upper byte, high-z read: upper byte (early) l h l l x row/col lower byte, high-z upper byte, data-in read-write l l l h ? l l ? h row/col data-out, data-in 1, 2 edo page-mode read l h ? l h ? l h l col data-out 2 edo page-mode write l h ? l h ? l l x col data-in 2 edo page-mode read-write l h ? l h ? l h ? l l ? h col data-out, data-in 1, 2 hidden refresh read l ? h ? l l l h l row/col data-out 2 ras -only refresh l h h x x row high-z cbr refresh h ? l l l x x x high-z 3 self refresh h ? l l h x x x high-z
9 mosel vitelic v53c16258h v53c16258h re v . 3.8 no v ember 1999 waveforms of read cycle waveforms of early write cycle ih v il v ras ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (r)(12) t cas (5) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rad (24) t rah (9) t asr (8) t rcs (7) t rch (14) t rrh (15) t car (44) t caa (20) t cac (18) t t hz (22) t lz (21) ih v il v we oh v ol v i/o 16258h-05 v alid da t a-out address t oes (52) rac (19) column address row address t oac (17) t hz (22) ih v il v oe t roh (16) ucas, lcas ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (w)(25) t cas (5) t rcd (6) t crp (13) t cah (1 1) t t rad (24) t rah (9) t asr (8) t t wcr (30) t rwl (31) t dh (33) t dhr (46) ih v il v ih v il v ih v il v 16258h-06 t t cwl (26) wch (28) t t ds (32) column address v alid da t a-in high-z ras ucas, lcas we oe i/o address t car (44) asc (10) wcs (27) wp (29) row address don? care undefined
10 v53c16258h re v . 3.8 no v ember 1999 mosel vitelic v53c16258h waveforms of oe -controlled write cycle waveforms of read-modify-write cycle ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rah (9) t asr (8) row address column address t woh (34) t dh (33) t oed (35) ih v il v ih v il v ih v il v 16258h-07 v alid da t a-in t ds (32) t rad (24) ras we oe i/o t csh (4) address t car (44) t t cas (5) rsh (w)(12) t wp (29) r wl (31) t cwl (26) t ucas, lcas column address row address v v ih v il v ih v il v t rp (3) t crp (13) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rah (9) t asr (8) wp (29) r wl (31) t oed (35) t ih v il v ih v il v ih v il v 16258h-08 v alid da t a-out t rac (19) t cwl (26) t t rad (24) t acs t t oac (17) t t dh (33) t oeh (53) t ds (32) hz (22) cac (18) t lz (21) v alid da t a-in ih v il v oh ol ras we oe i/o address t r wc (36) t rr w (37) t ar (23) t csh (4) t rsh (w)(25) t cr w (40) t r wd (39) cwd (38) t a wd (41) t t caa (20) ucas, lcas don? care undefined
11 mosel vitelic v53c16258h v53c16258h re v . 3.8 no v ember 1999 waveforms of edo page mode read cycle waveforms of edo page mode write cycle v alid d a t a out v alid d a t a out column address ca c (18) t hz (22) t lz hz (22) hz (22) r o w address column address ih v il v ih v il v rp (3) t ih v il v ih v il v oh v ol v t rah (9) t asr (8) t rcs (7) t rch (14) t csh (4) ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (r)(12) t cas (5) t cah (1 1) t t ar (23) t cas (5) t cas (5) pc (42) t crp (13) t t column address t t car (44) t cah (1 1) t rcs (7) t rcs (7) t rch (14) t o a c (17) t t o a c (17) t caa (20) t rrh (15) lz (21) t ra c (19) t t ca c (18) t oep (54) v alid d a t a out t crp (13) t t ras ucas , lcas we oe i/o address t asc (10) t coh (5) ca c (18) t hz (22) t caa (20) t oes (52) cap (45) t cah (1 1) 16258h-09 r o w add ih v il v ih v il v ih v il v ih v il v t t asr (8) ih v il v cp (43) t asc (10) rcd (6) t rsh (w)(25) column address t cah (1 1) t cas (5) t cas (5) t car (44) t rad (24) t cwl (26) v alid d a t a in t crp (13) t wcs (27) wp (29) t cah (1 1) t asc (10) t cah (1 1) t dh (33) t ds (32) ih v il v column address rah (9) column address t crp (13) t t wch (28) t cwl (26) t wcs (27) wp (29) t wch (28) t t cwl (26) t wcs (27) wp (29) t wch (28) t v alid d a t a in t dh (33) t ds (32) v alid d a t a in t dh (33) t ds (32) t rp (3) t ar (23) ras we oe i/o address open open t r wl (31) t t csh (4) t ras (1) t pc (42) t t cas (5) ucas , lcas 16258h-10 don? care undefined
12 v53c16258h re v . 3.8 no v ember 1999 mosel vitelic v53c16258h waveforms of edo page mode read-write cycle waveforms of ras -only refresh cycle r o w add ih v il v ih v il v rp (3) t ih v il v i/oh v i/ol v t t asr (8) column address ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (w)(25) column address t cah (1 1) t cas (5) t cas (5) t t t crp (13) t cah (1 1) t asc (10) t t cwd (38) t lz (21) ih v il v column address t asc (10) rah (9) t wp (29) t cwl (26) t t cwl (26) t r wl (31) t a wd (41) t caa (20) t t o a c (17) t a wd (41) t o a c (17) in t ca c (18) t oed (35) t ds (32) t dh (33) t lz in out hz (22) t oed (35) ds (32) t dh (33) t t cap (43) t t ca c (18) t caa (20) lz in hz (22) t oed (35) ds (32) t dh (33) t t t ca c (18) t caa (20) cap (43) t t wp (29) t t wp (29) t cwl (26) t car (44) t rad (24) ras we oe i/o address t a wd (41) out ra c (19) t o a c (17) t r wd (39) cah (1 1) pcm (50) t t csh (4) t cas (5) t cwd (38) hz (22) cwd (38) out ucas , lcas oeh (53) t 16258h-11 ih v il v ras ih v il v rp (3) t ih v il v t ras (1) t rc (2) t crp (13) t asr (8) t rah (9) we, oe = don? care no te: address r o w add ucas , lcas 16258h-12 don? care undefined
13 mosel vitelic v53c16258h v53c16258h re v . 3.8 no v ember 1999 waveforms of cas -before- ras refresh counter test cycle waveforms of cas -before- ras refresh cycle ih v il v ih v il v rp (3) t ih v il v t csr (47) t rsh (w)(25) t ras (1) t chr (49) t rcs (7) t wcs (27) t lz (21) ih v il v ih v il v ih v il v t dh (33) t cp (43) t cas (5) t rch (14) t rrh (15) t hz (22) t r w l (31) t cwl (26) t ds (32) ih v il v ih v il v read cycle write cycle t wch (28) i/o address we we i/o d out d in ras oe ucas , lcas 16258h-13 i/o ih v il v ras oh v ol v ih v il v ucas , lcas t ras (1) t rc (2) t cp (43) t hz (22) t csr (47) rp (3) t t rpc (48) t chr (49) rp (3) t no te: we, oe, a 0 ? 8 = don? care 16258h-14 don? care undefined
14 v53c16258h re v . 3.8 no v ember 1999 mosel vitelic v53c16258h waveforms of hidden refresh cycle (read) waveforms of hidden refresh cycle (write) ih v il v oh v ol v rp (3) t ih v il v t asr (8) t crp (13) t rcd (6) t rsh (r)(12) t rcs (7) 16258h-15 t chr (49) t rad (24) t asc (10) t t cah (1 1) row add column address t rrh (15) t oac (17) t lz (21) t hz (22) t hz (22) ih v il v ih v il v ih v il v ras ucas, lcas we oe i/o address v alid da t a rah (9) t caa (20) t cac (18) t rac (19) t ras (1) rp (3) t t ras (1) t ar (23) t crp (13) t rc (2) t rc (2) ih v il v ih v il v rp (3) t ih v il v t ras (1) t rc (2) t asr (8) t crp (13) rp (3) t t rcd (6) t rsh (12) t wcs (27) 16258h-16 t ras (1) t ar (23) t chr (49) t crp (13) t rad (24) t asc (10) t rah (9) t cah (1 1) row add column address t wch (28) t ds (32) ih v il v ih v il v ih v il v v alid da t a-in t dhr (46) t rc (2) ras ucas, lcas we oe i/o address t dh (33) don? care undefined
mosel vitelic v53c16258h 15 v53c16258h re v . 3.8 no v ember 1999 waveforms of edo-page-mode read-early-write cycle (pseudo read-modify-write) waveforms of self refresh cycle ucas , lcas we oe i/o address ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ras v alid d a t a out v alid d a t a out r o w address column address column address column address v alid d a t a in t ras t csh t crp t rcd t cas t cp t cp t cp t cas t cas t pc t ar t rad t asr t rah t rcs t rch t wcs t caa t caa t ra c t ca c t cap t ca c 16258h-17 t coh t ds t dh t oe t wch t cah t asc t cah t asc t cah t asc t car t pc t rsh t rp ih v il v t rp (3) 16258l 05 ih v il v ih v il v t rass (57) t rps (58) t rpc (48) t cp (43) t csr (47) t chd (60) t rpc (48) t open chs (59) ucas, lcas ih v il v address ih v il v oh v ol v i/o ras we oe don? care undefined
16 mosel vitelic v53c16258h v53c16258h re v . 3.8 no v ember 1999 functional description the v53c16258h is a cmos dynamic ram optimized for high data bandwidth, low power applications. it is functionally similar to a traditional dynamic ram. the v53c16258h reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. the row address is latched by the row address strobe ( ras ). the column address ?lows through?an internal address buffer and is latched by the column address strobe ( cas ). because access time is primarily dependent on a valid column address rather than the precise time that the cas edge occurs, the delay time from ras to cas has little effect on the access time. memory cycle a memory cycle is initiated by bringing ras low. any memory cycle, once initiated, must not be ended or aborted before the minimum t ras time has expired. this ensures proper device operation and data integrity. a new cycle must not be initiated until the minimum precharge time t rp /t cp has elapsed. read cycle a read cycle is performed by holding the write enable ( we ) signal high during a ras / cas operation. the column address must be held for a minimum specified by t ar . data out becomes valid only when t oac , t rac , t caa and t cac are all satisifed. as a result, the access time is dependent on the timing relationships between these parameters. for example, the access time is limited by t caa when t rac , t cac and t oac are all satisfied. write cycle a write cycle is performed by taking we and cas low during a ras operation. the column address is latched by cas . the write cycle can be we controlled or cas controlled depending on whether we or cas falls later. consequently, the input data must be valid at or before the falling edge of we or cas , whichever occurs last. in the cas - controlled write cycle, when the leading edge of we occurs prior to the cas low transition, the i/o data pins will be in the high-z state at the beginning of the write function. ending the write with ras or cas will maintain the output in the high-z state. in the we controlled write cycle, oe must be in the high state and t oed must be satisfied. extended data output page mode edo page operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. maintaining ras low while performing successive cas cycles retains the row address internally and eliminates the need to reapply it for each cycle. the column address buffer acts as a transparent or flow-through latch while cas is high. thus, access begins from the occurrence of a valid column address rather than from the falling edge of cas , eliminating t asc and t t from the critical timing path. cas latches the address into the column address buffer. during edo operation, read, write, read-modify-write or read-write-read cycles are possible at random addresses within a row. following the initial entry cycle into hyper page mode, access is t caa or t cap controlled. if the column address is valid prior to the rising edge of cas , the access time is referenced to the cas rising edge and is specified by t cap . if the column address is valid after the rising cas edge, access is timed from the occurrence of a valid address and is specified by t caa . in both cases, the falling edge of cas latches the address and enables the output. edo provides a sustained data rate of 83 mhz for applications that require high bandwidth such as bit- mapped graphics or high-speed signal processing. the following equation can be used to calculate the maximum data rate: self refresh self refresh mode provides internal refresh con- trol signals to the dram during extended periods of inactivity. device operation in this mode provides additional power savings and design ease by elimi- nation of external refresh control signals. self re- fresh mode is initiated with a cas before ras (cbr) refresh cycle, holding both ras low (t rass ) and cas low (t chd ) for a specified period. both of these parameters are specified with minimum val- ues to guarantee entry into self refresh operation. once the device has been placed in to self refresh mode the cas clock is no longer required to main- tain self refresh operation. data rate 512 t r c 511 t p c + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =
mosel vitelic v53c16258h 17 v53c16258h re v . 3.8 no v ember 1999 the self refresh mode is terminated by returning the ras clock to a high level for a specified (t rps ) minimum time. after termination of the self refresh cycle normal accesses to the device may be initiat- ed immediately, providing that subsequent refresh cycles utilize the cas before ras (cbr) mode of operation. data output operation the v53c16258h input/output is controlled by oe , cas , we and ras . a ras low transition enables the transfer of data to and from the selected row address in the memory array. a ras high transition disables data transfer and latches the output data if the output is enabled. after a memory cycle is initiated with a ras low transition, a cas low transition or cas low level enables the internal i/o path. a cas high transition or a cas high level disables the i/o path and the output driver if it is enabled. a cas low transition while ras is high has no effect on the i/o data path or on the output drivers. the output drivers, when otherwise enabled, can be disabled by holding oe high. the oe signal has no effect on any data stored in the output latches. a we low level can also disable the output drivers when cas is low. during a write cycle, if we goes low at a time in relationship to cas that would normally cause the outputs to be active, it is necessary to use oe to disable the output drivers prior to the we low transition to allow data in setup time (t ds ) to be satisfied. power-on after application of the v cc supply, an initial pause of 200 m s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a ras clock). eight initialization cycles are required after extended periods of bias without clocks (greater than the refresh interval). during power-on, the v cc current requirement of the v53c16258h is dependent on the input levels of ras and cas . if ras is low during power-on, the device will go into an active cycle and i cc will exhibit current transients. it is recommended that ras and cas track with v cc or be held at a valid v ih during power-on to avoid current surges. table 1. v53c16258h data output operation for various cycle types cycle type i/o state read cycles data from addressed memory cell cas -controlled write cycle (early write) high-z we -controlled write cycle (late write) oe controlled. high oe = high-z i/os read-modify-write cycles data from addressed memory cell edo read cycle data from addressed memory cell edo write cycle (early write) high-z edo read-modify- write cycle data from addressed memory cell ras -only refresh high-z cas -before- ras refresh cycle data remains as in previous cycle cas -only cycles high-z
18 v53c16258h re v . 3.8 no v ember 1999 mosel vitelic v53c16258h package outlines 40-pin plastic soj 40/44l-pin tsop-ii 1.025 typ . (1.035 max.) [26.04 typ . (26.29 max.)] 0.050 0.006 [1.27 0.152] 0.04 [0.1] 0.026 min [0.660 min] 0.144 max [3.66 max] 0.400 0.005 [10.16 0.127] 0.440 0.005 [11.18 0.127] 40 1 21 20 0.368 0.010 [9.35 0.254] 0.010 unit in inches [mm] 0.025 0.018 +0.004 ?.002 +0.004 ?.002 0.635 +0.102 ?.051 + 0.004 ?0.002 0.254 +0.102 ?.051 0.457 +0.102 ?.051 0.721 ?0.729 [18.31 ?18.52] 0.0315 bsc [.8001 bsc] 40 21 1 20 0.039 ?0.047 [0.991 ?1.193] 0.396 ?0.404 [10.06 ?10.26] 0.462 ?0.470 [11.73 ?11.94] 0.012 ?0.016 [0.305 ?0.406] 0.002 ?0.008 [0.051 ?0.203] 0.0047 ?0.0083 [0.119 .211] 0 ? 0.017 ?0.023 [0.432 ?0.584] base plane sea ting plane unit in inches [mm]
19 mosel vitelic v53c16258h v53c16258h re v . 3.8 no v ember 1999 notes
mosel vitelic w orld wide offices v53c16258h ?cop yr ight 1999, mosel vitelic inc. 11/99 pr inted in u .s .a. mosel vitelic 3910 n. first street, san jose , ca 95134-1501 ph: (408) 433-6000 f ax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u .s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2666-3307 fax: 852-2770-8011 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin rd. science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan wbg marive west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-7125 phone: 81-43-299-6000 fax: 81-43-299-6555 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 01698-748515 fax: 01698-748516 germany (continental europe & israel) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341

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