*rohs directive 2002/95/ec jan 27 2003 including annex october 2005 ?revised may 2007 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp820xhdm overvoltage protectors tisp8200hdm buffered p-gate scr dual tisp8201hdm buffered n-gate scr dual complementary buffered-gate scrs for dual polarity slic overvoltage protection tisp8200hdm 8-soic (210 mil) package (top view) *rohs compliant high performance protection for slics with +ve & -ve battery supplies tisp8200hdm negative overvoltage protector ?wide -20 to -110 v programming range ?low +15 ma max. gate triggering current ?high -150 ma min. holding current tisp8201hdm positive overvoltage protector ?wide +20 to +110 v programming range ?low -15 ma max. gate triggering current ?+20 ma min. holding current rated for international surge wave shapes wave shape standard i ppsm a 2/10 gr-1089-core 500 10/700 itu-t k.20/21/45 150 10/1000 gr-1089-core 100 md-8soic(210)-007-a nc - no internal connection terminal typical application names shown in parenthesis 1 2 3 45 6 7 8 k1 a a k2 g k1 k2 nc (tip) (ground) (ground) (ring) (-v (bat) ) (tip) (ring) tisp8200hdm device symbol sd-tisp8-001-a g k1 k1 k2 k2 a a circuit application diagram tisp8201hdm 8-soic (210 mil) package (top view) md-8soic(210)-008-a nc - no internal connection terminal typical application names shown in parenthesis 1 2 3 45 6 7 8 a1 k k a2 g a1 a2 nc (tip) (ground) (ground) (ring) (+v (bat) ) (tip) (ring) tisp8201hdm device symbol sd-tisp8-002-a g a1 a1 a2 a2 k k - v bat slic protection tisp8201hdm ai-tisp8-002-b tip ring c2 220 nf +v bat c1 220 nf tisp8200hdm ..................................................ul recognized component
october 2005 ?revised may 2007 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp820xhdm overvoltage protectors description the ti s p8200hdm/ti s p8201hdm combination ha s been de s igned to protect dual polarity s upply rail monolithic s lic s ( s ub s criber line interface circuit s ) again s t overvoltage s on the telephone line cau s ed by lightning, a.c. power contact and induction. protection again s t negative overvoltage s i s given by the ti s p8200hdm. protection again s t po s itive overvoltage s i s given by the ti s p8201hdm. both part s are in 8- s oic (210 mil) s urface mount package s . the ti s p8200hdm ha s an array of two buffered p-gate s cr s with a common anode connection. each s cr cathode and gate ha s a s eparate terminal connection. the npn buffer tran s i s tor s reduce the gate s upply current. in u s e, the cathode s of the ti s p8200hdm s cr s are connected to the two conductor s of the pot s line. the gate s are connected to the appropriate negative voltage battery feed of the s lic driving the line conductor pair, s o that the ti s p8200hdm protection voltage track s the s lic negative s upply voltage. the anode of the ti s p8200hdm i s connected to the s lic common. negative overvoltage s are initially clipped clo s e to the s lic negative s upply by emitter follower action of the npn buffer tran s i s tor. if s ufficient clipping current flow s , the s cr will regenerate and s witch into a low voltage on- s tate condition. a s the overvoltage s ub s ide s the high holding current of the s cr helps prevent d.c. latchup. the ti s p8201hdm ha s an array of two buffered n-gate s cr s with a common cathode connection. each s cr anode and gate ha s a s eparate terminal connection. the pnp buffer tran s i s tor s reduce the gate s upply current. in u s e, the anode s of the ti s p8201hdm s cr s are connected to the two conductor s of the pot s line. the gate s are connected to the appropriate po s itive voltage battery feed of the s lic driving that line pair, s o that the ti s p8201hdm protection voltage track s the s lic po s itive s upply voltage. the cathode of the ti s p8201hdm i s connected to the s lic common. po s itive overvoltage s are initially clipped clo s e to the s lic po s itive s upply by emitter follower action of the pnp buffer tran s i s tor. if s ufficient clipping current flow s the s cr will regenerate and s witch into a low voltage on- s tate condition. a s the overvoltage s ub- s ide s the s lic pull s the conductor voltage down to it s normal negative value and thi s commutate s the conducting s cr into a rever s e bia s ed condition. how to order device package carrier order as marking code standard quantity tisp8200hdm 8-soic (210 mil) embossed tape reeled TISP8200HDMR-S 8200h 2000 h 1 0 2 8 s - r m d h 1 0 2 8 p s i t m d h 1 0 2 8 p s i t t i n u e u l a v l o b m y s g n i t a r repetitive pea k off-state voltage, v gk v 0 = drm -120 v repetitive pea k reverse voltage, v ga v v 0 7 - = rrm 120 non-repetitive pea k impulse current (see notes 1, 2 and 3) 2/10 s (telcordia gr-1089-core, 2/10 s voltage wave shape) 5/310 s (itu-t k.44, 10/700 s voltage wave shape used in k.20/21/45) 10/1000 s (telcordia gr-1089-core, 10/1000 s voltage wave shape) i ppsm -500 -150 -100 a non-repetitive pea k on-state current, 50/60 hz (see notes 1, 2, 3 and 4) 10 ms 1 s 7 s 900 s i tsm 60 14 7 3.5 a junction temperature t j -55 to +150 c storage temperature range t stg -65 to +150 c notes: 1. initially the device must be in thermal equilibrium with t j = 25 c. the surge may be repeated after the device returns to its initial conditions. 2. these non-repetitive rated currents are pea k values. the rated current values may be applied to any cathode-anode terminal pair. 3. rated currents only apply if pins 1 & 8 (k1,tip) are connected together, pins 4 & 5 (k2, ring) are connected together and pin s 6 & 7 (a, ground) are connected together. 4. these non-repetitive rated terminal currents are for the tisp8200hdm and tisp8201hdm together. device (a)-terminal positive current values are conducted by the tisp8201hdm and (k)-terminal negative current values by the tisp8200hdm. tisp8200hdm absolute maximum ratings, t a = 25 ? (unless otherwise noted)
october 2005 ?revised may 2007 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp820xhdm overvoltage protectors tisp8201hdm absolute maximum ratings, t a = 25 ? (unless otherwise noted) t i n u e u l a v l o b m y s g n i t a r repetitive pea k off-state voltage, v ga v 0 = drm 120 v repetitive pea k reverse voltage, v gk v v 0 7 = rrm -120 non-repetitive pea k impulse current (see notes 5, 6 and 7) 2/10 s (telcordia gr-1089-core, 2/10 s voltage wave shape) 5/310 s (itu-t k.44, 10/700 s voltage wave shape used in k.20/21/45) 10/1000 s (telcordia gr-1089-core, 10/1000 s voltage wave shape) i ppsm 500 150 100 a non-repetitive pea k on-state current, 50/60 hz (see notes 5, 6, 7 and 8) 10 ms 1 s 7 s 900 s i tsm 60 14 7 3.5 a junction temperature t j -55 to +150 c storage temperature range t stg -65 to +150 c notes: 5. initially the device must be in thermal equilibrium with t j = 25 c. the surge may be repeated after the device returns to its initial conditions. 6. these non-repetitive rated currents are pea k values. the rated current values may be applied to any cathode-anode terminal pair. 7. rated currents only apply if pins 1 & 8 (a1, tip) are connected together, pins 4 & 5 (a2, ring) are connected together and pi ns 6 & 7 (k, ground) are connected together. 8. these non-repetitive rated terminal currents are for the tisp8200hdm and tisp8201hdm together. device (a)-terminal positive current values are conducted by the tisp8201hdm and (k)-terminal ne g ative current values by the tisp8200hdm. t i n u x a m p y t n i m 3 e r u g i f e e s c1, c2 gate decoupling capacitor 220 nf t i d n o c t s e t r e t e m a r a p t i n u x a m p y t n i m s n o i i drm repetitive pea k off-state current v d = v drm , v gk a 5 - 0 = i rrm repetitive pea k reverse current v r = v rrm , v ga a 5 v 0 7 - = v (bo) brea k over voltage dv/dt = -250 v/ms, r source = 300 v ga v 2 8 - v 0 8 - = v (bo) impulse brea k over voltage dv/dt -1000 v/s, linear voltage ramp, maximum ramp value = -500 v di/dt = -20 a/s, linear current ramp, maximum ramp value = -10 a v ga = -80 v -90 v i h holding current (i k ) i t = -1 a, di/dt = 1 a/ms, v ga a m 0 5 1 - v 0 8 - = i gt gate trigger current (i k ) i t = -5 a, t p(g) 20 s, v ga a m 5 1 v 0 8 - = c o off-state capacitance f = 1 mhz, v d = 1 v rms, gate open v d = -2 v 65 pf v d = -50 v 30 recommended operating conditions tisp8200hdm electrical characteristics, t a = 25 ? (unless otherwise noted)
october 2005 ?revised may 2007 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp820xhdm overvoltage protectors tisp8201hdm electrical characteristics, t a = 25 ? (unless otherwise noted) t i d n o c t s e t r e t e m a r a p t i n u x a m p y t n i m s n o i i drm repetitive pea k off-state current v d = v drm , v ga a 5 0 = i rrm repetitive pea k reverse current v r = v rrm , v gk a 5 - v 0 7 = v (bo) brea k over voltage dv/dt = 250 v/ms, r source = 300 v gk v 2 8 v 0 8 = v (bo) impulse brea k over voltage dv/dt 1000 v/s, linear voltage ramp, maximum ramp value = 500 v di/dt = 20 a/s, linear current ramp, maximum ramp value = 10 a v gk = 80 v 90 v i h holding current (i a ) i t = 1 a, di/dt = -1 a/ms, v gk a m 0 2 v 0 8 = i gt gate trigger current (i a ) i t = 5 a, t p(g) 20 s, v gk a m 5 1 - v 0 8 = c o off-state capacitance f = 1 mhz, v d = 1 v rms, gate open v d = 2 v 50 pf v d = 50 v 30 thermal characteristics t i d n o c t s e t r e t e m a r a p t i n u x a m p y t n i m s n o i r ja junction to ambient thermal resistance eia/jesd51-7 pcb, eia/jesd51-2 environment, p tot = 4 w (see note 9) 55 c/w note 9. eia/jesd51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring trac k widths.
october 2005 ?revised may 2007 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp820xhdm overvoltage protectors parameter measurement information figure 2. tisp8201hdm ak terminal characteristic figure 1. tisp8200hdm ka terminal characteristic quadrant i blocking characteristic quadrant iii switching characteristic +v -v v ga v d i h i tsm i ppsm v (bo) i d +i -i v gk(bo) v rrm v r i r i rrm pm8xacba -v v gk v d v (bo) i h i tsm i ppsm i d quadrant iii blocking characteristic +i -i quadrant i switching characteristic v ga(bo) v rrm v r i r i rrm +v pm8xabba
october 2005 ?revised may 2007 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp820xhdm overvoltage protectors applications information figure 4. typical overcurrent protection slic -v bat slic protection tisp8201hdm ai-tisp8-001-b tip ring d3 c2 220 nf +v bat overcurrent protection gr-1089-core overcurrent protection 1 f1b b1250t f1a b1250t fuse (bourns) gr-1089-core overcurrent protection 2 telcordia gr-1089-core issue 3 compliant lfr (custom) c1 220 nf tisp8200hdm 100 k d1 100 k d2 r1 r2 figure 3. typical application circuit
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