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3-217 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc7126 tc7126a 3-1/2 digit analog-to-digital converters features n low temperature drift internal reference tc7126 ....................................... 80 ppm/ c typ tc7126a ..................................... 35 ppm/ c typ n guaranteed zero reading with zero input n low noise .................................................... 15 m v p-p n high resolution .............................................. 0.05% n low input leakage current ...................... 1 pa typ 10 pa max n precision null detectors with true polarity at zero n high-impedance differential input n convenient 9v battery operation with low power dissipation ........................ 500 m w typ 900 m w max typical applications n thermometry n bridge readouts: strain gauges, load cells, null detectors n digital meters and panel meters voltage/current/ohms/power, ph n digital scales, process monitors general description the tc7126a is a 3-1/2 digit cmos analog-to-digital converter (adc) containing all the active components nec- essary to construct a 0.05% resolution measurement sys- tem. seven-segment decoders, digit and polarity drivers, voltage reference, and clock circuit are integrated on-chip. the tc7126a directly drives a liquid crystal display (lcd), and includes a backplane driver. a low-cost, high-resolution indicating meter requires only a display, four resistors, and four capacitors. the tc7126a's extremely low power drain and 9v battery operation make it ideal for portable applications. the tc7126a reduces linearity error to less than 1 count. roll-over error (the difference in readings for equal magnitude but opposite polarity input signals) is below 1 count. high-impedance differential inputs offer 1 pa leak- age current and a 10 12 w input impedance. the 15 m v p-p noise performance guarantees a "rock solid" reading, and the auto-zero cycle guarantees a zero display reading with a 0v input. the tc7126a features a precision, low-drift internal voltage reference and is functionally identical to the tc7126. a low-drift external reference is not normally required with the tc7126a. ordering information part code tc7126x x xxx a or blank* r (reversed pins) or blank (cpl pkg only) * "a" parts have an improved reference tc package code (see below) : package temperature code package range ckw 44-pin pqfp 0 c to +70 c clw 44-pin plcc 0 c to +70 c cpl 40-pin pdip 0 c to +70 c ipl 40-pin pdip (non-a only) C 25 c to +85 c v ref + tc7126 tc7126a 33 34 240 k w 10 k w 31 29 39 38 40 v ref 0.33 ? 0.1 ? v 1 osc 3 osc 2 osc to analog common (pin 32) 1 conversion/sec c osc 560 k w 180 k w 0.15 ? 0.01 f analog input + c ref c ref + v in + v in analog common v int v buff c az 20 21 1 segment drive 2?9 22?5 pol bp v + minus sign backplane 28 50 pf lcd 1 m w 27 30 32 35 36 9v + r osc 26 note: pin numbers refer to 40-pin dip. 40-pin plastic dip 44-pin plastic quad flat package formed leads 44-pin plastic chip carrier plcc available packages typical operating circuit tc7126/a-8 11/6/96
3-218 telcom semiconductor, inc. 3-1/2 digit analog-to-digital converters tc7126 tc7126a absolute maximum ratings* supply voltage (v + to v C )......................................... +15v analog input voltage (either input) (note 1) ........ v + to v C reference input voltage (either input) ................. v + to v C clock input ...................................................... test to v + operating temperature range c devices .............................................. 0 c to +70 c i devices ........................................... C 25 c to +85 c storage temperature range ................ C 65 c to +150 c lead temperature (soldering, 10 sec) ................. +300 c power dissipation, (t a 70 c), (note 2) 44-pin pqfp .................................................... 1.00w 44-pin plcc .....................................................1.23w 40-pin plastic pdip .......................................... 1.23w *static-sensitive device. unused devices must be stored in conductive material. protect devices from static discharge and static fields. stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics: v s = +9v, f clk = 16 khz, and t a = +25 c, unless otherwise noted. symbol parameter test conditions min typ max unit input zero input reading v in = 0v C000.0 000.0 +000.0 digital full scale = 200 mv reading zero reading drift v in = 0v, 0 c t a +70 c 0.2 1 m v/ c ratiometric reading v in = v ref , v ref = 100 mv 999 999/1000 1000 digital reading nl linearity error full scale = 200 mv or 2v C 1 0.2 1 count max deviation from best fit straight line roll-over error Cv in = +v in ? 200 mv C 1 0.2 1 count e n noise v in = 0v, full scale = 200 mv 15 m v p-p i l input leakage current v in = 0v 1 10 pa cmrr common-mode rejection v cm = 1v, v in = 0v, 50 m v/v ratio full scale = 200 mv scale factor temperature v in = 199 mv, 0 c t a +70 c 1 5 ppm/ c coefficient ext ref temp coeff = 0 ppm/ c analog common v ctc analog common 250 k w between common and v + temperature coefficient 0 c t a +70 c ("c" devices): tc7126 80 ppm/ c tc7126a 35 75 ppm/ c C 25 c t a +85 c ("i" device): tc7126a 35 100 ppm/ c v c analog common voltage 250 k w between common and v + 2.7 3.05 3.35 v lcd drive v sd lcd segment drive voltage v + to v C = 9v 4 5 6 v p-p v bd lcd backplane drive voltage v + to v C = 9v 4 5 6 v p-p power supply i s power supply current v in = 0v, v + to v C = 9v (note 6) 55 100 m a notes: 1. input voltage may exceed supply voltages when input current is limited to 100 m a. 2. dissipation rating assumes device is mounted with all leads soldered to pc board. 3. refer to "differential input" discussion. 4. backplane drive is in-phase with segment drive for "off" segment and 180 out-of-phase for "on" segment. frequency is 20 times conversion rate. average dc component is less than 50 mv. 5. see "typical operating circuit." 6. during auto-zero phase, current is 10C20 m a higher. a 48 khz oscillator increases current by 8 m a (typical). common current not included.
3-219 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 3-1/2 digit analog-to-digital converters tc7126 tc7126a pin configurations 27 28 29 30 31 32 33 7 4 3 2 1 nc tc7126ckw tc7126ackw (flat package) 12 13 14 15 17 18 g 44 43 42 41 39 38 40 common 16 37 c az 36 v buff 35 v int 34 v 19 20 21 22 d 26 8 + 25 9 24 10 23 11 5 6 c osc test nc nc v 3 3 d 2 c 2 b 2 a 2 f 2 e 2 nc osc 2 osc 1 ref c ref c 2 3 a 3 g 3 bp pol ab 4 e 3 f 3 b 3 33 34 35 36 37 38 39 13 10 9 8 7 common v ref 18 19 20 21 23 24 3 ab 4 pol nc bp nc b 6543 144 2 a osc 22 43 osc 42 osc 41 test 40 25 26 27 28 f e g a c g 32 14 c az 2 31 15 v buff 2 30 16 v int e 29 17 d nc 11 12 nc c d 3 2 f a 2 2 2 b 3 3 3 3 3 2 tc7126clw tc7126aclw (plcc) 1 2 3 v 1 b 1 c 1 d 1 v + f 1 g 1 e 1 d 1 c 1 b 1 a 1 f 1 g 1 e 1 + ref c ref c + + v in v in v ref + v ref + v ref + v in v in tc7126cpl tc7126acpl TC7126IPL tc7126aipl 1 2 3 4 osc 1 5 6 7 8 9 10 11 12 test v analog common c az v + d normal pin configuration 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2 c 2 b 2 a 2 f 2 e 2 d 3 b 3 f 3 e 3 ab 4 10's 100's 1000's 100's osc 2 osc 3 + ref v ref c + ref c ref v + in v in v buff v int v g c a g bp (backplane) pol (minus sign) 3 3 3 2 tc7126rcpl tc7126arcpl tc7126ripl tc7126aripl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 100's 1000's 100's reverse pin configuration 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 d 1 c 1 b 1 a 1 f 1 g 1 e 1 1's v + d 2 c 2 b 2 a 2 f 2 e 2 d 3 b 3 f 3 e 3 ab 4 pol (minus sign) d 1 c 1 b 1 a 1 f 1 g 1 e 1 1's 10's osc test v analog common c az osc 2 osc + ref v ref c + ref c ref v + in v in v buff v int v g c a g bp (backplane) 3 3 3 2 3 1 nc = no internal connection
3-220 telcom semiconductor, inc. 3-1/2 digit analog-to-digital converters tc7126 tc7126a pin description 40-pin pdip pin number normal (reverse) name description 1 (40) v + positive supply voltage. 2 (39) d 1 activates the d section of the units display. 3 (38) c 1 activates the c section of the units display. 4 (37) b 1 activates the b section of the units display. 5 (36) a 1 activates the a section of the units display. 6 (35) f 1 activates the f section of the units display. 7 (34) g 1 activates the g section of the units display. 8 (33) e 1 activates the e section of the units display. 9 (32) d 2 activates the d section of the tens display. 10 (31) c 2 activates the c section of the tens display. 11 (30) b 2 activates the b section of the tens display. 12 (29) a 2 activates the a section of the tens display. 13 (28) f 2 activates the f section of the tens display. 14 (27) e 2 activates the e section of the tens display. 15 (26) d 3 activates the d section of the hundreds display. 16 (25) b 3 activates the b section of the hundreds display. 17 (24) f 3 activates the f section of the hundreds display. 18 (23) e 3 activates the e section of the hundreds display. 19 (22) ab 4 activates both halves of the 1 in the thousands display. 20 (21) pol activates the negative polarity display. 21 (20) bp backplane drive output. 22 (19) g 3 activates the g section of the hundreds display. 23 (18) a 3 activates the a section of the hundreds display. 24 (17) c 3 activates the c section of the hundreds display. 25 (16) g 2 activates the g section of the tens display. 26 (15) v C negative power supply voltage. 27 (14) v int the integrating capacitor should be selected to give the maximum voltage swing that ensures component tolerance build-up will not allow the integrator output to saturate. when analog common is used as a reference and the conversion rate is 3 readings per second, a 0.047 m f capacitor may be used. the capacitor must have a low dielectric constant to prevent roll-over errors. see "integrating capaci- tor" section for additional details. 28 (13) v buff integration resistor connection. use a 180 k w resistor for a 200 mv full-scale range and a 1.8 m w resistor for a 2v full-scale range. 29 (12) c az the size of the auto-zero capacitor influences system noise. use a 0.33 m f capacitor for 200 mv full scale, and a 0.033 m f capacitor for 2v full scale. see paragraph on auto-zero capacitor for more details. 30 (11) v in C the low input signal is connected to this pin. 31 (10) v in + the high input signal is connected to this pin. 32 (9) analog this pin is primarily used to set the analog common-mode voltage for battery operation or in systems where the input signal is referenced to the power supply. see paragraph on analog common for more details. it also acts as a reference voltage source. 33 (8) c ref C see pin 34. common
3-221 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 3-1/2 digit analog-to-digital converters tc7126 tc7126a pin description (cont.) 40-pin pdip pin number normal (reverse) name description 34 (7) c + ref a 0.1 m f capacitor is used in most applications. if a large common-mode voltage exists (for example, the v in C pin is not at analog common), and a 200 mv scale is used, a 1 m f capacitor is recommended and will hold the roll-over error to 0.5 count. 35 (6) v C ref see pin 36. (5) v + ref the analog input required to generate a full-scale output (1999 counts). place 100 mv between pins 35 and 36 for 199.9 mv full scale. place 1v between pins 35 and 36 for 2v full scale. see paragraph on reference voltage. 36 (4) test lamp test. when pulled high (to v + ), all segments will be turned on and the display should read C1888. it may also be used as a negative supply for exter- nally-generated decimal points. see paragraph under test for additional informa- tion. 37 (3) osc 3 see pin 40. 38 (2) osc 2 see pin 40. 40 (1) osc 1 pins 40, 39 and 38 make up the oscillator section. for a 48 khz clock (3 readings 39per second), connect pin 40 to the junction of a 180 k w resistor and a 50 pf capacitor. the 180 k w resistor is tied to pin 39 and the 50 pf capacitor is tied to pin 38. figure 1. basic dual-slope converter where: v r = reference voltage t si = signal integration time (fixed) t ri = reference voltage integration time (variable). general theory of operation (all pin designations refer to the 40-pin dip) dual-slope conversion principles the tc7126a is a dual-slope, integrating analog-to- digital converter. an understanding of the dual-slope con- version technique will aid in following detailed tc7126a operational theory. the conventional dual-slope converter measurement cycle has two distinct phases: (1) input signal integration (2) reference voltage integration (deintegration) the input signal being converted is integrated for a fixed time period (t si ), measured by counting clock pulses. an opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. the reference integration time is directly proportional to the input signal (t ri ). in a simple dual-slope converter, a complete conver- sion requires the integrator output to "ramp-up" and "ramp- down." a simple mathematical equation relates the input signal, reference voltage, and integration time: + ref voltage analog input signal + display switch driver control logic integrator output clock counter polarity control phase control v in v in v full scale 1.2 v full scale variable reference integrate time fixed signal integrate time integrator comparator ' ' 1v r t ri rc rc v in (t) dt = , t si 0
3-222 telcom semiconductor, inc. 3-1/2 digit analog-to-digital converters tc7126 tc7126a analog gates close a feedback loop around the integrator and comparator. this loop permits comparator offset volt- age error compensation. the voltage level established on c az compensates for device offset voltages. the auto-zero phase residual is typically 10 m v to 15 m v. the auto-zero cycle length is 1000 to 3000 clock periods. signal integration phase the auto-zero loop is entered and the internal differen- tial inputs connect to v in + and v in C . the differential input signal is integrated for a fixed time period. the tc7126a signal integration period is 1000 clock periods, or counts. the externally-set clock frequency is 4 4 before clocking the internal counters. the integration time period is: t si = 3 1000, where f osc = external clock frequency. the differential input voltage must be within the device common-mode range when the converter and measured system share the same power supply common (ground). if the converter and measured system do not share the same power supply common, v in C should be tied to analog com- mon. polarity is determined at the end of signal integrate phase. the sign bit is a true polarity indication, in that signals less than 1 lsb are correctly determined. this allows precision null detection limited only by device noise and auto-zero residual offsets. reference integrate phase the third phase is reference integrate, or deintegrate. v in C is internally connected to analog common and v in + is connected across the previously-charged reference capaci- tor. circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. the time required for the output to return to zero is proportional to the input signal and is between 0 and 2000 internal clock periods. the digital reading displayed is: 1000 digital section the tc7126a contains all the segment drivers neces- sary to directly drive a 3-1/2 digit lcd. an lcd backplane driver is included. the backplane frequency is the external clock frequency 4 800. for 3 conversions per second the backplane frequency is 60 hz with a 5v nominal amplitude. 4 f osc v in v ref 30 20 10 0 normal mode rejection (db) 0.1/t 1/t 10/t input frequency t = measurement period for a constant v in : v in = v r . t ri t si the dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. noise immunity is an inherent benefit. noise spikes are integrated, or averaged, to zero during integration periods. integrating adcs are immune to the large conversion errors that plague succes- sive approximation converters in high-noise environments. interfering signals with frequency components at multiples of the averaging period will be attenuated. integrating adcs commonly operate with the signal integration period set to a multiple of the 50 hz/60 hz power line period. analog section in addition to the basic integrate and deintegrate dual- slope cycles discussed above, the tc7126a design incor- porates an auto-zero cycle. this cycle removes buffer amplifier, integrator, and comparator offset voltage error terms from the conversion. a true digital zero reading results without external adjusting potentiometers. a complete con- version consists of three phases: (1) auto-zero phase (2) signal integrate phase (3) reference integrate phase auto-zero phase during the auto-zero phase, the differential input signal is disconnected from the circuit by opening internal analog gates. the internal nodes are shorted to analog common (ground) to establish a zero input condition. additional figure 2. normal-mode rejection of dual-slope converter
3-223 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 3-1/2 digit analog-to-digital converters tc7126 tc7126a figure 3. tc7126a block diagram tc7126a thousands hundreds tens units 4 39 osc v test 1 to switch drivers from comparator output clock 7 segment decode 40 38 2 osc 3 osc 1 control logic 26 500 w data latch + buff c ref r int v + c az v int 28 29 27 33 36 34 10 ? 31 zi & az int az & de (? 32 int 26 integrator to digital section de (+) de (? de (+) de (? analog common c ref + v in + v in v c int v ref + v ref zi & az c ref + 35 + lcd segment drivers 4 200 bp f osc v v th = 1v v + internal digital gound low tempco v ref comparator az zi v + ?2.8v 1 r osc c osc 7 segment decode 7 segment decode 21 typical segment output internal digital ground segment output v + 0.5 ma 2 ma 6.2v lcd +
3-224 telcom semiconductor, inc. 3-1/2 digit analog-to-digital converters tc7126 tc7126a the tc7126a is a drop-in replacement for the tc7126 and icl7126 that offers a greatly improved internal refer- ence temperature coefficient. no external component value changes are required to upgrade existing designs. component value selection auto-zero capacitor (c az ) the c az size has some influence on system noise. a 0.33 m f capacitor is recommended for 200 mv full-scale applications where 1 lsb is 100 m v. a 0.033 m f capacitor is adequate for 2v full-scale applications. a mylar-type dielec- tric capacitor is adequate. reference voltage capacitor (c ref ) the reference voltage, used to ramp the integrator output voltage back to zero during the reference integrate phase, is stored on c ref . a 0.1 m f capacitor is acceptable when v ref C is tied to analog common. if a large common- mode voltage exists (v ref C 1 analog common) and the application requires a 200 mv full scale, increase c ref to 1 m f. roll-over error will be held to less than 0.5 count. a mylar-type dielectric capacitor is adequate. integrating capacitor (c int ) c int should be selected to maximize integrator output voltage swing without causing output saturation. due to the tc7126a's superior analog common temperature co- efficient specification, analog common will normally sup- ply the differential voltage reference. for this case, a 2v full-scale integrator output swing is satisfactory. for 3 readings per second (f osc = 48 khz), a 0.047 m f value is suggested. for 1 reading per second, 0.15 m f is recom- mended. if a different oscillator frequency is used, c int must be changed in inverse proportion to maintain the nominal 2v integrator swing. an exact expression for c int is: when a segment driver is in-phase with the backplane signal, the segment is off. an out-of-phase segment drive signal causes the segment to be on, or visible. this ac drive configuration results in negligible dc voltage across each lcd segment, ensuring long lcd life. the polarity segment driver is on for negative analog inputs. if v in + and v in C are reversed, this indicator would reverse. on the tc7126a, when the test pin is pulled to v + , all segments are turned on. the display reads C1888. during this mode, lcd segments have a constant dc voltage impressed. do not leave the display in this mode for more than several minutes; lcds may be destroyed if operated with dc levels for extended periods. the display font and segment drive assignment are shown in figure 4. system timing the oscillator frequency is 4 4 prior to clocking the internal decade counters. the three-phase measurement cycle takes a total of 4000 counts (16,000 clock pulses). the 4000-count cycle is independent of input signal magni- tude. each phase of the measurement cycle has the following length: (1) auto-zero phase: 1000 to 3000 counts (4000 to 12,000 clock pulses) for signals less than full scale, the auto-zero phase is assigned the unused reference integrate time period. (2) signal integrate: 1000 counts (4000 clock pulses) this time period is fixed. the integration period is: t si = 4000 , where f osc is the externally-set clock frequency. (3) reference integrate: 0 to 2000 counts (0 to 8000 clock pulses) where: f osc = clock frequency at pin 38 v fs = full-scale input voltage r int = integrating resistor v int = desired full-scale integrator output swing. at 3 readings per second, a 750 w resistor should be placed in series with c int . this increases accuracy by compensating for comparator delay. c int must have low dielectric absorption to minimize roll-over error. a polypro- pylene capacitor is recommended. 1 f osc display font 1000's 100's 10's 1's figure 4. display font and segment assignment c int =, (( ) ) (4000) v int 1 f osc v fs r int
3-225 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 3-1/2 digit analog-to-digital converters tc7126 tc7126a in some applications, a scale factor other than unity may exist between a transducer output voltage and the required digital reading. assume, for example, a pressure transducer output for 2000 lb/in. 2 is 400 mv. rather than dividing the required full-scale voltage* v ref 200 mv 100 mv 2v 1v *v fs = 2 v ref . input voltage by two, the reference voltage should be set to 200 mv. this permits the transducer input to be used directly. the differential reference can also be used where a digital zero reading is required when v in is not equal to zero. this is common in temperature-measuring instrumentation. a compensating offset voltage can be applied between analog common and v in C . the transducer output is con- nected between v in + and analog common. device pin functional description (pin numbers refer to 40-pin dip) differential signal inputs v in + (pin 31), v in C (pin 30) the tc7126a is designed with true differential inputs and accepts input signals within the input stage common- mode voltage range (v cm ). typical range is v + C1v to v C +1v. common-mode voltages are removed from the system when the tc7126a operates from a battery or floating power source (isolated from measured system), and v in C is con- nected to analog common (v com ). (see figure 5.) in systems where common-mode voltages exist, the tc7126a's 86 db common-mode rejection ratio minimizes error. common-mode voltages do, however, affect the inte- grator output level. a worst-case condition exists if a large positive v cm exists in conjunction with a full-scale negative differential signal. the negative signal drives the integrator output positive along with v cm (see figure 6.) for such applications, the integrator output swing can be reduced below the recommended 2v full-scale swing. the integrator output will swing within 0.3v of v + or v C without increased linearity error. differential reference v ref + (pin 36), v ref C (pin 35) the reference voltage can be generated anywhere within the v + to v C power supply range. to prevent roll-over type errors being induced by large common-mode voltages, c ref should be large compared to stray node capacitance. the tc7126a offers a significantly improved analog common temperature coefficient. this potential provides a very stable voltage, suitable for use as a voltage reference. the temperature coefficient of analog common is typically 35 ppm/ c for the tc7126a and 80 ppm/ c for the tc7126. analog common (pin 32) the analog common pin is set at a voltage potential approximately 3v below v + . the potential is guaranteed to be between 2.7v and 3.35v below v + . analog common is tied internally to an n-channel fet capable of sinking integrating resistor (r int ) the input buffer amplifier and integrator are designed with class a output stages. the output stage idling current is 6 m a. the integrator and buffer can supply 1 m a drive current with negligible linearity errors. r int is chosen to remain in the output stage linear drive region, but not so large that pc board leakage currents induce errors. for a 200 mv full scale, r int is 180 k w . a 2v full scale requires 1.8 m w . oscillator components c osc should be 50 pf; r osc is selected from the equation: f osc = . for a 48 khz clock (3 conversions per second), r = 180 k w . note that f osc is 4 4 to generate the tc7126a's inter- nal clock. the backplane drive signal is derived by dividing f osc by 800. to achieve maximum rejection of 60 hz noise pickup, the signal integrate period should be a multiple of 60 hz. oscillator frequencies of 240 khz, 120 khz, 80 khz, 60 khz, 40 khz, etc. should be selected. for 50 hz rejection, oscillator frequencies of 200 khz, 100 khz, 66-2/3 khz, 50 khz, 40 khz, etc. would be suitable. note that 40 khz (2.5 readings per second) will reject both 50 hz and 60 hz. reference voltage selection a full-scale reading (2000 counts) requires the input signal be twice the reference voltage. component nominal full-scale voltage value 200 mv 2v c az 0.33 m f 0.033 m f r int 180 k w 1.8 m w c int 0.047 m f 0.047 m f note: f osc = 48 khz (3 readings per sec). 0.45 rc
3-226 telcom semiconductor, inc. 3-1/2 digit analog-to-digital converters tc7126 tc7126a figure 5. common-mode voltage removed in battery operation with v in = analog common 100 m a. this fet will hold the common line at 3v should an external load attempt to pull the common line toward v + . analog common source current is limited to 1 m a. therefore, analog common is easily pulled to a more negative voltage (i.e., below v + C 3v). the tc7126a connects the internal v + in and v C in in- puts to analog common during the auto-zero phase. during the reference-integrate phase, v C in is connected to analog common. if v + in is not externally connected to analog com- mon, a common-mode voltage exists, but is rejected by the converter's 86 db common-mode rejection ratio. in battery operation, analog common and v C in are usually connected, removing common-mode voltage concerns. in systems where v C in is connected to power supply ground or to a given voltage, analog common should be connected to v C in . the analog common pin serves to set the analog sec- tion reference, or common point. the tc7126a is specifi- cally designed to operate from a battery or in any measure- ment system where input signals are not referenced (float) with respect to the tc7126a's power source. the analog common potential of v + C3v gives a 7v end of battery life voltage. the common potential has a 0.001%/% voltage coefficient and a 15 w output impedance. with sufficiently high total supply voltage (v + Cv C >7v), analog common is a very stable potential with excellent temperature stability (typically 35 ppm/ c). this potential can be used to generate the tc7126a's reference voltage. an external voltage reference will be unnecessary in most cases because of the 35 ppm/ c temperature coefficient. see "tc7126a internal voltage reference" discussion. test (pin 37) the test pin potential is 5v less than v + . test may be used as the negative power supply connection for external cmos logic. the test pin is tied to the internally-generated negative logic supply through a 500 w resistor. the test pin load should not be more than 1 ma. see "digital section" for additional information on using test as a negative digital logic supply. if test is pulled high (to v + ), all segments plus the minus sign will be activated. do not operate in this mode for more than several minutes. with test= v + , the lcd segments are impressed with a dc voltage which will destroy the lcd. tc7126a internal voltage reference the tc7126a's analog common voltage temperature stability has been significantly improved (figure 7). the "a" version of the industry-standard tc7126 device allows users to upgrade old systems and design new systems without external voltage references. external r and c val- ues do not need to be changed. figure 10 shows analog common supplying the necessary voltage reference for the tc7126a. v buff c az v int bp pol segment drive osc 1 osc 3 osc 2 v v + v ref + v ref analog common v v + v v + gnd gnd measured system power source 9v lcd tc7126a + v v + in in figure 6. common-mode voltage reduces available integrator swing (v com 1 v in ) r i + v in v c i integrator v i = [ [ v cm v in input buffer c i = = r i integration capacitor integration resistor 4000 f integration time t i == where: v i cm osc + + t i r i c i
3-227 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 3-1/2 digit analog-to-digital converters tc7126 tc7126a typical guaranteed maximum typical typical 200 180 160 140 120 100 80 60 40 20 0 analog common temperature coefficient (ppm/?) tc7126a icl7136 no maximum specified no maximum specified icl7126 figure 8. tc7126a internal voltage reference connection figure 7. analog common temperature coefficient applications information liquid crystal display sources several manufacturers supply standard lcds to inter- face with the tc7126a 3-1/2 digit analog-to-digital con- verter. decimal point and annunciator drive the test pin is connected to the internally-generated digital logic supply ground through a 500 w resistor. the test pin may be used as the negative supply for external cmos gate segment drivers. lcd annunciators for decimal points, low battery indication, or function indication may be added without adding an additional supply. no more than 1 ma should be supplied by the test pin: its potential is approximately 5v below v + . flat package the tc7126a is available in an epoxy 64-pin formed- lead flat package. a test socket for the tc7126acbq device is available: part no. ic 51-42 manufacturer: yamaichi distribution: nepenthe distribution 2471 east bayshore suite 520 palo alto, ca 94043 (415) 856-9332 ratiometric resistance measurements the tc7126a's true differential input and differential reference make ratiometric readings possible. in ratiometric operation, an unknown resistance is measured with respect to a known standard resistance. no accurately-defined reference voltage is needed. the unknown resistance is put in series with a known standard and a current passed through the pair. the voltage developed across the unknown is applied to the input and the voltage across the known resistor applied to the refer- ence input. if the unknown equals the standard, the display will read 1000. the displayed reading can be determined from the following expression: displayed reading = 3 1000. the display will overrange for r unknown 3 2 3 r standard . r unknown r standard v analog common tc7126a v ref + 32 35 36 26 240 k w 10 k w v ref v ref 1 + 9v set v ref = 1/2 v full scale v + representative manufacturer address/phone part numbers * crystaloid 5282 hudson dr., c5335, h5535, electronics hudson, oh 44236 t5135, sx440 216-655-2429 and 720 palomar avenue fe 0801, sunnyvale, ca 94086 fe 0203 408-523-8200 vgi, inc. 1800 vernon st., ste. 2 i1048, i1126 roseville, ca 95678 916-783-7878 hamlin, inc. 612 e. lake st., 3902, 3933, 3903 lake mills, wi 53551 414-648-2361 * note: contact lcd manufacturer for full product listing/specifications.
3-228 telcom semiconductor, inc. 3-1/2 digit analog-to-digital converters tc7126 tc7126a 8 14 7 13 12 11 10 9 1 2 3 4 5 6 tc7126a 9v + v in 9 m w 900 k w 90 k w 10 k w 2v 20v 200v 200 mv 1n4148 10 m w 1 m w 0.02 ? 1 m w 10% 47 k w 1w 10% 20 k w 10% 6.8 ? 1 ? com c1 = 3 pf to 10 pf, variable c2 = 132 pf, variable + + ad636 2.2 ? 0.01 ? 10 k w 240 k w segment drive lcd 39 40 28 27 38 29 26 1 35 32 31 30 26 36 bp v + v v + ref v ref analog common v + in v + out v c1 c2 figure 9. decimal point and annunciator drives figure 11. 3-1/2 digit true rms ac dmm v ref + v ref v in + v in analog common tc7126a lcd r standard r unknown v + tc7126a decimal point select v + v + test gnd 4030 to lcd decimal points bp tc7126a bp test 37 21 v + v + gnd to lcd decimal point to backplane 4049 multiple decimal point or annunciator driver simple inverter for fixed decimal point or display annunciator figure 10. low parts count ratiometric resistance measurement
3-229 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 3-1/2 digit analog-to-digital converters tc7126 tc7126a figure 12. temperature sensor figure 13. positive temperature coefficient resistor temperature sensor figure 14. integrated circuit temperature sensor tc7126a + 9v v + 2 6 8 3 nc gnd 4 temperature dependent output 3 5 4 1 2 ref02 adj v out temp constant 5v 51 k w 1/2 lm358 v out = 1.86v @ +25? r 1 50 k w 50 k w r 2 common v in v in + v ref v ref + v v + 51 k w r 4 r 5 tc7126a v + v v in v in + v ref + v ref common 5.6 k w 160 k w r 2 20 k w 1n4148 9v r 1 20 k w + r 3 0.7%/? ptc tc7126a v + v v in v in + v ref + v ref common 50 k w r 2 160 k w 300 k w 300 k w r 1 50 k w 1n4148 sensor 9v +

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