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cy2213 high frequency programmable pecl clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07263 rev. *h revised august 10, 2012 high frequency programmable pecl clock generator features jitter peak-peak (typical) = 35 ps lvpecl output default select option serially configurable multiply ratios output edge rate control 16-pin tssop high frequency 3.3 v operation benefits high accuracy clock generation one pair of differential output drivers phase-locked loop (pll) multiplier select 8-bit feedback counter and 6-bit reference counter for high accuracy minimize electromagnetic interference (emi) industry standard, low cost package saves on board space clkb clk ser clk xin xout pll xtal oscillator xm ser data s oe logic block diagram
cy2213 document number: 38-07263 rev. *h page 2 of 16 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 frequency table ............................................................... 3 cy2213 two-wire serial interfac e ......... .............. ............ 4 introduction .................................................................. 4 serial interface specifications ..................................... 4 serial interface format ................................................ 4 serial interface transfer format ................................. 4 absolute maximum conditions ....................................... 6 crystal requirements ...................................................... 6 electrical characteristics ................................................. 6 dc electrical specifications ........................................ 6 3.3 v dc device characteristi cs ................................. 6 ac electrical specifications ......................................... 7 ac device characteristics ... ........................................ 7 state transition characteristics .................................. 8 functional specifications ................................................ 8 crystal input ................................................................ 8 select input ................................................................. 8 pecl clock output driver ..... ...................................... 8 signal waveforms ....................................................... 9 jitter ........................................................................... 10 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc solutions ......................................................... 16
cy2213 document number: 38-07263 rev. *h page 3 of 16 pinouts figure 1. 16-pin tssop pinout cy2213 1 2 3 4 5 6 7 8 9 12 11 10 13 16 15 14 clk vdd s ser data vss clkb vss vdd xin vss vddx ser clk oe vdd xout vssx pin definitions pin name pin number pin description vddx 1 3.3 v power supply for crystal driver vssx 2 ground for crystal driver xout 3 reference crystal feedback xin 4 reference crystal input vdd 5 3.3 v power supply (all v dd pins must be tied directly on board) oe 6 output enable, 0 = output disable, 1 = output enable (no internal pull up) vss 7 ground ser clk 8 serial interface clock ser data 9 serial interface data vdd 10 3.3 v power supply (all v dd pins must be tied directly on board) vss 11 ground clkb 12 lvpecl output clock (complement) clk 13 lvpecl output clock vss 14 ground vdd 15 3.3 v power supply (all v dd pins must be tied directly on board) s 16 pll multiplier select input, pull up resistor internal frequency table s m (pll multiplier) example input crystal frequency clk, clkb 0 16 25 mhz 400 mhz 1 8 15.625 mhz 125 mhz
cy2213 document number: 38-07263 rev. *h page 4 of 16 cy2213 two-wire serial interface introduction the cy2213 has a two-wire serial interface designed for data transfer operations, and is used for programming the p and q values for frequency generation. s clk is the serial clock line controlled by the master device. s data is a serial bidirectional data line. the cy2213 is a slave device and can either read or write information on the dataline upon request from the master device. figure 2 shows the basic bus connections between master and slave device. the buses are shared by a number of devices and are pulled high by a pull up resistor. serial interface specifications figure 3 shows the basic transmission specification. to begin and end a transmission, the mast er device generates a start signal (s) and a stop signal (p). start (s) is defined as switching the s data from high to low while the s clk is at high. similarly, stop (p) is defined as switching the s data from low to high while holding the s clk high. between these two signals, data on s data is synchronous with the clock on the s clk . data is allowed to change only at low period of clock, and must be stable at the high period of clock. to acknowledge, drive the s data low before the s clk rising edge and hold it low until the s clk falling edge. serial interface format each slave carries an address. the data transfer is initiated by a start signal (s). each transfer segment is 1 byte in length. the slave address and the read/write bit are first sent from the master device after the start signal. the addressed slave device must acknowledge (ack) the master device. depending on the read/write bit, the master device ei ther writes data into (logic 0) or reads data (logic 1) from the slave device. each time a byte of data is successfully transferr ed, the receiving device must acknowledge. at the end of t he transfer, the master device generates a stop signal (p). serial interface transfer format figure 3 shows the serial interface transfer format used with the cy2213. two dummy bytes must be transferred before the first data byte. the cy2213 has only three bytes of latches to store information, and the third byte of data is reserved. extra data is ignored. figure 2. device connections figure 3. serial interface specifications s clk s data s clk _c s clk _in s data _c s data _in master device r p s clk _in s data _c s data _in slave device v dd r p start (s) stop (p) s clk s data valid data acknowledge
cy2213 document number: 38-07263 rev. *h page 5 of 16 to program the cy2213 using the two-wire serial interface, set the selpq bit high. the default setting of this bit is low. the p and q values are determined by the following formulas: p final = (p 7..0 + 3) 2 q final = q 5..0 + 2. if the qcntbyp bit is set high, then q final defaults to a value of 1. the default setting of this bit is low. if the selpq bit is set low, the pll multipliers are set using the values in the select function table. cyberclocks? has been developed to generate p and q values for stable pll operation. this software is downloadable from www.cypress.com pll frequency = reference x p/q = output figure 4. cy2213 transfer format ack 1 bit 8 bits data 1 p slave address ack s dummy byte 0 r/w dummy byte 1 ack 1 bit 1 bit ack 1 bit 7 bits 8 bits 1 bit data 0 ack 1 bit 8 bits 1 bit 8 bits table 1. serial interface address for the cy2213 a6 a5 a4 a3 a2 a1 a0 r/w 11001010 table 2. serial interface programming for the cy2213 b7 b6 b5 b4 b3 b2 b1 b0 data0 qcntbyp selpq q<5> q<4> q<3> q<2> q<1> q<0> data1 p<7> p<6> p<5> p<4> p<3> p<2> p<1> p<0> data2 reserved reserved reserved reserved reserved reserved reserved reserved figure 5. pll block diagram reference pll q p vco ? output
cy2213 document number: 38-07263 rev. *h page 6 of 16 absolute maximum conditions the following table reflects stress ratings only, and fu nctional operation at the ma ximums are not guaranteed. crystal requirements requirements to use parallel mode fundamental xtal. external capaci tors are required in the cryst al oscillator circuit. please refer to the application note entitled crystal oscillator topics for details. electrical characteristics dc electrical specifications 3.3 v dc device characteristics (driving load, figure 6 ) (driving load, figure 7 ) parameter description min max unit v dd, abs maximum voltage on v dd , or v ddx with respect to ground ?0.5 4.0 v v i, abs maximum voltage on any pin with respect to ground ?0.5 v dd + 0.5 v parameter description min max unit x f crystal fundamental frequency 10 31.25 mhz parameter description min max unit v dd supply voltage 3.00 3.60 v t a ambient operating temperature 0 70 c v il input signal low voltage at pin s ? 0.35 v dd v ih input signal high voltage at pin s 0.65 ? v dd r pup internal pull up resistance 10 100 k ? t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms parameter description min typ max unit v oh output high voltage, referenced to v dd ?1.02 ?0.95 ?0.88 v v ol output low voltage, referenced to v dd ?1.81 ?1.70 ?1.62 v parameter description min typ max unit v oh output high voltage 1.1 1.2 1.3 v v ol output low voltage 0 0 0 v
cy2213 document number: 38-07263 rev. *h page 7 of 16 ac electrical specifications ac device characteristics parameter description min max unit f in input frequency with driven reference 1 133 mhz f xtal,in input frequency with crystal input 10 31.25 mhz c in,cmos input capacitance at s pin [1] ?10pf parameter description min max unit t cycle clock cycle time 2.50 (400 mhz) 8.00 (125 mhz) ns t jcrms cycle-to-cycle rms jitter ? 0.25% % t cycle at 125 mhz frequency ? 20 ps at 400 mhz frequency ? 6.25 ps t jcpk cycle-to-cycle jitter (pk-pk) ? 1.75% % t cycle at 125 mhz frequency ? 140 ps at 200 mhz frequency, xf = 25 mhz ? 55 ps at 400 mhz frequency ? 43.75 ps t jprms period jitter rms ? 0.25% % t cycle at 125 mhz frequency ? 20 ps at 400 mhz frequency ? 6.25 ps t jppk period jitter (pk-pk) ? 2.0% % t cycle at 125 mhz frequency ? 160 ps at 200 mhz frequency, xf = 25 mhz ? 65 ps at 400 mhz frequency ? 50 ps t jlt long term rms jitter (p < 20) ? 1.75% % t cycle at 125 mhz frequency ? 140 ps at 400 mhz frequency ? 43.75 ps t jlt long term rms jitter (20 < p < 40) ? 2.5% % t cycle at 125 mhz frequency ? 200 ps at 400 mhz frequency ? 62.5 ps t jlt long term rms jitter (40 < p < 60) ? 3.5% % t cycle at 125 mhz frequency ? 280 ps at 400 mhz frequency ? 87.5 ps phase noise phase noise at 10 khz (x8 mode) at 125 mhz ?107 ?92 dbc dc long term average output duty cycle 45 55 % t dc,err cycle-cycle duty cycle error at x8 with 15.625 mhz input ? 70 ps t cr , t cf output rise and fall times (measured at 20% ? 80% of v ohmin and v olmax ) 100 400 ps bw loop pll loop bandwidth 50 khz (?3 db) 8 mhz (?20 db) note 1. capacitanc e measured at frequency = 1 mhz, dc bias = 0.9v, and vac < 100 mv
cy2213 document number: 38-07263 rev. *h page 8 of 16 state transition characteristics specifies the maximum settling time of the clk and clkb outputs from device power up. for v dd and v ddx any sequences are allowed to power up and power down the cy2213. functional specifications crystal input the cy2213 receives its reference from an external crystal. pin xin is the reference crystal inpu t, and pin xout is the reference crystal feedback. the parameters for the crystal are illustrated in ac device characteristics on page 7 . the oscillator circuit requires external capacitors. please refer to the application note entitled crystal oscillator topics for details. select input there is only one select input, pin s. this pin selects the frequency multiplier in the pll, and is a standard lvcmos input. the s pin has an internal pull up resistor. the multiplier selection is illustrated in frequency table on page 3 . pecl clock output driver figure 6 and figure 7 show the clock output driver. from to transition latency description v dd /v ddx on clk/clkb normal 3 ms time from v dd /v ddx is applied and settled to clk/clkb outputs settled. figure 6. output driving load (-1) 82 ? pecl differential driver 82 ? 130 ? 130 ? 130 ? 130 ? 50 ? 50 ? v dd measurement point measurement point figure 7. output driving load (-2) pecl differential driver 62 ? 45 ? 45 ? 62 ? 45 ? 45 ? measurement point measurement point
cy2213 document number: 38-07263 rev. *h page 9 of 16 an alternative termination scheme can be us ed to drive a standard pecl fanout buffer. the pecl differential driver is designed for low voltage, high frequency operation. it signif icantly reduces the transient switching noise and power dissipation when compared to conventional cmos drivers. t he nominal value of the channel impedance is 50 ? . the pull up and pull down resistors provide matching channel termination. the combination of the differential driver and the output network determines the voltage swing on the channel. the output clock is specified at the measurement point indicated in figure 6 on page 8 and figure 7 on page 8 . signal waveforms a physical signal that appears at the pins of the device is deemed valid or invalid depending on its voltage and timing relations with other signals. this section defines the voltage and timing waveforms for the input and out put pins of the cy2213. the device characteristics tables list the specifications for the device parameters that are defined here. input and output voltage waveforms are defined as shown in figure 9 . rise and fall times are defined as the 20% and 80% measurement points of v ohmin ? v olmax . the device parameters are defined in table 3 . figure 10 on page 10 shows the definition of long term duty cycle, which is simply the clk waveform high time divided by the cycle time (defined at the crossing point). long te rm duty cycle is the average over many (>10,000) cycles. dc is def ined as the out put clock long term duty cycle. figure 8. output driving load (-3) 135 ? pecl differential driver 135 ? 79 ? 79 ? 79 ? 79 ? 50 ? 50 ? v dd measurement point measurement point table 3. definition of device parameters parameter definition v oh , v ol clock output high and low voltages v ih , v il v dd lvcmos input high and low voltages t cr , t cf clock output rise and fall times figure 9. voltage waveforms t cr t cf v(t) v ohmin 80% 20% v olmax
cy2213 document number: 38-07263 rev. *h page 10 of 16 jitter this section defines the specific ations that relate to timing uncertainty (or jitter) of the input and output waveforms. figure 11 shows the definition of period jitter with respect to the falling edge of the clk signal. period jitter is the difference between the minimum and maximum cycle times over many cycles (typically 12,800 cycles at 400 mhz). equal requirements apply for rising edges of the clk signal. t jp is defined as the output period jitter. figure 12 shows the definition of cycle- to-cycle jitter with respect to the falling edge of the clk signal. cycle-to-cycle jitter is the difference between cycle times of adjacent cycles over many cycles (typically 12,800 cycles at 400 mhz). equal requirements apply for rising edges of the clk signal. t jc is defined as the clock output cycl e-to-cycle jitter. figure 13 on page 11 shows the definition of cycle-to-cycle duty cycle error. cycle-to-cycle duty cycle error is defined as the difference between high-times of adjacent cycles over many cycles (typically 12,800 cycles at 400 mhz). equal requirements apply to the low-times. t dc , err is defined as the clock output cycle-to-cycle duty cycle error. figure 14 on page 11 shows the definition of long-term jitter error. long term jitter is defined as the accumulated timing error over many cycles (typically 12,800 cycl es at 400 mhz). it applies to both rising and falling edges. t jlt is defined as the long term jitter. figure 10. duty cycle jitter t pw+ t cycle clk clkb dc = t pw+ /t cycle figure 11. period jitter t cycle t jp = t cycle,max ? t cycle, min. over many cycles clk clkb figure 12. cycl e-to-cycle jitter t cycle,i t jc = t cylce,i ? t cycle,i+1 over many consecutive cycles clk clkb t cycle, i+1
cy2213 document number: 38-07263 rev. *h page 11 of 16 figure 13. cycle-to-c ycle duty cycle error tpw+,i t dc,err = t pw+,i ? t pw+,i+1 over many consecutive cycles clk clkb tpw+,i+1 tcycle,i+1 tcycle, i+1 cycle i cycle i+1 figure 14. long-term jitter t jlt = t max ? t min over many cycles clk clkb t min t max
cy2213 document number: 38-07263 rev. *h page 12 of 16 ordering information ordering code definitions ordering code package type operating range operating voltage cy2213zxc-1 16-pin tssop commercial, to 400 mhz 3.3 v CY2213ZXC-1T 16-pin tssop ? tape and reel commercial, to 400 mhz 3.3 v x = blank or t blank = tube; t = tape and reel fixed temperature range: c = commercial pb-free package type: z = 16-pin tssop part identifier company id: cy = cypress c x z cy 2213 - 1 x
cy2213 document number: 38-07263 rev. *h page 13 of 16 package diagrams figure 15. 16-pin tssop (4.40 mm body) z16.173/zz16.173 package outline, 51-85091 51-85091 *d
cy2213 document number: 38-07263 rev. *h page 14 of 16 acronyms document conventions units of measure acronym description cmos complementary metal-oxide semiconductor dc duty cycle emi electromagnetic interference lvcmos low voltage complementary metal-oxide semicon- ductor lvpecl low voltage pseudo (posit ive) emitter coupled logic oe output enable pecl pseudo (positive) emitter coupled logic pll phase locked loop tssop thin-shrink small outline package symbol unit of measure ? c degree celsius k ? kilohm mhz megahertz ms millisecond ns nanosecond ? ohm % percent pf picofarad ps picosecond vvolt
cy2213 document number: 38-07263 rev. *h page 15 of 16 document history page document title: cy2213, high frequency programmable pecl clock generator document number: 38-07263 rev. ecn submission date orig. of change description of change ** 113090 02/06/02 dsg change from spec number: 38-01100 to 38-07263 *a 113512 05/24/02 ckn added pll block diagram ( figure 5 ) and pll frequency equation *b 121882 12/14/02 rbi power up requirem ents added to operating conditions *c 123215 12/19/02 ljn previous revision was released with incorrect *a numbering in footer; *a should have been *b (and was changed accordingly) *d 124012 03/05/03 ckn added -2 to data sheet; edited line 3 of benefits *e 126557 05/27/03 rgl added 200 mhz jitter spec. added optional output termination *f 2738056 07/14/09 cxq obsolete document. *g 2742301 07/22/09 cxq undo obsolete document. removed all references to obsolete -2 option. changed ordering information entry to pb-free cy2213zxc-1 and -1t. revised the version of package drawing from 51-85091 ** to 51-85091 *a. *h 3709157 08/10/2012 puru added ordering code definitions . updated package diagrams (spec 51-85091 (changed revision from *a to *d)). added acronyms and units of measure . updated in new template.
document number: 38-07263 rev. *h revised august 10, 2012 page 16 of 16 cyberclocks? is a trademark of cypress semiconductor corp. all produ cts and company names mentioned in this document may be the trademarks of their respective holders. cy2213 ? cypress semiconductor corporation, 2002-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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