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data brief for further information contact your local stmicroelectronics sales office. november 2008 rev 1 1/11 11 STEVAL-IPE005V1 demonstration programmer board based on the stpm01 features full compatible with the stpm01 energy meter and with the appropriate manager software integrated system designed to provide a complete, ready-to-use energy meter high-end solution for power metering based on the str710 microcontroller with embedded rtc external memory interface (emi) ready to drive 1 mbyte of on-board sram. on-board optical insulated serial line on-board charge pump access to the stpm01 device registers, using a dedicated spi bus interface applications demonstration purposes: ? connecting the demonstration board to an ac power source and changing all the settings parameters through the gui interface and the hardware programmer/ reader board to evaluate and develop a custom application description the STEVAL-IPE005V1 demonstration board works in conjunction with the stpm01 energy meter assp device and with the stpm01 manager software. it is an integrated system designed to provide the user with a complete, ready-to-use energy meter application. this board is a high-end solution for power metering based on the str710 microcontroller with an embedded rtc and an external memory interface (emi) ready to drive 1mbyte of on-board sram. the demonstration board also integrates an on-board optical insulated serial line allowing isolation of the board ground reference in order to avoid propagation of over-voltage on the pc side. moreover, the on-board charge pump allows burning the stpm01 energy meter assp device registers. access to the stpm01 device registers is ensured using a dedicated spi bus interface. the stpm01 programmer kit demonstrates how effectively the stpm01 can be used in real-world energy meter applications and it helps the user to develop his own application. STEVAL-IPE005V1 www.st.com
demonstration board schematics STEVAL-IPE005V1 2/11 1 demonstration board schematics 1.1 microcontroller and main parts schematic figure 1. microcontroller and main parts schematic not reset booten +3v3 gnd tx_1_i/0 0 _ x t 0 _ x t jtms dbgrqs not reset jtck not jtrst jtdo jtdi +3v3 gnd a1 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a16 a17 a18 cs.1 a15 a14 d0 d12 d8 d9 d14 d5 d4 d7 d11 d3 d1 d10 d2 d15 d6 d13 +3v3 gnd a2 nwe0 nwe1 nrd a19 vout +1v8 vbkp +5v +3v3 gnd gnd +3v3 +5v +1v8 wakeup gnd jtdi jtdo not jtrst jtms jtck mosi sclk miso gnd not reset dbgrqs rx_0 +5v +3v3 gnd +5v p1.0 p1.1 p1.2 p0.10 p0.7 +5v +3v3 p0.0 p0.6 p0.2 p0.4 p0.5 +3v3 gnd +3v3 gnd ck i t x c t ri t x c t r o t x c t ro t x c t r system_default wakeup +3v3 vbkp gnd not reset gnd tx_0 gnd rtcxti jtms 126 p0.2 p0.4 p0.0 rtcxto p0.1 system_default ck p0.7 p0.6 jtdi jtck booten not jtrst jtdo p0.10 p0.5 rx_0 dbgrqs cs.1 nrd rn12 a23 a22 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cn p1.6 +1v8 vbkp rn13 nwe0 nwe1 rn14 orange tx_1_i/0 p1.0 p1.1 p1.2 7 11 12 18 23 24 25 26 27 28 29 75 76 85 19 20 37 39 41 43 48 10 4 111 108 107 89 88 74 45 90 91 106 105 110 109 87 70 69 68 60 57 56 53 66 vbkp +5v +1v8 +3v3 +3v3 +3v3 +3v3 power esd power management gnd +3v3 +5v +1v8 vbkp r4 560 r4 560 u2 esda6v1-5w6-sot323-6l u2 esda6v1-5w6-sot323-6l i/o1 1 i/o2 3 i/o3 4 i/o4 5 i/o5 6 gnd 2 charge pump chargepump +5v0 str7_otp_en str7_sbs str7_sbg gnd stpm01_sda stpm01_scs stpm01_syn stpm01_scl j9 enable uart0 tx j9 enable uart0 tx 1 2 emi_sram not cs_sram not oe we1 we0 d0 d1 d2 d3 d4 d5 d6 d7 d13 d15 d12 d8 d14 d10 d9 d11 gnd +3v3 a1 a2 a3 a4 a5 a6 a7 a8 a9 a11 a10 a12 a13 a14 a15 a16 a17 a18 a19 vout r1 560 r1 560 r5 22 r5 22 r7 22 r7 22 sw1 momentary sw1 momentary r9 22 r9 22 boot boot boot_en sw2 sw1 +3v3 gnd u3 esda6v1-5w6-sot323-6l u3 esda6v1-5w6-sot323-6l i/o1 1 i/o2 3 i/o3 4 i/o4 5 i/o5 6 gnd 2 r3 560 r3 560 general usb system rtc sts adc can i2c0 spi0 spi1 uart0 uart1 uart2 debug timer1 gpio port emi supply u1 str710fz2t6-tqfp144 general usb system rtc sts adc can i2c0 spi0 spi1 uart0 uart1 uart2 debug timer1 gpio port emi supply u1 str710fz2t6-tqfp144 p2.0/cs.0 7 p2.1/cs.1 8 p2.2/cs.2 11 p2.3/cs.3 12 a.0 98 a.1 99 a.2 100 a.3 101 a.4 102 a.5 114 a.6 115 a.7 116 a.8 117 a.9 118 a.10 119 a.11 120 a.12 121 a.13 122 a.14 130 a.15 131 a.16 132 a.17 133 a.18 134 a.19 135 p2.4/a.20 13 p2.5/a.21 14 p2.6/a.22 15 p2.7/a.23 17 d.0 61 d.1 62 d.2 63 d.3 64 d.4 65 d.5 78 d.6 79 d.7 80 d.8 81 d.9 82 d.10 92 d.11 93 d.12 94 d.13 95 d.14 96 d.15 97 rd 2 we.0 137 we.1 136 p2.8 18 p2.9 23 p2.10 24 p2.11 25 p2.12 26 p2.13 27 p2.14 28 p2.15 29 p1.4/t1.icapa 75 p1.5/t1.icapb 76 p1.6/t1.ocmpb 77 p1.7/t1.ocmpa 85 vss1 42 vss2 59 vss3 84 vss4 103 vss5 112 vss6 128 vss7 139 vss8 5 vss9 21 p0.15/wakeup 47 stby 51 v33.1 6 v33.2 22 v33.3 40 v33.4 83 v33.5 104 v33.6 113 avdd 66 v18.1 58 v18.2 129 v18bkp 55 ck 46 p1.8 86 p1.9 105 p1.10/usbclk 106 usbdn 91 usbdp 90 rstin 52 ckout 45 rtcxti 49 rtcxto 50 booten 16 jtdi 30 jtms 31 jtck 32 jtdo 33 jtrst 34 p1.0/t3.ocmpb/ain.0 71 p1.1/t3.icapa/ain.1 72 p1.2/t3.ocmpa/ain.2 73 p1.3/t3.icapb/ain.3 74 p1.11/canrx 88 p1.12/cantx 89 p1.13/hclk/io.scl 107 p1.14/hclk/io.scl 108 p1.14/htxd 111 p0.0/s0.miso/u3.tx 123 p0.1/s0.mosi/u3.rx 124 p0.2/s0.sclk/i1.scl 125 p0.3/s0.ssn/i1.sda 126 p0.4/s1.miso 127 p0.5/s1.mosi 140 p0.6/s1.sclk 141 p0.7/s1.ssn 142 p0.8/u0.rx/u0.tx 143 p0.9/u0.tx/boot.0 144 p0.10/u1.rx/u1.tx 1 p0.11/u1.tx/boot.1 3 p0.12/scclk 4 p0.13/u2.rx/t2.ocmpa 9 p0.14/u4.tx/t2.icapa 10 dbgros 44 nc 35 test1 36 test2 38 vssbkp 54 avss 67 nc 19 nc 20 nc 37 nc 39 nc 41 nc 43 nc 48 nc 53 nc 56 nc 57 nc 68 nc 69 nc 70 nc 87 nc 109 nc 110 nc 60 v33.7 138 r8 22 r8 22 reset reset gnd +3v3 clk - rtc clk ck rtcxti rtcxto +3v3 gnd tp10 tp10 1 c49 10uf c49 10uf sw2 momentary sw2 momentary c1 100n c1 100n c2 100n c2 100n r2 560 r2 560 opto isolated uart uartx gnd +3v3 +5v tx_0 rx_0 jtag jtms not jtrst jtdi jtck jtdo dbgrqs not reset +3v3 gnd r6 560 r6 560 spi_buffer spi_buffer gnd str7_read_en str7_scs str7_write_en str7_mosi str7_miso str7_scl str7_syn stpm01_scs stpm01_sda stpm01_sclk stpm01_syn 5v 3.3v
STEVAL-IPE005V1 demonstration board schematics 3/11 1.2 power management figure 2. power management schematic +5v +3v3 +1v8 +1v8 +5v +3v3 gnd vbkp +5v vbkp +1v8 +5v +3v3 +5v j2 enable vbkp j2 enable vbkp 1 2 j3 enable 1v8 j3 enable 1v8 1 2 d6 1n4001 d6 1n4001 c11 10n 50v c11 10n 50v r25 560 r25 560 cn2 dc-in9v cn2 dc-in9v 1 2 c13 10n 50v c13 10n 50v c25 100n 25v c25 100n 25v d2 blu d2 blu j4 dc-in9v j4 dc-in9v 1 2 c22 10n 50v c22 10n 50v tp3 test point tp3 test point 1 r26 560 r26 560 c17 100n 25v c17 100n 25v c24 47uf c24 47uf l1 fbead l1 fbead 1 2 d3 yellow d3 yellow c20 10n 50v c20 10n 50v c15 100n 25v c15 100n 25v r24 560 r24 560 u5 ld108518 - d2pak-a u5 ld108518 - d2pak-a vout 3 vin 2 gnd 1 tp4 test point tp4 test point 1 lf01 bnx002 lf01 bnx002 b 3 psg 1 cg 2 cg 5 cg 6 cb 4 d1 green d1 green u6 ld108533 - d2pak-a u6 ld108533 - d2pak-a vout 3 vin 2 gnd 1
demonstration board schematics STEVAL-IPE005V1 4/11 1.3 reset and clock circuits figure 3. reset and clock circuits
STEVAL-IPE005V1 demonstration board schematics 5/11 1.4 boot management and jtag circuit figure 4. boot management and jtag circuits
demonstration board schematics STEVAL-IPE005V1 6/11 figure 5. opto-isolated uart
STEVAL-IPE005V1 demonstration board schematics 7/11 1.5 external ram memory figure 6. external ram memory
demonstration board schematics STEVAL-IPE005V1 8/11 1.6 spi signals buffering figure 7. spi signals buffering str7_scs str7_write_en str7_mosi scs3v str7_miso miso3v sda5v str7_scl str7_sy n stpm01_scs read_en3v read_en sclk5v sy n5v scs5v rev_0_c8 stpm01_sda mosi3v r41 4.7k sda5v stpm01_sclk 3.3v writ e_en3v rev_0_c10 stpm01_sy n 5v 5v 3.3v sy n3v from str7 to stpm01 from stpm01 to str7 spi buffe r sclk3v 5v 5v 3.3v 3.3v charge pump spi sig nals b uffe r spi buffe r u15 m74hc126 1g 1 1a 2 1y 3 2g 4 2a 5 2y 6 gnd 7 vcc 14 4g 13 4a 12 4y 11 3g 10 3a 9 3y 8 u14 m74hc126 1g 1 1a 2 1y 3 2g 4 2a 5 2y 6 gnd 7 vcc 14 4g 13 4a 12 4y 11 3g 10 3a 9 3y 8 gnd str7_read_en
STEVAL-IPE005V1 demonstration board schematics 9/11 1.7 charge pump and spi connector figure 8. charge pump and spi connect votp str7_sbg str7_sbs scs stpm01_sda syn votp votp votp votp votp scl str7_sbg str7_otp_en str7_sbg str7_sbg stpm01_scs scs stpm01_scl scl stpm01_syn syn stpm01_syn str7_otp_en stpm01_scs str7_sbs str7_sbg stpm01_scl stpm01_sda gnd +5v0 stpm01_syn str7_otp_en str7_sbs stpm01_scs str7_sbg stpm01_scl stpm01_sda gnd vcc vcc vcc vcc vcc r30 12k r30 12k d5 bas70-04/sot d5 bas70-04/sot 3 1 2 d4 bas70-04/sot d4 bas70-04/sot 3 1 2 c38 10n c38 10n c37 10n c37 10n c35 10n c35 10n r29 1k r29 1k r28 330 r28 330 r27 47k r27 47k j8 con3 j8 con3 1 2 3 c32 1u c32 1u q4 bc807-25 q4 bc807-25 3 2 1 q3 bc807-25 q3 bc807-25 3 2 1 c33 100nf c33 100nf c34 100nf c34 100nf + c31 10uf + c31 10uf c30 100nf c30 100nf u11 m74hc126 u11 m74hc126 1g 1 1a 2 1y 3 2g 4 2a 5 2y 6 gnd 7 vcc 14 4g 13 4a 12 4y 11 3g 10 3a 9 3y 8 j7 con10 j7 con10 1 3 5 7 9 2 4 6 8 10 u12 m74hc126 u12 m74hc126 1g 1 1a 2 1y 3 2g 4 2a 5 2y 6 gnd 7 vcc 14 4g 13 4a 12 4y 11 3g 10 3a 9 3y 8 u13 m74hc14 u13 m74hc14 1a 1 1y 2 2a 3 2y 4 3a 5 3y 6 gnd 7 vcc 14 6a 13 6y 12 5a 11 5y 10 4a 9 4y 8 r31 12k r31 12k c36 56p c36 56p
revision history STEVAL-IPE005V1 10/11 2 revision history table 1. document revision history date revision changes 24-nov-2008 1 initial release.
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