?20 10 fairchild semiconductor corporation fdd5810 _f085 rev. a 1 (w) www.fairchildsemi.com fdd5810 _f085 n-channel logic level trench ? mosfet 1 fdd5810 _f085 n-channel logic level trench ? mosfet ! 60v, 36a, 27m " features ! r ds(on) = 22m "!# typ.), v gs = 5v, i d = 29a ! q g(5) = 13nc (typ.), v gs = 5v ! low miller charge ! low q rr body diode ! uis capability (single pulse / repetitive pulse) ! qualified to aec q101 ! rohs compliant applications ! motor / body load control ! abs systems ! powertrain management ! injection system ! dc-dc converters and off-line ups ! distributed power architecture and vrms ! primary switch for 12v and 24v systems g s d to-252 d-pak (to-252) d g s l e a d f r e e m t a e l n t i o m p e n i may 20 10
fdd5810 _f085 rev. a 1 (w) www.fairchildsemi.com 2 absolute maximum ratings t c = 25c unless otherwise noted thermal characteristics package marking and ordering information electrical characteristics t j = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics symbol parameter ratings units v dss drain to source voltage 60 v v gs gate to source voltage $ 20 v i d drain current continuous (v gs = 10v) 37 a drain current continuous (v gs = 5v) 33 a continuous (t a = 25 o c, v gs = 10v, with r % ja = 52 o c/w) 7.4 a pulsed figure 4 a e as single pulse avalanche energy (note 1) 45 mj p d power dissipation 72 w derate above 25 o c 0.48 w/ o c t j , t stg operating and storage temperature -55 to 175 o c r % jc maximum thermal resistance junction to case to-252 2 .1 o c/w r % ja thermal resistance junction to ambient to-252, 1in 2 copper pad area 52 o c/w device marking device package reel size tape width quant ity fdd5810 fdd5810 _f085 to-252aa 330mm 16mm 2500 units symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 & a, v gs = 0v 60 - - v i dss zero gate voltage drain current v ds = 48v - - 1 & a v gs = 0v t c = 150 o c - - 250 i gss gate to source leakage current v gs = $ 20v - - $ 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 & a 1 1.6 2 v r ds(on) drain to source on resistance i d = 32a, v gs = 10v - 18 22 m " i d = 29a, v gs = 5v - 22 27 i d = 32a, v gs = 10v, t j = 175 o c - 43 53 c iss input capacitance v ds = 25v, v gs = 0v, f = 1mhz - 1420 1890 pf c oss output capacitance - 150 200 pf c rss reverse transfer capacitance - 65 100 pf r g gate resistance f = 1mhz - 3.5 - " q g total gate charge at 10v v gs = 0v to 10v v dd = 30v i d = 35a - 24 34 nc q g total gate charge at 5v v gs = 0v to 5v - 13 18 nc q g(th) threshold gate charge v gs = 0v to 1v - 1.3 - nc q gs gate to source gate charge - 4.0 - nc q gs2 gate charge threshold to plateau - 2.7 - nc q gd gate to drain miller charge - 5.0 - nc fdd5810 _f085 n-channel logic level trench ? mosfet
fdd5810 _f085 rev. a 1 (w) www.fairchildsemi.c om 3 switching char acteristics drain-sourc e diode characteristics notes: 1: starting t j = 25c, l = 110h, i as = 28a, v dd = 54v, v gs = 10v. t on tur n-on time v dd = 30v, i d = 35a v gs = 5v, r gs = 11 " - - 130 ns t d(on) tur n-on delay time - 12 - ns t r rise time - 75 - ns t d(off) turn-off d elay time - 26 - ns t f fal l time - 34 - ns t off tur n-off time - - 90 ns v sd source to drain diode voltage i sd = 32a - - 1.2 5 v i sd = 16a - - 1.0 v t rr reverse rec overy time i f = 35a , di/dt = 100a/ & s - - 39 ns q rr revers e recovery charge i f = 35a , di/dt = 100a/ & s - - 35 nc fdd5810 _f085 n-channel logic level trench ? mosfet
fdd5810 _f085 rev. a 1 (w) www.fairchildsemi.com 4 typical characteristics t j = 25c unless otherwise noted figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal imp edance figure 4. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 25 50 75 100 125 150 175 0 10 20 30 40 i d , drain current (a) t c , case temperature ( o c ) v gs = 5v v gs = 10v 0.01 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 2 t, rectangular pulse duration (s) z % jc , normalized thermal impedance notes: duty factor: d = t 1 /t 2 peak t j = p dm x r % jc + t c p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 duty cycle - descending order single pulse 100 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 600 30 i dm , peak current (a) t, pulse width (s) t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: transconductance may limit current in this region v gs = 5v fdd5810 _f085 n-channel logic level trench ? mosfet
fdd5810 _f085 rev. a 1 (w) www.fairchildsemi.com 5 figure 5. forward bias safe operating area note: refer to fairchild application notes an7514 and an7 515 figure 6. unclamped inductive switching capability figure 7. transfer characteristics figure 8. satur atio n characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature typical characteristics t j = 25c unless otherwise noted 1 10 100 0.1 1 10 100 200 10us 100us 1ms 10ms i d , drain current (a) v ds , drain to source voltage (v) operation in this area may be limited by r ds(on) single pulse t j = max rated t c = 25 o c dc 200 1 10 100 0.001 0.01 0.1 1 10 100 500 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r !' 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 0 20 40 60 0 1.0 2.0 3.0 4.0 5.0 i d , drain current (a) v gs , gate to source voltage (v) t j = 175 o c t j = 25 o c t j = -55 o c pulse duration = 80 & s duty cycle = 0.5% max v dd = 6v 0 20 40 60 0 0.5 1.0 1.5 2.0 2.5 i d , drain current (a) v ds , drain to source voltage (v) pulse duration = 80 & s duty cycle = 0.5% max t c = 25 o c v gs = 10v v gs = 3.5v v gs = 3v v gs = 4.5v v gs = 4v v gs = 5v 14 18 22 26 2 4 6 8 10 i d = 1a v gs , gate to source voltage (v) i d = 35a r ds(on) , drain to source on resistance (m " ) pulse duration = 80 & s duty cycle = 0.5% max 30 -80 -40 0 40 80 120 160 200 0.4 0.8 1.2 1.6 2.0 2.4 2.8 pulse duration = 80 & s duty cycle = 0.5% max i d = 32a v gs = 10v normalized drain to source on-resistance t j , junction temperature ( o c ) fdd5810 _f085 n-channel logic level trench ? mosfet
fdd5810 _f085 rev. a 1 (w) www.fairchildsemi.com 6 figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage figure 14. gate charge waveforms for constant gate current typical characteristics t j = 25c unless otherwise noted 0.2 0.5 0.8 1.1 1.4 -80 -40 0 40 80 120 160 200 v gs = v ds , i d = 250 & a normalized gate t j , junction temperature ( o c) threshold voltage 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 160 200 t j , junction temperature ( o c) normalized drain to source i d = 250 & a breakdown voltage 100 1000 0.1 1 10 60 10000 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss c oss c rss 10 0 2 4 6 8 10 0 5 10 15 20 25 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 30v i d = 35a i d = 1a waveforms in descending order: fdd5810 _f085 n-channel logic level trench ? mosfet
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