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general description the max5940a/max5940b/max5940c/max5940d pro- vide complete interface function for a powered device (pd) to comply with the ieee 802.3af standard in a power-over-ethernet system. max5940a/max5940b/ max5940c/max5940d provide the pd with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. these devices also feature power-mode undervoltage lockout (uvlo) with wide hysteresis and power- good outputs. the max5940a/max5940b are available with an absolute maximum rating of 80v and the max5940c/max5940d are rated for an absolute maxi- mum rating of 90v. an integrated mosfet provides pd isolation during detection and classification. all devices guarantee a leak- age current offset of less than 10? during the detection phase. a programmable current limit prevents high inrush current during power-on. the device features power- mode uvlo with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition between detection, classifica- tion, and power-on/-off phases. the max5940a/max5940c provide an active-high (pgood) open-drain output and a fixed uvlo threshold. the max5940b/max5940d provide both active-high (pgood) and active-low ( pgood) outputs and have an adjustable uvlo threshold with the default value compli- ant to the 802.3af standard. all devices are designed to work with or without an external diode bridge. the max5940a/max5940b/max5940c/max5940d are available in 8-pin so packages and are rated over the extended temperature range of -40? to +85?. applications ip phones security cameras wireless access nodes ieee 802.3af power devices computer telephony features ? fully integrated ieee 802.3af-compliant pd interface ? pd detection and programmable classification signatures ? less than 10? leakage current offset during detection ? integrated mosfet for isolation and inrush current limiting ? 90v absolute maximum rating (max5940c/max5940d) ? gate output allows external control of the internal isolation mosfet ? programmable inrush current control ? programmable undervoltage lockout (max5940b/max5940d only) ? wide uvlo hysteresis accommodates twisted- pair cable voltage drop ? pgood/ pgood outputs to enable downstream dc-dc converters ? -40? to +85? operating temperature range max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet ________________________________________________________________ maxim integrated products 1 ordering information 60v 68nf gnd v ee gate rclass pgood dc-dc converter gnd -48v r cl *optional. gnd v+ load v reg d1* out 2 3 4 5 6 8 c out c gate r disc 25.5k ss_shdn max5014 max5940a max5940c d2* typical operating circuits 19-2991; rev 2; 2/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available pin configurations appear at end of data sheet. part temp range pin- package uvlo max5940aesa -40? to +85? 8 so fixed max5940besa -40? to +85? 8 so adjustable MAX5940CESA -40? to +85? 8 so fixed max5940desa -40? to +85? 8 so adjustable typical operating circuits continued at end of data sheet.
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = (gnd - v ee ) = 48v, gate = pgood = pgood = out = open, uvlo = v ee , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c. all voltages are referenced to v ee , unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages are referenced to v ee , unless otherwise noted.) gnd (max5940a/max5940b) ...............................-0.3v to +80v gnd (max5940c/max5940d)...............................-0.3v to +90v out, pgood ...........................................-0.3v to (gnd + 0.3v) rclass, gate ......................................................-0.3v to +12v uvlo ........................................................................-0.3v to +8v pgood to out.........................................-0.3v to (gnd + 0.3v) maximum input/output current (continuous) out to v ee ...................................................................500ma gnd, rclass to v ee .....................................................70ma uvlo, pgood , pgood to v ee .....................................20ma gate to v ee ....................................................................80ma continuous power dissipation (t a = +70?) 8-pin so (derate 5.9mw/? above +70?)..................470mw operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units detection mode input offset current (note 2) i offset v in = 1.4v to 10.1v 10 ? effective differential input resistance (note 3) dr v in = 1.4v up to 10.1v with 1v step, out = pgood = gnd 550 k classification mode classification current turn-off threshold (note 4) v th , clss v in rising 20.8 21.8 22.5 v class 0, r cl = 10k 02 class 1, r cl = 732 = = = = class 4, r cl = 178 power mode operating supply voltage v in v in = (gnd - v ee )67v operating supply current i in measure at gnd, not including r disc 0.4 1 ma max5940a/max5940c 34.3 35.4 36.6 default power turn-on voltage v uvlo , on v in increasing max5940b/max5940d, uvlo = v ee 37.4 38.6 39.9 v default power turn-off voltage v uvlo , off v in decreasing, uvlo = v ee for max5940b/max5940d 30 v max5940a/max5940c 4.2 default power turn-on/off hysteresis v hyst, uvlo max5940b/max5940d, uvlo = v ee 7.4 v external uvlo programming range v in,ex set uvlo externally (max5940b/ max5940d only) (note 7) 12 67 v uvlo external reference voltage v ref , uvlo 2.400 2.460 2.522 v uvlo external reference voltage hysteresis hyst ratio to v ref,uvlo 19.2 20 20.9 % uvlo bias current i uvlo uvlo = 2.460v -1.5 +1.5 ?
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet _______________________________________________________________________________________ 3 note 1: all min/max limits are production tested at +85?. limits at +25? and -40? are guaranteed by design. note 2: the input offset current is illustrated in figure 1. note 3: effective differential input resistance is defined as the differential resistance between gnd and v ee without any external resistance. see figure 1. note 4: classification current is turned off whenever the ic is in power mode. note 5: see table 2 in the pd classification mode section. r disc and r cl must be ?%, 100ppm or better. i class includes the ic bias current and the current drawn by r disc . note 6: see the thermal dissipation section for details. note 7: when uvlo is connected to the midpoint of an external resistor-divider with a series resistance of 25.5k ( 1%), the turn- on threshold set-point for the power mode is defined by the external resistor-divider. make sure the voltage on the uvlo pin does not exceed its maximum rating of 8v when v in is at the maximum voltage (max5940b only). note 8: when the uvlo input voltage is below v th,g,uvlo, the max5940b sets the uvlo threshold internally. note 9: an input voltage or v uvlo glitch below their respective thresholds shorter than or equal to t off_dly does not cause the max5940a/max5940b/max5940c/max5940d to exit power-on mode (as long as the input voltage remains above an opera- ble voltage level of 12v). note 10: guaranteed by design. note 11: pgood references to out while pgood references to v ee . parameter symbol conditions min typ max units uvlo input ground sense threshold (note 8) v th , g , uvlo 50 440 mv uvlo input ground sense glitch rejection uvlo = v ee 7s power turn-off voltage, undervoltage lockout deglitch time (note 9) t off_dly v in , v uvlo falling 0.32 ms t a = +25? (note 10) 0.6 1.1 isolation switch n-channel mosfet on-resistance r on output current = 300ma, v gate = 6v, measured between out and v ee t a = +85? 0.8 1.5 isolation switch n-channel mosfet off-threshold voltage v gsth out = gnd, v gate - v ee, output current < 1? 0.5 v gate pulldown switch resistance r g power-off mode, v in = 12v, uvlo = v ee for max5940b 38 80 gate charging current i g v gate = 2v 5 10 15 a gate high voltage v gate i gate = 1? 5.59 5.76 5.93 v v out - v ee , |v out - v ee | decreasing, v gate = 5.75v 1.16 1.23 1.31 v pgood, pgood assertion v out threshold v outen hysteresis 70 mv (gate - v ee ) increasing, out = v ee 4.62 4.76 4.91 v pgood, pgood assertion v gate threshold v gsen hysteresis 80 mv pgood, pgood output low voltage (note 11) v oldcdc i sink = 2ma; for pgood, out (gnd - 5v) 0.4 v pgood leakage current (note 11) gate = high, gnd - v out = 67v 1 a pgood leakage current (note 11) gate = v ee , pgood - v ee = 67v 1 a electrical characteristics (continued) (v in = (gnd - v ee ) = 48v, gate = pgood = pgood = out = open, uvlo = v ee , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c. all voltages are referenced to v ee , unless otherwise noted.) (note 1)
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet 4 _______________________________________________________________________________________ i in i ini + 1 i ini i offset dr i 1v v ini v ini + 1 i offset ? i ini - v ini dr i dr i ? (v ini + 1 - v ini ) = 1v (i ini + 1 - i ini ) (i ini + 1 - i ini ) v in figure1. effective differential input resistance/offset current detection current vs. input voltage max5940a/b toc01 input voltage (v) detection current (ma) 8 6 4 2 0.1 0.2 0.3 0.4 0.5 0 010 r disc = 25.5k i in + i rdisc classification current vs. input voltage max5940a/b toc02 input voltage (v) classification current (ma) 25 20 15 10 5 10 20 30 40 50 0 030 class 0 class 1 class 2 class 3 class 4 effective differential input resistance vs. input voltage max5940a/b toc03 input voltage (v) effective differential input resistance (m ) 10 8 6 4 2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 012 input offset current vs. input voltage max5940a/b toc04 input voltage (v) input offset current ( a) 9 7 5 3 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 -3.5 111 normalized uvlo vs. temperature max5940a/b toc05 temperature ( c) normalized uvlo 60 35 10 -15 0.992 0.994 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.010 0.990 -40 85 uvlo = v ee pgood output low voltage vs. current max5940a/b toc06 i sink (ma) v pgood (mv) 15 10 5 50 100 150 200 250 0 020 typical operating characteristics (v in = (gnd - v ee ) = 48v, gate = pgood = pgood = out = open, uvlo = v ee (max5940b), t a = -40? to +85?. typical values are at t a = +25?. all voltages are referenced to v ee , unless otherwise noted.)
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet _______________________________________________________________________________________ 5 pgood output low voltage vs. current max5940a/b toc07 i sink (ma) v pgood (mv) 15 10 5 80 160 240 320 400 0 020 out leakage current vs. temperature max5940a/b toc08 temperature ( c) out leakage current (na) 60 35 10 -15 4 8 12 16 20 0 -40 85 v out = 67v inrush current control (v in = 12v) max5940a/b toc09 1ms/div v gate 5v/div i inrush 100ma/div v out to v ee 10v/div pgood 10v/div inrush current control (v in = 48v) max5940a/b toc10 2ms/div v gate 5v/div i inrush 100ma/div v out to v ee 50v/div pgood 50v/div inrush current control (v in = 67v) max5940a/b toc11 2ms/div v gate 5v/div i inrush 100ma/div v out to v ee 50v/div pgood 50v/div typical operating characteristics (continued) (v in = (gnd - v ee ) = 48v, gate = pgood = pgood = out = open, uvlo = v ee (max5940b), t a = -40? to +85?. typical values are at t a = +25?. all voltages are referenced to v ee , unless otherwise noted.)
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet 6 _______________________________________________________________________________________ pin description pin max5940a/ max5940c max5940b/ max5940d name function 1, 7 n.c. no connection. not internally connected. ? uvlo undervoltage lockout programming input for power mode. when uvlo is above its threshold, the device enters power mode. connect uvlo to v ee to use the default undervoltage lockout threshold. connect uvlo to an external resistor-divider to define a threshold externally. the series resistance value of the external resistors must add to 25.5k (?%) and replaces the detection resistor. to keep the device in undervoltage lockout, pull uvlo to between v th,g,uvlo and v ref,uvlo . 22 rclass classification setting. add a resistor from rclass to v ee to set a pd class (see tables 1 and 2). 33 gate gate of internal n-channel power mosfet. gate sources 10? when the device enters power mode. connect an external 100v ceramic capacitor (c gate ) from gate to out to program the inrush current. pull gate to v ee to turn off the internal mosfet. the detection and classification functions operate normally when gate is pulled to v ee . 44v ee negative input power. source of the integrated isolation n-channel power mosfet. connect v ee to -48v. 5 5 out output voltage. drain of the integrated isolation n-channel power mosfet. 66 pgood power-good indicator output, active-high, open-drain. pgood is referenced to out. pgood goes high impedance when v out is within 1.2v of v ee and when gate is 5v above v ee . otherwise, pgood is pulled to out (given that v out is at least 5v below gnd). connect pgood to the on pin of a downstream dc-dc converter. ? pgood power-good indicator output, active-low, open-drain. pgood is referenced to v ee . pgood is pulled to v ee when v out is within 1.2v of v ee and when gate is 5v above v ee . otherwise, pgood goes high impedance. connect pgood to the on pin of a downstream dc-dc converter. 8 8 gnd ground. gnd is the positive input terminal. detailed description operating modes the pd front-end section of the max5940_ operates in 3 different modes, pd detection signature, pd classifica- tion, and pd power, depending on its input voltage (v in = gnd - v ee ). all voltage thresholds are designed to oper- ate with or without the optional diode bridge while still complying with the ieee 802.3af standard (see figure 4). detection mode (1.4v v in 10.1v) in detection mode, the power source equipment (pse) applies two voltages on v in in the range of 1.4v to 10.1v (1v step minimum), and then records the current mea- surements at the two points. the pse then computes v/ i to ensure the presence of the 25.5k signature resistor. in this mode, most of the max5940_ internal cir- cuitry is off and the offset current is less than 10?. if the voltage applied to the pd is reversed, install pro- tection diodes on the input terminal to prevent internal damage to the max5940_ (see the typical application circuits ). since the pse uses a slope technique ( v/ i) to calculate the signature resistance, the dc offset due to the protection diodes is subtracted and does not affect the detection process.
classification mode (12.6v v in 20v) in the classification mode, the pse classifies the pd based on the power consumption required by the pd. this allows the pse to efficiently manage power distri- bution. the ieee 802.3af standard defines five different classes as shown in table 1. an external resistor (r cl ) connected from rclass to v ee sets the classification current. the pse determines the class of a pd by applying a volt- age at the pd input and measures the current sourced out of the pse. when the pse applies a voltage between 12.6v and 20v, the max5940_ exhibit a current charac- teristic with values indicated in table 2. the pse uses the classification current information to classify the power requirement of the pd. the classification current includes the current drawn by the 25.5k detection signature resistor and the supply current of the max5940_ so the total current drawn by the pd is within the ieee 802.3af standard figures. the classification current is turned off whenever the device is in power mode. power mode during power mode, when v in rises above the under- voltage lockout threshold (v uvlo,on ), the max5940_ gradually turn on the internal n-channel mosfet q1 (see figure 2). the max5940_ charge the gate of q1 with a constant current source (10?, typ). the drain- to-gate capacitance of q1 limits the voltage rise rate at the drain of the mosfet, thereby limiting the inrush current. to reduce the inrush current, add external drain-to-gate capacitance (see the inrush current limit section). when the drain of q1 is within 1.2v of its source voltage and its gate-to-source voltage is above 5v, the max5940_ asserts the pgood/ pgood out- puts. the max5940_ have a wide uvlo hysteresis and turn-off deglitch time to compensate for the high impedance of the twisted-pair cable. undervoltage lockout the max5940_ operate up to a 67v supply voltage with a default uvlo turn-on (v uvlo,on ) set at 35v (max5940a/max5940c) or 39v (max5940b/max5940d) and a uvlo turn-off (v uvlo,off ) set at 30v. the max5940b/max5940d have an adjustable uvlo thresh- old using a resistor-divider connected to uvlo (see figure 3). when the input voltage is above the uvlo threshold, the ic is in power mode and the mosfet is on. when the input voltage goes below the uvlo thresh- old for more than t off_dly , the mosfet turns off. max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet _______________________________________________________________________________________ 7 class usage r cl ( ) maximum power used by pd (w) 0 default 10k 0.44 to 12.95 1 optional 732 0.44 to 3.84 2 optional 392 3.84 to 6.49 3 optional 255 6.49 to 12.95 4 not allowed 178 reserved* * class 4 reserved for future use. table 1. pd power classification/r cl selection class current seen at v in (ma) ieee 802.3af pd classification current specification (ma) class r cl ( )v in * (v) min max min max 0 10k 12.6 to 20 0204 1 732 12.6 to 20 9.17 11.83 9 12 2 392 12.6 to 20 17.29 19.71 17 20 3 255 12.6 to 20 26.45 29.55 26 30 4 178 12.6 to 20 36.6 41.4 36 44 * v in is measured across the max5940 input pins, which does not include the diode bridge voltage drop. table 2. setting classification current
max5940a/max5940b/max5940c/max5940d to adjust the uvlo threshold (max5940b/max5940d only), connect an external resistor-divider from gnd to uvlo and from uvlo to v ee . use the following equations to calculate r1 and r2 for a desired uvlo threshold: r1 = 25.5k - r2 where v in,ex is the desired uvlo threshold. since the resistor-divider replaces the 25.5k pd detection resis- tor, ensure that the sum of r1 and r2 equals 25.5k ?%. when using the external resistor-divider, the max5940b/max5940d has an external reference volt- age hysteresis of 20% (typ). when uvlo is pro- grammed externally, the turn-off threshold is 80% (typ) of the new uvlo threshold. rkx v v ref uvlo in ex 2255 = . , , ieee 802.3af pd interface controller for power-over-ethernet 8 _______________________________________________________________________________________ r1 gnd uvlo gnd (uvlo) ( ) max5940b. gate r2 r3 max5940b max5940d classification rclass (pgood) 6.8v en ref 2.46v 200mv v ee v gate 1.2v, ref 5v, ref q4 pgood out q3 q1 q2 en 20% figure 2. block diagram r1 uvlo gnd v ee r2 v in = 12v to 67v max5940b max5940d figure 3. setting undervoltage lockout with an external resistor-divider
inrush current limit the max5940_ charge the gate of the internal mosfet with a constant current source (10?, typ). the drain- to-gate capacitance of the mosfet limits the voltage rise rate at the drain, thereby limiting the inrush current. add an external capacitor from gate to out to further reduce the inrush current. use the following equation to calculate the inrush current: pgood/ pgood outputs (max5940a/max5940c only) pgood is an open-drain, active-high logic output. pgood goes high impedance when v out is within 1.2v of v ee and when gate is 5v above v ee . otherwise, pgood is pulled to v out (given that v out is at least 5v below gnd). connect pgood to the on pin of a down- stream dc-dc converter. connect a 100k pullup resis- tor from pgood to gnd if needed. (max5940b/max5940d only) pgood is an open-drain, active-low logic output. pgood is pulled to v ee when v out is within 1.2v of v ee and when gate is 5v above v ee . otherwise, pgood goes high impedance. connect pgood to the on pin of a downstream dc-dc converter. connect a 100k pullup resistor from pgood to gnd if needed. thermal dissipation during classification mode, if the pse applies the maxi- mum dc voltage, the maximum voltage drop from gnd to v rclass will be 13v. if the maximum classification cur- rent of 42ma flows through the max5940_, then the maxi- mum dc power dissipation will be 546mw, which is slightly higher than the maximum dc power dissipation of the ic at maximum operating temperature. however, according to the ieee 802.3af standard, the duration of the classification mode is limited to 75ms (max). the max5940_ handle the maximum classification power dis- sipation for the maximum duration time without sustaining any internal damage. if the pse violates the ieee 802.3af standard by exceeding the 75ms maximum classification duration, it may cause internal damage to the ic. iix c c inrush g out gate = max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet _______________________________________________________________________________________ 9
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet 10 ______________________________________________________________________________________ r1* 60v 68nf uvlo gnd v ee gate rclass pgood pgood dc-dc converter phy gnd -48v tx rx rj-45 power-over spair pairs 3 6 1 2 4 5 7 8 gnd -48v r2* r cl *r1 and r2 are optional and when used, they must total 25.5k and replace the 25.5k resistor. gnd v+ v reg out 1 2 3 4 5 6 7 8 c out c gate r disc 25.5k ss_shdn max5014 max5940b max5940d power-over signal pairs load + - + - v reg typical application circuits application circuit 1 figure 4. pd with power-over-ethernet (power is provided by either the signal pairs or the spare pairs)
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet ______________________________________________________________________________________ 11 60v 68nf uvlo gnd v ee gate rclass pgood pgood dc-dc converter gnd -48v wall adapter supply r cl d1 gnd v+ vreg pgood out 1 2 3 4 5 6 7 8 c out c gate r disc 25.5k ss_shdn max5014 max5940b max5940d load pgood v ee gate v ee gate d3 ps2701a-1 cmpt3904 100k 2.0k cmpt3904 typical application circuits (continued) figure 5. adding wall adapter input supply (wall adapter supply takes precedence over power-over-ethernet) application circuit 2 diode d1 prevents the power-over-ethernet to back drive the wall adapter. whenever the wall adapter power is greater than (v d3 + approximately 2v), the gate is pulled low to pinch off the power-over-ethernet. the wall adapter power pollutes the discovery signa- ture, preventing pse from detecting this pd.
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet 12 ______________________________________________________________________________________ 60v 68nf uvlo gnd v ee gate rclass pgood pgood dc-dc converter gnd -48v wall adapter supply r cl d1 gnd v+ vreg out 1 2 3 4 5 6 7 8 c out c gate r disc 25.5k ss_shdn max5014 max5940b max5940d load r4 4k 2w d2 typical application circuits (continued) figure 6. adding wall adapter input supply (wall adapter supply and power-over-ethernet co-exist, the one with higher voltage provides power to the load) application circuit 3 d2 prevents the wall adapter power from polluting the discovery and classification signatures. the optional r4 provides the 10ma minimum power maintenance signature to keep the power-over-ethernet from discon- necting.
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet ______________________________________________________________________________________ 13 60v 68nf uvlo gnd v ee gate rclass pgood pgood dc-dc converter gnd -48v wall adapter supply r cl d1 gnd v+ vreg out 1 2 3 4 5 6 7 8 c out c gate r disc 25.5k ss_shdn max5014 max5940b max5940d load typical application circuits (continued) application circuit 4 if the wall adapter supply comes up first, it provides power to the load and pollute the discovery and classi- fication signatures. if the power-over-ethernet comes up first, it powers the load until taken over by a wall adapter with higher output voltage. figure 7. adding wall adapter input supply (the one with higher voltage provides power to the load)
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet 14 ______________________________________________________________________________________ pgood out v ee 1 2 8 7 gnd n.c. rclass gate n.c. so top view 3 4 6 5 max5940a max5940c pgood out v ee 1 2 8 7 gnd pgood rclass gate uvlo so 3 4 6 5 max5940b max5940d pin configurations r1** 60v 68nf uvlo gnd v ee gate rclass pgood pgood dc-dc converter gnd -48v r2** r cl *optional. **r1 and r2 are optional and when used, they must total 25.5k and replace the 25.5k resistor. v reg out 1 2 3 4 5 6 7 8 c out c gate r disc 25.5k max5940b max5940d d1* d2* gnd v+ ss_shdn max5014 load typical operating circuits (continued) chip information transistor count: 3,643 process: bicmos
max5940a/max5940b/max5940c/max5940d ieee 802.3af pd interface controller for power-over-ethernet maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) soicn .eps package outline, .150" soic 1 1 21-0041 b rev. document control no. approval proprietary information title: top view front view max 0.010 0.069 0.019 0.157 0.010 inches 0.150 0.007 e c dim 0.014 0.004 b a1 min 0.053 a 0.19 3.80 4.00 0.25 millimeters 0.10 0.35 1.35 min 0.49 0.25 max 1.75 0.050 0.016 l 0.40 1.27 0.394 0.386 d d min dim d inches max 9.80 10.00 millimeters min max 16 ac 0.337 0.344 ab 8.75 8.55 14 0.189 0.197 aa 5.00 4.80 8 n ms012 n side view h 0.244 0.228 5.80 6.20 e 0.050 bsc 1.27 bsc c h e e b a1 a d 0 -8 l 1 variations:

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