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| geometry process details principal device types cmlt7410 cmpt7410 cmst7410 cmut7410 gross die per 5 inch wafer 54,330 process cp741v small signal transistors pnp - low vce(sat) transistor chip process epitaxial planar die size 17.7 x 17.7 mils die thickness 7.1 mils base bonding pad area 3.8 x 3.8 mils emitter bonding pad area 3.8 x 3.8 mils top side metalization al-si - 30,000? back side metalization au - 12,000? www.centralsemi.com r2 (22-march 2010)
process cp741v typical electrical characteristics www.centralsemi.com r2 (22-march 2010) |
Price & Availability of CP741V10
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