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? semiconductor components industries, llc, 2012 september, 2012 ? rev. 0 1 publication order number: dta114yd/d mun5114dw1, nsba114ydxv6, nsba114ydp6 dual pnp bias resistor transistors r1 = 10 k , r2 = 47 k pnp transistors with monolithic bias resistor network this series of digital transistors is designed to replace a single device and its external resistor bias network. the bias resistor transistor (brt) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base ? emitter resistor. the brt eliminates these individual components by integrating them into a single device. the use of a brt can reduce both system cost and board space. features ? s and nsv prefix for automotive and other applications requiring unique site and control change requirements; aec-q101 qualified and ppap capable ? simplifies circuit design ? reduces board space ? reduces component count ? these devices are pb ? free, halogen free/bfr free and are rohs compliant maximum ratings (t a = 25 c, common for q1 and q2, unless otherwise noted) rating symbol max unit collector ? base voltage v cbo 50 vdc collector ? emitter voltage v ceo 50 vdc collector current ? continuous i c 100 madc input forward voltage v in(fwd) 40 vdc input reverse voltage v in(rev) 6 vdc stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. ordering information device package shipping ? mun5114dw1t1g, SMUN5114DW1T1G sot ? 363 3,000 / tape & reel nsba114ydxv6t1g sot ? 563 4,000 / tape & reel nsba114ydp6t5g sot ? 963 8,000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refe r to our tape and reel packaging specifications brochure, brd8011/d. http://onsemi.com marking diagrams 0d/q = specific device code m = date code* =pb ? free package (note: microdot may be in either location) *date code orientation may vary depending upon manufacturing location. sot ? 363 case 419b sot ? 563 case 463a sot ? 963 case 527ad pin connections (3) (2) (1) q 1 q 2 r 1 r 2 r 1 r 2 (4) (5) (6) m 1 0d m 1 0d m 1 6 q
mun5114dw1, nsba114ydxv6, nsba114ydp6 http://onsemi.com 2 thermal characteristics characteristic symbol max unit mun5114dw1 (sot ? 363) one junction heated total device dissipation t a = 25 c (note 1) (note 2) derate above 25 c (note 1) (note 2) p d 187 256 1.5 2.0 mw mw/ c thermal resistance, (note 1) junction to ambient (note 2) r ja 670 490 c/w mun5114dw1 (sot ? 363) both junction heated (note 3) total device dissipation t a = 25 c (note 1) (note 2) derate above 25 c (note 1) (note 2) p d 250 385 2.0 3.0 mw mw/ c thermal resistance, (note 1) junction to ambient (note 2) r ja 493 325 c/w thermal resistance, (note 1) junction to lead (note 2) r jl 188 208 c/w junction and storage temperature range t j , t stg ? 55 to +150 c nsba114ydxv6 (sot ? 563) one junction heated total device dissipation t a = 25 c (note 1) derate above 25 c (note 1) p d 357 2.9 mw mw/ c thermal resistance, junction to ambient (note 1) r ja 350 c/w nsba114ydxv6 (sot ? 563) both junction heated (note 3) total device dissipation t a = 25 c (note 1) derate above 25 c (note 1) p d 500 4.0 mw mw/ c thermal resistance, junction to ambient (note 1) r ja 250 c/w junction and storage temperature range t j , t stg ? 55 to +150 c nsba114ydp6 (sot ? 963) one junction heated total device dissipation t a = 25 c (note 4) (note 5) derate above 25 c (note 4) (note 5) p d 231 269 1.9 2.2 mw mw/ c thermal resistance, (note 4) junction to ambient (note 5) r ja 540 464 c/w nsba114ydp6 (sot ? 963) both junction heated (note 3) total device dissipation t a = 25 c (note 4) (note 5) derate above 25 c (note 4) (note 5) p d 339 408 2.7 3.3 mw mw/ c thermal resistance, (note 4) junction to ambient (note 5) r ja 369 306 c/w junction and storage temperature range t j , t stg ? 55 to +150 c 1. fr ? 4 @ minimum pad. 2. fr ? 4 @ 1.0 x 1.0 inch pad. 3. both junction heated values assume total power is sum of two equally powered channels. 4. fr ? 4 @ 100 mm 2 , 1 oz. copper traces, still air. 5. fr ? 4 @ 500 mm 2 , 1 oz. copper traces, still air. mun5114dw1, nsba114ydxv6, nsba114ydp6 http://onsemi.com 3 electrical characteristics (t a = 25 c, common for q 1 and q 2 , unless otherwise noted) characteristic symbol min typ max unit off characteristics collector ? base cutoff current (v cb = 50 v, i e = 0) i cbo ? ? 100 nadc collector ? emitter cutoff current (v ce = 50 v, i b = 0) i ceo ? ? 500 nadc emitter ? base cutoff current (v eb = 6.0 v, i c = 0) i ebo ? ? 0.2 madc collector ? base breakdown voltage (i c = 10 a, i e = 0) v (br)cbo 50 ? ? vdc collector ? emitter breakdown voltage (note 6) (i c = 2.0 ma, i b = 0) v (br)ceo 50 ? ? vdc on characteristics dc current gain (note 6) (i c = 5.0 ma, v ce = 10 v) h fe 80 140 ? collector ? emitter saturation voltage (note 6) (i c = 10 ma, i b = 0.3 ma) v ce(sat) ? ? 0.25 vdc input voltage (off) (v ce = 5.0 v, i c = 100 a) v i(off) ? 0.7 ? vdc input voltage (on) (v ce = 0.2 v, i c = 1.0 ma) v i(on) ? 0.9 ? vdc output voltage (on) (v cc = 5.0 v, v b = 2.5 v, r l = 1.0 k ) v ol ? ? 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.5 v, r l = 1.0 k ) v oh 4.9 ? ? vdc input resistor r1 7.0 10 13 k resistor ratio r 1 /r 2 0.17 0.21 0.25 6. pulsed condition: pulse width = 300 msec, duty cycle 2%. figure 1. derating curve ambient temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0 50 100 150 200 250 400 p d , power dissipation (mw) 150 (1) (2) (3) (1) sot ? 363; 1.0 x 1.0 inch pad (2) sot ? 563; minimum pad (3) sot ? 963; 100 mm 2 , 1 oz. copper trace 350 300 mun5114dw1, nsba114ydxv6, nsba114ydp6 http://onsemi.com 4 typical characteristics mun5114dw1, nsba114ydxv6 1000 100 10 1 figure 2. v ce(sat) vs. i c 10 02030 i c , collector current (ma) 40 50 figure 3. dc current gain figure 4. output capacitance 01020 50 i c , collector current (ma) i c , collector current (ma) figure 5. output current vs. input voltage 100 10 1 0.1 0.01 0.001 012 34 v in , input voltage (v) 56 7 figure 6. input voltage vs. output current v r , reverse voltage (v) v ce(sat) , collector ? emitter voltage (v) i c /i b = 10 ? 55 c 150 c 25 c h fe , dc current gain f = 10 khz i e = 0 a t a = 25 c c ob , output capacitance (pf) v o = 5 v 150 c ? 55 c 25 c i c , collector current (ma) v o = 0.2 v v in , input voltage (v) 25 c 1 0.1 0.01 40 30 0.1 1 100 10 v ce = 10 v 25 c 150 c ? 55 c 10 010 20304050 100 10 1 0.1 150 c ? 55 c 9 8 7 6 5 4 3 2 1 0 mun5114dw1, nsba114ydxv6, nsba114ydp6 http://onsemi.com 5 typical characteristics nsba114ydp6 1000 100 10 1 figure 7. v ce(sat) vs. i c 10 02030 i c , collector current (ma) 40 50 figure 8. dc current gain figure 9. output capacitance 01020 50 i c , collector current (ma) i c , collector current (ma) figure 10. output current vs. input voltage 100 10 1 0.1 0.01 0.001 01 2 3 4 v in , input voltage (v) 567 figure 11. input voltage vs. output current v r , reverse voltage (v) v ce(sat) , collector ? emitter voltage (v) i c /i b = 10 ? 55 c 150 c 25 c h fe , dc current gain f = 10 khz i e = 0 a t a = 25 c c ob , output capacitance (pf) v o = 5 v 150 c ? 55 c 25 c i c , collector current (ma) v o = 0.2 v v in , input voltage (v) 25 c 1 0.1 0.01 40 30 0.1 1 100 10 v ce = 10 v 25 c 150 c ? 55 c 7 010 20304050 100 10 1 0.1 150 c ? 55 c 6 5 4 3 2 1 0 11 10 11 12 mun5114dw1, nsba114ydxv6, nsba114ydp6 http://onsemi.com 6 package dimensions sc ? 88/sc70 ? 6/sot ? 363 case 419b ? 02 issue w notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. 419b ? 01 obsolete, new standard 419b ? 02. e 0.2 (0.008) mm 123 d e a1 a a3 c l 654 ? e ? b 6 pl dim min nom max millimeters a 0.80 0.95 1.10 a1 0.00 0.05 0.10 a3 b 0.10 0.21 0.30 c 0.10 0.14 0.25 d 1.80 2.00 2.20 0.031 0.037 0.043 0.000 0.002 0.004 0.004 0.008 0.012 0.004 0.005 0.010 0.070 0.078 0.086 min nom max inches 0.20 ref 0.008 ref h e h e e 1.15 1.25 1.35 e 0.65 bsc l 0.10 0.20 0.30 2.00 2.10 2.20 0.045 0.049 0.053 0.026 bsc 0.004 0.008 0.012 0.078 0.082 0.086 mm inches scale 20:1 0.65 0.025 0.65 0.025 0.50 0.0197 0.40 0.0157 1.9 0.0748 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* sc ? 88/sc70 ? 6/sot ? 363 mun5114dw1, nsba114ydxv6, nsba114ydp6 http://onsemi.com 7 package dimensions h e dim min nom max millimeters a 0.50 0.55 0.60 b 0.17 0.22 0.27 c d 1.50 1.60 1.70 e 1.10 1.20 1.30 e 0.5 bsc l 0.10 0.20 0.30 1.50 1.60 1.70 0.020 0.021 0.023 0.007 0.009 0.011 0.059 0.062 0.066 0.043 0.047 0.051 0.02 bsc 0.004 0.008 0.012 0.059 0.062 0.066 min nom max inches sot ? 563, 6 lead case 463a issue f e m 0.08 (0.003) x b 6 5 pl a c ? x ? ? y ? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. d e y 12 3 4 5 l 6 1.35 0.0531 0.5 0.0197 mm inches scale 20:1 0.5 0.0197 1.0 0.0394 0.45 0.0177 0.3 0.0118 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h e 0.08 0.12 0.18 0.003 0.005 0.007 mun5114dw1, nsba114ydxv6, nsba114ydp6 http://onsemi.com 8 package dimensions sot ? 963 case 527ad issue e dim min nom max millimeters a 0.34 0.37 0.40 b 0.10 0.15 0.20 c 0.07 0.12 0.17 d 0.95 1.00 1.05 e 0.75 0.80 0.85 e 0.35 bsc 0.95 1.00 1.05 h e e d c a h e 123 4 5 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e do not include mold flash, protrusions, or gate burrs. x y top view side view e b x 0.08 6x y bottom view 6x 0.35 pitch 1.20 0.20 dimensions: millimeters recommended package outline mounting footprint l 0.19 ref l2 0.05 0.10 0.15 l 6x l2 6x 6x 0.35 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 dta114yd/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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