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clo c k distribution - s m t 1 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz functional diagram typical applications features general description t he hmc988 l p3e is ideal for: ? b asestation digital pre-distortion paths(dpd) ? high performance automated t est equipment(a t e) ? b ackplane clock skew management ? phase coherence of multiple clock paths ? clock delay management to improve setup & hold time margins ? pc b signal fight time offset circuits ? t rack and hold circuits for adc/dacs dc - 4 ghz -170 d b c/hz foor @ 100 mhz output -164 d b c/hz foor @ 2 ghz output i ntegrated jitter 35 fs r ms @ 100 mhz output 13 fs r ms (calculated) @ 2 ghz output adjustable output phase with soft/hard reset sync adjustable output delay in 60 steps of 20 ps flexible i nput i nterface: l vpec l , l vd s ,cm l ,cm os compatible ac or dc coupling o n - chip t ermination 50 ? (100 ? differential) o utput driver ( l vpec l ): 800 mvpp l vpec l into 50 ? s ingle-ended (+3 d b m fo) u p to 8 addressable dividers per s p i bus 3.3 v operation or 5 v operation with o ptional on- chip regulator for best performance 3 x 3 qf n l eadless s m t package t he hmc988 l p3e is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32. i t is a versatile device with additional functionality including adjustable output phase, adjustable delay in 60 steps of ~ 20 ps, a clock synchronization function, and a clock invert option. housed in a compact 3x3 mm s m t qfn package, the clock divider offers a high level of functionality. t he device works with 3.3 v supply or may be connected to 5 v supply and utilize the optional on-chip regulator. t his on-chip regulator may be bypassed. u p to 8 addressable hmc988 l p3e devices can be used together on the s p i bus. t he hmc988 l p3e is ideally suited for data converter applications with extremely low phase noise requirements. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 2 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz table 1. electrical specifcations u nless otherwise specifed: t = +25 c. current consumptions assumes fne adjustable delay is disabled. phase noise degrades approximately 15 d b if using fne delay adjustment. parameter conditions min t yp. max u nits i nput frequency r ange dc 4 ghz o utput frequency r ange dc 4 ghz divide r atios 1/2/4/8/16/32 maximum fine delay adjust frequency dc 1 ghz vdd with on-chip regulator +3.7 +4.5 +5.5 v vdd bypass on-chip regulator +3.1 +3.3 +3.5 v i nput s wing ( l vpec l or acc) +2 vpp o utput s wing ( l vpec l ) +1.8 (single-ended) vpp +1.2 (diffiential) vppd r ise/fall t ime ( l vpec l out ) 20%/80% 90 ps i nput commom mode dc b ias +1.6 +2 +2.5 v o utput common mode voltage +2 v phase n oise (100 mhz) [1] @ 100 mhz out @ 500 mhz out @ 1 ghz out @ 2 ghz out -170 -168 -166 -164 d b c/hz jitter density [2] @ 100 mhz out @ 500 mhz out @ 1 ghz out @ 2 ghz out 7.12 1.8 1.13 2.84 asec/hz i ntegrated jitter [3] @ 100 mhz out @ 500 mhz out [4] @ 1 ghz out [4] @ 2 ghz out [4] 35 9 5 13 fsec f o m (figure of merit) -254 d b c/hz coarse delay adjustment r ange 1/2 to * t in p ut i nput cycles fine delay adjustment r ange 60 steps of ~ 20 ps 300 1500 ps fine delay adjjustment r esolution 20 ps fine delay adjustment s tep count 60 p srr [5] with r egulator am -70 -80 db c pm -80 -92 db c b ypass r egulator am -40 -50 db c pm -50 -70 db c current consumption s tand-by current - chip disabled using r egulator case 0.7 ma bypass r egulator case 0.01 ma mininum current [6] 68 ma additive divider 16 21 ma delay l ine current 12 44 ma for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 3 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz table 1. electrical specifcations u nless otherwise specifed: t = +25 c. current consumptions assumes fne adjustable delay is disabled. phase noise degrades approximately 15 d b if using fne delay adjustment. parameter conditions min t yp. max u nits l vpec l t ermination l oad current 26 40 ma propagation delay delay l ine disabled 210 ps delay vs t emp 250 mhz ( s etpoint 15) 350 fs/ c 1 ghz ( s etpoint 15) 150 fs/ c [1] phase noise performance is characterized using the hmc1034 as a source at ~2 ghz, 9 d b m differential. for sinusoidal low-frequency inputs, the phase noise may degrade. for example, a single-ended 100 mhz 9 d b m sin-wave in bypass mode produces a phase noise foor of -164 d b c/ hz as opposed to -170 d b c/hz. [2] t o calculate jitter density, (10^((floor phase noise)/20)/2)*(1/frequency) i.e jitter density@ 500 mhz = (10^(-168/20)/2)*(1/500000000) [3] i ntegrated b andwidth start from 12 k hz to 20 mhz, jitter density x desired customized b w i.e integrated jitter @ 2 ghz over a 6 ghz b w = 2.84 asec/hz x 6 ghz 1asec = 1/1000 of a femtosecond, only 100 mhz number is meaured with 100 mhz wenzel and hmc988 in bypass mode [4] t hese integrated jitter number are based on calculation [5] s pur caused by 100 mvpp agressor tone on input supply. t his specifcation is the level of the ssb spur which appears symmetrically around the output frequency when the input supply stimulated by a 100 mvpp aggressive tone @ 30 khz. t he spur level is linearly proportional to the aggres - sor tone amplitude. i t is relatively independent of input and output frequencies, and input power level. when regulated, at least 3.7 v must be applied to the input power supply to provide sufficient p srr . t he spur level is not appreciably different for single ended or differential operation. t he frequency response to the aggressive tone is fat from 1 khz to 50 khz offset. above 50 khz the solution p srr improves strongly, but is largely dependant on board decoupling capacitance and is not a direct indication of the raw part performance. [6] when divider is bypassed,no termination loads and delay line disabled case. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 4 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz typical performance characteristics u nless otherwise specifed: t = 27 c, r egulated vdd = 3.3 v, 1.5 ghz, 6 d b m in, ac coupled single ended input and output, 120 ?/leg dc termination, ac coupled into 50 ? measuring load. figure 1. phase noise performance vs divider ratio at 1.5 ghz div 1/2/4/8/16 -200 -180 -160 -140 -120 -100 1 10 100 1000 10000 100000 source div 1(bypass) div 2 div 4 div 8 div 16 offset (khz) phase noise (dbc/hz) figure 2. phase noise performance vs temperature at 1.5 ghz div 2 figure 3. phase noise floor performance vs input swing -170 -165 -160 -155 -150 -145 -140 -135 -130 1 10 100 1000 10000 100mhz bypass single-ended 1500mhz div 2 single-ended 1500mhz div 2 differential input swing (mvpp) phase noise (dbc/hz) figure 4. phase noise floor performance vs output frequency [1] -170 -168 -166 -164 -162 100 1000 output frequnecy (mhz) phase noise (dbc/hz) 3000 instrument noise floor bypass divide by 2 divide by 4 divide by 8 figure 5. vout vs frequency over temperature [2] 0 0.5 1 1.5 2 2.5 0.1 1 7 27c 85c -40c output level (vpp) output frequency (ghz) figure 6. delay vs delay line setpoint [3] [1] measured differential input and out at various frequencies. u nder 300 mhz, the measurment is restricted by the instrument. [2] measured single-ended. 120 ? dc termination, 3.3 v 1 +6 d b m single-ended input. hmc988 l p3e ac coupled to 50 ? instrument with divider bypass [3] corrected for board delay 210 ps for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com -170 -160 -150 -140 -130 -120 -110 1 10 100 1000 10000 100000 27c 85c -40c offset (khz) phase noise (dbc/hz) 0 500 1000 1500 2000 0 13 26 39 52 150 mhz 1000 mhz delay (ps) delay line setting 60 delay off 210
clo c k distribution - s m t 5 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz figure 7. s-parameters-s22 [4] figure 8. s-parameters-s11 [4] -20 -15 -10 -5 0 100000 1000000 s22(single-ended) s22(differnetial) power (db) frequency (khz) 5e+06 -40 -35 -30 -25 -20 -15 -10 -5 0 1e+5 1e+6 s11(single-ended) s11(differnetial) power (db) frequency (khz) 5e+6 figure 9. input sensitivity [5] 0 20 40 60 80 100 120 140 160 180 200 012345 input power level (mvpp) input frequency (ghz) recommended operating region figure 10. supply voltage vs input voltage [6] 2.6 2.8 3 3.2 3.4 3.6 vout(regulated) vout(non regulated) 3 3.5 4 4.5 5 5.5 vout (v) vin (v) figure 11. time domain 1 ghz input, 500 mhz output [7] -400 -300 -200 -100 0 100 200 300 400 0 500 1000 1500 2000 2500 3000 3500 4000 amplitute (mvpp) time (ps) 210 [4] measured with 200 ? dc termination, 10 ? series resistor in front, ac couple 1 nf 3.3 v [5] measured single-ended. 120 ? dc termination, 3.3 v hmc988 l p5e ac coupled to 50 ? instrument(d so 8104 b ) with divider bypass. e s d diode will start to turn on if maximum input power exceeds 12 d b m. [6] o n chip regulator enable mode measured at p in cap_3v vs regulator bypass mode [7] measured with 1 ghz 400 mvpp source as single ended input, hmc988 l p3e div 2. b oard delay 210 ps for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 6 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz table 1. pin descriptions table 2. pin descriptions pin n umber function description 1,4,5 ch i p0, ch i p1, ch i p2 chip s p i address 2,3 os cp, os c n differential s ignal i nput 6 gp o general purpose o utput pin & s erial data o ut 7 s di s erial data i nput 8 sc k s erial data clock 9 sl e s erial data l atch enable 10,11 di vn , d i vp differential o utput s ignal 12 vdd3_decap decoupling point for internally generated supply 13 tri g external s y n c or sli p control pin for slip/synchronization start 14 f b _decap decoupling point for regulator 15 b gap_decap decoupling point for regulator 16 vdd5 r egulator i nput s upply voltage for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 7 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz table 3. absolute maximum ratings parameter r ating max vdd to paddle on suply pin -0.3 v to +5.5 v os cp, os c n max r f power 13 d b m os cp, os c n differential dc -0.3 v to 3.6 v l vpec l min o utput l oad r esistor 100 ? to g nd l vpec l o utput l oad current 40 ma/leg digital l oad 1 k ? min digital i nput voltage r ange -0.3 v to 3.6 v t hermal r esistance (jxn to gnd paddle) 25 0 c/w o perating t emperature r ange -40 o c to +85 o c s torage t emperature r ange -65 o c to + 125 o c maximum junction t emperature +125 o c r efow s oldering peak t emperature 260 o c t ime at peak t emperature 40 sec e s d s ensitivity h b m class 1c s tresses above those listed under absolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 8 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz outline drawing not e s : [1] pac k age bo dy ma t e ri a l : lo w str e ss in jec tion m ol ded p l a sti c sili ca a n d sili c on i mp r eg n a t ed. [2] l ead a n d g roun d padd l e ma t e ri a l : c o ppe r a llo y. [3] l ead a n d g roun d padd l e p l a tin g: 100% ma tt e tin . [4] d i me nsions a r e in in che s [m illi me t e rs ]. [5] l ead s pac in g tol er a n ce is non -c u m ul a ti ve. [6] pad burr l e n g t h s ha ll b e 0.15 mm max. pad burr he i gh t s ha ll b e 0.05 mm max. [7] pac k age wa r p s ha ll not exceed 0.05 mm [8] a ll g roun d l ead s a n d g roun d padd l e m ust b e sol de r ed to pc b r f g roun d. [9] r efe r to h ittit e app li ca tion not e f or su gge st ed pc b l a n d pa tt e rn . table 4. package information part n umber package b ody material l ead finish m sl r ating package marking [1] hmc988 l p3e r oh s -compliant l ow s tress i njection molded plastic 100% matte s n m sl 1 [2] h988 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260 c for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 9 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz evaluation pcb t he circuit board used in the application should use r f circuit design techniques. s ignal lines should have 50 ? impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. t he evaluation circuit board shown is available from hittite upon request. evaluation pcb schematic to view this evaluation pc b s chematic please visit www.hittite.com and choose HMC988LP3E from the search by part number pull down menu to view the product splash page. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 10 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz table 5. evaluation order information i tem contents part n umber evaluation pc b o nly hmc988 l p3e evaluation pc b eva l 01-hmc988 l p3e evaluation k it hmc988 l p3e evaluation pc b usb i nterface b oard 6 usb a male to usb b female cable cd ro m (contains u ser manual, evaluation pc b s chematic, evaluation s oftware, hittite p ll design s oftware) e kit 01-hmc988 l p3e for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 11 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz theory of operation i n addition to hmc988 l p3e excellent low noise performance, the device offers additional functionality including: modular confguration s ynchronization function adjustable fine delay adjustable coarse delay t rigger o ptions o ptional o n-chip r egulator gp o modular confguration t he hmc988 l p3e has been designed so that up to 8 devices can be placed on one s p i bus. t he part has a 3-bit addressable chip addresses (ch i p0 pin, ch i p1 pin, ch i p2 pin) so that each chip can be controlled individually. i n addition, hmc988 l p3e has a broadcast mode which allows up to 8 hmc988 l p3e devices to be simultaneously controlled, or triggered. i n b roadcast mode each hmc988 l p3e device will listen to the same chip address, namely 111. t ypical application of hmc988 l p3e is shown in figure 1. figure 1. typical application of HMC988LP3E for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 12 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz although the hmc988 l p3e has only 8 s p i chip addresses, one of which (111) is used in the broadcast mode, it is still possible to use broadcast mode and control 8 hmc988 l p3e devices on one s p i bus, according to the following procedure: communicate with frst 7 hmc988 l p3e devices in a standard s p i mode. s elect their chip addresses and write to the registers of interest. 1. after communicating with frst 7 devices, with chip addresses ranging from (000 to 110), ensure that b roadcast mode for all of them is disabled by writing to r eg04h[0] = 0 to each device. 2. communicate with the 8th device, with chip addresses (111) in standard mode. t he rest of the devices will not be listening because their b roadcast mode is disabled ( r eg04h[0] = 0). 3. i f a broadcast to all devices on the s p i bus is required, b roadcast mode needs to be enabled ( r eg04h[0] = 1) for each device separately. after the b roadcast mode is enabled in each device, the s p i controller can write to the s p i bus in a standard way while selecting chip address (111). all of the hmc988 l p3e devices will be listening. synchronization function i f the hmc988 l p3e is used in a typical application as shown in figure 1 , it may be advantageous for some or all of the outputs to be synchronized. t he hmc988 l p3e can accomplish this using its s y n c functionality. as shown in figure 2 , the s ync function ensures that all outputs launch synchronously, a number of input cycles after the the s y n c function is triggered. t he delay, measured in the number of input cycles, is governed by equation 1 where x is the number of input cycles and n is the divide ratio selection ( r eg02h[2:0] ) of hmc988 l p3e. 1 if n = 1 n 1 if n > 1 2 x ?? ?? = ?? ?? + ?? ?? ?? ?? figure 2. HMC988LP3E sync function timing diagram eq (1) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 13 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz adjustable coarse delay t he hmc988 l p3e provides the option to delay the output one cycle of the input signal using its sli p function. t his function in essence prevents the input signal from cycling for 1 period and causes a corresponding phase shift in the output signal. t iming diagram of the execution of the s lip function is show in figure 3 . i n addition, the hmc988 l p3e allows the user to select the launch phase of the output signal relative to the input signal by programming r eg06h[2] . when this functionality is used in conjunction with the s lip function, it allows the user to adjust the delay/phase of the output signal, in increments of half period of the input signal. example of a half period delay is shown in. figure 4. i n order to achieve the half period delay, the hmc988 l p3e delays the output by one full period of the input signal, by using the sli p function, then r eg06h[2] value is changed from 1 (rising edge) to 0 (falling edge) and the output is effectively sped up by half cycle of the input, resulting in a total delay of one half of the period of the input signal. s imilar methodology can be deployed to delay the output signal by x.5 or more cycles, in effect the user would deploy the s lip function to x+1 times and then switch the trigger from rising edge to falling edge to achieve a total delay of x.5. figure 3. HMC988LP3Es slip function timing diagram for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 14 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz adjustable fine delay i n addition to the 1/2 cycle delay offered by the slip function, the output of the hmc988 l p3e can be delayed in ~20 ps steps, by programing r eg07h[5:0] . anywhere from 0 to 60. t he delay function follows equation 2. delay (reg07h) 20ps + 300ps ? at higher frequencies (> 200 mhz), the step size compresses near the high end of the range when using the fne delay. please note that the phase noise can degrade by 15 d b . trigger details i n hmc988 l p3e, the s ync and the s lip functions can both be implemented using the external tri g pin or by using the s p i interface. t he circuit diagram for s y n c and sli p controls pins is shown in figure 5 . n ote that the s y n c and sli p should not be applied at the same time. figure 4. delay by 1/2 of input clock cycle timing diagram eq (2) figure 5. sync/slip circuit diagram for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 15 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz executing sync/slip using external pin i n order to execute s y n c or sli p function using the external pin, simply assert the external tri g pin of the hmc988 l p3e. t he functions will trigger on the rising edge of the external s y n c or sli p pin . n ote that the corresponding s y n c or sli p external trigger awareness function needs to be enabled in the hmc988 l p3e. n ote that r eg04h[1] and r eg04h[2] should never be equal to 1 at the same time. if 1 is written to r eg04h[1] , than 0 needs to be written to r eg04h[2] , and vice-versa. execute sync/slip using the spi interface pin 9, s erial l atch enable ( sl e), of the hmc988 l p3e causes s p i bits to change states and therefore acts as a trigger if the s y n c and sli p functions are chosen to be executed using the s p i interface. n ote that the s y n c signal is level sensitive, and must remain 1 in order to keep the internal divider running. t he slip signal is rising-edge sensitive, and must be returned low at some point before the next trigger. optional on-chip regulator t he hmc988 l p3e has an optional on-chip regulator that can be used or bypassed. t he regulator requires an input voltage 3.8 v. t he on-chip regulator circuit is shown in figure 6 . t he regulator can be bypassed by programing r eg04h[5] = 1. i n that case identical voltage should be applied to input of the regulator (vdd5) and vdd3_decap. gpo t he hmc988 l p3e has a gp o (general purpose o utput) pin that can be used for obtaining various internal states of the device (many of which are only used for internal testing), or as an s p i output. t he function of the gp o pin is confgured in r eg05h. figure 6. regulator circuit diagram for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 16 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz HMC988LP3E input stage t he hmc988 l p5e input stage, figure 7 , is fexible. i t can be driven single-ended or differential, with l vpec l , l vd s , or cm l signals. i f driven single-ended, a large ac coupling cap to ground should be used on the undriven input. t he input impedance is 50 single-ended (100 differential). t he dc bias level of 2.0 v can be generated internally by programming r eg04h[3] = 0 (default confguration), supplied externally, or generated via an l vpec l termination network inside the part. figure 7. HMC988LP3E input stage for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 17 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz HMC988LP3E output stage t he l vpec l output driver produces up to 1.6 vppd swing into 50 loads. l vpec l drivers are terminated with off-chip resistors that provide the dc current through the emitter-follower output stage. t he output stage has a switch which disconnects the output driver from the load when not used. t he switch series resistor signifcantly improves the output match when driving into 50 transmission lines. t he switch series resistor causes a small dc level shift and swing degradation, depending on the termination current. i f unused, disabled l vpec l outputs can be left foating, terminated, or grounded. figure 8. HMC988LP3E output stage for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 18 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz serial port write operation table 6. spi open mode - write timing characteristics parameter conditions min. t y p. max. units t 1 t2 t3 t4 t5 t 6 sdi setup time sdi hold time sen low duration sen high duration sclk 9 r ising edge to sen rising edge s erial port clock speed sen to sclk r ecovery t ime 3 3 10 10 10 dc 10 50 ns ns ns ns ns mhz ns a typical w rit e cycle is shown in figure 9 . a. t he master (host) places 9 bit data, d8:d0, m sb frst, on s d i on the frst 9 falling edges of s c lk . b. t he slave () shifts in data on s d i on the frst 9 rising edges of s c lk c. master places 4 bit register address to be written to, r3:r0, m sb frst, on the next 4 falling edges of s c lk (10 -13) d. s lave shifts the register address bits on the next 4 rising edges of s c lk (10-13). e. master places 3 bit chip address, a2:a0, m sb frst, on the next 3 falling edges of s c lk (14-16). f. s lave shifts the chip address bits on the 3 rising edges of s c lk (14-16). g. master asserts s e n after the 16th rising edge of s c lk . h. s lave registers the s d i data on the rising edge of s e n . figure 9. s p i t iming diagram, write o peration serial port read operation i n order ensure correct read operation a pull-down resistor to ground (~1-2k o hm) is recommended on the s erial data o ut line from the part. a typical r ead cycle is shown in figure 10 . i n general, s d o line is always active during the w rit e cycle. s d o will contain the data from the addresses pointed to by r eg00h . i f r eg00h is not changed, the same data will always be present on the s d o . i f it is desired to r ead from a specifc address, it is necessary in the frst s p i cycle to write the desired address to r eg00h , then in the next s p i cycle the desired data will be available on the s d o . an example of the two cycle procedure to read from any random address is as follows: for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 19 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz t he master (host), on the frst 9 falling edges of s c lk places 9 bit data, d8:d0, m sb frst, on s d i as shown in figure 10 . d8:d0 should be set to zero. d3:d0 = address of the register to be r ead on the next cycle. a. t he slave () shifts in data on s d i on the frst 9 rising edges of s c lk b. master places 4 bit register address , r3:r0, ( the address the w rit e add r e ss register), m sb frst, on the next 4 falling edges of s c lk (10-13). r3:r0=0000. c. s lave shifts the register bits on the next 4 rising edges of s c lk (10-13). d. master places 3 bit chip address, a2:a0, m sb frst, on the next 3 falling edges of s c lk (14-16). e. s lave shifts the chip address bits on the next 3 rising edges of s c lk (14-16). f. master asserts s e n after the 16th rising edge of s c lk . g. s lave registers the s d i data on the rising edge of s e n . h. master clears s e n to complete the address transfer of the two part r ead cycle. i. i f we do not wish to write data to the chip at the same time as we do the second cycle , then it is recommended to simply rewrite the same contents on s d i to r egister zero on the r ead back part of the cycle. j. master places the same s d i data as the previous cycle on the next 16 falling edges of s c lk . k. s lave () shifts the s d i data on the next 16 rising edges of s c lk . l. s lave places the desired data (i.e. data from address in r eg00h [3:0]) on s d o on the next 16 rising edges of s c lk . m. master asserts s e n after the 16th rising edge of s c lk to complete the cycle. n ote that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the s d o output to prevent a possible bus contention issue. table 7. spi open mode - read timing characteristics parameter conditions min. t y p. max. units t 1 t2 t3 t4 t5 t6 t7 sdi setup time sdi hold time sen low duration sen high duration sclk r ising edge to sdo time sen to sclk r ecovery t ime sclk 16 r ising edge to sen rising edge 3 3 10 10 10 10 8.2+0.2ns/ pf ns ns ns ns ns ns ns for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 20 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz figure 10. spi diagram, read operation 2- cycles for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 21 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz register map table 8. reg 00h - id register (read only) b it n ame width default description [3:0] r ead control 4 (write o nly) [4] s oft r eset [4:0] chip i d ( r ead o nly) table 9. reg 01h - enables b it n ame width default description [0] master chip enable 1 1 [1] r x b uffer enable 1 1 [2] divider core enable 1 1 [3] o utput buffer enable 1 1 [8:4] r eserved 5 0 table 10. reg 02h - divide/delay select b it n ame width default description [2:0] divide r atio s elect 2 2 0: b ypass 1: /2 2: /4 3: /8 4: /16 5: /32 6: n /a 7: n /a [8:3] r eserved 6 0 table 11. reg 03h - bias b it n ame width default description [1:0] r eserved 2 2 [3:2] r eserved 2 2 [5:4] t ransmit b uffer s wing s elect 2 2 0: 1.2 vppd 1: 1.6 vppd 2: 2 vppd 3: 2.7 vppd [8:6] s y n c delay adjustment 3 3 can be used to equalize s y n c delay between dividers. 1000+(0-7)*80 ps for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
clo c k distribution - s m t 22 HMC988LP3E v01.0512 programmable clock divider and delay dc - 4 ghz table 12. reg 04h - confguration b it n ame width default description [0] b roadcast mode 1 0 if 1, a write to chip addr 111 will be listened to by all slaves. u seful for synchronizing multiple dividers [1] external s y n c pin e n 1 1 external pin can be used to start-up divider synchronously. [2] external sli p pin e n 1 0 external pin can be used to slip divider synchronously b oth ext sli p and ext s y n c bits should not be 1 at the same time [3] r x b uffer dc b ias s elect 1 0 u se 1 for sinusoidal / non- l vpec l ac coupled inputs [4] delay l ine enable 1 0 u se 0 for natural low-noise path, 1 enables the fne delay [5] o n-chip r egulator b ypass 1 0 1 bypass the on-chip regulator, 0 enable the on-chip regulator [8:6] r eserved 3 0 table 13. reg 05h - general purpose output b it n ame width default description [2:0] gp o s elect 2 0 0: 0 1: 1 2: slip req 3: 0 4: sync req 5: sync delayed 6: waiting for clock pulse (post sync) 7: spare [3] force gp o pin on gp o only 1 0 no automux to serial data output [4] force gp o pin on s d o only 1 0 no automux to gp o selected data p riorit y [5] force gp o pin to hiz 1 0 force gp o pin to hiz [8:6] r eserved 3 0 table 14. reg 06h - spi triggers b it n ame width default description [0] s p i s y n c s ignal 1 1 0 - holds divider in reset, 1 allows startup [1] s p i sli p s ignal 1 0 a 0 to 1 level change is sensed by the input clock, and causes a full input cycle-slip. t he signal must be maintained for > 4 t vco input clock cycles before brought low. [2] o utput l aunch phase 1 0 0: falling edge (early) 1: r ising edge ( l ate) t o delay the output by 1/2 cycle you can switch from early to late. t o go back, you must force n -1 full cycle slips, and switch back from late to early. [8:3] r eserved 6 0 table 15. reg 07 - delay lines b it n ame width default description [5:0] delay l ine s etpoint 6 4 delay = s etpoint *20 ps + 300 ps (max of 300 -> 1500 ps) [8:6] r eserved 3 0 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com

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