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data sheet MPC92439 revision 4 october 27, 2009 1 ?2009 integrated device technology, inc. 900mhz, low voltage, lvpecl clock syntheesizer MPC92439 the MPC92439 is a 3.3 v compatible, pll ba sed clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. with output fre quencies from 3.125 mhz to 900 mhz and the support of differential lvpecl output signals the device meets the needs of the most demanding clock applications. features ? 3.125 mhz to 900 mhz synthesized clock output signal ? differential lvpecl output ? lvcmos compatible control inputs ? on-chip crystal oscillator for reference frequency generation ? alternative lvcmos compatible reference input ? 3.3v power supply ? fully integrated pll ? minimal frequency overshoot ? serial 3-wire programming interface ? parallel programming interface for power-up ? 28-plcc and 32-lqfp packaging ? 28-lead and 32-lead pb-free packages available ? sige technology ? ambient temperature range 0 c to + 70 c ? pin and function compatible to the mc12439 and mpc9239 functional description the internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. the frequency of the internal crystal oscillator or external reference clock signal is multiplied by the pll. the vco within the pll operates over a range of 400 to 900 mhz. its output is scaled by a divider that is configured by either the serial or parallel interfaces. the crystal oscillator frequency f xtal , the pll feedback-divider m and the pll post-divider n de- termine the output frequency. the feedback path of the pll is internal. the pll adjusts the vco output frequency to be m times the reference frequency by adjustin g the vco control voltage. note that for some values of m (either too high or too lo w) the pll will not achieve phase lock. the pll will be stable if the vco frequency is within the specified vco frequency range (400 to 900 mhz). the m-value must be programmed by the serial or parallel interface. the pll post-divider n is configured through ei ther the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). this divi der extends performance of the part while providing a 50% duty cycle. th e output driver is driven differentially from the output divider, and is capable of drivin g a pair of transmission lines terminated 50 ? to v cc ? 2.0v. the positive supply voltage for the internal pll is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. the configuration logic has two sections: serial and parallel. the parallel interface uses the values at the m[6:0] and n[ 1:0] inputs to configure the in ternal counters. it is recom- mended on system reset to hold the p_load input low until power becomes valid. on the low-to-high transition of p_load , the parallel inputs are captured. the parallel interface has priority over the serial in terface. internal pullup resistor s are provided on the m[6:0] and n[1:0] inputs prevent the lvcmos compatible co ntrol inputs from floating. the serial inter- face centers on a twelve bit shift register. the shift register shifts once per rising edge of the s_clock input. the serial input s_data must meet setup and hold timing as specified in the ac characteristics section of this docum ent. the configuration latches will capture the value of the shift register on the high -to-low edge of the s_load input. see programming interface for more information. the test output reflects various internal node values, and is controlled by the t[2:0] bits in the serial data stream. in order to minim ize the pll jitter, it is recommended to avoid active signal on the test output. the pw r_down pin, when asserted, will synchronously divide the fout b y 16. the power down sequence is clocked by the pll reference clock, thereby causing the frequency reduction to happen relatively slo wly. upon de-assertion of the pwr_down pin, the fo ut input will step back up to its programmed frequency in four discrete increments. pr o pose d 900mhz low voltage clock synthesizer ordering information device package MPC92439ei plcc-28 (pb-free) MPC92439fa lqfp-32 MPC92439ac lqfp-32 (pb-free) MPC92439klf vfqfn-32 (pb-free) k suffix 32-lead vfqfn package pb-free package fn suffix (1) 28-lead plcc package case 776-02 ei suffix (2) 28-lead plcc package case 776-02 fa suffix (1) 32-lead lqfp package case 873a-03 ac suffix (2) 32-lead lqfp package case 873a-03 notes: (1) fn, fa suffix: leaded terminations (2) ei, ac suffix: lead-free, rohs-compliant, epp proposed
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 2 ?2009 integrated device technology, inc. figure 1. MPC92439 logic diagram figure 2. MPC92439 28-lead plcc pinout (top view) figure 3. MPC92439 32-lead package pinout (top view) xtal_in xtal_out s_load s_data s_clock m[0:6] xtal 11 00 01 10 m-latch n-latch 10 ? 20 mhz t-latch 2 test 3 le 0 bits 11-5 bits 3-4 bits 0-2 12-bit shift register n[1:0] oe p/s 1 2 4 8 fout test v cc v cc xtal_sel fref_ext v cc 1 0 16 1 0 pwr_down pll ref fb vco 400 ? 900 mhz 0 to 127 7-bit m-divider 7 oe 1 01 p_load fout 1 4 3 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 78 6 5 v cc xtal_out p_load oe m[0] m[1] m[2] m[3] fout gnd v cc test gnd s_clock n[1] n[0] nc xtal_sel m[6] m[5] m[4] s_data s_load v cc_pll pwr_down fref_ext xtal_in MPC92439 f out gnd test v cc v cc gnd fout nc m[3] m[2] m[1] m[0] p_load nc n1 n0 nc xtal_sel m[6] m[5] m[4] s_clock s_load v cc_pll v cc_pll power_down fref_ext xtal_in 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 v cc oe xtal_out s_data MPC92439 fout
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 3 ?2009 integrated device technology, inc. figure 4. 32-lead vf qfn package pinout (top view) 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 gnd test v cc v cc gnd fout fout v cc nc m[3] m[2] m[1] m[0] p_load oe xtal_out s_clock s_data s_load v cc_pll v cc_pll power_down fref_ext xtal_in n1 n0 nc xtal_sel m[6] m[5] m[4] nc MPC92439 p roposed
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 4 ?2009 integrated device technology, inc. table 1. pin configurations pin i/o default type function xtal_in, xtal_out 6 analog cry stal oscillator interface fref_ext input 0 lvcmos alternative pll reference input fout, fout output lvpecl differential clock output test output lvcmos test and device diagnosis output xtal_sel input 1 lvcmos pll reference select input pwr_down input 0 lvcmos configuration input for power dow n mode. assertion (deassertion) of power down will decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps. pwr_down assertion (deassertion) is sy nchronous to the input reference clock. s_load input 0 lvcmos serial configuration control input. th is inputs controls the loading of the configuration latches with the contents of the shift register . the latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. p_load input 1 lvcmos parallel configuration control input. this input controls the l oading of the configuration latches with the content of the parall el inputs (m and n). the latches will be transparent when this signal is low, thus the parallel data must be stable on the low- to-high transition of p_load . p_load is state sensitive. s_data input 0 lvcmos serial configuration data input. s_clock input 0 lvcmos serial configuration clock input. m[0:6] input 1 lvcmos parallel configuration for pll feedback divider (m). m is sampled on the low-to-high transition of p_load . n[1:0] input 1 lvcmos parallel configuration for post-pll divider (n). n is sampled on the low-to-high transition of p_load . oe input 1 lvcmos output enable (active high) the output enable is synchronous to the output cl ock to eliminate the possibility of runt pulses on the fout output. oe = l low stops fout in the logic low state (fout = l, fout = h ). gnd supply ground negative power supply (gnd). v cc supply v cc positive power supply for i/o and core. all v cc pins must be connected to the positive power supply for correct operation. v cc_pll supply v cc pll positive power suppl y (analog power supply). nc do not connect table 2. output frequency range and pll post-divider n pwr_down n vco output frequency division fout frequency range 1 0 0 0 0 2 200 - 450 mhz 0 0 1 4 100 -225 mhz 0 1 0 8 50-112.5 mhz 0 1 1 1 400-900 mhz 1 0 0 32 12.5-28.125 mhz 1 0 1 64 6.25-14.0625 mhz 1 1 0 128 3.125-7.03125 mhz 1 1 1 16 25-56.25 mhz
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 5 ?2009 integrated device technology, inc. table 3. function table input 0 1 xtal_sel fref_ext xtal interface oe outputs disabled, fout is stopped in the logic low state (fout = l, fout = h) outputs enabled pwr_down output divider 1 output divider 16 table 4. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc ? 2 v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c in input capacitance 4.0 pf inputs ja lqfp 32 thermal resistance junction to ambient jesd 51-3, single layer test board jesd 51-6, 2s2p multi-layer test board thermal resistance junction to ambient 32 vfqfn 2.5 43.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 1 37.6 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 0 33.7 c/w c/w c/w c/w c/w c/w c/w c/w c/w c/w c/w natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min meters per second jc lqfp 32 thermal resistance junction to case 23.0 26.3 c/w mil-spec 883e method 1012.1 table 5. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. exposure to these conditions or conditions beyond t hose indicated may adversely affect device reli ability. functional operat ion at absolute-maxim um-rated conditions is not implied. symbol characteristics min max unit condition v cc supply voltage ?0.3 4.6 v v in dc input voltage ?0.3 v cc + 0.3 v v out dc output voltage ?0.3 v cc + 0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature ?65 125 c proposed
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 6 ?2009 integrated device technology, inc. table 6. dc characteristics (v cc = 3.3v 5%, t a = 0c to +70c) symbol characteristics min typ max unit condition lvcmos control inputs (fref_ext, power_down, xtal_sel, p_load , s_load, s_data, s_clock, m[0:8], n[0:1]. oe) v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage 0.8 v lvcmos i in input current (1) 1. inputs have pull-down resistors affecting the input current. 200 av in = v cc or gnd differential clock output f out (2) 2. outputs terminated 50 ? to v tt = v cc ? 2v. v oh output high voltage v cc ?1.02 v cc ?0.74 v lvpecl v ol output low voltage v cc ?1.95 v cc ?1.60 v lvpecl test and diagnosis output test v oh output high voltage 2.0 v i oh = ?0.8 ma v ol output low voltage 0.55 v i ol = 0.8 ma supply current i cc_pll maximum pll supply current 20 ma v cc_pll pins i cc maximum supply current 62 110 ma all v cc pins table 7. ac characteristics (v cc = 3.3 v 5%, t a = 0c to +70c) (1) 1. ac characteristics apply for parallel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition f xtal crystal interface frequency range 10 20 mhz f vco vco frequency range (2) 2. the input frequency f xtal and the pll feedback divider m must match the vco frequency range: f vco = f xtal m 400 900 mhz f max output frequency n = 11 ( 1) n = 00 ( 2) n = 01 ( 4) n = 10 ( 8) 400 200 100 50 900 450 225 112.5 mhz mhz mhz mhz pwr_down = 0 f s_clock serial interface programming clock frequency (3) 3. the frequency of s_clock is limited to 10 mhz in serial programming mode. s_clock can be switched at higher frequencies when used as test clock in test mode 6. see applications information for more details. 010mhz t p,min minimum pulse width (s-load, p_load )50 ns dc output duty cycle 45 50 55 % t r , t f output rise/fall time 0.05 0.3 ns 20% to 80% t s setup time s_data to s_clock s_clock to s_load m, n to p_load 20 20 20 ns ns ns t s hold time s_data to s_clock m, n to p_load 20 20 ns ns t jit(cc) cycle-to-cycle jitter (rms 1 ) (4) n=11 (1) n=00 (2) n=01 (4) n=10 (8) 4. maximum cycle jitter measured at the lowest vco frequency. figure 5 shows the cycle jitter vs. frequency characteristics 12 25 55 65 ps t jit(cc) period jitter (rms 1 ) (5) n=11 (1) n=00 (2) n=01 (4) n=10 (8) 5. maximum period jitter measured at the lowest vco frequency. figure 6 shows the period jitter vs. frequency characteristics 13 23 36 40 t lock maximum pll lock time 10 ms
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 7 ?2009 integrated device technology, inc. table 8. MPC92439 frequency operating range (in mhz) vco frequency for an crystal interface frequency of output frequency for f xtal =16 mhz and for n = m m[6:0] 10 12 14 16 18 20 1 2 4 8 20 0010100 400 21 0010101 420 22 0010110 440 23 0010111 414 460 24 0011000 432 480 25 0011001 400 450 500 400 200 100 50 26 0011010 416 468 520 416 208 104 52 27 0011011 432 486 540 432 216 108 54 28 0011100 448 504 560 448 224 112 56 29 0011101 406 464 522 580 464 232 116 58 30 0011110 420 480 540 600 480 240 120 60 31 0011111 434 496 558 620 496 248 124 62 32 0100000 448 512 576 640 512 256 128 64 33 0100001 462 528 594 660 528 264 132 66 34 0100010 408 476 544 612 680 544 272 136 68 35 0100011 420 490 560 630 700 560 280 140 70 36 0100100 432 504 576 648 720 576 288 144 72 37 0100101 444 518 592 666 740 592 296 148 74 38 0100110 456 532 608 684 760 608 304 152 76 39 0100111 468 546 624 702 780 624 312 156 78 40 0101000 400 480 560 640 720 800 640 320 160 80 41 0101001 410 492 574 656 738 820 656 328 164 82 42 0101010 420 504 588 672 756 840 672 336 168 84 43 0101011 430 516 602 688 774 860 688 344 172 86 44 0101100 440 528 616 704 792 880 704 352 176 88 45 0101101 450 540 630 720 810 900 720 360 180 90 46 0101110 460 552 644 736 828 736 368 184 92 47 0101111 470 564 658 752 846 752 376 188 94 48 0110000 480 576 672 768 864 768 384 192 96 49 0110001 490 588 684 784 882 784 392 196 98 50 0110010 500 600 700 800 900 800 400 200 100 51 0110011 510 612 714 816 816 408 204 102 52 0110100 520 624 728 832 832 416 208 104 53 0110101 530 636 742 848 848 424 212 106 54 0110110 540 648 756 864 864 432 216 108 55 0110111 550 660 770 880 880 440 220 110 56 0111000 560 672 784 896 896 448 224 112 57 0111001 570 684 798 58 0111010 580 696 812 59 0111011 590 708 826 60 0111100 600 720 840 61 0111101 610 732 854 62 0111110 620 744 868 63 0111111 630 756 882 64 1000000 640 768 896 ... ... ... ...
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 8 ?2009 integrated device technology, inc. programming interface programming the MPC92439 programming the MPC92439 amounts to properly configuring the internal pll dividers to produce the desired synthesized frequency at the output. the output frequency can be represented by this formula: f out = f xtal ? m n(1) where f xtal is the crystal frequency, m is the pll feedback-divider and n is the pll post-divider. the input frequency and the selection of the feedback divider m is lim ited by the vco-frequency range. f xtal and m must be configured to match the vco frequency range of 400 to 900 mhz in order to achieve stable pll operation: m min = f vco,min (f xtal ) and (2) m max = f vco,max (f xtal )(3) for instance, the use of a 16 mh z input frequency requires the configuration of the pll feedback divider between m = 25 and m = 56. table 8 shows the usable vco frequency and m divider range for other example input frequencies. assuming that a 16 mhz input frequency is used, equation (1) reduces to: f out = 16 m n(4) substituting n for the four available values for n (1, 2, 4, 8) yields: example calculation for an 16 mhz input frequency for example, if an output frequen cy of 384 mhz was desired, the following steps would be taken to identify the appropriate m and n values. 384 mhz falls within the frequency range set by an n value of 2, so n[1:0]=00. for n = 2, fout = 8 ? m and m = fout 8. therefore, m = 384 8 = 48, so m[6:0] = 0110000. following this procedure a user can generate any whole frequency between 50 mhz and 900 mhz. the size of the programmable frequency steps will be equal to: f step = f xtal n(5) applications information jitter performance of the MPC92439 figure 5 and figure 6 illustrate the rms jitter performance of the MPC92439 across its specified vco frequency range. the cycle-to- cycle and period jitter is a func tion of the vco frequency and the output divider n. the general trend is that as the output frequency increases (higher vco frequency and lower n-divider) the MPC92439 output jitter decreases. optimum jitter performance can be achieved at higher vco and ou tput frequencies. the maximum cycle-to-cycle and period jitter published in table 7 correspond to the jitter performance at the lowest vco frequency limit). figure 5. MPC92439 cycle-to-cycle jitter figure 6. MPC92439 period jitter using the parallel and serial interface the m and n counters can be loaded either through a parallel or serial interface. the parallel interface is controlled via the p_load signal such that a low to high tr ansition will latch the information present on the m[6:0] and n[1:0] inputs into the m and n counters. when the p_load signal is low the input latches will be transparent and any changes on the m[6:0] and n[1:0] inputs will affect the fout output pair. to use the serial port the s_clock signal samples the information on the s_data line and loads it into a 12 bit shift register. note that the p_load signal must be high for the serial load operation to function . the test register is loaded with the first three bits, the n register with the next two, and the m register with the final eight bits of the data stream on the s_data input. for each register the most significant bi t is loaded first (t2, n1 and m6). a pulse on the s_load pin after the shift register is fully loaded will transfer the divide values into the counters. the high to low table 9. output frequency range for f xtal = 16 mhz n f out f out range f out step 10 value 00 2 8 ? m 200-450 mhz 8 mhz 01 4 4 ? m 100-225 mhz 4 mhz 10 8 2 ? m 50-112.5 mhz 2 mhz 11 1 16 ? m 400-900 mhz 16 mhz cycle-to-cycle jitter vs. vco frequency parameter: output divider n 0 10 20 30 40 50 60 70 400 500 600 700 800 900 vco frequency [mhz] tjit(cyc) [ps] rms n=1 n=2 n=4 n=8 period jitter vs. vco frequency parameter: output divider n 0 5 10 15 20 25 30 35 40 400 500 600 700 800 900 vco frequency [mhz] tjit(cyc) [ps] rms n=1 n=2 n=4 n=8
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 9 ?2009 integrated device technology, inc. transition on the s_load input will latch the new divide values into the counters. figure 7 illustrates the timing diagram for both a parallel and a serial load of the MPC92439 synthesizer. m[6:0] and n[1:0] are normall y specified once at power-up through the parallel interface, and then possibly again through the serial interface. this approach allo ws the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. using the test and diagnosis output test the test output provides visibility for one of the several internal nodes as determined by the t[2:0] bits in the serial configuration stream. it is not configurable thro ugh the parallel interface. although it is possible to select the node that represents fout, the lvcmos output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. the t2, t1 and t0 control bits are preset to ?000' when p_load is low so that the pecl fout output s are as jitter-free as possible. any active signal on the test output pin will have detrimental affects on the jitter of the pecl output pair. in normal operations, jitter specifications are only guaran teed if the test output is static. the serial configuration port c an be used to select one of the alternate functions for this pin. most of the signals available on the test output pin are useful only for performance verification of the MPC92439 itself. however, the pll bypass mode may be of interest at the board level for functional debug. when t[2:0] is set to 110 the MPC92439 is placed in pll bypass mode. in this mode the s_clock input is fed directly into the m and n dividers. the n divider drives the fout differential pair and the m counter drives the t est output pin. in this mode the s_clock input could be used for low speed board level functional test or debug. bypassing the pll and driving fout directly gives the user more control on the test clocks sent through the clocktree shows the functional setup of the pll bypass mode. because the s_clock is a cmos level the input frequency is limited to 200 mhz. this means the fastest the fout pin can be toggled via the s_clock is 100 mhz as the divide ratio of the post-pll divider is 2 (if n = 1). note that the m count er output on the t est output will not be a 50% duty cycle. figure 7. serial interface timing diagram power supply filtering the MPC92439 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. random noise on the v cc_pll pin impacts the device characteristics. the MPC92439 provides separate power supplies for the digital circuitry (v cc ) and the internal pll (v cc_pll ) of the device. the purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive inter nal analog phase-locked loop. in a controlled environment such as an evaluation board, this level of isolation is sufficient. however, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simplest form of isolation is a power supply filter on the v cc_pll pin for the MPC92439. figure 8 illustrates a typical power supply filter scheme. the MPC92439 is most susceptible to noise with spectral content in the 1 khz to 1 mhz range. therefor e, the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between table 10. test and debug configuration for test t[2:0] test output t2 t1 t0 000 12-bit shift register out (1) 1. clocked out at the rate of s_clock\ 0 0 1 logic 1 010f xtal 2 0 1 1 m-counter out 100fout 1 0 1 logic 0 1 1 0 m-counter out in pll-bypass mode 111fout 4 table 11. debug configuration for pll bypass (1) 1. t[2:0] = 110. ac specificat ions do not apply in pll bypass mode output configuration fout s_clock n test m-counter out (2) 2. clocked out at the rate of s_clock (2 ? n) s_clock s_data s_load m[6:0] n[1:0] p_load t2 t1 t0 n1 n0 m6 m5 m4 m3 m2 m1 m0 m, n first bit last bit
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 10 ?2009 integrated device technology, inc. the v cc supply and the MPC92439 pin of the MPC92439. from the data sheet, the v cc_pll current (the current sourced through the v cc_pll pin) is maximum 20 ma, assuming that a minimum of 2.835 v must be maintained on the v cc_pll pin. the resistor shown in figure 8 must have a resistance of 10?15 ? to meet the voltage drop criteria. the rc filter pictur ed will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 khz. as the noise freque ncy crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. generally, the resistor/c apacitor filter will be cheaper, easier to implement and provide an adequate le vel of supply filtering. a higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. a 1000 h choke will show a significant impedance at 10 khz frequencies and above. because of the current draw and the voltage that must be maintained on the v cc_pll pin, a low dc resistance inductor is required (less than 15 ? ). figure 8. v cc_pll power supply filter layout recommendations the MPC92439 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. figure 9 shows a representative board layout for the MPC92439. there exists many different potential board la youts and the one pictured is but one. the important aspect of the layout in figure 9 is the low impedance connections between vcc and gnd for the bypass capacitors. combining good quality general purpose chip capacitors with good pcb layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC92439 outp uts. it is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. note the dotted lin es circling the crystal oscillator connection to the device. the oscillator is a series resonant circuit and the voltage amplitude across the cr ystal is relatively small. it is imperative that no actively switchin g signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. special att ention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. although the MPC92439 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll), there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter and bypass schemes discussed in th is section should be adequate to eliminate power supply noise related problems in most designs. figure 9. pcb board layout recommendation for the plcc28 package the on-chip crystal oscillator the MPC92439 features an integrat ed on-chip crystal oscillator to minimize system implementation cost . the integrated oscillator is a pierce-type that uses the crystal in its parallel resonance mode. it is recommended to use a 10 to 20 mhz crystal with a load specification of c l = 10 pf. crystals with a load specification of c l = 20 pf may be used at the expense of an slightly higher frequency than specified for the crystal. externally connected capacitors on both the xtal_in and xtal_out pins are not required but can be used to fine-tune the crystal frequency as desired. the crystal, the trace and optional capacitors should be placed on the board as close as possible to the MPC92439 xtal_in and xtal_out pins to reduce crosstalk of active signals into the oscillator. short and wide traces further reduce parasitic inductance and resistance. it is further recommended to guard the crystal circuit by placing a ground ring around the traces and oscillator components. see table 12 for recommended cryst al specifications. v cc_pll v cc MPC92439 c 1 , c 2 = 0.01...0.1 f v cc c f = 22 f r f = 10-15 ? c 2 c 1 table 12. recommended crystal specifications parameter value crystal cut fundamental at cut resonance mode parallel crystal frequency 10 - 20 mhz shunt capacitance c 0 5 - 7 pf load capacitance c l 10 pf equivalent series resistance esr 20?60 ? 1 c2 cf xtal c1 c1 = v cc = gnd = via
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 11 ?2009 integrated device technology, inc. as an alternative to parallel resonance mode crystals, the oscillator also works with crystal s specified in the series resonance mode. with series resonance crystals, the oscillator frequency and the synthesized output frequency of the MPC92439 will be a approximately 350-400 ppm higher than using crystals specified for parallel frequency mode. this is applicable to applications using the MPC92439 in sockets designed for the pin and function compatible mc12439 synthesizer, which has an oscillator using the crystal in its series resonance mode. table 13 shows the recommended specifications for series resonance mode crystals table 13. alternative crystal specifications parameter value crystal cut fundamental at cut resonance mode series crystal frequency 10 - 20 mhz shunt capacitance c 0 5 - 7 pf equivalent series resistance esr 50?80 ?
package dimensions MPC92439 revision 4 october 27, 2009 12 ?2009 integrated device technology, inc. MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer case 776-02 issue d plcc plastic package package outline and package dimensions
package dimensions 12 ref dim min max millimeters a a1 7.00 bsc a2 0.80 bsc b 9.00 bsc b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 d d1 e e e1 l l1 1.00 ref r1 0.08 0.20 r2 s 1 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.08 --- 0? 7? 9.00 bsc 7.00 bsc 0.50 0.70 q q 0.20 ref d1 d/2 e e1 1 8 9 17 25 32 d1/2 e1/2 e/2 4x d 7 a d b a-b 0.20 h d 4x a-b 0.20 c d 6 6 4 4 detail g pin 1 index detail ad r r2 0.25 gauge plane a2 a a1 ( 0.1 c c 32x 28x h detail g f f e/2 a, b, d 3 section f-f base c1 c b b1 metal a-b m 0.20 d c 5 8 plating notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums a, b, and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08-mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion: 0.07-mm. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25-mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1-mm and 0.25-mm from the lead tip. MPC92439 revision 4 october 27, 2009 1 3 ?2009 integrated device technology, inc. MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer case 873a-03 issue b lqfp plastic package
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer MPC92439 revision 4 october 27, 2009 1 4 ?2009 integrated device technology, inc. package outline - k suffix for 32 lead vfqfn table 14. package dimensions reference document: jede c publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 14 . to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil singulation or sawn singulation n-1 n chamfer 1 2 n-1 1 2 n radius n-1 1 2 n aa dd cc bb 4 4 4 4 4 4 bottom view w/type b id bottom view w/type c id bottom view w/type a id there are 3 methods of indicating pin 1 corner at the back of the vfqfn package are: 1. type a: chamfer on the paddle (near pin 1) 2. type b: dummy pad between pin 1 and n. 3. type c: mouse bite on the paddle (near pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50 pr o posed proposed
MPC92439 data sheet 900mhz, low vo ltage, lvpecl clock synthesizer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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