cy27022 clock generator for net-md system cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number:38-07293 rev. *e revised august 10, 2009 features supports clock requirement for mini disc 16.9344 mhz crystal or clock input 12.000 mhz for usb clock output 10.0352 mhz for controller clock output 90.3168 mhz/180.6336 mhz selectable clock output load capacitance for crystal (cl = 12.1 pf typ) 3.3v operation 8-pin soic package description the cy27022 is a clock generator that integrates clock require- ments for a net-md system. the cy27022 supports usb clock, mini disc, and cpu clock requirements. pinout figure 1. pin diagram - 8-pin soic table 1. frequency table (input = 16.9344 mhz) pin number name output frequency fs 1 clkc 12.000 mhz x 5 clkb 90.3168 mhz 0 5 clkb 180.6336 mhz 1 6 clka 10.0352 mhz x clkc gnd xin xout vdd clka clkb fs 1 2 3 4 8 7 6 5 soic table 2. pin definition - 8 soic pin number pin name i/o description 1 clkc o 12.000 mhz clock output 2 gnd pwr device ground 3 xin i 16.9344 mhz reference crystal or external clock input 4 xout o reference crystal feedback (float if xin is driven by external reference clock) 5 clkb o selectable clock output, see ta b l e 1 . 6 clka o 10.0352 mhz clock output 7 vdd pwr +3.3v power supply 8 fs i frequency selection input pin. this pin controls the frequency presented on clkb. internal pull up [+] feedback
cy27022 document number:38-07293 rev. *e page 2 of 4 maximum ratings the voltage on any input or i/o pin cannot exceed the power pin during power up. these user guidelines are not tested. maximum input voltage relative to gnd: ............. ............?0.3v maximum input voltage relative to v dd :.................. v dd + 0.3v storage temperature: ................ ........... ............. ?65 to +150c operating temperature:.........................................0c to +70c maximum esd protection ................................................... 2kv maximum power supply:.....................................................5.5v operating voltage: ..................................................... 2.9v?3.6v this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, precautions are taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out are constrained to the range: gnd < (v in or v out ) < v dd unused inputs are always to an appropriate logic voltage level (either gnd or v dd ). dc parameters ac parameters table 3. dc parameters [2] (v dd = 3.3v 10%, t a = 0 to 70c) parameter description conditions min typ max unit v il input low voltage see note 1 0.8 v v ih input high voltage see note 1 2.0 v i il input low current see note 1 ?72 -15 a iih input high current see note 1 10 a idd3.3v dynamic supply cu rrent no output load, fs = 1 (180-mhz mode) 19 28 ma v ol output low voltage i ol = 4.0 ma 0.4 v v oh output high voltage i oh = ?4.0 ma 2.4 v c xtal crystal pin capacitance xin, xout pin capacitance 23 pf notes 1. applicable to input signal: fs. internal pull up resistor value may vary between 70k and 170k. 2. the voltage on any input or io pin cannot exceed the power pin during power up. 3. parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with fully loaded outputs 4. measured between 0.2*v dd and 0.8*v dd volts. 5. measured between 0.2*v dd and 0.7*v dd volts. 6. clocks trigger at 1.5 volts. 7. all outputs have a 15 pf load. table 4. ac parameters [3] parameter description comments min typ max unit tr1 rise time clka and clkc at rated load [4, 5, 6, 7] 23ns tf1 fall time clka and clkc at rated load [4, 5, 6, 7] 23ns tr2 rise time clkb at rated load [4, 5, 6, 7] 1.5 ns tf2 fall time clkb at rated load [4, 5, 6, 7] 1.5 ns tpu power up to stable output all output clocks [5] 3ms tdc clock duty cycle all clocks at rated load [ 6, 7] 45 50 55 % tj1 clock jitter clka and clkc at rated load [4, 5, 6, 7] 250 ps tj2 clock jitter clkb at rated load [4, 5, 6, 7] 150 ps [+] feedback
cy27022 document number:38-07293 rev. *e page 3 of 4 package drawing and dimensions figure 2. 8-pi n (150-mil) soic ordering information ordering code package type operating range operating voltage cy27022sct 8-pin soic - tape and reel commercial (0 to 70c) 3.3v10% cy27022sxc 8-pin soic (pb-free) commercial (0 to 70c) 3.3v10% CY27022SXCT 8-pin soic (pb-free) - tape and reel commercial (0 to 70c) 3.3v10% seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 8 lead (150 mil) soic - s08 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 51-85066-c [+] feedback
document number:38-07293 rev. *e revised august 10, 2009 page 4 of 4 all products and company names mentioned in this document may be the trademarks of their respective holders. cy27022 ? cypress semiconductor corporation, 2002-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com document history document title: cy27022 clock generator for net-md system document number: 38-07293 rev. ecn no. submission date orig. of change description of change ** 116146 08/14/02 osm new data sheet *a 122884 12/22/02 rbi added power up requirements to maximum ratings *b 406494 see ecn xht/cft obsolete specification. suns et review clean up. personalized clock chips for japanese customer and no longer in use. *c 1191263 see ecn kvm revived the data sheet as the device is still active. added pb-free part numbers. updated note 2 to remove me ntion of multiple supplies and voltage sequencing. replaced in stances of vss with gnd. *d 2710266 05/22/09 kvm/pyrs remove obs olete part number from ordering information table: cy27022sc *e 2748211 08/10/09 tsai posting to external web. [+] feedback
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