mitsubishi semiconductor PS11016 flat-base type insulated type jan. 2000 PS11016 integrated functions and features ? 3-phase igbt inverter bridge configured by the latest 3rd. generation igbt and diode technologies. ? circuit for dynamic braking of motor regenerative energy. ? inverter output current capability i o (note 1): application acoustic noise-less 2.2kw/ac200v class 3 phase inverter and other motor control applica- tions. package outlines mitsubishi semiconductor PS11016 flat-base type insulated type integrated drive, protection and system control functions: ? for p-side igbts : drive circuit, high voltage isolated high-speed level shifting, short-circuit protection (sc), bootstrap circuit supply scheme (single drive-power-supply) and under voltage protection (uv). ? for n-side igbts : drive circuit, short circuit protection (sc), control-supply under voltage and over voltage protection (ov/ uv), sys- tem over-temperature protection (ot), fault output (f o ) signaling circuit, and current-limit warning signal output (cl) ? for brake circuit igbt : drive circuit ? warning and fault signaling : f o1 : short circuit protection for lower-leg igbts and input interlocking against spurious arm shoot-through. f o2 : n-side control supply abnormality locking (ov/uv) f o3 : system over-temperature protection (ot). cl : warning for inverter current overload condition ? for system feedback control : analogue signal feedback reproducing actual inverter phase current (3 f ). ? input interface : 5v cmos/ttl compatible, schmitt trigger input, and arm-shoot-through interlock protection. (note 1) : the inverter output current is assumed to be sinu- soidal and the peak current value of each of the above loading cases is defined as : i op = i o ? ` 2 (fig. 1) type name PS11016 100% load 11.0a (rms) 150% over load 16.5a (rms), 1min 4- f 4 13 8.5 (7.75) 2 0.3 92.5 1 83.5 0.5 6 0.3 56 0.8 71.5 0.5 80.5 1 0.6 0.5 78.75 1.2 31 32 34 35 36 4-r4 label 33 0.5 2.5 23 1 76.5 1 20.4 1 50.8 0.8 27 1 10.16 0.3 5 (10.35) 1 cbu+ 2 cbu 3 cbv+ 4 cbv 5 cbw+ 6 cbw 7 gnd 8 nc 9 vdh 10 cl 11 fo1 12 fo2 13 fo3 14 cu 15 cv 16 cw 17 up 18 vp 19 wp 20 un 21 vn 22 wn 23 br 31 p 32 br 33 n 34 u 35 v 36 w terminals assignment: 2.45 0.3
mitsubishi semiconductor PS11016 flat-base type insulated type jan. 2000 vdh gnd b p r s t c z n m cbu cbu+ cbv cbv+ cbw cbw+ application specific intelligent power module cu cv cw cl, fo 1 , fo 2 , fo 3 u p v p w p v n w n b r u n protection circuit control supply fault sense fo logic drive circuit input signal conditioning z : surge absorber. c : ac filter (ceramic condenser 2.2~6.5nf) [note : additionally an appropriate line-to line surge absorber circuit may become necessary depending on the application environment]. w ac 200v line output v u ac 200v line input brake resistor connection, inrush prevention circuit, etc. protection circuit level shifter drive circuit current sensing circuit note 1) to prevent chances of signal oscillation, a series resistor (1k w ) coupling at each output is recommended. note 2) by virtue of integrating an photo-coupler inside the module, direct coupling to cpu, without any external opto or trans former isolation is possible. note 3) all outputs are open collector type. each signal line should be pulled up to plus side of the 5v power supply with appr oximately 5.1k w resistance. note 4) the wiring between power dc link capacitor and p/n terminals should be as short as possible to protect the asipm agains t catastrophic high surge voltage. for extra precaution, a small film snubber capacitor (0.1~0.22 m f, high voltage type) is recommended to be mounted close to these p and n dc power input pins. analogue signal output corresponding to each phase current (5v line) note 1) pwm input (5v line) note 2) fault output (5v line) note 3) t s each output igbt collector current brake igbt collector current brake diode anode current internal functions block diagram (fig. 2) v v 450 500 applied between p-n applied between p-n, surge-value applied between p-u, v, w, br or u, v, w, br-n applied between p-u, v, w, br or u, v, w, br-n t c = 25 c note: ( ) means i c peak value supply voltage supply voltage (surge) v cc v cc(surge) condition symbol item ratings unit maximum ratings (tj = 25 c) inverter part (including brake part) v p or v n v p(s) or v n(s) i c ( i cp ) i c (i cp ) i f (i fp ) each output igbt collector-emitter static voltage each output igbt collector-emitter switching surge voltage 600 600 30 ( 60) 15 (30) 15 (30) v v a a a v 20 applied between v dh -gnd, c bu+ -c buC , c bv+ -c bvC , c bw+ -c bwC v dh , v db supply voltage symbol item ratings unit control part condition C0.5 ~ 7 15 C0.5 ~ 7 15 1 v v ma v ma ma v cin v fo i fo v cl i cl i co input signal voltage fault output supply voltage fault output current current-limit warning (cl) output voltage cl output current analogue current signal output current C0.5 ~ 7.5 applied between u p v p w p u n v n w n br-gnd applied between f o1 f o2 f o3 -gnd sink current of f o1 f o2 f o3 applied between cl-gnd sink current of cl sink current of cu cv cw
mitsubishi semiconductor PS11016 flat-base type insulated type jan. 2000 circuit current input on threshold voltage input off threshold voltage input pull-up resister min. v fbr ton tc(on) toff tc(off) trr tc 2.3 2.4 2.9 4.5 0.040 collector-emitter saturation voltage fwdi forward voltage v ce(sat) v ec ratings c/w c/w c/w c/w c/w junction to case thermal resistance condition symbol item ratings unit (note 2) (fig. 3) 60 hz sinusoidal ac applied between all terminals and the base plate for 1 minute. mounting screw: m3.5 t j t stg t c v iso junction temperature storage temperature module case operating temperature isolation voltage mounting torque C20 ~ +125 C40 ~ +125 C20 ~ +100 2500 0.78 ~ 1.27 c c c vrms nm total system note 2) the item defines the maximum junction temperature for the power elements (igbt/diode) of the asipm to ensure safe opera tion. how- ever, these power elements can endure instantaneous junction temperature as high as 150 c instantaneously . to make use of this ad- ditional temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary in formation is requested to be provided before use. condition symbol item ratings inverter igbt (1/6) inverter fwdi (1/6) brake igbt brake fwdi case to fin, thermal grease applied rth(j-c) q rth(j-c) f rth(j-c) q rth(j-c) f rth(c-f) min. thermal resistance typ. max. unit (fig. 3) case temperature measurement point (3mm from the base surface) v dh = v db = 15v, input = on, tj = 25 c, ic = 30a condition symbol item typ. max. unit ? no destruction ? f o output by protection operation electrical characteristics (tj = 25 c, v dh = 15v, v db = 15v unless otherwise noted) contact thermal resistance tj = 25 c, ic = C30a, input = off i dh v th(on) v th(off) r i ? no destruction ? no protecting operation ? no f o output v ce(sat)br brake igbt collector-emitter saturation voltage brake diode forward voltage v dh = 15v, input = on, tj = 25 c, ic = 15a tj = 25 c, i f = 15a, input = off switching times 1/2 bridge inductive, input = on v cc = 300v, ic = 30a, tj = 125 c v dh = 15v, v db = 15v note : ton, toff include delay time of the internal control circuit fwd reverse recovery time short circuit endurance (output, arm, and load, short circuit modes) v cc 400v, input = on (one-shot) tj = 125 c start 13.5v v dh = v db 16.5v v cc 400v, tj 125 c, ic < i ol (cl) operation level, input = on, 13.5v v dh = v db 16.5v switching soa v dh = 15v, v cin = 5v 0.8 2.5 integrated between input terminal-v dh 0.35 0.35 1.3 1.4 3.0 150 0.7 0.15 0.5 2.9 2.9 3.5 0.9 2.0 150 2.0 4.0 2.9 1.8 1.0 v v v v m s m s m s m s m s ma v v k w
mitsubishi semiconductor PS11016 flat-base type insulated type jan. 2000 supply voltage ripple input on voltage input off voltage pwm input frequency arm shoot-through blocking time supply voltage d v dh , d v db v cin(on) v cin(off) f pwm t dead 10.0 16.50 18.00 11.55 t d(read) i cl(h) i cl(l) i ol sc ot otr uv dh uv dhr ov dh ov dhr uv db uv dbr t dv i fo(h) i fo(l) 0.77 t xx electrical characteristics (tj = 25 c, v dh = 15v, v db = 15v unless otherwise noted) 3.37 idle active trip level reset level trip level reset level trip level reset level trip level reset level filter time idle active ic = 0a ic = i op (200%) ic = ? op (200%) t int v co v c+ (200%) v c (200%) | d v co | v c+ v c d v c (200%) t c = ?0 ~ +100 c, tj 125 c v dh = 15v t c = ?0 c ~ 100 c (fig. 4) t c 100 c, tj 125 c v dh = 15v, t c = ?0 c ~ +100 c (note 3) pwm input frequency condition symbol ratings f pwm min. typ. max. unit v dh = 15v, t c = ?0 c ~ 100 c ic > i op (200%), v dh = 15v (fig. 4) |v co -v c (200%)| after input signal trigger point (fig. 8) fault output current open collector output v d = 15v, t c = ?0 c ~ 100 c (note 4) tj = 25 c (fig. 7) (note 5) analogue signal over all linear variation item t dead allowable input on-pulse width allowable input signal dead time for blocking arm shoot-through relates to corresponding input (except break part) analogue signal linearity with output current offset change area vs temperature analogue signal output voltage limit r ch analogue signal data hold accuracy analogue signal reading time correspond to max. 500 m s data hold period only, ic = i op (200%) (fig. 5) cl warning operation level short circuit over current trip level 1 2.5 1.87 4.0 ? 31.2 50.6 100 11.05 open collector output 65 2.27 1.17 15 1.1 1 38.0 65.0 110 90 11.0 12.00 12.50 19.20 10 1 15 500 100 2.57 1.47 3.67 0.7 1 5 46.0 120 12.0 12.5 12.75 13.25 20.15 18.65 1 ? khz m s m s ns v v v mv v v v % m s m a ma a a c c v v v v m s m a ma 17.50 relates to corresponding inputs, (except brake part), t c = ?0 c ~ +100 c input inter-lock sensing 2.97 signal output current of cl operation over temperature protection supply circuit under & over voltage protection 11.5 10.5 v v v dh = 15v (note 3) : (a) allowable minimum input on-pulse width : this item applies to p-side circuit only. (b) allowable maximum input on-pulse width : this item applies to both p-side and n-side circuits excluding the brake circuit. (note4) : cl output : the "current limit warning (cl) operation circuit outputs warning signal whenever the arm current exceeds this limit. the circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme. (note5) : the short circuit protection works instantaneously when a high short circuit current flows through an internal igbt ri sing up momen- tarily. the protection function is, thus meant primarily to protect the asipm against short circuit distraction. therefore, thi s function is not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due t o excessive temperature rise. instead, the analogue current output feature or the over load warning feature (cl) should be approp ri- ately used for such current regulation or over load control operation. in other words, the pwm signals to the asipm should be s hut down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back from its f o1 pin of the asipm indicating a short circuit situation. recommended conditions v 400 (max.) applied across p-n terminals condition symbol item ratings v cc unit v dh , v db control supply voltage applied between v dh -gnd, c bu+ -c bu , c bv+ -c bv , c bw+ -c bw using application circuit using application circuit 15 1.5 1 (max.) 0 ~ 0.3 4.8 ~ 5.0 2 ~ 15 2.5 (min.) v v/ m s v v khz m s
mitsubishi semiconductor PS11016 flat-base type insulated type jan. 2000 200 ?00 analogue output signal data hold range 1 2 3 4 5 400 300 100 0 ?00 ?00 ?00 0 v c +(200%) v c0 v c (200%) v c (v) v c + v c min max real load current peak value.(%)(i c =i o 5 2) v dh =15v t c = 20 ~ 100?c (fig. 4) note : input interlock protection circuit ; it is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta- neously in ?ow level. by this interlocking, both upper and lower igbts of this mal-triggered phase are cut off, and ? o signal is outputted. after an ?nput interlock?operation the circuit is latched. the ? o is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later. v ch (5 m s) v ch (505 m s) 0v v c 500 m s r ch = v ch (505 m s)-v ch (5 m s) v ch (5 m s) note ; ringing happens around the point where the signal output voltage changes state from ?nalogue?to ?ata hold?due to test circuit arrangement and instrumentational trouble. therefore, the rate of change is measured at a 5 m s delayed point. 0v 0v 0v 0v 0v input signal v cin(p) of each phase upper arm input signal v cin(n) of each phase lower arm gate signal v o(p) of each phase upper arm (asipm internal) gate signal v o(n) of each phase upper arm (asipm internal) error output f o1 note : short circuit protection operation. the protection operates with ? o flag and reset on a pulse-by-pulse scheme. the protection by gate shutdown is given only to the igbt that senses an overload (excluding the igbt for the ?rake?. s c delay time short circuit sensing signal v s error output f o1 gate signal vo of each phase upper arm(asipm internal) input signal v cin of each phase upper arm 0v 0v 0v 0v fig. 4 output current analogue signaling linearity fig. 5 output current analogue signaling ?ata hold definition fig. 6 input interlock operation timing chart fig. 7 timing chart and short circuit protection operation
mitsubishi semiconductor PS11016 flat-base type insulated type jan. 2000 r u p ,v p ,w p ,u n ,v n ,w n ,br f 01 ,f 02 ,f 03 ,cl cu,cv,cw gnd(logic) asipm 5v cpu r 5.1k w 10k w 0.1nf 0.1nf on on on on 0 0 0 v pn dc-bus voltage control voltage supply boot-strap voltage n-side input signal p-side input signal brake input signal f o 1 output signal v db v cin(n) v cin(p) v cin(br) f oi v dh b) a) pwm starts n-side igbt current n-side fwdi current t(hold) td(read) delay time +i cl ? cl on off on off 0 0 on off 0 ref v cin v(hold) i c (v s ) v c v cl fig. 8 inverter output analogue current sensing and signaling timing chart fig. 10 recommended i/o interface circuit fig. 9 start-up sequence normally at start-up, fo and cl output signals will be pulled-up high to supply voltage (off level); however, f o1 output may fall to low (on) level at the instant of the first on input pulse to an n-side igbt. this can happen particularly when the boot-strap capacitor is of large size. f o1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph a) boot-strap charging scheme : apply a train of short on pulses at all n-igbt input pins for ad- equate charging (pulse width = approx. 20 m s number of pulses =10 ~ 500 depending on the boot-strap capacitor size) b) f o1 resetting sequence: apply on signals to the following input pins : br ? un/vn/wn ? up/vp/wp in that order.
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