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| 1 general description the MAX3711 limiting amplifier and laser driver provides a highly integrated, low-cost, high-performance pmd solution. the low-jitter laser diode driver provides transmit aver - age power control (apc) of laser bias current as well as an integrated modulation current control loop (extinction ratio control, or erc). the erc eliminates the need for temperature lookup tables (luts) controlling the modula - tion current. the low-noise limiting amplifier maximizes optical sen - sitivity and has adjustable sd/los threshold plus pro - grammable output levels. the differential cml output stage features a slew-rate adjustment for 1.25gbps operation. integrated bias current monitor and tx power monitor enable a low-cost implementation of modules with digital diagnostics. a novel auto-calibration mode enables low-cost fiber optic module production. an integrated 3-wire digital interface controls the laser driver and limiting amplifier functions, and enables communication with a low-cost controller. the MAX3711 is offered in a small, 4mm x 4mm, 24-pin tqfn package with exposed pad, and operates over the -40 n c to +95 n c temperature range. benefits and features s simplifies module manufacturing ? enables single-temperature module testing ? production laser auto-calibration mode s improved performance ? integrated apc loop (operates up to 3.125gbps) ? integrated erc loop (operates up to 2.7gbps) ? 1.3mv p-p receiver sensitivity s flexibility ? lvds, lvpecl, and cml compatible high- speed i/os ? programmable i/o polarity ? 3-wire digital interface s safety and reliability ? integrated safety features with fault mask register ? supports sfp msa and sff-8472 digital diagnostic ? selectable analog monitor of laser power or bias current at bmon pin applications oc-3 to oc-48 sfp/sff transceivers ethernet sfp/sff transceivers cpri/obsai sfp/sff transceivers cwdm sfp transceivers 19-6025; rev 0; 9/11 ordering information appears at end of data sheet. MAX3711 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
2 v ccx , v ccto , v ccd ............................................... -0.3v to 4.0v voltage range at disable, sda, scl, csel, fault, los, mdref ........................... -0.3v to (v cc + 0.3v) voltage range at rin+, rin- ........ (v cc - 1.7v) to (v cc + 0.3v) voltage range at rout+, rout- .......... (v cc - 2v) to (v cc + 0.3v) voltage range at tin+, tin- .................... -0.3v to (v cc + 0.3v) voltage range at tout ....................................... 0.3v to v ccto voltage range at iout ......... (v ccto - 1.8v) to (v ccto + 1.2v) current range into fault, los, mdin, sda ...................................................... -1ma to +5ma current out of rout+, rout- ........................................... 40ma current into tout ............................................................ 180ma current into iout ............................................................. 120ma voltage range at bmon ......................................... -0.3v to v cc continuous power dissipation (t a = +70 n c) tqfn (derate 27.8mw/ n c above +70 n c) .................. 2222mw storage temperature range .......................... -55 n c to +150 n c die attach temperature ................................................. +400 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v cc = 2.97v to 3.63v, t a = -40c to +95c; cml receiver output is ac-coupled to differential 100? load; registers are set to default values, unless implied by test conditions. typical values are at v cc = 3.3v, t a = +25c, data rate = 2.5gbps, i bias = 20ma, and i mod = 40ma, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units operating conditions power supply voltage v cc 2.97 3.3 3.63 v power supply power-supply current i cc includes rx cml output current, excludes tx i bias = 20ma, i mod = 40ma 75 110 ma power-on reset v cc for enable high v ccx connected to v ccd 2.55 2.75 v v cc for enable low v ccx connected to v ccd 2.3 2.45 v rx input specification differential input resistance r in 75 100 125 i input sensitivity v inmin 2 23 - 1 prbs, 2.5gbps, tx_en = 0 (note 2) 1.3 2 mv p-p input overload v inmax (note 2) 1.2 v p-p differential input return loss s dd11 device powered on, f p 2ghz 19 db device powered on, f p 5ghz 12 common-mode input return loss s cc11 device powered on, 1ghz p f p 2ghz 11 db device powered on, 2ghz p f p 5ghz 14 rx output specification differential output resistance r outdiff 75 100 125 i differential output return loss s dd22 device powered on, f p 2ghz 19 db device powered on, 2ghz p f p 5ghz 15 common-mode output return loss s cc22 device powered on, f p 2ghz 14 db device powered on, 2ghz p f p 5ghz 10 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 3 electrical characteristics ( continued ) (v cc = 2.97v to 3.63v, t a = -40c to +95c; cml receiver output is ac-coupled to differential 100? load; registers are set to default values, unless implied by test conditions. typical values are at v cc = 3.3v, t a = +25c, data rate = 2.5gbps, i bias = 20ma, and i mod = 40ma, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units cml differential output voltage 4mv p-p p v in p 1200mv p-p , set_cml[3:0] = 10d 600 800 1000 mv p-p 4mv p-p p v in p 1200mv p-p , set_cml[3:0] = 0 410 cml differential output voltage when disabled output ac-coupled, v inmax at input, set_cml[3:0] = 10d (note 2) 5 mv p-p data output transition time (20% to 80%) (note 2) 4mv p-p p v in p 1200mv p-p , slew_rate = 1 85 115 ps 4mv p-p p v in p 1200mv p-p , slew_rate = 0 140 200 los output high voltage v oh r los = 4.7k i - 10k i to v cc v cc - 0.1 v los output low voltage v ol r los = 4.7k i - 10k i to v cc 0 0.4 v rx transfer characteristics deterministic jitter (notes 2, 3) dj 2.5gbps, 4mv p-p p v in p 1200mv p-p , set_cml[3:0] = 10d 7 15 ps p-p 1.25gbps, 4mv p-p p v in p 1200mv p-p , set_cml[3:0] = 10d 10 20 125mbps, 4mv p-p p v in p 1200mv p-p , set_cml[3:0] = 10d, k28.5 pattern 21 random jitter rj input = 4mv p-p at 2.5gbps, 1111 0000 pattern, set_cml[3:0] = 10d (notes 2, 4) 3.5 5 ps rms low-frequency cutoff (simulated value) i/o coupling capacitors = 1 f f 10 khz small-signal bandwidth (simulated value) slew_rate = 1 2.0 ghz los specifications (notes 2, 5) los hysteresis 10log(v deassert /v assert ) 1.25 2.2 db los assert/deassert time (note 6) 2.3 30 f s los assert sensitivity range los_range = 0 4.6 36 mv p-p los_range = 1 14 115 los assert/deassert level (low range, los_range = 0) los assert set_los = 5 3 3.8 4.6 mv p-p set_los = 31 18 23 28 set_los = 63 36 47 56 los deassert set_los = 5 5 6.5 8 set_los = 31 32 39 46 set_los = 63 64 80 95 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 4 electrical characteristics ( continued ) (v cc = 2.97v to 3.63v, t a = -40c to +95c; cml receiver output is ac-coupled to differential 100? load; registers are set to default values, unless implied by test conditions. typical values are at v cc = 3.3v, t a = +25c, data rate = 2.5gbps, i bias = 20ma, and i mod = 40ma, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units los assert/deassert level (high range, los_range = 1) los assert set_los = 5 9 11.5 14 mv p-p set_los = 31 55 68 80 set_los = 63 115 138 160 los deassert set_los = 5 15 19 23 set_los = 31 97 117 136 set_los = 63 197 238 278 tx input specifications differential input resistance 13 k i internal common-mode bias voltage for ac-coupled operation 1.3 v differential input voltage dc-coupled, 100 i , differential resistors, figure 1 and figure 3 0.2 1.6 v p-p common-mode input voltage range dc-coupled, figure 1 and figure 3 1.125 v cc - v in /2.5 v disable input current disable = v cc 10 f a disable = gnd 33 60.5 disable input high voltage v ih 1.8 v cc v disable input low voltage v il 0 0.8 v disable input hysteresis v hyst 80 mv disable input impedance r pull pullup resistor 60 100 138 k i tx output specifications fault output high voltage v oh r fault is 4.7k i - 10k i to v cc v cc - 0.1 v fault output low voltage v ol r fault is 4.7k i - 10k i to v cc 0 0.4 v laser modulator maximum modulation-on current 85 ma minimum modulation-on current 5 ma modulation current dac stability 10ma p i mod p 85ma (notes 2, 7) 1 4 % modulation current rise/fall time (note 2) 20% to 80%, 10ma p i mod p 85ma, r load = 12 i , trf[1:0] = 11b 65 120 ps 20% to 80%, 10ma p i mod p 85ma, r load = 12 i , trf[1:0] = 00b 72 compliance voltage at tout v tout instantaneous voltage, 10ma p i mod p 85ma 0.6 2.4 v 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 5 electrical characteristics ( continued ) (v cc = 2.97v to 3.63v, t a = -40c to +95c; cml receiver output is ac-coupled to differential 100? load; registers are set to default values, unless implied by test conditions. typical values are at v cc = 3.3v, t a = +25c, data rate = 2.5gbps, i bias = 20ma, and i mod = 40ma, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units deterministic jitter (notes 2, 3) dj 10ma p i mod p 85ma, 2.5gbps 15 40 ps p-p 10ma p i mod p 85ma, 1.25gbps 15 10ma p i mod p 85ma, 125mbps, k28.5 pattern 20 random jitter (notes 2, 4) rj 10ma p i mod p 20ma, 1111 0000 pattern 1.2 1.65 ps rms 20ma p i mod p 85ma, 1111 0000 pattern 1 1.45 bias generator maximum bias current current into tout 70 ma minimum bias current current into tout 1 ma bias current dac stability 2ma p i bias p 70ma, v tout = 2v (notes 2, 7) 1 4 % bias current monitor current gain i bias / i bmon external resistor to gnd defines voltage gain, i bias = 1.5ma 54 58 72 a/a external resistor to gnd defines voltage gain, i bias = 5.7ma 54 65 73 external resistor to gnd defines voltage gain, i bias = 39ma 64 72 80 external resistor to gnd defines voltage gain, i bias = 70ma 64 72 80 compliance voltage range at bmon v bmon 0 1.8 v bmon current gain stability (as bias monitor) 2ma p i bias p 70ma (notes 2, 7) 2 5 % laser control specifications apc loop stability (1.25gbps, 2 23 - 1 prbs pattern) (note 8) i mdinavg = 50 f a, k md x se = 0.005 0.1 10log(db) i mdinavg = 2ma, k md x se = 0.05 0.1 apc loop stability (2.5gbps, 2 23 - 1 prbs pattern) (note 8) i mdinavg = 50 f a, k md x se = 0.005 0.1 10log(db) i mdinavg = 2ma, k md x se = 0.05 0.1 erc loop stability (1.25gbps, 2 23 - 1 prbs pattern, e r = 11db) (note 8) i mdinavg = 50 f a, k md x se = 0.005 0.5 10log(db) i mdinavg = 2ma, k md x se = 0.05 0.5 erc loop stability (2.5gbps, 2 23 - 1 prbs pattern, e r = 11db) (note 8) i mdinavg = 50 f a, k md x se = 0.005 1.3 10log(db) i mdinavg = 2ma, k md x se = 0.05 1.1 mdin bias voltage v mdin 1.2 v md average current range i mdinavg average current into mdin 50 2000 f a programmable extinction ratio range e r p1/p0 (dpc closed-loop operation) 5 16 24 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 6 electrical characteristics ( continued ) (v cc = 2.97v to 3.63v, t a = -40c to +95c; cml receiver output is ac-coupled to differential 100? load; registers are set to default values, unless implied by test conditions. typical values are at v cc = 3.3v, t a = +25c, data rate = 2.5gbps, i bias = 20ma, and i mod = 40ma, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units md current monitor/bmon activation time from the rising edge of the final scl clock of the 3-wire cycle to 90% of steady state at bmon 100 ns safety features fault threshold voltage at tout v tout fault always occurs for v tout < 0.35v, fault never occurs for v tout r 0.55v 0.35 0.55 v fault threshold voltage at mdin v mdin fault always occurs for v mdin < 0.3v, fault never occurs for v mdin r 0.5v 0.3 0.5 v fault threshold voltage at iout fault always occurs for v iout < v ccto - 1.7v, fault never occurs for v iout r v ccto - 1.45v, v ccto = 3.3v v ccto - 1.7 v ccto - 1.45 v fault threshold voltage at v ccto fault always occurs for v ccto < 2v; fault never occurs for v ccto r 2.95v 2 2.95 v maximum laser current in disable state combined total current into tout during fault, disable = 1, or tx_en = 0 100 f a tx timing specifications dpc loop initialization time t apcinit i bias = 40ma and i mod = 60ma, i bias_int = 8ma, time from restart to i bias and i mod at 90% of steady state 3 f s disable assert time t off time from rising edge of disable input signal to i bias and i mod at 10% of steady state (note 2) 30 100 ns disable negate time t on time from falling edge of disable input signal to i bias and i mod at 90% of steady state (note 2) 200 300 ns fault assert time t fault time from fault condition to fault high, c fault p 20pf, r fault is 4.7k i - 10k w to v cc (note 2) 2.5 10 f s disable to reset minimum required time disable must be held high to reset a fault 100 ns rx output level dac full-scale voltage v fs set_cml[3:0] = 15d 820 1000 mv p-p resolution 4 bits 40 mv p-p los threshold dac full-scale voltage los_range = 0 47 mv p-p los_range = 1 138 resolution los_range = 0 0.75 mv p-p los_range = 1 2.2 integral nonlinearity set_los[5:0] = 5d to 63d q 0.7 lsb 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 7 electrical characteristics ( continued ) (v cc = 2.97v to 3.63v, t a = -40c to +95c; cml receiver output is ac-coupled to differential 100? load; registers are set to default values, unless implied by test conditions. typical values are at v cc = 3.3v, t a = +25c, data rate = 2.5gbps, i bias = 20ma, and i mod = 40ma, unless otherwise noted.) (note 1) note 1: specifications at t a = -40 n c and t a = +95 n c are guaranteed by design and characterization, . note 2: guaranteed by design and characterization, t a = -40 n c to +95 n c. note 3: the data input transition time is controlled by 4th-order bessel filter with f -3db = 0.75 x 1.25ghz and f -3db = 0.75 x 2.5ghz, respectively. the deterministic jitter caused by this filter is not included in the dj. a 2 23 - 1 prbs equivalent pat - tern was used. note 4: rj was tested without input filter. note 5: for all rx los specifications los_lowbw = 1 for 1.25gbps operation and los_lowbw = 0 for 2.5gbps operation. note 6: measurement includes an input ac-coupling capacitor of 0.1 f f. the signal at the rin input is switched between two amplitudes: signal_on and signal_off. 1) receiver operates at sensitivity level plus 1db power penalty parameter symbol conditions min typ max units bias current dac full-scale current i fs_bias i bias = (12 + biasreg[9:0]) x lsb_bias 70 78 ma resolution lsb_bias 10-bit dac 75 f a modulation current dac full-scale current i fs_mod i mod = (20 + modreg[8:0]) x lsb_mod 85 89 ma resolution lsb_mod 9-bit dac 167 f a 3-wire digital interface input high voltage v ih 2.0 v cc v input low voltage v il 0.8 v input hysteresis v hyst 80 mv input leakage current i il , i ih voltage at pin 0v to v cc , internal pullup or pulldown 75k i typical 85 f a output high voltage v oh external pullup of 4.7k i to v cc v cc - 0.1 v output low voltage v ol external pullup of 4.7k i to v cc 0.4 v 3-wire digital interface timing (figure 6) scl clock frequency f scl 1 mhz scl pulse-width high t ch 0.5 f s scl pulse-width low t cl 0.5 f s sda setup time t ds 100 ns sda hold time t dh 100 ns scl rise to sda propagation time t d 5 ns csel pulse-width low t csw 500 ns csel leading time before the first scl edge t l 500 ns csel trailing time after the last scl edge t t 500 ns sda, scl external load c b total bus capacitance on one line 20 pf 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 8 electrical characteristics ( continued ) (v cc = 2.97v to 3.63v, t a = -40c to +95c; cml receiver output is ac-coupled to differential 100? load; registers are set to default values, unless implied by test conditions. typical values are at v cc = 3.3v, t a = +25c, data rate = 2.5gbps, i bias = 20ma, and i mod = 40ma, unless otherwise noted.) (note 1) figure 1. tin input voltage diagram a) signal_off = 0 signal_on = 10log(min_assert_level) + 8db b) signal_on = 10log(max_deassert_level) + 1db signal_off = 0 2) receiver operates at overload signal_off = 0 signal_on = 1.2v p-p max_deassert_level and min_assert_level are measured for one set_los setting note 7: stability is defined [i measured ) - (i reference )]/(i reference ) over the listed current range temperature and supply varia - tion. reference current measured at v cc = 3.3v and t a = +25 n c. measured current is measured at v cc = 3.3v 5% and t a = -40 n c to +95 n c. note 8: k md is the laser diode to monitor diode gain in a/w. se is the lasers slope efficiency. input common mode compliance (v) v cc - 0.05v v cc - 0.2v v cc - 0.32v v cc - 1.28v v cc - 1.49v v cc /2 1.275v 1.149v 1.125v 0.2v 0.4v 0.6v 0.8v 1.0v 1.2v 1.4v 1.6v tin operational range 50 to v cc - 2v 130 to v cc and 82 to gnd differential inpu t swing (v p-p ) dc-coupled cm l lvpecl lvpecl cmos single-ended input range lvds 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 9 typical operating characteristics (typical values are at v cc = 3.3v, t a = +25c, data pattern = 2 23 - 1 prbs, unless otherwise noted.) i bias current vs. set_ibias[7:0] (open loop operation) MAX3711 toc07 set_ibias[7:0] i bias (ma) 250 200 150 100 50 10 20 30 40 50 60 70 80 90 0 0 300 this is the precondition value for bias current if ibupdt = 1. i mod current vs. set_imod[7:0] (open loop operation) MAX3711 toc06 set_imod[7:0] i mod (ma p-p ) 250 200 150 100 50 10 20 30 40 50 60 70 80 90 100 0 0 300 this is the precondition value for mod current if imupdt = 1. bit-error rate vs. differential input amplitude (2.5gbps) MAX3711 toc05 differential input amplitude (mv p-p ) ber 1.4 1.3 1.2 1.1 1.0 0.9 1e-10 1e-09 1e-08 1e-07 1e-06 1e-05 1e-04 1e-11 0.8 1.5 tx_en = 0 tx_en = 1 bit-error rate vs. differential input amplitude (1.25gbps) MAX3711 toc04 differential input amplitude (mv p-p ) ber 0.8 0.7 0.6 1e-10 1e-09 1e-08 1e-07 1e-06 1e-05 1e-04 1e-11 0.5 0.9 tx_en = 0 tx_en = 1 rx input-based los threshold vs. set_los (los_en = 1 and los_range = 1) MAX3711 toc03 set_los[5:0] los threshold (mv p-p ) 60 50 40 30 20 10 50 100 150 200 250 0 07 0 2.5gbps los_lowbw = 0 deassert assert rx input-based los threshold vs. set_los (los_en = 1 and los_range = 0) MAX3711 toc02 set_los[5:0] los threshold (mv p-p ) 60 50 30 40 20 10 10 20 30 40 50 60 70 80 90 0 07 0 2.5gbps los_lowbw = 0 deassert assert differential rx output swing vs. set_cml MAX3711 toc01 set_cml[3:0] differential output (v p-p ) 14 12 10 8 6 4 2 0.5 0.6 0.7 0.8 0.9 1.0 0.4 01 6 2.488gbps optical eye MAX3711 toc08 58ps/div dpc closed loop 11.9db e r 3.07gbps optical eye MAX3711 toc09 56ps/div apc closed loop 8.6db e r 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 10 pin configuration pin description pin name output function equivalent circuit 1 fault transmitter fault, open-drain. logic-high indicates a fault condition has been detected (fault_pol = 1). it remains high even after the fault condition has been removed. a logic-low occurs when the fault condition has been removed and the fault latch has been cleared by toggling the disable signal, or by setting modectrl = 68h. fault should be pulled up to 3.3v supply through a 4.7k i to 10k i resistor. note that pulling up the pin to a supply voltage above v ccx can turn on the esd protection diode. 2 disable transmitter disable input, ttl/cmos. set to logic-low for normal operation (dis_pol = 1). logic-high or open disables both the modulation current and the bias current. internally pulled up by a 100k i resistor to v ccx . v ccx fault esd protection v ccx v ccx v ccx disable esd protection 100k 23 24 22 21 8 7 9 disable rout+ rout- scl 10 fault mdref iout tout mdin tp 12 rin+ 45 6 17 18 16 14 13 v ccx ep los n.c. n.c. sda v ccd csel v ccto 3 15 rin- 20 11 tin+ v ccx 19 12 tin- bmon tqfn (4mm x 4mm) top view + MAX3711 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 11 pin description (continued) pin name output function equivalent circuit 3 csel chip-select input, cmos. setting csel to logic-high starts a cycle. setting csel to logic- low ends the cycle and resets the control state machine. internally pulled down by a 75k i resis - tor to ground. 4, 5 rout+, rout- differential receiver data output, cml. this out - put has 50 i terminations to v cc . polarity is set by the rx_pol bit. 6 scl serial-clock input, cmos. internally pulled down by a 75k i resistor to ground. 7 v ccd power supply. provides supply voltage to the digital block. 8 sda serial-data bidirectional input, cmos. open- drain output. this pin has a 75k i internal pullup, but it requires an external 4.7k i to 10k i pullup to meet 3-wire timing specifications. v ccx v ccd csel esd protection 75k v ccx rout+ rout- esd protection set_cml 50 50 v ccd v ccd scl esd protection 75k v ccd v ccd v ccd sda esd protection 75k 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 12 pin description (continued) pin name output function equivalent circuit 9, 10 n.c. no connection. not internally connected. 11, 12 tin+/tin- differential transmitter data input. this differen - tial 13k i input is compatible with lvds, pecl, and cml input levels. the polarity is set by the tx_pol bit. 13 tp test pin. leave pin unconnected. 14 tout noninverting laser diode modulation and bias current output. connect to the cathode of the laser diode. a differential 1 at tin results in cur - rent flow at the laser. 15 iout inverting laser diode modulation and bias current output. connect to the anode of the laser diode. 16 v ccto power-supply connection. provides supply volt - age to the transmitter output. v ccx 1.3v tin+ tin- esd protection 6.3k 210 6.3k 210 iout v ccto tout esd protection modreg biasreg 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 13 pin description (continued) pin name output function equivalent circuit 17 mdref monitor diode reference. connect this to a fil - tered v ccto . 18 mdin monitor diode input. connect this pin to the anode of the monitor diode. mdin can be left open for open-loop operation. keep capacitance minimized at this pin. 19 bmon bias current/laser power monitor output. current out of this pin develops a ground-refer - enced voltage across external resistor(s) that is proportional to the laser bias current or mdin pin current. the current sourced by this pin is typi - cally 1/72 the laser bias current. 20, 23 v ccx transceiver power supply. provides supply volt - age to the receiver and transmitter cores. 21, 22 rin-, rin+ differential receiver data input. contains 100 i differential termination on-chip. connect these inputs to the tia outputs using 1 f f coupling capacitors. v ccx mdin v ccx mdref 40 v ccx bmon esd protection v ccx v ccx - 1.2v rin+ rin- esd protection 50 50 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 14 pin description (continued) pin name output function equivalent circuit 24 los receiver loss-of-signal (los) output, open drain. this output goes to a logic-high when the level of the input signal drops below the set_los register threshold. polarity is set by los_pol. all los circuitry can be disabled by setting los_en = 0. the los output is pulled up to host v cc with a 4.7k i to 10k i resistor. ep exposed pad. ground. this is the only electri - cal connection to ground on the MAX3711 and must be soldered to circuit board ground for proper thermal and electrical performance (see the exposed-pad package and thermal considerations section). v ccx los esd protection 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 15 figure 2. functional diagram v ccd v ccx - 1.2v 1.3v 50 75k 75k 75k 100k 6.5k 6.5k 50 50 rout+ rout- los iout tout bmon mdin mdref bias monitor tx power monitor 50 1 0 1 0 1 0 1 0 rin+ rin- sda scl csel disable fault tin+ tin- az_en los_range ro_en sq_en slew_rate los_pol los_en dis_pol fault_pol tx_pol tx_en krmd kimd rx_pol v ccx offset correction slew-rate control output control logic loss of signal 6b dac set_los 4b dac set_cml 8b set_2xapc 9b dac modreg 10b dac biasreg 3-wire interface power-on reset cascode eye safety and output control apc/erc loop laser power startup management 8b set_imod 8b set_ibias 125mbps to 3.125gbps limiting amplifier digit al control circuitr y 125mbps to 3.125gbps laser driver v ccx MAX3711 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 16 detailed description the MAX3711 combines a high-gain limiting amplifier with a laser driver. the limiting amplifier includes offset cancellation and programmable signal-detect threshold. the laser driver includes average power and extinction ratio control, average or peak laser power measurement capability, overcurrent limiting, bias current/md current monitor, and fault detection. a 3-wire serial control inter - face enables an external controller to set all parameters necessary for operation of the limiting amplifier and laser diode driver. the interface enables real-time laser bias and/or modulation current control and provides operation and status readouts. the features and performance are specifically designed to be compatible with low-cost microcontrollers. the MAX3711 includes all the logic required for laser protec - tion, control loop operation, and monitor diode current measurement. 1.25mbps to 3.125gbps limiting amplifier block description limiting amplifier the limiting amplifier consists of a multistage amplifier, offset-correction circuit, output buffer, and loss-of-signal/ signal-detect circuitry. its low noise (1.3mv p-p typical sensitivity) and high gain can provide 0.3db to 0.5db of additional sensitivity in typical 2.5gbps applications. programmable configuration options (los threshold, los polarity, cml output with adjustable level, slew rate, and output polarity) enhance layout flexibility and rosa compatibility. high-speed input signal path the inputs, rin, have an internal 100 i differential termination and should be ac-coupled to the trans- impedance amplifier. offset cancellation the limiting amplifier has approximately 68db of gain, which makes it very susceptible to both dc off - sets and pulse-width distortion in the signal from the transimpedance amplifier. a low-frequency feedback loop provides offset cancellation to compensate for these effects; the nominal small-signal low-frequency cutoff of the offset cancellation loop is 10khz when 1 f f ac-coupling capacitors are used. loss-of-signal circuitry (los) this block detects amplitude of the incoming signal and compares it against a preset threshold, which is con - trolled by set_los [5:0]. the programming range of the los assert level is 3.8mv p-p to 138mv p-p . changing the los threshold during operation (i.e., with - out executing a reset) does not cause a glitch or incor - rect los output. the detector has 2db of hysteresis to control chatter at the los output. the los output polarity is controlled by the los_pol bit. the entire los circuit block can be disabled by setting los_en = 0. output drivers the cml data outputs, rout, are terminated with 50 i to v ccx . the differential output level can be programmed through the set_cml [3:0] register between 410mv p-p and 1000mv p-p , and the output polarity can be inverted. serial commands can also be used to manually disable the output (to its common-mode voltage, i.e., near zero differential voltage dc), or cause the limiting amp to automatically disable the output under an los condition (squelch through the sq_en bit). the output slew rate can be optimized for either 2.5gbps or low data-rate operation by setting the slew_rate bit. 1.25mbps to 3.125gbps laser driver block description the laser driver consists of tin q differential high-speed input buffers, tin q polarity switch buffers, disable ttl/cmos input buffer, combined laser modulator and bias generator, monitor diode current input buffer with calibration features, analog bias current monitor, analog transmit power monitor, apc and erc loop circuitry, eye- safety monitoring, and fault output buffer. differential high-speed input buffers the high-speed laser driver data inputs, tin q , are com - patible with lvds, lvpecl, and cml outputs. tin q should be dc-coupled with external differential termina - tion of 100 i placed close to the input pins. the tin q inputs can also be dc-coupled to an lvds output using 100 i differential termination. the polarity of tin q can be inverted by the tx_pol bit. laser modulator and bias generator the laser modulator provides dc coupled current into the cathode of the laser diode at the tout pin. the modulation current amplitude is set by modreg [8:0]. 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 17 the modulation current dac guarantees modulation amplitudes up to 85ma. the amplitude of the laser bias current is controlled by biasreg [9:0]. the laser bias current dac guarantees values up to 70ma. note that tout and iout are not differential in the gen - eral sense; tout must be connected to the laser diode cathode and the cascoded iout pin must be connected to the laser diode anode. monitor diode current input buffer the input stage covers a large input signal range by having adjustable gain settings. the kimd[1:0] bits set the current gain. this is followed by an adjustable tran - simpedance amplifier (tia). the tia gain settings are programmed by the krmd[2:0] bits. the input has high bandwidth, allowing the MAX3711 to monitor not only average laser power, but also extinction ratio. mdin current is mirrored at the bmon output and select - ed by setting mdmon_en = 1 and mon_sel = 1. in this mode, the current sourced by bmon is scaled by k imd , where the value k imd is set by the kimd[1:0] bits. the high bandwidth of the mdinCbmon path enables tun - ing of the laser-to-monitor diode external components to minimize crosstalk and to optimize filtering on the mdin signal. average power and extinction ratio control circuitry the MAX3711 includes full closed-loop control of laser average power and extinction ratio. figure 4 shows the dual power control, or dpc, loop. operation is as follows: the monitor diode (md) is connected to the mdin pin, and the md current is amplified by a gain set by the kimd[1:0] and krmd[2:0] bits. the output of the mdin input buffer is sent through a programmable filter, controlled by the cprg[4:0], mdlbw[1:0], and mdrng bits. the filter output is fed to a 10ms/s analog-to-dig - ital converter (adc), where the peak values of both the high current and the low current (pro - portional to the high power and low power of the laser) are determined and converted to 16-bit digi - tal words, md0regh [7:0] and md0regl [7:0], and md1regh [7:0] and md1regl [7:0]. the val - ues are md0[15:8] = md0regh[7:0], md0[7:0] = md0regl[7:0], md1[15:8] = md1regh[7:0], md1[7:0] = md1regl[7:0]. the number of averages used to generate md1[15:0] and md0[15:0] is deter - mined by mdavg_cnt. figure 3. interfacing to the MAX3711 tin inputs tin lvpecl v cm = v cc x (82/212) v cc 130 v cc 130 82 82 tin lvds 100 v cm is set by the driver. tin cml 100 v cm = v cc - (v in /2.5) v cm is set by host v cc and the driver output swing. 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 18 to monitor average transmitter power, use the follow - ing equation: avg md m d0[15 : 0] m d1[1 5 : 0 ] 8 p 0.00292 512 kimd krmd k + = where k md is the laser diode to monitor diode gain in a/w. for example, if k md = 0.1, kimd[1:0] = 00 (gain = 1), krmd[2:0] = 000 (gain = 2800 i ), md0[15:0] = 35750d, and md1[15:0] = 44680d, the calculated p avg = 1mw. returning to the main forward path of the dpc, md1[15:0] and md0[15:0] are used to compute the average power and extinction ratio at the mdin input in the computation block ( figure 4 ). these values are compared with the target values of average power ( set_2xapc [7:0]) and extinction ratio (erset[3:0] bits). if the error magnitude is greater than the value set by thrshld, then the output registers biasreg [9:0] and modreg [8:0] are updated with the error value. the update value is limited by the biasinc [3:0] and modinc [3:0] registers. the ibiasmax [7:0] and imodmax [7:0] values are used to limit biasreg [9:2] and modreg [8:1]. note only the upper 8 bits of the output current registers are compared. the control block ( figure 4 ) controls the updating and startup behavior of the entire dpc. the bits apc_en and dpc_en control the operating mode of the dpc: full dpc mode. dpc_en = 1, apc_en = x: biasreg [9:0] and modreg [8:0] are controlled based on the set_2xapc [7:0] register and erset[3:0] targets. apc only mode. dpc_en = 0, apc_en = 1: the biasreg [9:0] register is controlled based on the set_2xapc [7:0] target and modreg [8:0] is controlled directly through set_imod [7:0]. modinc [4:0] is used to adjust the lower bits of modreg [8:0] using twos complement to increase or decrease its value. figure 4. dpc loop diagram bmon (i bias /72) md0regh[7:0], md0regl[7:0] md1regh[7:0], md1regl[7:0] biasinc[4:0] set_2xapc[7:0] set_imod[7:0] modinc[4:0] set_ibias[7:0] ibiasmax[7:0] imodmax[7:0] biasreg[9:0] modreg[8:0] dac dac i bias i mod computation control adc mdin disable mdmon_en, mon_sel mdavg_cnt thrshld restart dpc_run dpc_stop apc_en logic dis_pol tx_en mod_en dpc_en bias_en imupdt_en ibupdt_en erset[3:0] kimd[1:0], krmd[2:0] cprg[4:0], mdlbw[1:0], mdrng 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 19 open loop mode. dpc_en = 0, apc_en = 0: the biasreg [9:2] register is controlled directly by set_ibias [7:0] and modreg [8:1] is controlled directly by set_imod [7:0]. registers biasinc [4:0] and modinc [4:0] are used to adjust the lower bits of biasreg [9:0] and modreg [8:0] using twos complement. the dpc acquisition mode is controlled by several bits: restart, ibupdt_en, imupdt_en, dpc_run, and dpc_stop. anytime the dpc fsm is reset (through an unmasked fault or if restart is issued), biasreg [9:2] and modreg [8:1] are optionally reinitialized to set_ibias [7:0] and set_imod [7:0], respectively. reinitialization is accomplished by setting bit ibupdt_en (for biasreg [9:0]) or imupdt_en (for modreg [8:0]) to 1. the bit restart resets the state machine, sets dpc_run = 1, and reinitializes biasreg [9:2] and modreg [8:1], subject to ibupdt_en and imupdt_en, respectively. the state machine then moves to a coarse acquisition mode, a binary- search mode, and finally a steady-state mode where averaging begins. in steady-state mode, the ssmode status bit is set high and restart is reset. in coarse acquisition mode, the biasreg [9:0] step size is 2 x biasinc [3:0] and the modreg [8:0] step size is 2 x modinc [3:0]. an update is made every 200ns. the bit dpc_stop prevents the dpc from updat - ing the output registers, while dpc_run allows the dpc to operate. if a 1 is written to dpc_stop, dpc_run is reset to 0. if a 1 is written to dpc_run , dpc_stop is reset to 0. writing a 0 to either bit has no affect. if the state machine is not in steady state, setting dpc_stop = 1 forces it into steady state. note that the loop no longer updates biasreg [9:0] and modreg [8:0] since dpc_stop is high. power-on reset (por) a power-on-reset circuit provides proper startup sequenc - ing and ensures that the laser is off while the supply volt - age is ramping or below a specified threshold (~2.55v). the serial interface can also be used to command a man - ual reset at any time by setting softreset = 1, which is identical to a power-on reset. when using softreset, the MAX3711 transmitter must be disabled, either by the disable pin or by setting tx_en = 0. either power-on or soft reset requires approximately 50 f s to complete. the recommended por procedure is as follows: ? por sets all registers to their defaults. ? controller initiates 3-wire communication after por with MAX3711 by repeatedly reading out the lvflag (v ccto flag) bit until the 1-to-0 transition occurs (v ccto is needed for the tx output and dpc only). ? controller writes/initializes all registers (see the dpc startup procedure). bmon functions the bmon pin can be selected to either provide a moni - tor of the laser bias current or the mdin pin current. it sources 1/72 of the laser bias current when the mon_sel bit is 0 (default). a resistor to ground sets the full-scale voltage range and can be monitored by an external adc. when bmon is set to replicate the mdin current (mon_sel = 1 and mdmon_en = 1), the pin sources a kimd[1:0]-scaled md current. eye safety circuitry the eye safety circuitry consists of fault detection, faults, and fault masking. certain pins of the device are moni - tored for conditions that indicate non-standard operation ( figure 5 ). a fault disables the transmitters bias and modulation current dacs and the tx circuitry remains in a fault state until cleared by toggling disable, cycling power, or writing 68h to modectrl [7:0]. faults are maskable, meaning that by setting the mask bits high, specific faults do not cause the device to become disabled. faults are indicated by the txinlos, fmd, fiout, lvflag, and ftout bits . note that a fault at mdin (indicated by fmd) can be masked, but still causes the dpc to stop opera - tion, regardless of the mask. in this condition, the dpc must be started to resume operation (set dpc_run = 1 or restart = 1). 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 20 figure 5. eye safety circuitry 0.35v <0> tx_fault <1> ftout <2> fiout <3> fmd <4> txinlos <5> res <6> res <7> lvflag i mod i bias v ccto - 1.7v 0.3v txin+ txin- tout iout mdin v ccto disable 1.3v ac signal detect fault clear mode por threshold por 100k modectrl = 68h register (txst a t1) register (txstat1) address = h0x1e reset 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 21 table 1. circuit response to single-point faults note 1: normaldoes not affect laser power. note 2: supply-shorted current is assumed to be primarily on the circuit board (outside this device) and the main supply is col - lapsed by the short. note 3: normal in functionality, but performance could be affected. warning: shorted to v cc or shorted to ground on some pins can violate the absolute maximum ratings . pin name short to v cc short to gnd open 1 fault no effect, but open-drain nmos output life can be stressed (note 1) no effect (note 1) no effect (note 1) 2 disable tx output is off if dis_pol = 1 (default) no effect if dis_pol = 0 no effect if dis_pol = 1 (default) tx output is off if dis_pol = 0 (note 1) tx output is off if dis_pol = 1 (default) no effect if dis_pol = 0 3 csel no effect (note 1) no effect (note 1) no effect (note 1) 4 rout+ no effect (note 1) no effect (note 1) no effect (note 1) 5 rout- no effect (note 1) no effect (note 1) no effect (note 1) 6 scl no effect (note 1) no effect (note 1) no effect (note 1) 7 v ccd no effect por on por on 8 sda no effect, but open-drain nmos output life can be stressed (note 1) no effect (note 1) no effect (note 1) 9 n.c. no effect no effect no effect 10 n.c. no effect no effect no effect 11 tin+ txinlos flag asserted txinlos flag is asserted no effect depending on tin- amplitude 12 tin- txinlos flag asserted txinlos flag is asserted no effect depending on tin+ amplitude 13 tp no effect no effect no effect 14 tout laser diode is off fault asserted, laser power exceeds programmed value fault asserted 15 iout no effect fault asserted fault asserted 16 v ccto no effect lvflag flag asserted, laser diode is off lvflag asserted, laser diode is off 17 mdref no effect no effect no effect 18 mdin output current limited by ibiasmax[7:0] and imodmax[7:0] fmd flag asserted output current limited by ibiasmax[7:0] and imodmax[7:0] 19 bmon no effect no effect (note 1) no effect 20 v ccx no effect board supply collapsed, por on (note 2) no effect (note 3)redundant path 21 rin- no effect no effect no effect 22 rin+ no effect no effect no effect 23 v ccx no effect board supply collapsed, por on (note 2) no effect (note 3)redundant path 24 los no effect, but open-drain nmos output life can be stressed no effect no effect ep por on, i/o device life can be stressed (note 2) no effect por on 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 22 3-wire interface the MAX3711 implements a proprietary 3-wire digital interface, and an external controller generates the clock. the 3-wire interface consists of an sda bidirectional data line, an scl clock signal input, and a csel chip-select input (active high). the external master initiates a data transfer by asserting the csel pin. then it generates a clock signal after the csel pin has been set to a logic- high. all data transfers are most significant bit (msb) first. protocol each nonblock operation consists of 16-bit transfers (15- bit address/data, 1-bit rwn). the bus master generates 16 clock cycles to scl. all operations transfer 8 bits to the MAX3711; the rwn bit determines if the cycle is read or write. see table 2 . write mode (rwn = 0) the master generates 16 clock cycles at scl in total. it outputs a total of 16 bits (msb first) to the sda line at the falling edge of the clock. the master closes the trans - mission by setting csel to 0. figure 6 shows the 3-wire interface timing. read mode (rwn = 1) the master generates 16 clock cycles at scl in total. the master outputs a total of 8 bits (msb first) to the sda line at the falling edge of the clock. the sda line is released after the rwn bit has been transmitted. the slave outputs 8 bits of data (msb first) at the rising edge of the clock. the master closes the transmission by setting csel to 0. figure 6 shows the 3-wire interface timing. block write mode (rwn = 0) the master initiates the block write mode by writing h0x12 into the modectrl [7:0] register. the block write mode starts by stretching the csel interval beyond the 16 clock cycles, and it is exited automatically when the master has written into any register other than modectrl [7:0] and csel has been set to 0. the two different modes of operation are described below: block read mode (rwn = 1) the master initiates the block read mode by accessing any register address and setting the rwn bit to 1. the block read mode starts by stretching the csel interval beyond the 16 clock cycles, and it is exited automatically when the master has set csel to 0. table 2. digital communication word structure bit name description 15:9 address 7-bit internal register address 8 rwn 0: write; 1: read 7:0 data 8-bit read or write data block write mode 1 (starts at address h0x01) master sets csel to 1 addr h0x00 + rwn = 0 data h0x12 data 1 (addr h0x01) data 2 (addr h0x02) data 3 (addr h0x03) data 4 (addr h0x04) . . . data 19 (addr h0x13) master sets csel to 0 block write mode 2 (starts at any address) master sets csel to 1 addr h0x00 + rwn = 0 data h0x12 master sets csel to 0 master sets csel to 1 addr h0xn + rwn = 0 data 1 (addr h0xn) . . . data i (addr h0xn + i - 1) master sets csel to 0 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 23 figure 6. 3-wire digital interface timing diagram mode control to speed up the laser control by a factor of two, the modinc , biasinc , and apcinc registers can be updated in normal mode. all other registers are read-only in normal mode, which is the default mode. setup mode allows the master to write unrestricted data into any register except the status ( txstat1 , txstat2 , dpcstat , and rxstat ) and read-only ( biasreg , modreg , md1regh , md1regl , md0regh , md0regl ) registers. to enter the setup mode, h0x12 is written to the modectrl register. after the modectrl register has been set to h0x12 ,the next operation is unrestricted. the setup mode is automatically exited after the next operation is finished. this sequence must be repeated if further unrestricted settings are necessary. fault-clear mode allows the clearing of all faults, and restarts operation of the device. it is activated by writing 68h to the modectrl register. figure 7. 3-wire implementation recommendation using a generic microcontroller csel scl sda csel scl sda 12 34 56 78 a6 91 01 11 21 31 41 5 0 12 34 56 789 10 11 12 13 14 15 0 a5 a4 a3 a2 a1 rwn d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 rwn write mode read mode a0 a6 a5 a4 a3 a2 a1 a0 t l t l t ch t cl t ds t dh t ch t cl t ds t d t dh t t t t MAX3711 75k scl c sda csel scl sdi sdo csel 75k 75k 5k c p v ccd 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 24 register descriptions mode control register (modectrl), address: h0x00 receiver control register 1 (rxctrl1), address: h0x01 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name modectrl [7] modectrl [6] modectrl [5] modectrl [4] modectrl [3] modectrl [2] modectrl [1] modectrl [0] read/write w w w w w w w w por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the modectrl register sets the devices operational mode. bit name description d[7:0] modectrl[7:0] there are three operational modes for the device: 00h = normal mode (default) 12h = setup mode 68h = fault clear mode bit d7 d6 d5 d4 d3 d2 d1 d0 bit name x x x x x x los_lowbw ro_en read/write x x x x x x r/w r/w por state x x x x x x 0 1 reset upon read x x x x x x no no the rxctrl1 register sets the operation of the rx circuitry. bit name description d1 los_lowbw sets the bandwidth of the rx los circuitry. 0 = 2.5gbps (default) 1 = 1.25gbps d0 ro_en enables the rx output stage. 0 = disabled 1 = enabled (default) 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 25 receiver control register 2 (rxctrl2), address: h0x02 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name los_range los_en los_pol rx_pol sq_en rx_en slew_rate az_en read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 1 1 1 0 1 1 1 reset upon read no no no no no no no no the rxctrl2 register sets the operation of the rx circuitry. bit name description d7 los_range sets the amplitude range of the rx los circuitry. 0 = 5 to 36mv p-p assert threshold (default) 1 = 14 to 115mv p-p d6 los_en enables the los circuitry. 0 = disabled 1 = enabled (default) d5 los_pol sets the output polarity of the los output. 0 = inverse 1 = normal (default) d4 rx_pol sets the output polarity of rout. 0 = inverse 1 = normal (default) d3 sq_en enables squelch of the output due to input signal below los threshold. 0 = disabled (default) 1 = enabled d2 rx_en enables the entire rx block circuitry. 0 = disabled 1 = enabled (default) d1 slew_rate sets the slew rate of the rx output drivers. 0 = slow 1 = normal (default) d0 az_en auto-zero enable. this enables the rx input offset cancellation loop. 0 = disabled 1 = enabled (default) 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 26 cml output amplitude register (set_cml), address: h0x03 los threshold register (set_los), address: h0x04 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name x x x x set_cml[3] set_cml[2] set_cml[1] set_cml[0] read/write x x x x r/w r/w r/w r/w por state x x x x 1 0 1 0 reset upon read x x x x no no no no the set_cml register sets the amplitude of rout. bit name description d[3:0] set_cml[3:0] sets the amplitude of the rx output driver. typical values for amplitude: 0000 = 410mv p-p differential output amplitude . . . 1010 = 800mv p-p differential output amplitude (default) . . . 1111 = 1000mv p-p differential output amplitude bit d7 d6 d5 d4 d3 d2 d1 d0 bit name x x set_los[5] set_los[4] set_los[3] set_los[2] set_los[1] set_los[0] read/write x x r/w r/w r/w r/w r/w r/w por state x x 0 0 1 1 0 0 reset upon read x x no no no no no no the set_los register adjusts the threshold of the los circuitry. bit name description d[5:0] set_los[5:0] sets the threshold of the los circuitry. 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 27 transmitter configuration register (txcfg), address: h0x05 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name trf[1] trf[0] res res res res res res read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 0 0 0 1 1 0 reset upon read no no no no no no no no the txcfg register configures the tx circuitry. bit name description d[7:6] trf[1:0] adjusts the output rise/fall time of the laser transmitter. 00 = slow (default) 11 = fast d[5:0] res reserved 000110 = normal (default) 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 28 transmitter control register 1 (txctrl1), address: h0x06 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name dpc_stop res res mdrng txstatmsk [2] txstatmsk [1] txstatmsk [0] softres read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 0 0 1 1 1 0 reset upon read no no no no no no no yes the txctrl1 register configures the tx circuitry. bit name description d7 dpc_stop halts the apc and dpc loops. the dpc_run bit is reset. 0 = no action (default) 1 = halts loops and resets dpc_run bit d[6:5] res reserved 00 = normal (default) d4 mdrng md range bit. 0 = fast tosa md response (default) 1 = slow tosa md response d3 txstatmsk[2] sets mask for lvflag, ftout, and fiout. 0 = flags do cause fault condition 1 = flags do not cause fault condition (default) d2 txstatmsk[1] sets mask for txinlos. 0 = flag do cause fault condition 1 = flag do not cause fault conditon (default) d1 txstatmsk[0] sets mask for fmd. 0 = flag do cause fault condition 1 = flag do not cause fault condition (default) d0 softres resets the contents of the registers to their default values. the device must be disabled (disable pin or tx_en) to perform a soft reset. 0 = normal (default) 1 = reset 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 29 transmitter control register 2 (txctrl2), address: h0x07 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name fault_pol mon_sel mdmon_en aux_rstr txlos_md dis_pol res tx_pol read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 1 0 0 0 0 1 1 1 reset upon read no no no no no no no no the txctrl2 register configures the tx circuitry. bit name description d7 fault_pol sets the polarity of the fault pin. 0 = inverted 1 = normal (default) d6 mon_sel sets the bmon pin to output a mirror of bias current or mdin current. 0 = laser bias current mirrored at 1/72 ratio (default) 1 = mdin current mirrored at bmon d5 mdmon_en enables bmon output. 0 = laser bias current mirrored (overrides mon_sel) (default) 1 = mdin current mirrored at bmon at a ratio of the current gain setting at kimd d4 aux_rstr enables restarting of apc and erc loops by means of disable pin. 0 = disabled (default) 1 = enabled d3 txlos_md sets output power mode during a loss of signal at txin. 0 = output switches to average current value when tx los occurs (default) 1 = output unaffected when tx los occurs d2 dis_pol sets polarity for disable pin. 0 = inverted 1 = normal (default) d1 res reserved 1 = normal (default) d0 tx_pol sets tx data path polarity. 0 = inverted 1 = normal (default) 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 30 transmitter control register 3 (txctrl3), address: h0x08 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name res dpc_en apc_en kimd[1] kimd[0] krmd[2] krmd[1] krmd[0] read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the txctrl3 register configures the tx circuitry. bit name description d7 res reserved 0 = normal (default) d6 dpc_en enables dual power control of the laser (closed-loop control of bias and modulation cur - rent). 0 = erc loop disabled (freeze), apc loop mode depends on apc_en bit (default) 1 = erc and apc loops enabled d5 apc_en enables apc loop (closed-loop control of bias current). 0 = disabled (default) 1 = enabled d[4:3] kimd[1:0] sets the current gain of the md input in 3db steps. 00 = x1 (default) 01 = x0.5 1x = x0.25 d[2:0] krmd[2:0] sets the transimpedance gain of the md input in 1.5db steps. total md input stage gain is equal to kimd gain multiplied by the krmd gain. 000 = 2800 i (default) 001 = 1980 i 010 = 1400 i 011 = 990 i 1xx = 700 i 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 31 transmitter control register 4 (txctrl4), address: h0x09 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name dint_en arx_en mdavg_cnt ibupdt_en imupdt_en mdlbw[1] mdlbw[0] erset[3] read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 1 1 0 0 0 0 1 reset upon read no no no no no no no no the txctrl4 register configures the tx circuitry. bit name description d7 dint_en routes internal clock signal to the tx signal path (used in calibration). 0 = normal (default) 1 = routes internal data to the tx signal path. note that the data must be running at tin or the dpc loop freezes. d6 arx_en enables auto-ranging for the apc loop. 0 = auto-ranging disabled 1 = auto-ranging enabled; see the tracking error compensation section d5 mdavg_cnt sets the number of md averages. 0 = dpc updates based on 32 averages in steady state 1 = dpc updates based on 256 averages in steady state (default) d4 ibupdt_en sets the way biasreg [9:0] is written to: apc on: 0 = maintains last value of biasreg [9:0] in initialization (default) 1 = fault/restart initializes biasreg [9:2] with set_ibias [7:0] apc off: 0 = biasreg can only be changed by writing to biasinc [4:0] (default) 1 = if ibupdt_en is already set to 1 a write to set_ibias [7:0] is passed to biasreg [9:2] d3 imupdt_en sets the way modreg [8:0] is written to: erc on: 0 = maintains last value of modreg [8:0] in initialization (default) 1 = fault/restart initializes modreg [8:1] with set_imod [7:0] erc off: 0 = modreg [8:0] can only be changed by writing to modinc [4:0] (default) 1 = if imupdt_en is already set to 1 a write to set_imod [7:0] is passed to modreg [8:1] d[2:1] mdlbw[1:0] controls the bandwidth of the md input stage. 00 = normal mode (high-frequency signal feedthrough from tosa is small) (default) 01 = less bandwidth 10 = even less bandwidth 11 = lowest bandwidth (external filter capacitor required on md input to reduce exces - sive high-frequency signal feedthrough) d0 erset[3] sets range of extinction ratio. 0 = reduced e r setting (5 to 12) 1 = normal e r setting (10 to 24) (default) 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 32 transmitter control register 5 (txctrl5), address: h0x0a maximum bias current register (ibiasmax), address: h0x0b bit d7 d6 d5 d4 d3 d2 d1 d0 bit name erset[2] erset[1] erset[0] cprg[4] cprg[3] cprg[2] cprg[1] cprg[0] read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the txctrl5 register configures the tx circuitry. bit name description d[7:5] erset[2:0] sets extinction ratio for closed-loop operation. if erset[3] = 1: 000 = 10 (default) 001 = 12 010 = 14 011 = 16 100 = 18 101 = 20 110 = 22 111 = 24 if erset[3] = 0: 000 = 5 001 = 6 010 = 7 011 = 8 100 = 9 101 = 10 110 = 11 111 = 12 d[4:0] cprg[4:0] programs the internal md current reference filter. used during calibration to match extinction ratios of the external prbs data and the slower internal pattern enabled by dint_en. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name ibiasmax [7] ibiasmax [6] ibiasmax [5] ibiasmax [4] ibiasmax [3] ibiasmax [2] ibiasmax [1] ibiasmax [0] read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 0 1 0 0 1 0 reset upon read no no no no no no no no the ibiasmax register sets maximum bias current limit. bit name description d[7:0] ibiasmax[7:0] programs the maximum settable bias current (limits the maximum value that can be written to the biasreg [9:2] register). note that it only relates to the eight most signifi - cant bits of the biasreg register. 18d = 6.3ma bias current limit (default) 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 33 maximum modulation current register (imodmax), address: h0x0c initial or open-loop bias value register (set_ibias), address: h0x0d bit d7 d6 d5 d4 d3 d2 d1 d0 bit name imodmax [7] imodmax [6] imodmax [5] imodmax [4] imodmax [3] imodmax [2] imodmax [1] imodmax [0] read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 1 1 0 0 0 0 reset upon read no no no no no no no no the imodmax register sets maximum modulation current limit. bit name description d[7:0] imodmax[7:0] programs the maximum settable modulation current (limits the maximum value that can be written to the modreg [8:1] register). note that it only relates to the eight most sig - nificant bits of the modreg register. 48d = 19.5ma modulation current limit (default) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name set_ ibias[7] set_ ibias[6] set_ ibias[5] set_ ibias[4] set_ ibias[3] set_ ibias[2] set_ ibias[1] set_ ibias[0] read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 0 0 0 1 0 0 reset upon read no no no no no no no no the set_ibias register sets the initial or open-loop bias current. bit name description d[7:0] set_ibias[7:0] programs the initial or open-loop bias current. the value in this register is sent to the biasreg [9:0] registers eight most significant bits. 4d = 2.1ma bias current (default) 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 34 initial or open-loop modulation value register (set_imod), address: h0x0e bias increment register (biasinc), address: h0x0f bit d7 d6 d5 d4 d3 d2 d1 d0 bit name set_ imod[7] set_ imod[6] set_ imod[5] set_ imod[4] set_ imod[3] set_ imod[2] set_ imod[1] set_ imod[0] read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 0 1 0 1 0 0 reset upon read no no no no no no no no the set_imod register sets the initial or open-loop modulation current. bit name description d[7:0] set_imod[7:0] programs the initial or open-loop bias current. the value in this register is sent to the modreg [8:0] registers eight most significant bits. 20d = 10ma modulation current (default) bit d7 d6 d5 d4 d3 d2 d1 d0 bit name x x x biasinc[4] biasinc[3] biasinc[2] biasinc[1] biasinc[0] read/write x x x r/w r/w r/w r/w r/w por state x x x 0 0 0 0 0 reset upon read x x x no no no no no the biasinc register increments/decrements bias current as described below bit name description d[4:0] biasinc[4:0] apc enabled: biasinc[3:0] controls the bias step (coarse acquisition max step = 2 x biasinc[3:0]). apc disabled: laser bias current increment/decrement applied to biasreg [9:0] upon write (twos com - plement number, the range is +15/-16). 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 35 modulation increment register (modinc), address: h0x10 average laser power-setting register (set_2xapc), address: h0x11 apc increment register (apcinc), address: h0x12 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name x x x modinc[4] modinc[3] modinc[2] modinc[1] modinc[0] read/write x x x r/w r/w r/w r/w r/w por state x x x 0 0 0 0 0 reset upon read x x x no no no no no the modinc[4:0] register increments/decrements modulation current as described below. bit name description d[4:0] modinc[4:0] erc enabled: modinc [3:0] controls the mod step (coarse acquisition max step = 2 x modinc[3:0]). erc disabled: laser modulation current increment/decrement applied to modreg [8:0] upon write (twos complement number, the range is +15/-16). bit d7 d6 d5 d4 d3 d2 d1 d0 bit name set_ 2xapc[7] set_ 2xapc[6] set_ 2xapc[5] set_ 2xapc[4] set_ 2xapc[3] set_ 2xapc[2] set_ 2xapc[1] set_ 2xapc[0] read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 1 0 0 0 0 0 reset upon read no no no no no no no no the set_2xapc register sets the average laser power for the apc loop (see the design procedure section for more information). bit name description d[7:0] set_2xapc[7:0] average laser power setting x 2. this register must be maintained within the 64 to 255 range for proper operation. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name x x x x apcinc[3] apcinc[2] apcinc[1] apcinc[0] read/write x x x x r/w r/w r/w r/w por state x x x x 0 0 0 0 reset upon read x x x x no no no no the apcinc register increments/decrements the set_2xapc register. bit name description d[3:0] apcinc[3:0] increments or decrements the set_2xapc [7:0] value with the twos complement value from apcinc[3:0] (the range is +7/-8). 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 36 transmitter control register 6 (txctrl6), address: h0x13 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name thrshld dpc_run restart soft_rstr [1] soft_rstr [0] bias_en mod_en tx_en read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 1 0 0 0 1 1 0 reset upon read no no yes no no no no no the txctrl6 register configures the tx circuitry. bit name description d7 thrshld sets threshold for updating biasreg [9:0] in apc mode and biasreg[9:0] and modreg [8:0] in dpc mode. 0 = 0.125lsb (default) 1 = 0.75lsb d6 dpc_run controls the apc and erc loops. 0 = no action 1 = apc and erc loops start from prefreeze conditions (subject to ibupdt_en and imupdt_en if starting from reset state); resets dpc_stop bit (default) d5 restart forces apc and erc loops into acquisition mode from reset state. once the loop is in steady state, the restart bit is reset. 0 = disabled (default) 1 = enabled d[4:3] soft_rstr[1:0] soft restart for the dpc 00 = fastest acquisition (default) . . . 11 = slowest (least disruptive) acquisition d2 bias_en enables the bias dac. 0 = bias dac disabled 1 = bias dac enabled (default) d1 mod_en enables the modulation dac. 0 = mod dac disabled 1 = mod dac enabled (default) d0 tx_en enables the tx data path, control loops, and the bias and modulation dacs. 0 = tx disabled (default) 1 = tx enabled 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 37 bias dac readback register (biasreg), address: h0x16 modulation dac readback register (modreg), address: h0x17 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name biasreg [9] biasreg [8] biasreg [7] biasreg [6] biasreg [5] biasreg [4] biasreg [3] biasreg [2] read/write r r r r r r r r por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the biasreg register is a read-only register for the tx bias dac. bit name description d[7:0] biasreg[9:2] bias current dac readback. the two lsbs for this register are located at address h0x1f. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name modreg [8] modreg [7] modreg [6] modreg [5] modreg [4] modreg [3] modreg [2] modreg [1] read/write r r r r r r r r por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the modreg register is a read-only register for the tx modulation dac. bit name description d[7:0] modreg[8:1] modulation current dac readback. the lsb for this register is located at address h0x1f. 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 38 monitor diode top peak (averaged) register (md1regh), address: h0x18 monitor diode top peak (averaged) register (md1regl), address: h0x19 bit d7 d6 d5 d4 d3 d2 d1 d0 bit name md1regh [7] md1regh [6] md1regh [5] md1regh [4] md1regh [3] md1regh [2] md1regh [1] md1regh [0] read/write r r r r r r r r por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the md1regh register is a read-only register for md top peak current. bit name description d[7:0] md1regh[7:0] stored (averaged) value for monitor-diode current peak corresponding to optical p1. md1regh[7:0] is the upper 8 bits of the 16-bit value md1[15:0]. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name md1regl [7] md1regl [6] md1regl [5] md1regl [4] md1regl [3] md1regl [2] md1regl [1] md1regl [0] read/write r r r r r r r r por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the md1regl register is a read-only register for md top peak current. bit name description d[7:0] md1regl stored (averaged) value for monitor-diode current peak corresponding to optical p1. md1regl[7:0] is the lower 8 bits of the 16-bit value md1[15:0]. 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 39 monitor diode bottom peak (averaged) register (md0regh), address: h0x1a monitor diode bottom peak (averaged) register (md0regl), address: h0x1b bit d7 d6 d5 d4 d3 d2 d1 d0 bit name md0regh [7] md0regh [6] md0regh [5] md0regh [4] md0regh [3] md0regh [2] md0regh [1] md0regh [0] read/write r r r r r r r r por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the md0regh register is a read-only register for md current. bit name description d[7:0] md0regh stored (averaged) value for monitor-diode current peak corresponding to optical p0. md0regh[7:0] is the upper 8 bits of the 16-bit value md0[15:0]. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name md0regl [7] md0regl [6] md0regl [5] md0regl [4] md0regl [3] md0regl [2] md0regl [1] md0regl [0] read/write r r r r r r r r por state 0 0 0 0 0 0 0 0 reset upon read no no no no no no no no the md0regl register is a read-only register for md current. bit name description d[7:0] md0regl stored (averaged) value for monitor-diode current peak corresponding to optical p0. md0regl[7:0] is the lower 8 bits of the 16-bit value md0[15:0]. 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 40 los status register (rxstat), address: h0x1c dual power control status register (dpcstat), address: h0x1d bit d7 d6 d5 d4 d3 d2 d1 d0 (sticky) bit name x x x x x x x los_stat read/write x x x x x x x r por state x x x x x x x 0 reset upon read x x x x x x x yes* * once flagged, these sticky registers remain flagged (logic 1) until they are read. once read, they are reset to 0 if the source of the flag has been removed. the rxstat register is a status register for the rx circuitry. bit name description d0 los_stat copy of the los status. bit d7 d6 d5 (sticky) d4 (sticky) d3 (sticky) d2 (sticky) d1 (sticky) d0 (sticky) bit name x ssmode ibiasovfl ibiasudfl imodovfl imodudfl 2xapc_ovf 2xapc_udf read/write x r r r r r r r por state x 0 0 0 0 0 0 0 reset upon read x no yes* yes* yes* yes* yes* yes* * once flagged these sticky registers remain flagged (logic 1) until they are read. once read, they are reset to 0 if the source of the flag has been removed. the dpcstat register is a status register for the dpc circuitry. bit name description d6 ssmode dpc in steady state. d5 ibiasovfl apc/dpc attempting to increase biasreg [9:2] over ibiasmax [7:0]. d4 ibiasudfl apc/dpc attempting to underflow biasreg[9:0] register. d3 imodovfl dpc attempting to increase modreg [8:1] over imodmax [7:0]. d2 imodudfl dpc attempting to underflow modreg[8:0] register. d1 2xapc_ovf apcinc [3:0] setting attempting to overflow set_2xapc [7:0] register. d0 2xapc_udf apcinc[3:0] or set_2xapc[7:0] setting attempting to decrease set_2xapc[7:0] below minimum value. if arx_en = 0 or {kimd[1:0], krmd[2:0]} = {00, 000}, minimum value is 32. if arx_en = 1 and {kimd[1:0], krmd[2:0]} {00, 000}, minimum value is 180. 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 41 transmitter status register (txstat1), address: h0x1e transmitter status register (txstat2), address: h0x1f bit d7 (sticky) d6 (sticky) d5 (sticky) d4 (sticky) d3 (sticky) d2 (sticky) d1 (sticky) d0 (sticky) bit name lvflag res res txinlos fmd fiout ftout tx_fault read/write r r r r r r r r por state 0 0 0 0 0 0 0 0 reset upon read yes* yes* yes* yes* yes* yes* yes* yes* * once flagged, these sticky registers remain flagged (logic 1) until they are read. once read, they are reset to 0 if the source of the flag has been removed. the txstat1 register is a status register for the tx circuitry. bit name description d7 lvflag v ccto undervoltage detection (fault, maskable). d[6:5] res reserved 00 = normal (default) d4 txinlos indicates tin ac signal too low (fault, maskable). when the MAX3711 senses a loss of signal at tin, the dpc loop freezes. it resumes once a signal is detected again at tin. d3 fmd mdin shorted to gnd. fault is reported, dpc is stopped, and fault output is set high (fault, maskable). d2 fiout iout open or shorted to gnd. fault is reported and fault output is set high (fault, maskable). d1 ftout tout open or shorted to gnd. fault is reported and fault output is set high (fault, maskable). d0 tx_fault a copy of fault. bit d7 d6 d5 d4 d3 d2 d1 d0 bit name x x x x x biasreg[1] biasreg[0] modreg[0] read/write x x x x x r r r por state x x x x x 0 0 0 reset upon read x x x x x no no no the txstat2 register is a status register for the tx circuitry. bit name description d[2:1] biasreg[1:0] lsbs of the biasreg register. d0 modreg[0] lsb of the modreg register. 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 42 design procedure global recommendation it is recommended to write to the MAX3711 either through use of the block write mode or by writing to registers in sequential order to ensure the proper register updating. open-loop control of transmitter average power and modulation amplitude in this mode, the laser bias and modulation currents are set by means of an external controller. the apc loop can be closed externally by using the biasinc register to update the bias current dac value. the laser modulation current can be controlled by means of a lookup table (lut). if md0[15:0] and md1[15:0] are to be used by the controller for tx power monitoring, or to implement a power-control loop, the mdin gainskimd[1:0] and krmd[2:0] bitsmust be set appropriately so that the values in the md0regh [7:0] and md1regh [7:0] reg - isters do not hit the minimum and maximum limits of 16 and 256. to operate with open-loop control of modulation and bias current, the registers need to be set as shown in table 3 . once the laser is attached and the device is powered up, the ibiasmax [7:0] and imodmax [7:0] registers should be set to limits that prevent damage to the laser. then the transmitter is enabled by setting tx_en = 1. the default modulation and bias current is low, and it is likely that no optical power will be detected until these currents are increased. the bias and modulation current can be adjusted by either writing to the set_ibias [7:0] and set_imod [7:0] registers directly or by writing to the biasinc [4:0] and modinc [4:0] registers. closed-loop control of transmitter average power, open-loop control of modulation amplitude to operate in apc mode, the registers need to be set as shown in table 4 . for apc-only calibration, see stage 1 of the closed-loop control of transmitter average power and extinction ratio section. table 3. open-loop setup bits table 4. apc setup bits address bit(s) name description value h0x08 txctrl3 6 dpc_en dual power control enable 0 5 apc_en automatic power control enable 0 h0x09 txctrl4 4 ibupdt_en bias current update 1 3 imupdt_en modulation current update 1 hx013 txctrl6 0 tx_en transmitter enable 1 address bit(s) name description value h0x08 txctrl3 6 dpc_en dual power control enable 0 5 apc_en average power control enable 1 h0x09 txctrl4 4 ibupdt_en bias current update 1 3 imupdt_en modulation current update 1 h0x13 txctrl6 0 tx_en transmitter enable 1 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 43 closed-loop control of transmitter average power and extinction ratio to operate in dpc mode, the registers need to be set as shown in table 5 . laser calibration procedure this novel feature enables the customer to speed up the calibration process and reduce the requirement on test equipment. the customer needs to provide the following: a) extinction ratio and optical average power targets b) optical average power measurement fed back to the testing algorithm c) 2 15 - 1 to 2 31 - 1 prbs data pattern at data rate of interest d) testing algorithm based on spi read/write the device automatically sets the laser bias and modula - tion current to satisfy the e r and p avg targets. if transmit - ter operation at multiple power levels is required, calibra - tion at each power level is recommended to guarantee dpc loop performance. calibration scheme: stage 1: average laser power calibration 1) set bits as shown in table 4 for apc operation, or as shown in table 5 for dpc operation. 2) provide 2 15 - 1 to 2 31 - 1 prbs data at tin. 3) set txctrl4 dint_en = 1 and tx_pol = 1. 4) if dpc operation, set erset[3:0] to target and set cprg[4:0] to 15. 5) set ibiasmax [7:0] and imodmax [7:0] to appropri - ate values according to lasers capability. 6) set set_ibias [7:0] and set_imod [7:0] to 0. 7) set modinc [3:0] and biasinc [3:0] to nonzero val - ues. 8) set set_2xapc [7:0] to b4h (this allows for 1.5db tracking error compensation range using apcinc ). 9) set txctrl6[7:0] to 67h. 10) mdin gain adjustment (repeat loop until aver - age power is equal to or above the p avg target). a) stop the loop by setting txctrl1[7] to 1. b) decrease mdin stage gain (kimd x krmd) 1.5db by increasing krmd[2:0] one value, or by decreasing krmd[2:0] one value and increasing kimd[1:0] one value. c) restart the loop by setting txctrl6 [5] to 1. 11) reduce set_2xapc [7:0] until average power mea - surement reaches the target. 12) for dpc operation, continue to stage 2. stage 2: extinction ratio calibration 1) set dpc_stop to 1. 2) to verify p avg and e r , read md0regh [7:0] and md1regh [7:0] and use the equations below to calculate the apparent p avg and e r at mdin. averaging is recommended for improved accuracy. avg_apparent 2xapc p md0regh[7 : 0] m d1r e g h[7 : 0] 8 = = + m d1 md0 i 8 m d1r e g h[7 : 0] ir i md0regh[7 : 0] = = 3) if 2xapc and ir are not sufficiently close to the set_2xapc [7:0] and erset values, set dpc_ run = 1 and go to step 2. otherwise, continue to step 4. 4) set dint_en = 0. 5) read md0regh [7:0] and md1regh [7:0]. 6) adjust cprg[4:0] until md0regh [7:0] and md1regh [7:0] satisfy the ir equation from step 2. table 5. dpc setup bits address bit(s) name description value h0x08 txctrl3 6 dpc_en dual power control enable 1 5 apc_en average power control enable 1 h0x09 txctrl4 4 ibupdt_en bias current update 1 3 imupdt_en modulation current update 1 h0x13 txctrl6 0 tx_en transmitter enable 1 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 44 if a higher ir is desired, increase cprg[4:0]; like - wise, if a lower ir is desired, decrease cprg[4:0]. 7) set txctrl6 [7:0] to 67h to restart the loop and observe that md0regh [7:0] and md1regh [7:0] are at the desired values. power leveling it is recommended to use kimd and krmd to obtain different power level settings. calibrate the dpc loop at each power level. when switching between power levels this procedure should be followed. a) stop loop by setting dpc_stop = 1. b) change gain using kimd or krmd. c) run dpc by setting dpc_run = 1. tracking error compensation it is recommended to use the apcinc register in auto- ranging mode for tracking error compensation. when arx_en is set to 1, the set_2xapc register value is automatically maintained within 180 to 255 by adjusting the krmd and kimd registers accordingly. if {kimd, krmd} = {00, 000}, the minimum set_2xapc value is reduced from 180 to 32. applications information laser safety and iec 825 using the devices laser driver alone does not ensure that a transmitter design is compliant with iec 825. the entire transmitter circuit and component selections must be considered. each user must determine the level of fault tolerance required by the application, recognizing that maxim products are neither designed nor authorized for use as components in systems intended for surgical implant into the body, for applications intended to sup - port or sustain life, or for any other application in which the failure of a maxim product could create a situation where personal injury or death could occur. 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 45 register summary addr r/w register name bit name function/description default state notes h0x00 w modectrl 7:0 modectrl [7:0] 0h: normal mode 12h: setup mode 68h: fault clear mode 0 h0x01 rw rxctrl1 1 los_lowbw set bandwidth of the los circuitry 0 = for 2.5gbps 1 = for 1.25gbps to 125mbps 0 0 ro_en enables rx output stage 0 = disable 1 = enable 1 h0x02 rw rxctrl2 7 los_range 0 = 5 to 36mv p-p 1 = 14 to 115mv p-p 0 6 los_en 0 = disable 1 = enable 1 5 los_pol 0 = inverse 1 = normal 1 4 rx_pol 0 = inverse 1 = normal 1 3 sq_en 0 = disable 1 = enable 0 2 rx_en 0 = disable complete rx block, including los 1 = enable 1 1 slew_rate 0 = slow 1 = nominal 1 0 az_en 0 = disable 1 = enable 1 h0x03 rw set_cml 3:0 set_cml [3:0] sets cml output amplitude 0d = 410mv p-p 10d = 800mv p-p 15d = 1000mv p-p 1010 10d h0x04 rw set_los 5:0 set_los [5:0] programs the los threshold 00 1100 12d h0x05 rw txcfg 7:6 trf[1:0] output tuning 00 = slow output edge speed 11 = fast output edge speed 00 5:0 res reserved 000110 = normal 000110 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 46 register summary (continued) addr r/w register name bit name function/description default state notes h0x06 rw txctrl1 7 dpc_stop 0 = no action 1 = apc and erc loops freeze and dpc_run bit is reset 0 6:5 res reserved 00 = normal 00 4 mdrng md range bit 0 = fast tosa 1 = slow tosa 0 3:1 txstatmsk [2:0] [2] = lvflag, ftout, fiout mask [1] = txinlos mask [0] = fmd mask 1 1 1 0 softres soft reset 0 h0x07 rw txctrl2 7 fault_pol controls fault pin polarity 0 = inverted 1 = normal 1 6 mon_sel 0 = bias current monitor output 1 = md current monitor output 0 5 mdmon_en 1 = enables mdmon output 0 when low, bias current monitor is automati - cally selected (overrides mon_sel) 4 aux_rstr enables restarting of apc and erc loops by means of the disable input 0 = disabled 1 = enabled 0 3 txlos_md txin los mode 0 = output squelches to average current during tx los 1 = output unaffected during tx los 0 2 dis_pol 0 = inverted 1 = normal 1 1 res reserved 1 = normal 1 0 tx_pol 0 = inverted 1 = normal 1 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 47 register summary (continued) addr r/w register name bit name function/description default state notes h0x08 rw txctrl3 7 res reserved 0 = normal 0 6 dpc_en 0 = disabled 1 = enabled 0 5 apc_en 0 = apc loop disabled (freeze) 1 = apc loop enabled 0 4:3 kimd[1:0] current gain of md input stage 00 = x1 01 = x0.5 1x = x0.25 00 2:0 krmd[2:0] voltage gain of the md input stage 000 = 2800 w 001 = 1980 w 010 = 1400 w 011 = 990 w 1xx = 700 w 000 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 48 register summary (continued) addr r/w register name bit name function/description default state notes h0x09 rw txctrl4 7 dint_en 0 = normal tin routing 1 = routes internal data to tx signal path 0 used in cali - bration 6 arx_en 0 = auto-ranging disabled 1 = auto-ranging enabled 1 5 mdavg_cnt 0 = 32 averages in steady state 1 = 256 averages in steady state 1 4 ibupdt_en apc on: 0 = maintains last value of biasreg[9:0] in initialization (default) 1 = fault/restart initializes biasreg[9:2] with set_ibias[7:0] apc off: 0 = biasreg can only be changed by writing to biasinc[4:0] (default) 1 = if ibupdt_en is already set to 1 a write to set_ibias[7:0] is passed to biasreg[9:2] (subject to eob_en) 0 3 imupdt_en erc on: 0 = maintains last value of modreg[8:0] in initialization (default) 1 = fault/restart initializes modreg[8:1] with set_imod[7:0] erc off: 0 = modreg[8:0] can only be changed by writing to modinc[4:0] (default) 1 = if imupdt_en is already set to 1 a write to set_imod[7:0] is passed to modreg[8:1] (subject to eob_en) 0 2:1 mdlbw[1:0] controls the bandwidth of the md input stage 00 = normal mode ( hf signal feedthrough from the tosa is small) ... 11 = lowest bandwidth (external filter capacitor required on md input to reduce excessive hf signal feedthrough) 00 0 erset[3] 0 = reduced e r setting (5 to 12) 1 = normal e r setting (10 to 24) 1 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 49 register summary (continued) addr r/w register name bit name function/description default state notes h0x0a rw txctrl5 7:5 erset[2:0] sets extinction ratio. if erset[3] = 1 (normal): 000 = 10 001 = 12 010 = 14 011 = 16 100 = 18 101 = 20 110 = 22 111 = 24 if erset[3] = 0 (reduced): 000 = 5 001 = 6 010 = 7 011 = 8 100 = 9 101 = 10 110 = 11 111 = 12 000 4:0 cprg[4:0] programs the internal md current refer - ence filter 00000 h0x0b rw ibiasmax 7:0 ibiasmax [7:0] max bias dac setting allowed 0001 0010 18d h0x0c rw imodmax 7:0 imodmax [7:0] max mod dac setting allowed 0011 0000 48d h0x0d rw set_ibias 7:0 set_ibias [7:0] open-loop or initial value setting 0000 0100 4d h0x0e rw set_imod 7:0 set_imod [7:0] open-loop or initial value setting 0001 0100 20d h0x0f rw biasinc 4:0 biasinc [4:0] apc enabled: max bias step (coarse acquisition max step = 2 x biasinc[3:0]) apc disabled: laser bias current set - point inc/dec step size upon write 00000 h0x10 rw modinc 4:0 modinc [4:0] erc enabled: max mod step (coarse acquisition max step = 2 x modinc[3:0]) erc disabled: laser mod current setpoint inc/dec step size upon write 00000 h0x11 rw set_2xapc 7:0 set_2xapc [7:0] average laser power setting x 2 0010 0000 32d h0x12 rw apcinc 3:0 apcinc [3:0] updates set_2xapc[7:0] with twos complement apcinc[3:0] 0000 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 50 register summary (continued) addr r/w register name bit name function/description default state notes h0x13 rw txctrl6 7 thrshld sets threshold for updating biasreg[9:0] in apc mode and biasreg[9:0] and modreg[8:0] in dpc mode 0 = 0.125 lsb 1 = 0.75 lsb 0 6 dpc_run controls the apc and erc loops 0 = no action 1 = apc and erc loops restart from last saved prefreeze conditions (subject to ibupt_en and imupdt_en) and dpc_ stop bit is reset 1 5 restart forces loop out of steady-state mode and enables the startup state machine 0 = disabled 1 = enabled 0 4:3 soft_ rstr[1:0] 00 = fastest dpc acquisition . . . 11 = slowest (least disruptive) dpc acquisition 00 2 bias_en 0 = bias dac disabled 1 = bias dac enabled 1 1 mod_en 0 = mod dac disabled 1 = mod dac enabled 1 0 tx_en 0 = tx path and laser control loops dis - abled 1 = tx path and laser control loops enabled 0 h0x16 r biasreg 7:0 biasreg [9:2] bias current dac input readback 0000 0000 h0x17 r modreg 7:0 modreg [8:1] mod current dac input readback 0000 0000 h0x18 r md1regh 7:0 md1regh [7:0] (averaged) md current top peak digi - tized data 0000 0000 h0x19 r md1regl 7:0 md1regl [7:0] (averaged) md current top peak digi - tized data 0000 0000 h0x1a r md0regh 7:0 md0regh [7:0] (averaged) md current bottom peak digi - tized data 0000 0000 h0x1b r md0regl 7:0 md0regl [7:0] (averaged) md current bottom peak digi - tized data 0000 0000 h0x1c r rxstat 0 los_stat copy of the los status sticky 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 51 register summary (continued) note: sticky bits remain flagged even if the cause of the flag is removed. reading the bit resets it if the source of the flag has been removed. addr r/w register name bit name function/description default state notes h0x1d r dpcstat 6 ssmode dpc in steady state not sticky 5 ibiasovfl biasreg[9:2] input over max warning sticky 4 ibiasudfl biasreg[9:0] input underflow sticky 3 imodovfl modreg[8:1] input over max warning sticky 2 imodudfl modreg[8:0] input underflow sticky 1 2xapc_ovf set_2xapc[7:0] wraparound high sticky 0 2xapc_udf set_2xapc[7:0] wraparound low sticky h0x1e r txstat1 7 lvflag v ccto undervoltage detection fault, sticky, maskable 6:5 res reserved 4 txinlos indicates txin ac-signal too low fault, sticky, maskable 3 fmd mdin shorted to gnd. fault is reported and fault output is set high. fault, sticky, maskable; stops dpc regardless of mask 2 fiout iout open or shorted to gnd. fault is reported and fault output is set high. fault, sticky, maskable 1 ftout tout open or shorted to gnd. fault is reported and fault output is set high. fault, sticky, maskable 0 tx_fault a copy of fault fault, sticky h0x1f r txstat2 2:1 biasreg[1:0] lsbs of biasreg[9:0] 0 modreg[0] lsb of modreg[8:0] 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 52 layout considerations the high-speed data inputs and outputs are the most critical paths for the device, and great care should be taken to minimize discontinuities on these transmission lines between the connector and the ic. the following are some suggestions for maximizing the devices per - formance: ? the data inputs should be wired directly between the connector and ic without stubs. ? the data transmission lines to the laser should be kept as short as possible, and the impedance of the trans - mission lines must be considered part of the laser matching network. ? minimize capacitance on the mdin connection. ? an uninterrupted ground plane should be positioned beneath the high-speed i/os. ? ground path vias should be placed close to the ic and the input/output interfaces to allow a return cur - rent path to the ic and the laser. ? maintain 100 i differential transmission line imped - ance for the rin, rout, and tin i/os. ? use good high-frequency layout techniques and mul - tilayer boards with an uninterrupted ground plane to minimize emi and crosstalk. refer to the schematic and board layers of the MAX3711 evaluation kit data sheet for more information. exposed-pad package and thermal considerations the exposed pad on the MAX3711 is the only electrical connection to ground and provides a very low-thermal resistance path for heat removal from the ic. the pad is also electrical ground on the device and must be sol - dered to the circuit board ground for proper thermal and electrical performance. refer to application note 862: hfan-08.1: thermal considerations for qfn and other exposed-paddle packages for additional information. chip information process: sige bipolar ordering information package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. note: parts are guaranteed by design and characterization to operate over the -40c to +95c ambient temperature range (t a ) and are tested up to +85c. + denotes a lead(pb)-free/rohs-compliant package. * exposed pad. part temp range pin-package MAX3711etg+ -40c to +85c 24 tqfn-ep* package type package code outline no. land pattern no. 24 tqfn-ep t2444+3 21-0139 90-0021 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 53 typical application circuitoc-48 sfp module oc-48 sfp module v ccd rin+ los rout+ rout- tin+ tin- fault disable r mon2 r mon1 27 100 4.7k to 10k 80 39 10 8pf 22pf *ferrite bead: murata bml15hg102 **c mdin typically 10pf ***c mdref typically 100pf 1f 1f 4700pf 1f 1f rin- mdref v ccto iout tout mdin bmon 3-wire interface csel scl sda software 3-wire interface adc controller i 2 c v ccx 20-pin connector filter filter r fault 4.7k to 10k MAX3711 3.125gbps lam/ld max15059 v cc 0.1f 0.1f fr4 microstrip vcc_host z diff = 100 fr4 microstrip z diff = 100 host board serdes los mod-def1 (scl) mod-def2 (sda) 100pf tx_fault tx_disable c mdref *** c mdin ** ferrite bead* 20 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, inc. 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 54 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/11 initial release 125mbps to 3.125gbps integrated limiting amplifier/ laser driver with dual-loop power control MAX3711 |
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