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general description the MAX1302 multirange, low-power, 16-bit, succes- sive-approximation, analog-to-digital converter (adc) operates from a single +5v supply and achieves throughput rates up to 115ksps. a separate digital sup- ply allows digital interfacing with a 2.7v to 5.25v system using the spi-/qspi?-/microwire ? -compatible serial interface. partial power-down mode reduces the supply current to 1.3ma (typ). full power-down mode reduces the power-supply current to 1a (typ). the MAX1302 provides eight (single-ended) or four (true differential) analog input channels. each analog input channel is independently software programmable for seven single-ended input ranges (0v to +v ref /2, -v ref /2 to 0v, 0v to +v ref , -v ref to 0v, v ref /4, v ref /2, and v ref ), and three differential input ranges (v ref /2, v ref , 2 x v ref ). an on-chip +4.096v reference offers a small convenient adc solution. the MAX1302 also accepts an external reference voltage between 3.800v and 4.136v. the MAX1302 is available in a 24-pin tssop package and is specified for operation from -40c to +85c. applications industrial control systems data-acquisition systems avionics robotics features software-programmable input range for each channel single-ended input ranges 0v to +v ref /2, -v ref /2 to 0v, 0v to +v ref , -v ref to 0v, v ref /4, v ref /2, and v ref differential input ranges v ref /2, v ref , and 2 x v ref eight single-ended or four differential analog inputs (MAX1302) 6v overvoltage tolerant inputs internal or external reference 115ksps maximum sample rate single +5v power supply 24-pin tssop package MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ________________________________________________________________ maxim integrated products 1 pin configuration ordering information 24 23 22 21 20 19 18 17 1 2 + 3 4 5 6 7 8 agnd1 agnd2 avdd2 agnd3 ch2 ch1 ch0 avdd1 top view ref refcap dvdd dvddo ch6 ch5 ch4 ch3 16 15 14 13 9 10 11 12 dgnd dgndo dout sclk sstrb din cs ch7 tssop MAX1302 19-6249; rev 0; 3/12 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part pin-package c h a n n el s MAX1302aeug+ 24 tssop 8 MAX1302beug+ 24 tssop 8 qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corp. note: all devices are specified over the -40c to +85c oper- ating temperature range. + denotes a lead(pb)-free/rohs-compliant package.
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd1 to agnd1 ....................................................-0.3v to +6v avdd2 to agnd2 ....................................................-0.3v to +6v dvdd to dgnd ........................................................-0.3v to +6v dvddo to dgndo ..................................................-0.3v to +6v dvdd to dvddo......................................................-0.3v to +6v dvdd, dvddo to avdd1 ........................................-0.3v to +6v avdd1, dvdd, dvddo to avdd2 ..........................-0.3v to +6v dgnd, dgndo, agnd3, agnd2 to agnd1 ......-0.3v to +0.3v cs , sclk, din, dout, sstrb to dgndo............................................-0.3v to (v dvddo + 0.3v) ch0Cch7 to agnd1 ...................................................-6v to +6v ref, refcap to agnd1 ......................-0.3v to (v avdd1 + 0.3v) continuous current (any pin) ...........................................50ma continuous power dissipation (multilayer board, t a = +70c) 24-pin tssop (derate 13.9mw/c above +70c).....1111.1mw operating temperature range ...........................-40c to +85c junction temperature .....................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units dc accuracy (notes 1, 2) resolution 16 bits MAX1302a 1.0 2 integral nonlinearity inl MAX1302b 1.0 4 lsb differential nonlinearity dnl no missing codes -1 +2 lsb transition noise external or internal reference 1 lsb rms unipolar 0 7.5 single-ended inputs bipolar -1.0 7.5 offset error differential inputs (note 3) bipolar -2.0 10 mv channel-to-channel gain matching unipolar or bipolar 0.025 %fsr channel-to-channel offset error matching unipolar or bipolar 1.0 mv unipolar 3 bipolar 1 offset temperature coefficient fully differential 2 v/c unipolar 0.5 bipolar 0.8 gain error fully differential 1 %fsr unipolar 1.5 gain temperature coefficient bipolar 1.0 ppm/c dynamic specifications f in(sine-wave) = 5khz, v in = fsr - 0.05db, f sample = 130ksps (notes 1, 2) differential inputs, fsr = 2 x v ref 90 single-ended inputs, fsr = v ref 88 single-ended inputs, fsr = v ref /2 85 signal-to-noise plus distortion sinad single-ended inputs, fsr = v ref /4 80 82 db
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc _______________________________________________________________________________________ 3 electrical characteristics (continued) (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units differential inputs, fsr = 2 x v ref 90 single-ended inputs, fsr = v ref 88 single-ended inputs, fsr = v ref /2 85 signal-to-noise ratio snr single-ended inputs, fsr = v ref /4 82 db total harmonic distortion (up to the 5th harmonic) thd -98 db spurious-free dynamic range sfdr 90 99 db aperture delay t ad figure 21 15 ns aperture jitter t aj figure 21 100 ps channel-to-channel isolation 105 db conversion rate external clock mode, figure 2 114 external acquisition mode, figure 3 84 byte-wide throughput rate f sample internal clock mode, figure 4 106 ksps analog inputs (ch0?h7 MAX1302, agnd1) small-signal bandwidth all input ranges, v in = 100mv p-p (note 2) 1.5 mhz full-power bandwidth all input ranges, v in = 4v p-p (note 2) 700 khz r[2:1] = 001 -v ref /4 +v ref /4 r[2:1] = 010 -v ref /2 0 r[2:1] = 011 0 +v ref /2 r[2:1] = 100 -v ref /2 +v ref /2 r[2:1] = 101 -v ref 0 r[2:1] = 110 0 +v ref input voltage range (table 6) v ch_ r[2:1] = 111 -v ref +v ref v tr ue- d i ffer enti al anal og c om m on- m od e v ol tag e rang e v cmdr dif/ sgl = 1 (note 4) -4.75 +5.50 v common-mode rejection ratio cmrr d if/ s g l = 1, i np ut vol tag e r ang e = v r e f /4 75 db input current i ch_ -v ref < v ch_ < +v ref -1500 +650 a input capacitance c ch_ 5pf input resistance r ch_ 6k ?
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units internal reference (bypass refcap with 0.1? to agnd1 and ref with 1.0? to agnd1) reference output voltage v ref 4.056 4.096 4.136 v reference temperature coefficient tc ref 30 ppm/c ref shorted to agnd1 10 reference short-circuit current i refsc ref shorted to avdd -1 ma reference load regulation i ref = 0 to 0.5ma 0.1 10 mv external reference (refcap = avdd) reference input voltage range v ref 3.800 4.136 v refcap buffer disable threshold v rcth (note 5) v avdd1 - 0.4 v av d d 1 - 0.1 v v ref = +4.096v, external clock mode, external acquisition mode, internal clock mode, or partial power-down mode 90 200 reference input current i ref v ref = +4.096v, full power-down mode 0.1 10 a external clock mode, external acquisition mode, internal clock mode, or partial power-down mode 20 45 k ? reference input resistance r ref full power-down mode 40 m ? digital inputs (din, sclk, cs ) input high voltage v ih 0.7 x v dvddo v input low voltage v il 0.3 x v dvddo v input hysteresis v hyst 0.2 v input leakage current i in v in = 0v to v dvddo -10 +10 a input capacitance c in 10 pf digital outputs (dout, sstrb) v dvddo = 4.75v, i sink = 10ma 0.4 output low voltage v ol v dvddo = 2.7v, i sink = 5ma 0.4 v output high voltage v oh i source = 0.5ma v d v dd o - 0.4 v dout three-state leakage i ddo cs = dvddo -10 +10 a power requirements (avdd1 and agnd1, avdd2 and agnd2, dvdd and dgnd, dvddo and dgndo) analog supply voltage v avdd1 4.75 5.25 v digital supply voltage v dvdd 4.75 5.25 v
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc _______________________________________________________________________________________ 5 electrical characteristics (continued) (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units preamplifier supply voltage v avdd2 4.75 5.25 v digital i/o supply voltage v dvddo 2.70 5.25 v internal reference 3 3.5 avdd1 supply current i avdd1 external clock mode, external acquisition mode, or internal clock mode external reference 2.5 3 ma dvdd supply current i dvdd external clock mode, external acquisition mode, or internal clock mode 0.9 2 ma avdd2 supply current i avdd2 external clock mode, external acquisition mode, or internal clock mode 12 20 ma dvddo supply current i dvddo external clock mode, external acquisition mode, or internal clock mode 0.2 1 ma partial power-down mode 1.3 ma total supply current full power-down mode 2 a power-supply rejection ratio psrr all analog input ranges 0.5 lsb timing characteristics (figures 15 and 16) external clock mode 0.272 62 external acquisition mode 0.228 62 sclk period t cp internal clock mode 0.1 s external clock mode 109 external acquisition mode 92 sclk high pulse width (note 6) t ch internal clock mode 40 ns external clock mode 109 external acquisition mode 92 sclk low pulse width (note 6) t cl internal clock mode 40 ns din to sclk setup t ds 40 ns din to sclk hold t dh 0ns sclk fall to dout valid t do 40 ns cs fall to dout enable t dv 40 ns
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc 6 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units cs rise to dout disable t tr 40 ns cs fall to sclk rise setup t css 40 ns cs high minimum pulse width t cspw 40 ns sclk fall to cs rise hold t csh 0ns sstrb rise to cs fall setup (note 4) 40 ns dout rise/fall time c l = 50pf 10 ns sstrb rise/fall time c l = 50pf 10 ns note 1: parameter tested at v avdd1 = v avdd2 = v dvdd = v dvddo = 5v. note 2: see definitions in the parameter definitions section at the end of the data sheet. note 3: guaranteed by correlation with single-ended measurements. note 4: not production tested. guaranteed by design. note 5: to ensure external reference operation, v refcap must exceed (v avdd1 - 0.1v). to ensure internal reference operation, v refcap must be below (v avdd1 - 0.4v). bypassing refcap with a 0.1f or larger capacitor to agnd1 sets v refcap 4.096v. the tran- sition point between internal reference mode and external reference mode lies between the refcap buffer disable threshold minimum and maximum values (figures 17 and 18). note 6: the sclk duty cycle can vary between 40% and 60%, as long as the t cl and t ch timing requirements are met. analog supply current vs. analog supply voltage MAX1302 toc01 v avdd1 (v) i avdd1 (ma) 5.15 5.05 4.95 4.85 2.35 2.40 2.45 2.50 2.55 2.60 2.30 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c external clock mode preamplifier supply current vs. preamplifier supply voltage MAX1302 toc02 v avdd2 (v) i avdd2 (ma) 5.15 5.05 4.85 4.95 16 17 18 19 20 21 22 23 24 15 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c external clock mode digital supply current vs. digital supply voltage MAX1302 toc03 v dvdd (v) i dvdd (ma) 5.15 5.05 4.95 4.85 0.70 0.75 0.80 0.85 0.90 0.65 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c external clock mode typical operating characteristics (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.)
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc _______________________________________________________________________________________ 7 digital i/o supply current vs. digital i/o supply voltage MAX1302 toc04 v dvddo (v) i dvddo (ma) 5.15 5.05 4.85 4.95 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.10 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c external clock mode analog supply current vs. analog supply voltage MAX1302 toc05 v avdd1 (v) i avdd1 (ma) 5.15 5.05 4.95 4.85 0.47 0.49 0.51 0.53 0.55 0.45 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c partial power-down mode typical operating characteristics (continued) (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.) preamplifier supply current vs. preamplifier supply voltage MAX1302 toc06 v avdd2 (v) i avdd2 (ma) 5.15 5.05 4.95 4.85 0.12 0.14 0.16 0.18 0.20 0.10 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c partial power-down mode digital supply current vs. digital supply voltage MAX1302 toc07 v dvdd (v) i dvdd (ma) 5.15 4.85 5.05 4.95 0.122 0.124 0.126 0.128 0.130 0.132 0.134 0.136 0.120 4.75 5.25 partial power-down mode t a = +85 c t a = +25 c t a = -40 c
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc 8 _______________________________________________________________________________________ analog supply current vs. conversion rate MAX1302 toc08 conversion rate (ksps) i avdd1 (ma) 200 150 100 50 0.5 1.0 1.5 2.0 2.5 3.0 0 0 external clock mode partial power-down mode full power-down mode preamplifier supply current vs. conversion rate MAX1302 toc09 i avdd2 (ma) 5 10 15 20 25 0 conversion rate (ksps) 200 150 100 50 0 f clk = 7.5mhz (note 6) external clock mode full power-down mode, partial power-down mode typical operating characteristics (continued) (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.) digital supply current vs. conversion rate MAX1302 toc10 i dvdd (ma) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 0 conversion rate (ksps) 200 150 100 50 f clk = 7.5mhz (note 6) full power-down mode external clock mode, partial power-down mode digital i/o supply current vs. conversion rate MAX1302 toc11 conversion rate (ksps) i dvddo (ma) 200 150 100 50 0.1 0.2 0.3 0.4 0.5 0.6 0 0 f clk = 7.5mhz (note 6) external clock mode full power-down mode, partial power-down mode note 6: for partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples. partial power-down or full power-down modes were entered thereafter. by using this method, the conversion rate was found by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down or full power-down modes.
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc _______________________________________________________________________________________ 9 external reference input current vs. external reference input voltage MAX1302 toc12 external reference voltage (v) external reference current (ma) 4.10 4.05 4.00 3.95 3.90 3.85 0.13 0.14 0.15 0.16 0.12 3.80 4.15 all modes -0.10 -0.04 -0.06 -0.08 -0.02 0 0.02 0.04 0.06 0.08 0.10 -40 10 -15 35 60 85 gain drift vs. temperature MAX1302 toc13 temperature ( c) gain drift (%) +v ref /2 bipolar v ref bipolar range v ref /4 bipolar -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 -40 10 -15 356085 offset drift vs. temperature MAX1302 toc14 temperature ( c) offset error (mv) +v ref /4 bipolar range v ref bipolar channel-to-channel isolation vs. input frequency MAX1302 toc15 frequency (khz) isolation (db) 1000 100 10 -100 -80 -60 -40 -20 0 -120 1 10,000 f sample = 115ksps v ref bipolar range ch0 to ch2 common-mode rejection ratio vs. frequency MAX1302 toc16 frequency (khz) cmrr (db) 1000 100 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 1 10,000 f sample = 115ksps v ref bipolar range -2.0 -1.0 -1.5 0 -0.5 0.5 1.0 1.5 2.0 0 16,384 32,768 49,152 65,535 integral nonlinearity vs. digital output code MAX1302 toc17 digital output code inl (lsb) f sample = 115ksps v ref bipolar range -2.0 -1.0 -1.5 0 -0.5 0.5 1.0 1.5 2.0 0 16,384 32,768 49,152 65,535 differential nonlinearity vs. digital output code MAX1302 toc18 digital output code dnl (lsb) f sample = 115ksps v ref bipolar range -140 -60 -100 -120 -40 -80 -20 0 020 10 30 40 50 fft at 5khz MAX1302 toc19 temperature ( c) magnitude (db) f sample = 115ksps f in(sine wave) = 5khz v ref bipolar range 100 0 1 100 1000 snr, sinad, enob vs. analog input frequency 30 70 40 80 50 90 20 10 60 MAX1302 toc20 frequency (khz) snr, sinad (db) 10 f sample = 115ksps v ref bipolar range enob snr sinad typical operating characteristics (continued) (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.)
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc 10 ______________________________________________________________________________________ snr, sinad, enob vs . sample rate m ax1302 toc21 sa m ple rate (ksps) snr, sinad (db) enob (b i ts) 100 16 14 12 10 8 6 10 1 20 40 60 80 100 0 0 . 1 1000 snr, sinad q v ref bipolar range input frequency = 5khz enob -sfdr, thd vs. sample rate MAX1302 toc22 sample rate (ksps) -sfdr, thd (db) 100 10 1 -100 -80 -60 -40 -20 0 -120 0.1 1000 thd -sfdr -sfdr, thd vs . analog input frequency m ax1302 toc23 frequency (khz) -sfdr, thd (db) 100 10 -100 -80 -60 -40 -20 0 -120 1 1000 thd sfdr q v ref bipolar range sample rate = 115ksps -1.5 -0.5 -1.0 0.5 0 1.0 1.5 analog input current vs. analog input voltage MAX1302 toc24 analog input voltage (v) analog input current (ma) -6 -2 0 -4 2 4 6 small-signal bandwidth MAX1302 toc25 frequency (khz) attenuation (db) 1000 100 10 -25 -20 -15 -10 -5 0 -30 1 10,000 typical operating characteristics (continued) (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.)
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ______________________________________________________________________________________ 11 noise histogram (code edge) MAX1302 toc27 code number of hits 32,771 5000 10,000 15,000 20,000 25,000 30,000 35,000 0 32,769 32,772 32,774 32,770 32,773 65,534 samples noise histogram (code center) max11302 toc28 code number of hits 32,769 5000 10,000 15,000 20,000 25,000 30,000 35,000 40,000 0 32,770 32,768 32,772 32,771 32,773 32,767 65,534 samples reference voltage vs. time MAX1302 toc29 1v/div 0v 4ms/div full-power bandwidth MAX1302 toc26 frequency (khz) attenuation (db) 1000 100 10 -50 -40 -30 -20 -10 0 -60 1 10,000 typical operating characteristics (continued) (v avdd1 = v avdd2 = v dvdd = v dvddo = 5v, v agnd1 = v dgnd = v dgndo = v agnd2 = v agnd3 = 0v, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = avdd1, maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.)
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc 12 ______________________________________________________________________________________ pin description pin name function 1 avdd1 analog supply voltage 1. connect avdd1 to a +4.75v to +5.25v power-supply voltage. bypass avdd1 to agnd1 with a 0.1f capacitor. 2 ch0 analog input channel 0 3 ch1 analog input channel 1 4 ch2 analog input channel 2 5 ch3 analog input channel 3 6 ch4 analog input channel 4 7 ch5 analog input channel 5 8 ch6 analog input channel 6 9 ch7 analog input channel 7 10 cs active-low chip-select input. when cs is low, data is clocked into the device from din on the rising edge of sclk. with cs low, data is clocked out of dout on the falling edge of sclk. when cs is high, activity on sclk and din is ignored and dout is high impedance. 11 din serial data input. when cs is low, data is clocked in on the rising edge of sclk. when cs is high, transitions on din are ignored. 12 sstrb serial-strobe output. when using the internal clock, sstrb rising edge transitions indicate that data is ready to be read from the device. when operating in external clock mode, sstrb is always low. sstrb does not tri-state, regardless of the state of cs , and therefore requires a dedicated i/o line. 13 sclk serial clock input. when cs is low, transitions on sclk clock data into din and out of dout. when cs is high, transitions on sclk are ignored. 14 dout serial data output. when cs is low, data is clocked out of dout with each falling sclk transition. when cs is high, dout is high impedance. 15 dgndo digital i/o ground. dgnd, dgndo, agnd3, agnd2, and agnd1 must be connected together. 16 dgnd digital ground. dgnd, dgndo, agnd3, agnd2, and agnd1 must be connected together. 17 dvddo digital i/o supply voltage input. connect dvddo to a +2.7v to +5.25v power-supply voltage. bypass dvddo to dgndo with a 0.1f capacitor. 18 dvdd digital-supply voltage input. connect dvdd to a +4.75v to +5.25v power-supply voltage. bypass dvdd to dgnd with a 0.1f capacitor. 19 refcap bandgap-voltage bypass node. for external reference operation, connect refcap to avdd. for internal reference operation, bypass refcap with a 0.01f capacitor to agnd1 (v refcap 4.096v). 20 ref reference-buffer output/adc reference input. for external reference operation, apply an external reference voltage from 3.800v to 4.136v to ref. for internal reference operation, bypassing ref with a 1f capacitor to agnd1 sets v ref = 4.096v 1%.
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ______________________________________________________________________________________ 13 detailed description the MAX1302 multirange, low-power, 16-bit successive- approximation adc operates from a single +5v supply and has a separate digital supply allowing digital inter- face with 2.7v to 5.25v systems. this 16-bit adc has internal track-and-hold (t/h) circuitry that supports single- ended and fully differential inputs. for single-ended con- versions, the valid analog input voltage range spans from -v ref below ground to +v ref above ground. the maxi- mum allowable differential input voltage spans from -2 x v ref to +2 x v ref . data can be converted in a variety of software-programmable channel and data-acquisition configurations. microprocessor (p) control is made easy through an spi-/qspi-/microwire-compatible serial interface. the MAX1302 has eight single-ended analog input channels or four differential channels (see the block diagram ). each analog input channel is independently software programmable for seven single-ended input ranges (0v to +v ref /2, -v ref /2 to 0v, 0v to +v ref , -v ref to 0v, v ref /4, v ref /2, and v ref ) and three differential input ranges (v ref /2, v ref , and 2 x v ref ). additionally, all analog input channels are fault tolerant to 6v. a fault condition on an idle channel does not affect the conversion result of other channels. pin description (continued) pin name function 21 agnd3 analog signal ground 3. agnd3 is the adc negative reference potential. connect agnd3 to agnd1. dgnd, dgndo, agnd3, agnd2, and agnd1 must be connected together. 22 avdd2 analog supply voltage 2. connect avdd2 to a +4.75v to +5.25v power-supply voltage. bypass avdd2 to agnd2 with a 0.1f capacitor. 23 agnd2 analog ground 2. this ground carries approximately five times more current than agnd1. dgnd, dgndo, agnd3, agnd2, and agnd1 must be connected together. 24 agnd1 analog ground 1. dgnd, dgndo, agnd3, agnd2, and agnd1 must be connected together. 4?20ma plc acceleration pressure temperature wheatestone wheatestone 1 f 0.1 f agnd2 dgndo agnd3 dgnd avdd2 dvdd avdd1 0.1 f 0.1 f 0.1 f 5.0v 5.0v 5.0v MAX1302 cho ch1 ch2 ch3 ch4 ch5 ch6 ch7 ref agnd1 refcap 0.1 f 3.3v mc68hcxx c dvdd0 sclk cs din sstrb dout v dd sck i/o mosi i/o miso v ss figure 1. typical application circuit
MAX1302 power supplies to maintain a low-noise environment, the MAX1302 provides separate power supplies for each section of circuitry. table 1 shows the four separate power sup- plies. achieve optimal performance using separate avdd1, avdd2, dvdd, and dvddo supplies. alternatively, connect avdd1, avdd2, and dvdd together as close to the device as possible for a conve- nient power connection. connect agnd1, agnd2, agnd3, dgnd, and dgndo together as close as pos- sible to the device. bypass each supply to the corre- sponding ground using a 0.1f capacitor (table 1). if significant low-frequency noise is present, add a 10f capacitor in parallel with the 0.1f bypass capacitor. converter operation the MAX1302 adc features a fully differential, succes- sive-approximation register (sar) conversion tech- nique and an on-chip t/h block to convert voltage signals into a 16-bit digital result. both single-ended and differential configurations are supported with pro- grammable unipolar and bipolar signal ranges. track-and-hold circuitry the MAX1302 features a switched-capacitor t/h archi- tecture that allows the analog input signal to be stored as charge on sampling capacitors. see figures 2, 3, and 4 for t/h timing and the sampling instants for each operat- ing mode. the MAX1302 analog input circuitry buffers the input signal from the sampling capacitors, resulting in a constant analog input impedance with varying input voltage (figure 5). analog input circuitry select differential or single-ended conversions using the associated analog input configuration byte (table 2). the analog input signal source must be capable of dri- ving the adcs 6k ? input resistance (figure 6). figure 6 shows the simplified analog input circuit. the analog inputs are 6v fault tolerant and are protected by back-to-back diodes. the summing junction voltage, v sj , is a function of the channels input common-mode voltage: v r rr v r rr v sj cm . = + ? ? ? ? ? ? ++ + ? ? ? ? ? ? ? ? ? ? ? ? 1 12 2 375 1 1 12 8-channel, ? ref multirange inputs, serial 16-bit adc 14 ______________________________________________________________________________________ table 1. MAX1302 power supplies and bypassing power supply/ground supply voltage range (v) typical supply current (ma) circuit section bypassing dvddo/dgndo 2.7 to 5.25 0.2 digital i/o 0.1f to dgndo avdd2/agnd2 4.75 to 5.25 17.5 analog circuitry 0.1f to agnd2 avdd1/agnd1 4.75 to 5.25 3.0 analog circuitry 0.1f to agnd1 dvdd/dgnd 4.75 to 5.25 0.9 digital control logic and memory 0.1f to dgnd table 2. analog input configuration byte bit number name description 7 start start bit. the first logic 1 after cs goes low defines the beginning of the analog input configuration byte. 6c2 5c1 4c0 channel-select bits. sel[2:0] select the analog input channel to be configured (tables 4 and 5). 3 dif/ sgl differential or single-ended configuration bit. dif/ sgl = 0 configures the selected analog input channel for single-ended operation. dif/ sgl = 1 configures the channel for differential operation. in single-ended mode, input voltages are measured between the selected input channel and agnd1, as shown in table 4. in differential mode, the input voltages are measured between two input channels, as shown in table 5. be aware that changing dif/ sgl adjusts the fsr, as shown in table 6. 2r2 1r1 0r0 input-range-select bits. r[2:0] select the input voltage range, as shown in table 6 and figure 7.
as a result, the analog input impedance is relatively constant over the input voltage as shown in figure 5. single-ended conversions are internally referenced to agnd1 (tables 3 and 4). in differential mode, in+ and in- are selected according to tables 3 and 5. when con- figuring differential channels, the differential pair follows the analog configuration byte for the positive channel. for example, to configure ch2 and ch3 for a v ref dif- ferential conversion, set the ch2 analog configuration byte for a differential conversion with the v ref range (1010 1100). to initiate a conversion for the ch2 and ch3 differential pair, issue the command 1010 0000. analog input bandwidth the MAX1302 input-tracking circuitry has a 1.5mhz small-signal bandwidth. the 1.5mhz input bandwidth makes it possible to digitize high-speed transient events. harmonic distortion increases when digitizing signal fre- quencies above 15khz as shown in the -sfdr, thd vs. analog input frequency plot in the typical operating characteristics . analog input range and fault tolerance figure 7 illustrates the software-selectable single- ended analog input voltage range that produces a valid digital output. each analog input channel can be inde- pendently programmed to one of seven single-ended input ranges by setting the r[2:0] control bits with dif/ sgl = 0. MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ______________________________________________________________________________________ 15 cs sclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 din s c2 c1 c0 0 0 0 0 analog input track and hold* dout b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 byte 1 byte 2 byte 3 byte 4 sstrb hold track hold high impedance t acq high impedance *track and hold timing is controlled by sclk. f sample f sclk / 32 sampling instant figure 2. external clock-mode conversion (mode 0)
MAX1302 figure 8 illustrates the software-selectable differential analog input voltage range that produces a valid digital output. each analog input differential pair can be inde- pendently programmed to one of three differential input ranges by setting the r[2:0] control bits with dif/ sgl = 1. regardless of the specified input voltage range and whether the channel is selected, each analog input is 6v fault tolerant. the analog input fault protection is active whether the device is unpowered or powered. any voltage beyond fsr, but within the 6v fault-toler- ant range, applied to an analog input results in a full- scale output voltage for that channel. clamping diodes with breakdown thresholds in excess of 6v protect the MAX1302 analog inputs during esd and other transient events (figure 6). the clamping diodes do not conduct during normal device operation, nor do they limit the current during such transients. when operating in an environment with the potential for high-energy voltage and/or current transients, protect the MAX1302 externally. 8-channel, ? ref multirange inputs, serial 16-bit adc 16 ______________________________________________________________________________________ cs sclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 din sc2c1c00000 analog input track and hold* hold dout b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 byte 1 byte 2 byte 3 byte 4 sstrb intclk** 1 2 3 14 15 16 17 track hold high impedance t acq 100ns to 400ns f intclk 4.5mhz f sample f sclk / 32 + f intclk / 17 *track and hold timing is controlled by sclk. **intclk is an internal signal and is not accessible to the user. sampling instant figure 3. external acquisition-mode conversion (mode 1)
figure 6. simplified analog input circuit MAX1302 r2 r1 v sj *r source analog signal source r2 r1 v sj *r source analog signal source in_+ in_+ *minimize r source to avoid gain error and distortion. MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ______________________________________________________________________________________ 17 cs sclk 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 din s c2 c1 c0 0 0 0 0 analog input track and hold track dout b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 byte 1 byte 2 byte 3 sstrb intclk 1 2 3 25 26 27 28 9 10 11 12 13 14 15 16 10 11 12 13 14 hold hold high impedance t ac 100ns to 400ns f intclk 4.5mhz f sample f sclk / 24 + f intclk / 28 *track and hold timing is controlled by intclk, and is not accessible to the user. **intclk is an internal signal and is not accessible to the user. sampling instant figure 4. internal clock-mode conversion (mode 2) -1.5 -0.5 -1.0 0.5 0 1.0 1.5 analog input voltage (v) analog input current (ma) -6 -2 0 -4 2 4 6 figure 5. analog input current vs. input voltage
MAX1302 differential common-mode range the MAX1302 differential common-mode range (v cmdr ) must remain within -4.75v to +5.5v to obtain valid conversion results. the differential common-mode range is defined as: in addition to the common-mode input voltage limita- tions, each individual analog input must be limited to 6v with respect to agnd1. the range-select bits r[2:0] in the analog input config- uration bytes determine the full-scale range for the cor- responding channel (tables 2 and 6). figures 9, 10, and 11 show the valid analog input voltage ranges for the MAX1302 when operating with fsr = v ref /2, fsr = v ref , and fsr = 2 x v ref , respectively. the shaded area contains the valid common-mode voltage ranges that support the entire fsr. v ch ch cmdr _ _ = + () + () ? 2 8-channel, ? ref multirange inputs, serial 16-bit adc 18 ______________________________________________________________________________________ table 3. input data word formats data bit operation d7 (start) d6 d5 d4 d3 d2 d1 d0 conversion-start byte (tables 4 and 5) 1c2c1c00 0 0 0 analog-input configuration byte (table 2) 1 c2 c1 c0 dif/ sgl r2 r1 r0 mode-control byte (table 7) 1m2m1m01 0 0 0 table 4. channel selection in single-ended mode (dif/ sgl = 0) channel-select bit channel c2 c1 c0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd1 000+ - 001 + - 010 + - 011 + - 100 + - 101 + - 110 +- 111 +- table 5. channel selection in true-differential mode (dif/ sgl = 1) channel-select bit channel c2 c1 c0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd1 000+- 0 0 1 reserved 010 +- 0 1 1 reserved 100 +- 1 0 1 reserved 110 +- 1 1 1 reserved
digital interface the MAX1302 features a serial interface that is compat- ible with spi/qspi and microwire devices. din, dout, sclk, cs , and sstrb facilitate bidirectional communication between the MAX1302 and the master at sclk rates up to 10mhz (internal clock mode, mode 2), 3.67mhz (external clock mode, mode 0), or 4.39mhz (external acquisition mode, mode 1). the master, typically a microcontroller, should use the cpol = 0, cpha = 0, spi transfer format, as shown in the timing diagrams of figures 2, 3, and 4. the digital interface is used to: ? select single-ended or true-differential input channel configurations ? select the unipolar or bipolar input range ? select the mode of operation: external clock (mode 0) external acquisition (mode 1) internal clock (mode 2) reset (mode 4) partial power-down (mode 6) full power-down (mode 7) ? initiate conversions and read results chip select ( cs ) cs enables communication with the MAX1302. when cs is low, data is clocked into the device from din on the ris- ing edge of sclk and data is clocked out of dout on the falling edge of sclk. when cs is high, activity on sclk and din is ignored and dout is high impedance allowing dout to be shared with other peripherals. sstrb is never high impedance and therefore cannot be shared with other peripherals. serial strobe output (sstrb) as shown in figures 3 and 4, the sstrb transitions high to indicate that the adc has completed a conversion and results are ready to be read by the master. sstrb remains low in the external clock mode (figure 2) and consequently may be left unconnected. sstrb is dri- ven high or low regardless of the state of cs , therefore sstrb cannot be shared with other peripherals. MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ______________________________________________________________________________________ 19 001 010 011 100 101 110 111 0 -v ref /2 -v ref +v ref +v ref /2 +v ref /4 -v ref /4 each input is fault tolerant to 6v. (ch_) - agnd1 (v) input range selection bits, r[2:0] fsr = v ref / 2 fsr = v ref / 2 fsr = v ref / 2 fsr = v ref fsr = v ref fsr = v ref fsr = 2 x v ref + 3 / 4 v ref - 3 / 4 v ref figure 7. single-ended input voltage ranges 001 010 011 100 101 110 111 -v ref -2 x v ref +2 x v ref +v ref +v ref /2 -v ref /2 each input is fault tolerant to 6v. (ch_+) - (ch_-) (v) input range selection bits, r[2:0] 0 fsr = v ref fsr = 2 x v ref fsr = 4 x v ref - 3 / 2 v ref + 3 / 2 v ref figure 8. differential input voltage ranges
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc 20 ______________________________________________________________________________________ table 6. range-select bits dif/ sgl r2 r1 r0 mode transfer function 0 0 0 0 no range change* 0001 single-ended bipolar -v ref /4 to +v ref /4 full-scale range (fsr) = v ref /2 figure 12 0010 single-ended unipolar -v ref /2 to 0v fsr = v ref /2 figure 13 0011 single-ended unipolar 0v to +v ref /2 fsr = v ref /2 figure 14 0100 single-ended bipolar -v ref /2 to +v ref /2 fsr = v ref figure 12 0101 single-ended unipolar -v ref to 0v fsr = v ref figure 13 0110 single-ended unipolar 0v to +v ref fsr = v ref figure 14 0111 default setting single-ended bipolar -v ref to +v ref fsr = 2 x v ref figure 12 1 0 0 0 no range change** 1001 differential bipolar -v ref /2 to +v ref /2 fsr = v ref figure 12 1 0 1 0 reserved 1 0 1 1 reserved 1100 differential bipolar -v ref to +v ref fsr = 2 x v ref figure 12 1 1 0 1 reserved 1 1 1 0 reserved 1111 differential bipolar -2 x v ref to +2 x v ref fsr = 4 x v ref figure 12 * conversion-start byte (see table 3). ** mode-control byte (see table 3).
start bit communication with the MAX1302 is accomplished using the three input data word formats shown in table 3. each input data word begins with a start bit. the start bit is defined as the first high bit clocked into din with cs low when any of the following are true: ? data conversion is not in process and all data from the previous conversion has clocked out of dout. ? the device is configured for operation in external clock mode (mode 0) and previous conversion-result bits b15Cb3 have clocked out of dout. ? the device is configured for operation in external acquisition mode (mode 1) and previous conversion- result bits b15Cb7 have clocked out of dout. ? the device is configured for operation in internal clock mode, (mode 2) and previous conversion- result bits b15Cb4 have clocked out of dout. output data format output data is clocked out of dout in offset binary for- mat on the falling edge of sclk, msb first (b15). for output binary codes, see the transfer function section and figures 12, 13, and 14. configuring analog inputs each analog input has two configurable parameters: ? single-ended or true-differential input ? input voltage range these parameters are configured using the analog input configuration byte as shown in table 2. each analog input has a dedicated register to store its input configura- tion information. the timing diagram of figure 15 shows how to write to the analog input configuration registers. figure 16 shows dout and sstrb timing. transfer function an adcs transfer function defines the relationship between the analog input voltage and the digital output code. figures 12, 13, and 14 show the MAX1302 transfer functions. the transfer function is determined by the fol- lowing characteristics: ? analog input voltage range ? single-ended or differential configuration ? reference voltage the axes of an adc transfer function are typically in least significant bits (lsbs). for the MAX1302, an lsb is calcu- lated using the following equation: where n is the number of bits (n = 16) and fsr is the full-scale range (see figures 7 and 8). 1 2 4 096 . lsb fsr v v ref n = MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ______________________________________________________________________________________ 21 input voltage (v) common-mode voltage (v) 6 4 2 0 -2 -4 -6 -4 -2 0 2 4 6 -6 -8 8 v ref = 4.096v figure 9. common-mode voltage vs. input voltage (fsr = v ref ) input voltage (v) common-mode voltage (v) 6 4 2 0 -2 -4 -6 -4 -2 0 2 4 6 -6 -8 8 v ref = 4.096v figure 10. common-mode voltage vs. input voltage (fsr = 2 x v ref ) input voltage (v) common-mode voltage (v) 6 4 2 0 -2 -4 -6 -4 -2 0 2 4 6 -6 -8 8 v ref = 4.096v figure 11. common-mode voltage vs. input voltage (fsr = 4 x v ref )
MAX1302 mode control the MAX1302 contains one byte-wide mode-control register. the timing diagram of figure 15 shows how to use the mode-control byte, and the mode-control byte format is shown in table 7. the mode-control byte is used to select the conversion method and to control the power modes of the MAX1302. selecting the conversion method the conversion method is selected using the mode-con- trol byte (see the mode control section), and the conver- sion is initiated using a conversion start command (table 3, and figures 2, 3, and 4). the MAX1302 converts ana- log signals to digital data using one of three methods: ? external clock mode, mode 0 (figure 2) ? highest maximum throughput (see the electrical characteristics table) ? user controls the sample instant ? cs remains low during the conversion ? user supplies sclk throughout the adc con- version and reads data at dout ? external acquisition mode, mode 1 (figure 3) ? lowest maximum throughput (see the electrical characteristics table) ? user controls the sample instant ? user supplies two bytes of sclk, then drives cs high to relieve processor load while the adc converts ? after sstrb transitions high, the user supplies two bytes of sclk and reads data at dout ? internal clock mode, mode 2 (figure 4) ? high maximum throughput (see the electrical characteristics table) ? the internal clock controls the sampling instant 8-channel, ? ref multirange inputs, serial 16-bit adc 22 ______________________________________________________________________________________ 1 lsb = fsr x v ref 65,536 x 4.096v binary output code (lsb [hex]) ffff fffe fffd 8001 8000 7fff 0003 0002 0001 0000 fsr 0 1 2 3 32,768 65,533 65,535 input voltage (lsb [decimal]) (agnd1) fsr figure 13. ideal unipolar transfer function, single-ended input, -fsr to 0 1 lsb = fsr x v ref 65,536 x 4.096v binary output code (lsb [hex]) ffff fffe fffd 8001 8000 7fff 0003 0002 0001 0000 fsr 0 1 2 3 32,768 65,533 65,535 input voltage (lsb [decimal]) (agnd1) fsr figure 14. ideal unipolar transfer function, single-ended input, 0 to +fsr 1 lsb = fsr x v ref 65,536 x 4.096v binary output code (lsb [hex]) ffff fffe fffd 8001 8000 7fff 0003 0002 0001 0000 fsr -32,768 -32,766 0 +32,765 +32,767 input voltage (lsb [decimal]) agnd1 (dif/sgl = 0) 0v (dif/sgl = 1) fsr -1 +1 figure 12. ideal bipolar transfer function, single-ended or differential input
? user supplies one byte of sclk, then drives cs high to relieve processor load while the adc converts ? after sstrb transitions high, the user supplies two bytes of sclk and reads data at dout external clock mode (mode 0) the MAX1302s fastest maximum throughput rate is achieved operating in external clock mode. sclk con- trols both the acquisition and conversion of the analog signal, facilitating precise control over when the analog signal is captured. the analog input sampling instant is at the falling edge of the 14th sclk (figure 2). since sclk drives the conversion in external clock mode, the sclk frequency should remain constant while the conversion is clocked. the minimum sclk frequency prevents droop in the internal sampling capacitor voltages during conversion. sstrb remains low in the external clock mode, and as a result may be left unconnected if the MAX1302 will always be used in the external clock mode. MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ______________________________________________________________________________________ 23 cs sclk din dout 18 start sel2 sel1 sel0 r2 r1 r0 dif/sgl t cl t cp t ch t dv t css t ds t dh t csh t cspw t tr high impedance 18 start m2 m1 m0 1 0 0 0 analog input configuration byte mode control byte high impedance high impedance figure 15. analog input configuration byte and mode-control byte timing cs sclk dout t css high impedance sstrb t sscs msb t do note: sstrb and cs remain low in external clock mode (mode 0). figure 16. dout and sstrb timing table 7. mode-control byte bit number bit name description 7 start start bit. the first logic 1 after cs goes low defines the beginning of the mode-control byte. 6m2 5m1 4m0 mode-control bits. m[2:0] select the mode of operation as shown in table 8. 3 1 bit 3 must be a logic 1 for the mode-control byte. 2 0 bit 2 must be a logic 0 for the mode-control byte. 1 0 bit 1 must be a logic 0 for the mode-control byte. 0 0 bit 0 must be a logic 0 for the mode-control byte.
MAX1302 external acquisition mode (mode 1) the slowest maximum throughput rate is achieved with the external acquisition method. sclk controls the acquisition of the analog signal in external acquisition mode, facilitating precise control over when the analog signal is captured. the internal clock controls the con- version of the analog input voltage. the analog input sampling instant is at the falling edge of the 16th sclk (figure 3). for the external acquisition mode, cs must remain low for the first 15 clock cycles and then rise on or after the falling edge of the 16th sclk cycle as shown in figure 3. for optimal performance, idle din and sclk during the conversion. with careful board layout, transitions at din and sclk during the conversion have a minimal impact on the conversion result. after the conversion is complete, sstrb asserts high and cs can be brought low to read the conversion result. sstrb returns low on the rising sclk edge of the subsequent start bit. internal clock mode (mode 2) in internal clock mode, the internal clock controls both acquisition and conversion of the analog signal. the inter- nal clock starts approximately 100ns to 400ns after the falling edge of the eighth sclk and has a rate of about 4.5mhz. the analog input sampling instant occurs at the falling edge of the 11th internal clock signal (figure 4). for the internal clock mode, cs must remain low for the first seven sclk cycles and then rise on or after the falling edge of the eighth sclk cycle. after the conver- sion is complete, sstrb asserts high and cs can be brought low to read the conversion result. sstrb returns low on the rising sclk edge of the subsequent start bit. reset (mode 4) as shown in table 8, set m[2:0] = 100 to reset the MAX1302 to its default conditions. the default condi- tions are full power operation with each channel config- ured for v ref , bipolar, single-ended conversions using external clock mode (mode 0). partial power-down mode (mode 6) as shown in table 8, when m[2:0] = 110, the device enters partial power-down mode. in partial power- down, all analog portions of the device are powered down except for the reference voltage generator and bias supplies. to exit partial power-down, change the mode by issu- ing one of the following mode-control bytes (see the mode control section): ? external-clock-mode control byte ? external-acquisition-mode control byte ? internal-clock-mode control byte ? reset byte ? full power-down-mode control byte this prevents the MAX1302 from inadvertently exiting partial power-down mode because of a cs glitch in a noisy digital environment. full power-down mode (mode 7) when m[2:0] = 111, the device enters full power-down mode and the total supply current falls to 1a (typ). in full power-down, all analog portions of the device are powered down. when using the internal reference, upon exiting full power-down mode, allow 10ms for the internal reference voltage to stabilize prior to initiating a conversion. to exit full power-down, change the mode by issuing one of the following mode-control bytes (see the mode control section): ? external-clock-mode control byte 8-channel, ? ref multirange inputs, serial 16-bit adc 24 ______________________________________________________________________________________ m2 m1 m0 mode 0 0 0 external clock (default) 0 0 1 external acquisition 0 1 0 internal clock 0 1 1 reserved 1 0 0 reset 1 0 1 reserved 1 1 0 partial power-down 1 1 1 full power-down table 8. mode-control bits m[2:0]
? external-acquisition-mode control byte ? internal-clock-mode control byte ? reset byte ? partial power-down-mode control byte this prevents the MAX1302 from inadvertently exiting full power-down mode because of a cs glitch in a noisy digital environment. power-on reset the MAX1302 powers up in normal operation configured for external clock mode with all circuitry active (tables 7 and 8). each analog input channel (ch0Cch7) is set for single-ended conversions with a v ref bipolar input range (table 6). allow the power supplies to stabilize after power-up. do not initiate any conversions until the power supplies have stabilized. additionally, allow 10ms for the internal reference to stabilize when c ref = 1.0f and c recap = 0.1f. larger reference capacitors require longer stabilization times. internal or external reference the MAX1302 operates with either an internal or external reference. the reference voltage impacts the adcs fsr (figures 12, 13, and 14). an external reference is recom- mended if more accuracy is required than the internal ref- erence provides, and/or multiple converters require the same reference voltage. internal reference the MAX1302 contains an internal 4.096v bandgap refer- ence. this bandgap reference is connected to refcap through a nominal 5k ? resistor (figure 17). the voltage at refcap is buffered creating 4.096v at ref. when using the internal reference, bypass refcap with a 0.1f or greater capacitor to agnd1 and bypass ref with a 1.0f or greater capacitor to agnd1. external reference for external reference operation, disable the internal reference and reference buffer by connecting refcap to avdd1. with avdd1 connected to refcap, ref becomes a high-impedance input and accepts an external reference voltage. the MAX1302 external ref- erence current varies depending on the applied refer- ence voltage and the operating mode (see the external reference input current vs. external reference input voltage in the typical operating characteristics ). applications information noise reduction additional samples can be taken and averaged (over- sampling) to remove the effect of transition noise on conversion results. the square root of the number of samples determines the improvement in performance. for example, with 2/3 lsb rms (4 lsb p-p ) transition noise, 16 (4 2 = 16) samples must be taken to reduce the noise to 1 lsb p-p . interface with 4?0ma signals figure 19 illustrates a simple interface between the MAX1302 and a 4C20ma signal. 4C20ma signaling can be used as a binary switch (4ma represents a logic-low signal, 20ma represents a logic-high signal), or for pre- cision communication where currents between 4ma and 20ma represent intermediate analog data. for binary switch applications, connect the 4C20ma signal to the MAX1302 with a resistor to ground. for example, a 200 ? resistor converts the 4C20ma signal to a 0.8v to 4v signal. adjust the resistor value so the parallel com- bination of the resistor and the MAX1302 source impedance is 200 ? . in this application, select the sin- gle-ended 0v to v ref range (r[2:0] = 011, table 6). for applications that require precision measurements of continuous analog currents between 4ma and 20ma, use a buffer to prevent the MAX1302 input from divert- ing current from the 4C20ma signal. MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ______________________________________________________________________________________ 25 ref refcap agnd1 4.096v bandgap reference 5k ? 1x sar adc ref 4.096v 1.0 f 0.1 f v rcth MAX1302 figure 17. internal reference operation
MAX1302 bridge application the MAX1302 converts 1khz signals more accurately than a similar sigma-delta converter that might be con- sidered in bridge applications. the input impedance of the MAX1302, in combination with the current-limiting resistors, can affect the gain of the MAX1302. in many applications this error is acceptable, but for applica- tions that cannot tolerate this error, the MAX1302 inputs can be buffered (figure 20). connect the bridge to a low-offset differential amplifier and then the true differ- ential inputs of the MAX1302. larger excitation voltages take advantage of more of the v ref /2 differential input voltage range. select an input voltage range that matches the amplifier output. be aware of the amplifier offset and offset-drift errors when selecting an appro- priate amplifier. dynamically adjusting the input range software control of each channels analog input range and the unipolar endpoint overlap specification make it possible for the user to change the input range for a channel dynamically and improve performance in some applications. changing the input range results in a small lsb step-size over a wider output voltage range. for example, by switching between a -v ref /2 to 0v range and a 0v to v ref /2 range, an lsb is: but the input voltage range effectively spans from -v ref /2 to +v ref /2 (fsr = +v ref ). layout, grounding, and bypassing careful pcb layout is essential for best system perfor- mance. boards should have separate analog and digital ground planes and ensure that digital and analog sig- nals are separated from each other. do not run analog and digital (especially clock) lines parallel to one anoth- er, or digital lines underneath the device package. figure 1 shows the recommended system ground con- nections. establish an analog ground point at agnd1 and a digital ground point at dgnd. connect all analog grounds to the star analog ground. connect the digital grounds to the star digital ground. connect the digital ground plane to the analog ground plane at one point. for lowest noise operation, make the ground return to the star grounds power-supply low impedance and as short as possible. high-frequency noise in the avdd1 power supply degrades the adcs high-speed comparator perfor- mance. bypass avdd1 to agnd1 with a 0.1f ceramic surface-mount capacitor. make bypass capacitor con- nections as short as possible. parameter definitions integral nonlinearity (inl) inl is the deviation of the values on an actual transfer function from a straight line. this straight line is either a best straight-line fit or a line drawn between the end- points of the transfer function once offset and gain errors have been nullified. the MAX1302 inl is mea- sured using the endpoint method. () ,. vv ref ref 2 65 536 4 096 8-channel, ? ref multirange inputs, serial 16-bit adc 26 ______________________________________________________________________________________ ref refcap agnd1 4.096v bandgap reference 5k ? 1x sar adc ref 4.096v 1.0 f v rcth MAX1302 avdd1 max6341 v+ 1.0 f out gnd in figure 18. external reference operation
differential nonlinearity (dnl) dnl is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of greater than -1 lsb guarantees no missing codes and a monotonic transfer function. transition noise transition noise is the amount of noise that appears at a code transition on the adc transfer function. conversions performed with the analog input right at the code transi- tion can result in code flickering in the lsbs. channel-to-channel isolation channel-to-channel isolation indicates how well each analog input is isolated from the others. the channel-to- channel isolation for these devices is measured by applying a near full-scale magnitude 5khz sine wave to the selected analog input channel while applying an equal magnitude sine wave of a different frequency to all unselected channels. an fft of the selected chan- nel output is used to determine the ratio of the magni- tudes of the signal applied to the unselected channels and the 5khz signal applied to the selected analog input channel. this ratio is reported, in db, as channel- to-channel isolation. MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ______________________________________________________________________________________ 27 MAX1302 200 ? 4?20ma input 200 ? 4?20ma input ch0 ch8 c figure 19. 4C20ma application MAX1302 ch0 ref p ch1 low-offset differential amplifier bridge figure 20. bridge application
MAX1302 unipolar offset error -fsr to 0v when a zero-scale analog input voltage is applied to the converter inputs, the digital output is all ones (0xffff). ideally, the transition from 0xffff to 0xfffe occurs at agnd1 - 0.5 lsb. unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point, with all untested channels grounded. 0v to +fsr when a zero-scale analog input voltage is applied to the converter inputs, the digital output is all zeros (0x0000). ideally, the transition from 0x0000 to 0x0001 occurs at agnd1 + 0.5 lsb. unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point, with all untested channels grounded. bipolar offset error when a zero-scale analog input voltage is applied to the converter inputs, the digital output is a one followed by all zeros (0x8000). ideally, the transition from 0x7fff to 0x8000 occurs at (2 n-1 - 0.5) lsb. bipolar off- set error is the amount of deviation between the mea- sured midscale transition point and the ideal midscale transition point, with untested channels grounded. gain error when a positive full-scale voltage is applied to the con- verter inputs, the digital output is all ones (0xffff). the transition from 0xfffe to 0xffff occurs at 1.5 lsb below full scale. gain error is the amount of deviation between the measured full-scale transition point and the ideal full-scale transition point with the offset error removed and all untested channels grounded. unipolar endpoint overlap unipolar endpoint overlap is the change in offset when switching between complementary input voltage ranges. for example, the difference between the volt- age that results in a 0xffff output in the -v ref /2 to 0v input voltage range and the voltage that results in a 0x0000 output in the 0v to +v ref /2 input voltage range is the unipolar endpoint overlap. the unipolar endpoint overlap is positive for the MAX1302, preventing loss of signal or a dead zone when switching between adja- cent analog input voltage ranges. small-signal bandwidth a 100mv p-p sine wave is applied to the adc, and the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. full-power bandwidth a 95% of full-scale sine wave is applied to the adc, and the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. common-mode rejection ratio (cmrr) cmrr is the ability of a device to reject a signal that is common to or applied to both input terminals. the common-mode signal can be either an ac or a dc sig- nal or a combination of the two. cmr is expressed in decibels. common-mode rejection ratio is the ratio of the differential signal gain to the common-mode signal gain. cmrr applies only to differential operation. power-supply rejection ratio (psrr) psrr is the ratio of the output-voltage shift to the power-supply-voltage shift for a fixed input voltage. for the MAX1302, avdd1 can vary from 4.75v to 5.25v. psrr is expressed in decibels and is calculated using the following equation: for the MAX1302, psrr is tested in bipolar operation with the analog inputs grounded. aperture jitter aperture jitter, t aj , is the statistical distribution of the variation in the sampling instant (figure 21). aperture delay aperture delay, t ad , is the time from the falling edge of sclk to the sampling instant (figure 21). signal-to-noise ratio (snr) snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral com- ponents to the nyquist frequency excluding the funda- mental, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise plus distortion. rms noise plus distortion includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. sinad db signal noise rms rms ( ) log = ? ? ? ? ? ? 20 psrr db vv vvvv out out [ ] log . . (. ) (. ) = ? ? ? ? ? ? ? ? 20 525 475 525 475 8-channel, ? ref multirange inputs, serial 16-bit adc 28 ______________________________________________________________________________________
effective number of bits (enob) enob indicates the global accuracy of an adc at a specific input frequency and sampling rate. with an input range equal to the adcs full-scale range, calcu- late the enob as follows: total harmonic distortion (thd) for the MAX1302, thd is the ratio of the rms sum of the input signals first four harmonic components to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonic components. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the fundamental (maximum signal component) to the rms value of the next-largest spectral component. thd vvvv v log = +++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 enob sinad . . = ? ? ? ? ? ? ? 176 602 MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc ______________________________________________________________________________________ 29 t ad t aj intclk (mode 2) analog input track and hold track hold sample instant sclk (mode 0) 13 14 15 sclk (mode 1) 15 16 10 11 12 figure 21. aperture diagram
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc 30 ______________________________________________________________________________________ chip information process: bicmos block diagram MAX1302 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd1 analog input mux and multirange circuitry pga agnd2 avdd2 4.096v bandgap reference 1x 5k ? in ref refcap ref control logic and registers fifo clock out sar adc serial i/o agnd2 avdd2 agnd3 avdd1 dgnd dvdd dgndo sclk dout sstrb din cs dvdd0 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 24 tssop u24+1 21-0066 90-0118
MAX1302 8-channel, ? ref multirange inputs, serial 16-bit adc maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 31 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 3/12 initial release

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