1/4 rev. a structure silicon monolithic integrated circuit product name dual, low-dropout linear regulators type BD7003NUX functions ? 2-channel 300ma, cmos-type ldos. ? pin-programmable output voltage. 9 steps adjustable vo see the table of ?outpu t-voltage programming?. ? ldos power on/off enable control. ? 2.0mm 2.0mm package. ? small ceramic output capacitors(1 f) ? equipped with over current limiter and thermal shutdown circuit(tsd) . absolute maximum ratings (ta=25 ) parameter symbol rating unit maximum supply voltage (vin) vin -0.3 7 v maximum input voltage 1 (p1,p2,en1,en2) vinmax1 -0.3 7 v maximum input voltage 2 (vout1,vout2) vinmax2 -0.3 vin+0.3 v power dissipation pd 1360 mw operating temperature range topr -40 +85 storage temperature range tstg -55 +150 *this is the allowable loss of when it is mounted on a rohm specification board 40mm 40mm 1.5mmt to use at temperature higher than 25 ? c , derate 10.9mw per 1 ? c. operating range (ta=-40 ? c +85 ) (do not exceed pd) parameter symbol range unit input power supply voltage range vin 2.5 5.5 v this product is not especially designed to be protected from radioactivity.
2/4 rev. a electrical characteristics vin=3.7v, en1=en2=vin,ta =+25 , unless otherwise noted. parameter symbol min typ max unit condition output voltage range vout 1.5 - 3.3 v input voltage range vin 2.5 - 5.5 v output voltage accuracy vout -1.8 - 1.8 % iout=1ma maximum output current imax 300 - - ma short circuit current is c - 150 - ma vout = 0v ground pin current iq - 55 95 a iout=0ma - 35 65 one ldo shutdown, iout=0ma dropout voltage vdrop - 120 170 mv vin=2.5v, vout=2.6v, iout=100ma - 90 140 vin=2.7v, vout=2.8v, iout=100ma - 70 120 vin=3.2v, vout=3.3v,iout=100ma - 360 510 vin=2.5v, vout=2.6v, iout=300ma - 270 420 vin=2.7v, vout=2.8v, iout=300ma - 210 360 vin=3.2v, vout=3.3v, iout=300ma line regulation vlnr - 0.02 0.2 %/v vin=vout+1v to vin=5.5v, iout=10ma load regulation vldr - 0.2 0.6 % iout=1ma to 300ma ripple rejection psrr - 66 - db f=100hz,iout=10ma@vout=1.5v output noise en - 150 - vrms fbw=10hz to 100khz;iout=10ma en1,en2 enable input threshold vih 1.2 - - v regulator enabled vil - - 0.5 regulator shutdown enable input leakage current ien - 0.1 1 a ven=vin , ta=+25 shutdown supply current iqshdn - 0.1 1 a vout=0v , ta=+25 output-voltage programming pin name p1 p2 vout1 vout2 set up open open 1.50 2.80 open gnd 1.80 2.60 open vin 1.80 2.70 gnd open 1.80 2.80 gnd gnd 1.80 2.90 gnd vin 2.60 2.80 vin open 2.80 2.80 vin gnd 2.90 2.90 vin vin 2.80 3.30 output voltages, vout1 and vout2, are determined at power up by the state of p1 and p2(see the table of ?output-voltage programming?). subsequent charges to p1 and p2 do not change the output voltages unless the supply power is cycled, or all en inputs are simultaneously driven low to shutdown the device.
3/4 rev. a package block diagram pin description pin no. pin name 1 vin 2 en1 3 p2 4 p1 5 en2 6 gnd 7 vout2 8 vout1 [unit: mm] over current protection discharge circuit p error amp en1 output voltage control vref & tsd shutdown and power-on control ldo2 2 5 1 8 7 vout1 vout2 en2 en1 vin 4 3 p2 p1 6 gnd ldo1 vin 0 lot no. 0 3 b d 7
4/4 rev. a use-related cautions (1) absolute maximum ratings if applied voltage (vin), operating temperature range (topr), or other abso lute maximum ratings are exceeded, there is a risk of damage. since it is not possible to identify short, ope n, or other damage modes, if special modes in which absolute maximum ratings are exceeded are assumed, consider applying fuses or other physical safety measures. (2) recommended operating range this is the range within which it is possi ble to obtain roughly the expected characte ristics. for electric al characteristics, it is those that are guaranteed under th e conditions for each parameter. even when these are within the recommended operating range, voltage and temperature characteristics are indicated. (3) reverse connection of power supply connector there is a risk of damaging the lsi by reverse connection of the power supply connector. for protection from reverse connection, take measures such as exte rnally placing a diode between the power supply and the power supply pin of the lsi. (4) power supply lines in the design of the board pattern, make power supply and gnd line wiring low impedance. when doing so, although the digital power supply and analog pow er supply are the same potential, separate the digital power supply pattern and analog power suppl y pattern to deter digital noise from entering the analog power supply due to the common impedance of the wi ring patterns. simi larly take pattern de sign into account for gnd lines as well. furthermore, for all power supply pins of the lsi, in co njunction with inserting capac itors between power supply and gnd pins, when using electroly tic capacitors, determine cons tants upon adequately confirming that capacitance loss occurring at low temperatures is not a problem for various characteristics of the capacitors used. (5) gnd voltage make the potential of a gnd pin such that it will be the lowe st potential even if operating below th at. in addition, confirm that there are no pi ns for which the potential becomes less than a gnd by ac tually including transition phenomena. (6) shorts between pins and misinstallation when installing in the set board, pay adequate attention to orientation and placement discrepancies of the lsi. if it is installed erroneously, there is a risk of lsi damage. there also is a risk of damage if it is shorted by a foreign substance getting between pins , between a pin and a power supply or gnd. (7) operation in strong magnetic fields be careful when using the lsi in a strong magnetic field, since it may malfunction. (8) inspection in set board when inspecting the lsi in the set board, since there is a risk of stress to the lsi when capacitors are connected to low impedance lsi pins, be sure to discharge for each process. mo reover, when getting it on and off of a jig in the inspection process, always connect it after turning off the power supply , perform the inspection, and remove it after turning off the power supply. furthermore, as countermea sures against static electricity, use gro unding in the assembly process and take appropriate care in transport and storage. (9) input pins parasitic elements inevitably are formed on an lsi structur e due to potential relationships . because parasitic elements operate, they give rise to interference wi th circuit operation and may be the cause of malfunctions as well as damage. accordingly, take care not to apply a lower voltage than gnd to an input pin or use the lsi in other ways such that parasitic elements operate. moreover, do not apply a voltage to an input pin when the power supply voltage is not being applied to the lsi. furthermore, when the power supply voltag e is being applied, make each input pin a voltage less than the power supply voltage as well as within the guaranteed values of electrical characteristics. (10) ground wiring pattern when there is a small signal gnd and a large current gnd, it is recommended that yo u separate the large current gnd pattern and small signal gnd pattern and provide single point gr ounding at the reference point of the set so that voltage variation due to resistance components of the pattern wiring and large currents do not cause the small signal gnd voltage to change. take care that the gnd wiring pattern of externally attached components also does not change. (11) ex ternally attached capacitors when using ceramic capacitors for externally attached ca pacitors, determine constants upon taking into account a lowering of the rated capacitance due to dc bias and ca pacitance change due to factors such as temperature. (12) thermal shutdown circuit (tsd) when the junction temperature reaches the defined value, the thermal shutdown circuit operates and turns the switch off. the thermal shutdown circuit, which is aimed at isolat ing the lsi from thermal runaway as much as possible, is not aimed at the protection or guarantee of the lsi. therefore, do not continuously use the lsi with this circuit operating or use the lsi assuming its operation. (13) thermal design perform thermal design in which there are adequate margins by taking into account the pe rmissible dissipation (pd) in actual states of use. (14) rush current extra care must be taken on power coupling, power, gr ound line impedance, and pcb de sign while excess amount of rush current might instantly flow through the power line wh en powering-up a lsi which is equipped with several power supplies, depending on on/off sequence, and ramp delays.
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