page . 1 rev.0.3-sep.25.2009 PJ4N3KDW features ? r ds(on) , v gs @2.5v,i ds @1ma=7.0 ? r ds(on) , v gs @4.0v,i ds @10ma=5.0 ? advanced trench process technology ? high density cell design for ultra low on-resistance ? the mosfet elements are independent,eliminating interference ? mounting cost and area can be cut in half ? very low leakage current in off condition ? specially designed for battery operated systems,solid-state relays drivers : relays, displays, lamps, solenoids, memories, etc. ? low voltage drive (2.5v) makes this device ideal for portable equipment ? esd protected 2kv hbm ? in compliance with eu rohs 2002/95/ec directives mechanical data ? case: sot-363 package ? terminals : solderable per mil-std-750,method 2026 ? marking : 4n3 absolute maximum ratings (t a =25 o c ) note: 1. maximum dc current limited by the package 2. surface mounted on fr4 board, t < 5 sec pan jit reserves the right to improve product design,functions and reliability without notice 1 2 3 6 5 4 1 2 3 6 5 4 1 2 3 6 5 4 30v dual n-channel enhancement mode mosfet - esd protected parameter symbol limit units drain-source voltage v ds 30 v gate-source voltagee v gs + 20 v continuous drain current i d 100 ma pulsed drain current (1) i dm 800 ma maximum power dissipation t a =25 o c t a =75 o c p d 200 120 mw operating junction and storage temperature range t j ,t stg -55 to + 150 o c junction-to ambient thermal resistance (pcb mounted) 2 r ja 625 o c/w
page . 2 rev.0.3-sep.25.2009 PJ4N3KDW electrical characteristics (t a =25 o c ) parameter symbol test condition min. typ. max. units static drain-source breakdown voltage bv dss v gs =0v, i d =10ua 30 - - v gate threshold voltage v gs(th) v ds =3.0v, i d =100ua 0.8 - 1.5 v drain-source on-state resistance r ds(on) v gs =2.5v, i d =1ma - - 7 . 0 drain-source on-state resistance r ds(on) v gs =4.0v, i d =10ma - - 5.0 zero gate voltage drain current i dss v ds =30v, v gs =0v - - 1 ua gate body leakage i gss v gs =+ 20v, v ds =0v - - 5 ua forward transconductance g fs v ds =3v, i d =10ma 10 - - ms diode forward voltage v sd i s =115ma , v gs =0v - 0.78 1.3 v dynamic total gate charge q g v ds =15v, i d =10ma v gs =4.5v --0.8nc turn-on delay time td (on) v dd =5v , r l =500 i d =10ma , v gen =5v r g =10 -3035 ns rise time t r -8.512 turn-off delay time td (off) -84100 fall time t f -3240 input capacitance c iss v ds =5v, v gs =0v f=1.0mh z -2535 pf output capacitance c oss -812 reverse transfer capacitance c rss -2.55
page . 3 rev.0.3-sep.25.2009 mounting pad layout ? packing information t/r - 10k per 13" plastic reel t/r - 3k per 7? plastic reel order information legal statement copyright panjit international, inc 2009 the information presented in this document is believed to be accurate and reliable. the specifications and information herein are subject to change without notice. pan jit makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. pan jit products are not authorized for use in life support devices or systems. pan jit does not convey any license under its patent rights or rights of others. PJ4N3KDW
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