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isolated, dual channel, rs - 232 line driver/receiver data sheet ADM3252E rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features 2.5 kv fully isolated (power and data) rs - 232 transceiver iso power integrated, isolated dc - to - dc converter operational from single 3.3 v or 5 v supply 460 kbps data rate 2 tx and 2 rx c hannels meets eia/tia - 232e specifications esd protection to iec 1000 - 4 - 2 (801.2) on r in x and t out x pins contact discharge: 8 kv air gap discharge: 15 kv 0.1 f charge pump capacitors high common - mode transient immunity: >25 kv/ s safety and regulatory approvals (pending) ul recognition 250 0 v rms for 1 minute per ul 1577 vde c ertificate of c onformity iec 60747 - 5 - 2 (vde 0884, part 2) v iorm = 560 v peak csa component acceptance notice #5a operating temperature range: ?40c to +85c 44- ball chip scale package ball grid array (csp _ bga) applications isolated rs - 232 i nterface high noise data communications industrial communications industrial/telecommunications diagnostic ports medical equipment functional block dia gram figure 1 . general description the ADM3252E is a high speed, 2.5 kv , fully isolated, dual - channel rs - 232/v.28 transceiver device that is operational from a single 3.3 v or 5 v power supply. because of high esd pro tection on the r in1 , r in2 , t out1 , and t out2 pins, the ADM3252E is ideally suited for operation in electrically harsh environments or where rs - 232 cables are frequently plugged and unplugged. the ADM3252E provides four independent isolation channels using the integrated an d isolated power of iso power?. there is no requirement to use a separate isolated dc - to - dc converter. chip scale transformer i coupler ? technology from analog devices, inc., is used for both the isolation of the logic signals and the integrated dc - to - dc con verter. the result is a total isolation solution. iso power technology in the ADM3252E uses high frequency switching elements to transfer power through its transformer. special care must be taken during printed circuit board (pcb) layout to meet emissions standards. refer to the an - 0971 application note , recommendations for control of radiated emissions with iso power devices , for details on board layout considerations. the ADM3252E conforms to the eia/tia - 232e and itu - t v. 28 specifications and operates at data rates of up to 460 kbps. four external 0.1 f charge pump capacitors are used for the voltage doubler/inverter, permitting operation from a single 3.3 v or 5 v supply. the ADM3252E is available in a 44 - ball, chip scale package ball grid array (csp_bga) and is specified over the ?40c to +85c temperature range. rect reg v? c4 0.1f 16v voltage doubler c1+ c1? v+ v iso c2+ c2? voltage inverter v cc gnd gnd iso ADM3252E osc decode r r out1 r in1 * encode t in1 t t out1 encode decode decode r r out2 r in2 * encode t in2 t t out2 encode decode 10f 0.1f c3 0.1f 10v c2 0.1f 16v 0.1f 10f c1 0.1f 16v *internal 5k pull-down resistor on the rs-232 inputs. 10515-001
ADM3252E data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision h istory ............................................................................... 2 specifications ..................................................................................... 3 package characteristics ............................................................... 4 regula tory information (pending) ............................................ 4 insulation and safety - related specifications ............................ 5 absolute maximum ratings ....................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 10 isolation of power and data ...................................................... 10 charge pump voltage converter ............................................. 11 3.3 v logic to eia/tia - 232e transmitter ............................. 11 eia/tia - 232e to 3.3 v logic receiver ................................... 11 high baud rate ........................................................................... 11 applications i nformation .............................................................. 12 pcb layout ................................................................................. 12 start - up behavior ....................................................................... 12 dc correctness and magnetic field immunity ..................... 13 power considerations ................................................................ 13 thermal anal ysis ....................................................................... 14 insulation lifetime ..................................................................... 14 packagin g and ordering information ......................................... 15 outline dimensions ................................................................... 15 ordering guide .......................................................................... 15 revision history 4/ 12 rev ision 0: initial version
data sheet ADM3252E rev. 0 | page 3 of 16 specifications all voltage s are relative to their respective ground s, all minimum/maximum specifications apply over the entire recommended operating range , t a = ?40 c to +85 c , unless otherwise noted. table 1. parameter min typ max unit test conditions/comments dc characteristics v cc operating voltage range 3.0 3.3 5.5 v uvlo threshold rising 2.7 v undervoltage l ockout falling 2.3 v input supply current, i c c 20 35 ma no load 45 75 ma r l = 3 k , v cc = 3.0 v to 5.5 v 35 60 ma r l = 3 k , v cc = 3.3 v v iso output 3.3 v i iso = 0 a v iso maximum load current, i iso(max) 15 ma logic transmitter input s , t in1 and t in2 logic input current ?10 +0.01 +10 a logic input threshold low 0.3 v cc v high 0.7 v cc v receiver output s , r out1 and r out2 logic high output v cc ? 0.2 v cc v i routh = ?20 a v cc ? 0.5 v cc ? 0.3 v i routh = ?4 ma logic low output 0.0 0.1 v i routh = 20 a 0.2 0.4 v i routh = 4 ma rs -232 receiver inputs , r in1 and r in2 eia -232 input voltage range 1 ?30 +30 v threshold low 0.8 1.0 v threshold high 1.5 2.0 v hysteresis 0.45 v resistance 3 5 7 k transmitter outputs , t out1 and t out2 output voltage swing (rs -232) 5.0 5.2 v r l = 3 k to gnd transmitter output resistance 300 v cc = 0 v, v iso = 0 v output short - circuit current (rs - 232) 15 ma timing characteristics maximum data rate 460 kbps r l = 3 k to 7 k, c l = 50 pf to 1000 pf receiver propagation delay t phl 0.4 1 s t plh 0.4 1 s transmitter propagation delay 0.3 1.2 s r l = 3 k, c l = 1000 pf transmitter skew 30 ns receiver skew 300 ns transition region slew rate 10 v/ s measured from +3 v to ?3 v or ?3 v to +3 v, v cc = +3.3 v, r l = 3 k, c l = 1000 pf, t a = 25c
ADM3252E data sheet rev. 0 | page 4 of 16 parameter min typ max unit test conditions/comments ac specifications output rise/fall time, t r /t f (10% to 90%) 2.5 ns c l = 15 pf, cmos signal levels common - mode transient immunity logic high output 2 25 kv/ s v cm = 1 kv, transient magnitude = 800 v logic low output 2 25 kv/ s v cm = 1 kv, transient magnitude = 800 v refresh rate 1.0 mbps 1 guaranteed by design. 2 v cm is the maximum common - mode voltage slew rate that can be sustained while maintaining specification compliant operation. v cm is the common - mode potential difference between the logic and bus sides. the transient magnitude is the range over which the common - mode voltage is slewed. the common - mode voltage slew rates apply to both rising and falling common - mode edges. package characterist ics table 2. parameter symbol min typ max unit test conditions /comments package characteristics resistance (input -to - output) r i- o 10 12 capacitance (input -to - output) c i- o 2.2 pf f = 1 mhz input ca pacitance c i 4.0 pf ic junction -to - air thermal resistance ja 40 c/w regulator y information (pending) table 3. ul csa vde recognized u nder ul 1577 component recognition p rogram 1 approved under csa component acceptance notice #5a certified according to iec 60747 -5- 2 (vde 0884 part 2):2003 -01 2 single protection, 2500 v rms isolation voltage testing was conducted per csa 60950 -1- 07 and iec 60950 -1 2 nd e d. at 2.5 kv rated voltage basic insulation, 560 v peak basic insulation at 400 v rms (565 v peak) working voltage 1 in accordance with ul 1577, each ADM3252E is proof tested by applying an insulation test voltage 3000 v rms f or 1 second (current leakage detection limit = 15 a). 2 in accordance with iec 60747 - 5 - 2 (vde 0884 part 2):2003 - 01, each ADM3252E is proof tested by applying an insulation test voltage 1050 v peak for 1 second (partial discharge detection limit = 5 pc). the asterisk ( * ) marking branded on the component designates iec 60747 - 5 - 2 (vde 0884 part 2):2003 - 01 approval.
data sheet ADM3252E rev. 0 | page 5 of 16 insulation and s afety -r elated s pecifications table 4. parameter symbol value unit test conditions insulation and safety rated dielectric insulation voltage 2500 v rms 1 minute duration minimum external air gap (clearance) l(i01) 7.6 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 7.6 mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.01 7 mm distance through insulation tracking resistance (comparative tracking index) cti > 175 v isolation group llla
ADM3252E data sheet rev. 0 | page 6 of 16 absolute maximum rat ings table 5. parameter rating v cc , v iso ?0.3 v to +6 v v+ (v cc ? 0.3 v) to +13 v v? ?13 v to +0.3 v input voltages t in1 , t in2 ?0.3 v to (v cc + 0.3 v) r in1 , r in2 30 v output voltages t out1 , t out2 15 v r out1 , r out2 ?0.3 v to (v cc + 0.3 v) short - circuit duration t out1 , t out2 continuous power dissipation 750 mw operating temperature range industrial ?40c to +85c storage temperature ?65c to +150c pb - free temperature (soldering, 30 sec) 260c storage temperature prior to soldering 30c/ 60% rh max for 168 hours (msl3) bake temperature ( if r equired) 125c + 5c/ ? 0c for 48 hours esd caution s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y .
data sheet ADM3252E rev. 0 | page 7 of 16 pin configuration an d function descripti ons figure 2 . pin configuration table 6. pin function descriptions pin no. mnemonic description a1, l1 nc no connect. these pins are left unconnected. a2, b1, b2 v cc power supply input. a 10 f and a 0.1 f decoupling capacitor are required between v cc and ground. the device requires a voltage between 3.0 v and 5.5 v. a10, b10, c10 v iso supply voltage for isolator secondary side. a 10 f and a 0.1 f decoupling capacitor are required between v iso and ground. a11, l11 dnc do not connect. do not connect or route anything through these pins. b11 v+ internally generated positive supply. c1, c2, d2, e1, e2, f2, g1, g2, h2, j1, j2, k2, l2 gnd ground reference f or logic side . c11, e11, g10, g11 c1+ , c1 ?, c2?, c2+ positive and negative connections for charge pump capacitors. external capacitor s c1 and c2 are connected between these pins; a 0.1 f capacitor is recommended, but larger capacitors of up to 10 f can be used. d1 t in1 transmitter (driver) input 1. a logic low on this input generates a high on t out1 ; a logic high on this input generates a low on t out1 . this pin accepts ttl/cmos levels. this is a high impedance input pin ; therefore, it should not be left floating. d10, e10, f10, h10, j10, k10, l10 gnd iso ground reference f or isolated rs -232 s ide. d11 t out1 transmitter (driver) output 1. this pin outputs rs - 232 signal levels. f1 t in2 transmitter (driver) input 2. a logic low on this input generates a high on t out2 ; a logic high on this input generates a low on t out2 . this pin accepts ttl/cmos levels. this is a high impedance input pin; therefore, it should not be left floating. f11 t out2 transmitter (driver) output 2. this pin outputs rs - 232 signal levels. h1 r out1 receiver output 1. this pin outputs cmos logic levels. h11 r in1 receiver input 1. a logic low on this input generates a high on r out1 ; a logic high on this input generates a low on r out1 . this input pin accepts rs - 232 signal levels and has an internal 5 k pull - down resistor. j11 v? internally generated negative supply. k1 r out2 receiver output 2. this pin outputs cmos logic levels. k11 r in2 receiver input 2. a logic low on this input generates a high on r out2 ; a logic high on this input generates a low on r out2 . this input pin accepts rs - 232 signal levels and has an internal 5 k pull - down resistor. 10515-002 a 1 2 3 4 5 6 7 8 9 10 11 b c d e f g h j k l balls in column 3 to column 9 removed for isolation top view (not to scale) ADM3252E v cc v cc gnd gnd gnd gnd gnd gnd gnd gnd gnd nc v cc gnd t in1 gnd t in2 gnd r out1 gnd r out2 nc v iso v iso v iso gnd iso gnd iso gnd iso c2? gnd iso gnd iso gnd iso gnd iso dnc v+ c1+ t out1 c1? t out2 c2+ r in1 v? r in2 dnc
ADM3252E data sheet rev. 0 | page 8 of 16 typical performance characteristics figure 3 . supply current vs. temp erature , no l oad figure 4 . supply current vs. temperature , r l = 3 k? , c l = 1 nf figure 5 . supply current vs. load capacitance figure 6 . supply current vs. data rate figure 7 . transmit output vs. load capacitance figure 8 . transmit output vs. v cc 30 0 5 10 15 20 25 ?50 ?25 0 25 50 75 100 i cc (ma) temperature (c) v cc = 3.3v v cc = 5v 10515-101 70 65 60 55 50 45 40 35 30 ?50 ?25 0 25 50 75 100 i cc (ma) temperature (c) 10515-102 v cc = 3.3v v cc = 5v 120 100 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 i cc (ma) load capacitance (nf) 230kbps (3.3v) 460kbps (3.3v) 230kbps (5v) 460kbps (5v) 10515-103 r l = 3k 120 100 80 60 40 20 0 0 100 200 300 400 500 i cc (ma) data rate (kbps) v cc = 3.3v (1nf) r l = 3k v cc = 3.3v (220pf) v cc = 5v (1nf) v cc = 5v (220pf) 10515-104 8 ?8 ?6 ?4 ?2 0 2 4 6 0 0.2 0.4 0.6 0.8 1.0 1.2 tx output (v) load capacitance (nf) high low 10515-105 460kbps 460kbps 1mbps 1mbps r l = 3k 8 ?8 ?6 ?4 ?2 0 2 4 6 3.0 3.5 4.0 4.5 5.0 5.5 tx output (v) v cc (v) tx output high, r l = 3k tx output high, no load tx output low, r l = 3k tx output low, no load 10515-106
data sheet ADM3252E rev. 0 | page 9 of 16 figure 9 . transmitter input threshold vs. v cc figure 10 . receiver input threshold vs. temperature figure 11 . v iso vs. v iso load current figure 12 . 460 kbps data transmission, driver outputs tied to receiver inputs figure 13 . typical output voltage start - up transient , v cc = 3.3 v figure 14 . typical out put voltage start - up transient , v cc = 5 v 4 3 2 1 0 3.0 3.5 4.0 4.5 5.0 6.0 5.5 tx input (v) v cc (v) rising falling 10515-107 3.0 2.5 2.0 1.5 1.0 0.5 0 ?50 ?25 0 25 50 75 100 125 150 rx input (v) temperature (c) input rising input falling 10515-108 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 0 100 80 60 40 20 v iso (v) load current (ma) 10515-109 2 tx inputs @ 460kbps 3k, 1nf loads 10515-110 time (1s/div) t in1 /t in2 (2v/div) t out1 /r in1 (5v/div) r out1 (2v/div) r out2 (2v/div) t out2 /r in2 (5v/div) 10515-112 2 ch2 1.00v m500s a ch2 340mv no load fully loaded rs-232 10515-113 2 ch2 1.00v m500s a ch2 340mv no load fully loaded rs-232
ADM3252E data sheet rev. 0 | page 10 of 16 theory of operation figure 15 . functional block diagram the ADM3252E is a high speed, 2.5 kv , fully isolated, dual - channel rs - 232 transceiver device that operates from a single power supply. the internal circuitry consists of the following main sections: ? isolation of po wer and data ? charge pump voltage converter ? 3.3 v lo gic to eia/tia - 232e transmitter ? eia/t ia - 232e to 3.3 v logic receiver isolation of power a nd data the ADM3252E incorporates a dc - to - dc converter section, which works on principles that are common to most power supply designs. v cc power is supplied to an oscillating circuit that switches current into a chip scale air core transformer . power is tr ansferred to the secondary side where it is rectified to a high dc voltage. the power is then linearly regulated to 3.3 v and supplied to the secondary side data section and to the v iso pin. because the oscillator runs at a constant high frequency independent of the load, excess power is internally dissipated in the output voltage regulation process. limited space for tr ansformer coils and components adds to the internal power dissipation. this results in low power conversion efficiency. the transmitter input ( t in x ) accept s ttl/cmos input levels. the driver input signal that is applied to the t in x pin s is referenced to l ogic ground (gnd). it is coupled across the isolation barrier, inverted, and then appears at the transceiver section, referenced to isolated ground (gnd iso ). similarly, the receiver input (r in x ) accepts rs - 232 signal levels referenced to isolated ground (gnd iso ) . the r in x input is inverted and coupled across the isolation barrier to appear at the r out x pin, referenced to logic ground (gnd) . the digital signals are transmitted across the isolation barrier using i coupler technology. chip scale transformer windings couple the digital signals magnetically from one side of the barrier to the other. digital inputs are encoded into waveforms that are capable of exciting the primary transformer of the winding . at the secondary winding, the induced wa veforms are decoded into the binary value that was originally transmitted. figure 16 . typical operating circuit rect reg v? c4 0.1f 16v voltage doubler c1+ c1? v+ v iso c2+ c2? voltage inverter v cc gnd gnd iso ADM3252E osc decode r r out1 r in1 * encode t in1 t t out1 encode decode decode r r out2 r in2 * encode t in2 t t out2 encode decode 10f 0.1f c3 0.1f 10v c2 0.1f 16v 0.1f 10f c1 0.1f 16v ,17(51$/n 38//'2:15(6,6725217+(56,13876 10515-003 + c3 0.1f 10v + c1 0.1f 16v + c2 0.1f 16v 0.1f + c4 0.1f 16v v iso v+ c1+ c1? eia/tia-232e output t out1 eia/tia-232e input r in1 eia/tia-232e output t out2 eia/tia-232e input r in2 c2+ c2? v? gnd iso isolation barrier cmos output r out1 cmos output r out2 cmos input t in1 cmos input t in2 gnd 3.0v to 5.5v v cc 0.1f 10f ADM3252E 10f 10515-004
data sheet ADM3252E rev. 0 | page 11 of 16 charge pump voltage converter the charge pump voltage converter consists of a 200 khz oscillator and a switching m atrix. the converter generates a 6.6 v supply from the 3.3 v input level. this is achieved in two stages by using a switched capacitor technique , as shown in figure 17 and figure 18. figure 17 . charge pump voltage doubler f igure 18 . charge pump voltage inverter in the first stage , the 3.3 v input supply is doubled to 6.6 v using c1 as the charge storage element. in the second stage, the +6.6 v level is inverted to generate ?6.6 v using c2 as the storag e element. in figure 17, c3 is connected between v+ and v iso , but it is equally effective if c3 is connected between v+ and gnd iso . use c apacitor c3 and capacitor c4 to reduce the output ripple. their values are not critical and can be increased, if needed . larger capacitors (up to 10 f) can be used in place of c1, c2, c3, and c4. 3.3 v logic to eia/t ia - 232e t ransmitter the transmitter driver converts the 3.3 v logic input levels into rs - 232 output levels. when driving an rs - 232 load with v cc = 3.3 v, the output voltage swing is typically 6.6 v. eia/tia - 232e to 3.3 v logic receiver the receiver is an inverting level shifter that accepts the rs - 232 input level and translates it into a 3.3 v logic output level. the input has an internal 5 k? pull - down resistor to ground and is protected against overvo ltages of up to 30 v. an uncon nected input is pulled to 0 v by the internal 5 k? pull - down resistor , resulting in a logic 1 output level for an unconnected input or for an input connected to gnd. the receiver has a schmitt trigger input with a hysteresis level of 0.1 v. this ensures error free reception for both a noisy input and for an input with slow transition times. high baud rate the ADM3252E offers high slew rates, permitting data trans - miss ion at rates well in excess of the eia/tia - 232e specifications . hig her data rates are possible when running at reduced rs - 232 capacitive load levels. a s maller capacitive load , in effect , limits the cable length. see figure 7 for transmit output voltage levels at 1 mbps and figure 19 for a scope plot at 1 mbps. figure 19 . scope plot, 1 mbps o peration gnd c3 c1 s1 s2 s3 s4 v+ = 2v iso + + internal oscillator v iso v iso 10515-005 gnd iso c4 c2 s1 s2 s3 s4 gnd iso + + internal oscillator v+ v? = ?(v+) from voltage doubler 10515-006 10515-111 2 1 ch1 2.00v ch2 2.00v m400ns a ch2 680mv r l = 3k c l = 470pf tx input tx output
ADM3252E data sheet rev. 0 | page 12 of 16 application s information pcb layout the ADM3252E requires no external circuitry for its logic interfaces. power supply bypassing is required at the input and output supply pins (see figure 20 ). bypass capacitors are conveniently connected between pin b1 and pin c1 for v cc and between pin c10 and pin d10 for v iso . figure 20 . recommended printed circuit board layout to suppress noise and reduce ripple, a parallel combination of at least two capacitors is recommended. the recommended capacitor val ues are 0.1 f and 10 f for both v cc and v iso . the smaller capacitor must have a low esr; best practice suggests use of a ceramic capacitor. do not exceed 2 mm for t he total lead length bet ween both ends of the low esr capacitor and the input power supply pin. because it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipating into the pcb through the ground pins. if the device is used at high ambient temperatures, take care to provide a thermal path fr om the ground pins to the pcb ground plane. the board layout in figure 20 shows enlarged pads for the gnd and gnd iso pins. the bga balls are also gro uped together to simplify layout and routing. to sig n i ficantly reduce the temperature inside the chip, implement multiple vias from each of the pads to the ground plane. the dimensions of the expanded pads are at the discre - tion of the designer and the available board space. in applications involving high common - mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout such that any coupling that does occur equally affects all pins on a g iven component side. the power supply section of the ADM3252E uses a 180 mhz oscillator frequency to pass pow er through its chip scale trans formers. operation at these high frequencies may raise concerns abo ut radiated emissions and conducted noise. pcb layout and construction are very important tool s for controlling radiate d emissions. refer to the an - 0971 application note , recommendations for control of radiated emissions with iso power devices , for extensive guidance on radiation mechanisms and board layout considerations. start - up behavior the ADM3252E does not contain a soft start circuit. therefore, the start - up current and voltage behavior must be taken into account when designing with this device. when power is applied to v cc , the input switching circuit begins to operate and draw current when the uvlo minimum voltage is reached (approx imately 2.7 v). the switching circuit drives the maximum available power to the output until it reaches the regulation voltage , which is where pwm control begins. th e amount of current and the time required to reach regulation voltage depends on the load and the v cc slew rate. with a fast v cc slew rate (200 s or less), the peak current draws up to 100 ma/v of v cc . the input voltage goes high fas ter than the output can turn on; therefore, the peak current is proportional to the maximum input voltage. with a slow v cc slew rate (in the millisecond range), the input voltage is not changing quickly when v cc reaches the uvlo minimum voltage. the current surge is approxima tely 300 ma because v cc is nearly constant at the 2.7 v uvlo voltage. the behavior during startup is similar to when the device load is a short circuit . when powering up the device, do not limit the current available to the v cc power pin to less than 300 m a. the ADM3252E device may not be able to drive the output to th e regulation point if a current limiting device clamps the v cc voltage during startup. as a result, the ADM3252E device can draw large amounts of current at low voltage for extended periods of time. the output voltage of the ADM3252E device exhibits v iso overshoot to approximately 4 v during startup (see figure 13 and figure 14) . if this overshoot c ould potentially damage compo - nents attached to v iso , a voltage limiting device , such as a zener diode , can be used to clamp the voltage. a b c d e f g 9 10 8 11 7 5 6 4 2 3 1 h j k l c3 c1 c2 c4 a1 ball corner via to gnd iso via to gnd iso 0.1f 0.1f 10515-007
data sheet ADM3252E rev. 0 | page 13 of 16 dc correctness and m agnetic field immunity positive and negative logic transitions at the isolator input cause narr ow (~1 ns) pulses to be sent to the decoder via the trans - former. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 1 s, period ic sets of refresh pulses ( indicative of the correct input state ) are sent to ensure dc correctness at the output. if the decoder receives no internal pulses for more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional , in which case the isolator output is forced to a default state by the watchdog timer circuit. this situation should occur in the ADM3252E during power - up and power - down operations only . the limitation on the ADM3252E magnetic field immunity is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to falsely set or reset the decoder. the following analysis def ines the conditions under which this can occur. the pulses at the transformer output have an amplitude of >1.0 v. the decoder has a sensing threshold of about 0.5 v, thus estab - lishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d/dt ) ? r n 2 ; n = 1, 2, , n where: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometr y of the receiving coil internally and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated , as shown in figure 21. figure 21 . maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgaus s induces a voltage of 0.25 v at the receiving coil. this is approximately 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and is of the worst - case polarity), the r eceived pulse is reduced from >1.0 v to 0.75 v, which is still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the trans - formers. figure 22 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown in figure 22 , the ADM3252E is extremely immune and can be affected only by extremely large currents oper ated at high frequency very close to the component. for example, at a magnetic field frequency of 1 mhz, a 0.5 ka current placed 5 mm away from the ADM3252E is required to affect the operation of the component . figure 22 . maximum allowable current for various current - to - ADM3252E spacings note that in the presence of strong magnetic fields and high frequencies, any loops formed by pcb traces may induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. exercise care in the layout of such traces to avoid thi s possibility. power considerations the ADM3252E power input, data input channels on the primary side, and data channels on the secondary side are all protected from premature operation by under voltage lockout (uvlo) circuitry. below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh cir - cuits are idle. outputs remain in a high impedance state to prevent transmission of undefined st ates during power - up and power - down operations. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 10515-008 magnetic field frequency (hz) maximum allowable current (ka) 1k 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 10515-009
ADM3252E data sheet rev. 0 | page 14 of 16 during the application of power to v cc , the primary side circuitry (logic side ) is held idle until the uvlo preset voltage is reached. at that time, the data channels are initialize d to their default low o utput state s until they receive data pulses from the secondary side (rs - 232 side) . when the primary side is above the uvlo threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. th e outputs on the primary side remain in the default low state because no data comes from the secondary side inputs until secondary side power is established. the primary side oscillator also begins to operate, transferring power to the secondary power circ uits. the secondary v iso voltage is below its uvlo limit at this point , and the secondary side is not generating a regulation control signal . the primary side power oscillator can free run under these conditions, supplying the maximum amount of power to the secondary side. as the secondary side voltage rises to its regulation setpoint, a large inrush current transient is present at v cc . upon reaching the regulation point, the regulation control circuit produces the regulation control signal that mod ulates the oscillator on the primary side. the v cc current is then reduced and it is propor - tional to the load current. the duration of the inrush current depends on the v iso loading conditions and on the current and voltage available at the v cc pin . as th e secondary side converter begins to accept power from the primary side , the v iso voltage starts to rise. when the secondary side uvlo is reached, the secondary side outputs are initialized to their default low state until data is received from the corre sp onding primary side input. it can take up to 1 s after the secondary side is initialized for the state of the output to correlate to the primary side input. secondary side inputs sample their state s and transmit them to the primary side. outputs are valid about 1 s after the secondary side becomes active. because the rate of charge on the secondary side power supply is dependent on three factors: loading conditions, the input voltage, and the selected output voltage level , take care that the design allows the converter sufficient time to stabilize before valid data is required. when power is removed from v cc , the primary side converter and coupler shut down when the uvlo level is reached. the secondary side stops receiving power and starts to discharge. t he outputs on the secondary side hold the last state that they received from the primary side. either the uvlo level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches uvlo. thermal analysis the ADM3252E devic e consists of five internal die attached to a pcb laminate. for the purposes of thermal analysis , the device is treated as a thermal unit w ith the highest junction temper ature reflected in the ja value from table 2 . by f ollow ing the recommen - dations in the pcb layout section , thermal resistance to the pcb decreases , thereby allowing increased thermal margin at high ambient temperatures. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insula - tion degradation is dependent on the c haracteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADM3252E . the insulation lifetime of the ADM3252E depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structur e degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, o r dc. figure 23 , fi gure 24 , and figure 25 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. figure 23 . bipolar ac waveform figure 24 . unipolar ac waveform figure 25 . dc waveform 0v rated peak voltage 10515-010 0v rated peak voltage 10515-0 1 1 0v rated peak voltage 10515-012
data sheet ADM3252E rev. 0 | page 15 of 16 packaging and ordering information outline dimensions figure 26 . 44- ball chip scale package ball grid array [csp_bga] (bc - 44- 1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADM3252Eabcz ?40c to +85c 44- ball csp_bga bc -44-1 eval - ADM3252Eebz evaluation board 1 z = rohs compliant part. compliant with jedec standards mo-192-abd-1. 12-14- 2010-a 1.00 1.00 ref a b c d e f g 9 10 8 1 1 7 5 6 4 2 3 1 bottom view 10.00 bsc sq h j k l d e t a i l a top view detail a coplanarity 0.20 0.70 0.60 0.50 ball diameter seating plane 12.10 12.00 sq 11.90 1.55 1.44 1.35 a1 ball corner a1 ball corne r 0.48 nom 0.43 min 0.70 ref 0.26 ref 1.03 0.96 0.89
ADM3252E data sheet rev. 0 | page 16 of 16 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10515 - 0 - 4/12(0)

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