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june 2012 ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FSL117MRIN ? rev 1.0.0 FSL117MRIN ? green-mode fair child power switch (fps?) FSL117MRIN green-mode fairchild power switch (fps?) features ? advanced soft burst mode for low standby power and low audible noise ? random frequency fluctuation (rff) for low emi ? pulse-by-pulse current limit ? overload protection (olp), over-voltage protection (ovp), abnormal over-current protection (aocp), internal thermal shutdown (tsd) with hysteresis, output-short protection (o sp), line over-voltage protection (lovp), and under-voltage lockout (uvlo) with hysteresis ? low operating current (0.4ma) in burst mode ? internal startup circuit ? internal avalanche-rugged 700v sensefet ? built-in soft-start: 15ms ? auto-restart mode applications ? power supply for home appliances, lcd monitors, stbs, and dvd players description the FSL117MRIN is an integrated pulse width modulation (pwm) controller and 700v sensefet specifically designed for offline switched-mode power supplies (smps) with minimal external components. the pwm controller includes an integrated fixed- frequency oscillator, line over-voltage protection (lovp), under-voltage lockout (uvlo), leading-edge blanking (leb), optimized gate driver, internal soft-start, temperature-compensated prec ise current sources for loop compensation, and se lf-protection circuitry. compared with a discrete mosfet and pwm controller solution, the FSL117MRIN can reduce total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. this device provides a basic platform for cost-effective design of a flyback converter. ordering information part number package (1) operating junction temperature current limit (typ.) r ds(on) (max.) output power table (2) 230v ac 15% 85~265v ac adapter (3) open frame (4) adapter (3) open frame (4) FSL117MRIN 8-dip -40c ~ +125c 0.8a 11 ? 10w 15w 6w 10w notes: 1. pb-free package per jedec j-std-020b. 2. the junction temperature can limit the maximum output power. 3. typical continuous power in a non-v entilated enclosed adapt er measured at 50 ? c ambient temperature. 4. maximum practical continuous power in an open-frame design at 50 ? c ambient temperature.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 2 FSL117MRIN ? green-mode fairchild power switch (fps?) application circuit figure 1. typical application circuit internal block diagram figure 2. internal block diagram
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 3 FSL117MRIN ? green-mode fairchild power switch (fps?) pin configuration figure 3. pin assignments (top view) pin definitions pin # name description 1 gnd ground . this pin is the control ground and the sensefet source. 2 v cc power supply . this pin is the positive supply input, which provides the internal operating current for both startup and steady-state operation. 3 fb feedback . this pin is internally connected to t he inverting input of the pwm comparator. the collector of an opto-coupler is typically tied to this pin. for stable operation, a capacitor should be placed between this pin and gnd. if the voltage of this pin reaches 7v, the overload protection triggers, which shuts down the fps. 4 v in line over-voltage input . this pin is the input pin of line voltage. the voltage, which is divided by resistors, is input of this pin. if this pin voltage higher than v inh voltage, the lovp triggers, which shuts down the fps do not leave this pin floating. if lovp is not used, this pin should be connected directly to the gnd. 5 v str startup . this pin is connected directly, or throug h a resistor, to the high-voltage dc link. at startup, the internal high -voltage current source supplies internal bias and charges the external capacitor connected to the v cc pin. once v cc reaches 12v, the internal current source (i ch ) is disabled. 6 drain sensefet drain . high-voltage power sensefet drain connection . 7 8
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 4 FSL117MRIN ? green-mode fairchild power switch (fps?) absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v str v str pin voltage 700 v v ds drain pin voltage 700 v v cc v cc pin voltage 26 v v fb feedback pin voltage - 0.3 10.0 v v in v in pin voltage - 0.3 10.0 v i dm drain current pulsed (5) 4 a e as single pulsed avalanche energy (6) 50 mj p d total power dissipation (t c =25 ? c) (7) 1.5 w t j maximum junction temperature +150 ? c operating junction temperature (8) - 40 +125 ? c t stg storage temperature - 55 +150 ? c esd electrostatic discharge capability human body model, jesd22-a114 5 kv charged device model, jesd22-c101 2 notes: 5. non-repetitive rating: pulse width is limited by maximum junction temperature. 6. l=51mh, starting t j =25 ? c. 7. infinite cooling condition (refer to the semi g30-88) . 8. although this parameter guarantees ic operation, it does not guarantee all electrical characteristics. thermal impedance t a =25c unless otherwise specified. all items are tested with the standards jesd 51-2 and 51-10. symbol parameter value unit ja junction-to-ambient thermal impedance (9) 80 c/w jc junction-to-case thermal impedance (10) 20 c/w notes: 9. free standing without heat sink; without copper clad. (me asurement condition: just before junction temperature tj enter into otp.) 10. measured on the drain pin close to plastic interface.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 5 FSL117MRIN ? green-mode fairchild power switch (fps?) electrical characteristics t j = 25 ? c unless otherwise specified. symbol parameter conditions min. typ. max. unit sensefet section bv dss drain-source breakdown voltage v cc =0v, i d =200a 700 v i dss zero-gate-voltage drain current v ds =560v, t a =125 ? c 200 a r ds(on) drain-source on-state resistance v gs =10v, i d =0.5a 8.8 11.0 ? c iss input capacitance (11) v ds =25v, v gs =0v, f=1mhz 250 pf c oss output capacitance (11) v ds =25v, v gs =0v, f=1mhz 25 pf t r rise time v ds =350v, i d =1.0a 4 ns t f fall time v ds =350v, i d =1.0a 10 ns t d(on) turn-on delay v ds =350v, i d =1.0a 12 ns t d(off) turn-off delay v ds =350v, i d =1.0a 30 ns control section f s switching frequency (11) v cc =14v, v fb =4v 61 67 73 khz ? f s switching frequency variation (11) - 25 ? c < t j < 125 ? c 5 10 % d max maximum duty ratio v cc =14v, v fb =4v 61 67 73 % d min minimum duty ratio v cc =14v, v fb =0v 0 % i fb feedback source current v fb =0v 65 90 115 a v start uvlo threshold voltage v fb =0v, v cc sweep 11 12 13 v v stop after turn-on, v fb =0v 7.0 7.5 8.0 v t s/s internal soft-start time v str =40v, v cc sweep 15 ms v recomm recommended v cc range 13 23 v burst mode section v burh burst-mode voltage v cc =14v, v fb sweep 0.45 0.50 0.55 v v burl 0.30 0.35 0.40 v v hys 150 mv protection section i lim peak drain current limit di/dt=170ma/ ? s 0.70 0.80 0.90 a v sd shutdown feedback voltage v cc =14v, v fb sweep 6.45 7.00 7.55 v i delay shutdown delay current v cc =14v, v fb =4v 1.2 2.0 2.8 a t leb leading-edge blanking time (11,12) 300 ns v ovp over-voltage protection v cc sweep 23.0 24.5 26.0 v v inh line over-voltage protection threshold voltage v cc =14v, v in sweep 1.87 1.95 2.03 v v inhys line over-voltage protection hysteresis v cc =14v, v in sweep 0.06 v t osp output-short protection (11) threshold time osp triggered when t on v osp (lasts longer than t osp_fb ) 0.7 1.0 1.3 s v osp threshold v fb 1.8 2.0 2.2 v t osp_fb v fb blanking time 2.0 2.5 3.0 s tsd thermal shutdown temperature (11) shutdown temperature 125 135 145 ? c t hys hysteresis 60 ? c continued on the following page?
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 6 FSL117MRIN ? green-mode fairchild power switch (fps?) electrical characteristics (continued) t j = 25 ? c unless otherwise specified. symbol parameter conditions min. typ. max. unit total device section i op operating supply current, (control part in burst mode) v cc =14v, v fb =0v 0.3 0.4 0.5 ma i ops operating switching current, (control part and sensefet part) v cc =14v, v fb =2v 0.8 1.2 1.6 ma i start start current v cc =11v (before v cc reaches v start ) 85 120 155 ? a i ch startup charging current v cc =v fb =0v, v str =40v 0.7 1.0 1.3 ma v str minimum v str supply voltage v cc =v fb =0v, v str sweep 26 v notes: 11. although these parameters are guaranteed, they are not 100% tested in production. 12. t leb includes gate turn-on time.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 7 FSL117MRIN ? green-mode fairchild power switch (fps?) typical performance characteristics characteristic graphs are normalized at t a =25c. 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 4. operating supply current (i op ) vs. t a . figure 5. operating switching current (i ops ) vs. t a . 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 6. startup charging current (i ch ) vs. t a . figure 7. peak drain current limit (i lim ) vs. t a . 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 8. feedback source current (i fb ) vs. t a . figure 9. shutdown delay current (i delay ) vs. t a .
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 8 FSL117MRIN ? green-mode fairchild power switch (fps?) typical performance characteristics characteristic graphs are normalized at t a =25c. 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 10. uvlo threshold v oltage ( v start ) vs. t a . figure 11. uvlo threshold voltage ( v stop ) vs. t a . 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 12. shutdown feedback voltage (v sd ) vs. t a . figure 13. ove r - v oltage protection (v o v p ) vs. t a . 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] figure 14. switching frequency ( f s ) vs. t a . figure 15. maximum duty ratio (d max ) vs. t a
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 9 FSL117MRIN ? green-mode fairchild power switch (fps?) typical performance characteristics characteristic graphs are normalized at t a =25c. figure 16. line ovp (v inh ) vs. t a figure 17. hysteresis of lovp ( v inhys ) vs. t a. ? 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c] 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 \ 40'c \ 25'c 0'c 25'c 50'c 75'c 90'c 110'c 120'c 125'c normalized temperature [ c]
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 10 FSL117MRIN ? green-mode fairchild power switch (fps?) functional description 1. startup: at startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (c vcc ) connected to the v cc pin, as illustrated in figure 18. when v cc reaches 12v, the FSL117MRIN begins switching and the internal high- voltage current source is disabled. normal switching operation continues and the power is supplied from the auxiliary transformer winding unless v cc goes below the stop voltage of 7.5v. figure 18. startup block 2. soft-start : the internal soft-start circuit increases the pwm comparator inverting input voltage, together with the sensefet current, slowly after startup. the typical soft-start time is 15ms. the pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. the voltage on the output capacitors is progressively increased to smoothly establish the required output vo ltage. this helps prevent transformer saturation and reduces stress on the secondary diode during startup. 3. feedback control : this device employs current- mode control, as shown in figure 19. an opto-coupler (such as the fod817) and shunt regulator (such as the ka431) are typically used to implement the feedback network. comparing the feedback voltage with the voltage across the r sense resistor makes it possible to control the switching duty cy cle. when the reference pin voltage of the shunt regulator exceeds the internal reference voltage of 2.5v, the opto-coupler led current increases, pulling down the feedback voltage and reducing drain current. this typically occurs when the input voltage is increased or the output load is decreased. 3.1 pulse-by-pulse current limit : because current- mode control is employed, the peak current through the sensefet is limited by the inverting input of the pwm comparator (v fb *), as shown in figure 19. assuming that the 90 a current source flows only through the internal resistor (3r + r = 27k ? ), the cathode voltage of diode d2 is about 2.5v. since d1 is blocked when the feedback voltage (v fb ) exceeds 2.5v, the maximum voltage of the cathode of d2 is clamped at this voltage. th erefore, the peak value of the current through the sensefet is limited. 3.2 leading-edge blanking (leb) : at the instant the internal sensefet is turned on, a high-current spike usually occurs through the sensefet, caused by primary-side capacitance and secondary-side rectifier reverse recovery. excessive voltage across the r sense resistor leads to incorrect feedback operation in the current-mode pwm control. to counter this effect, the FSL117MRIN employs a leading-edge blanking (leb) circuit. this circuit inhibits the pwm comparator for t leb (300ns) after the sensefet is turned on. figure 19. pulse width modulation circuit
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 11 FSL117MRIN ? green-mode fairchild power switch (fps?) 4. protection circuits : the FSL117MRIN has several self-protective functions, such as overload protection (olp), abnormal over-current protection (aocp), output-short protection (osp), over-voltage protection (ovp), and thermal shutdown (tsd). all the protections are implemented as auto-restart. once a fault condition is detected, switching is terminated and the sensefet remains off. this causes v cc to fall. when v b cc b falls to the under-voltage lockout (uvlo) stop voltage of 7.5v, the pr otection is reset and the startup circuit charges the v cc capacitor. when v cc reaches the start voltage of 12.0v, the FSL117MRIN resumes normal operation. if the fault condition is not removed, the sensefet remains off and v cc drops to stop voltage again. in this manner, the auto-restart can alternately enable and disabl e the switching of the power sensefet until the faul t condition is eliminated. because these protection circ uits are fully integrated into the ic without external components, the reliability is improved without increasing cost. figure 20. auto-restart protection waveforms 4.1 overload protection (olp) : overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. in this situation, the protection circuit should trigger to protect the smps. however, even when the smps is in normal operation, the overload protection circuit can be triggered during load transition. to avoid this undesired operation, the over load protection circuit is designed to trigger only after a specified time to determine whether it is a tr ansient situation or a true overload situation. because of the pulse-by-pulse current-limit capability, the maximum peak current through the sensefet is li mited and, t herefore, the maximum input power is restricted with a given input voltage. if the output consumes more than this maximum power, the output voltage (v out ) decreases below the set voltage. this reduces the current through the opto-coupler led, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (v fb ). if v fb exceeds 2.5v, d1 is blocked and the 2.0a current source starts to charge c fb slowly up . in this condition, v fb continues increasing until it reaches 7.0v, when the switching operation is terminated, as shown in figure 21. the delay for shutdown is the time required to charge c fb from 2.5v to 7.0v with 2.0 a. a 25 ~ 50ms delay is typical for most applications. this protection is implemented as auto-restart mode. figure 21. overload protection 4.2 abnormal over-curre nt protection (aocp) : when the secondary rectifier diodes or the transformer pins are shorted, a steep current with extremely high di/dt can flow through the sensefet during the minimum turn-on time. overload protection is not enough to protec t the FSL117MRIN in that abnormal case; since severe current stress is imposed on the sensefet until olp is triggered. the internal aocp circuit is shown in figure 22. when the gate turn-on signal is applied to the power sensefet, the aocp block is enabled and monitors the current through the sensing-resistor. the voltage across the resistor is compared with a preset aocp level. if the sensing resistor voltage is greater than the aocp level, the set signal is applied to the s - r latch, resulting in the shutdown of the smps. figure 22. abnormal over-current protection
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 12 FSL117MRIN ? green-mode fairchild power switch (fps?) 4.3. output-short protection (osp) : if the output is shorted, steep current with extremely high di/dt can flow through the sensefet during the minimum turn- on time. such a steep current creates high-voltage stress on the drain of the sensefet when turned off. to protect the device from this abnormal condition, osp is included. it is comprised of detecting v fb and sensefet turn-on time. when the v fb is higher than 2.0v and the sensefet turn-on time is lower than 1.0 s, the FSL117MRIN recognizes this condition as an abnormal error and shuts down pwm switching until v cc reaches v start again. an abnormal condition output short is shown in figure 23. figure 23. output-short protection 4.4 over-voltage protection (ovp): if the secondary-side feedback circuit malfunctions or a solder defect causes an open ing in the feedback path, the current through the opto-coupler transistor becomes almost zero. then v fb climbs up in a similar manner to the overload sit uation, forcing the preset maximum current to be supplied to the smps until the overload protection is triggered. because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the overload protection is triggered, resulting in the breakdown of the devices in the secondary side. to prevent this situation, an ovp circuit is employed. in general, the v cc is proportional to the output voltage and the FSL117MRIN uses v cc instead of directly monitoring the output voltage. if v cc exceeds 24.5v, an ovp circuit is triggered, resulting in the termination of the switching operati on. to avoid undesired activation of ovp during normal operation, v cc should be designed to be below 24.5v. 4.5 thermal shutdown (tsd) : the sensefet and the control ic on a die in one package makes it easier for the control ic to detec t the temperature of the sensefet. if the temperature exceeds ~140 ? c, the thermal shutdown is tr iggered and stops operation. the FSL117MRIN operates in auto-restart mode until the temperature decreases to around 75 ? c, when normal operation resumes. 4.6 line over-voltage protection (lovp) : if the line input voltage is increased until unwanted level, high line input voltage brings high-voltage stress on the entire system. to protect from this abnormal condition, lovp is include d. it is comprised of detecting v in using divided resistors. when v in is higher than 1.95v, this condition is recognized as an abnormal error and pwm switching shuts down until v in decreases to around 1.89v (60mv hysteresis). figure 24. line over-voltage protection 5. soft burst mode : to minimize power dissipation in standby mode, the fsl117mri n enters burst mode. as the load decreases, the feedback voltage decreases. the device automatically enters burst mode when the feedback voltage drops below v burl (300mv), as shown in figure 25. at this point, switching stops and the outpu t voltages start to drop at a rate dependent on standb y current load. this causes the feedback voltage to rise. once it passes v burh (450mv), switching resumes. feedback voltage then falls and the process repeats. burst mode alternately enables and disables switching of the sensefet, reducing switching loss in standby mode. figure 25. burst-mode operation
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 13 FSL117MRIN ? green-mode fairchild power switch (fps?) 6. random frequency fluctuation (rff) : fluctuating switching frequency of an smps can reduce emi by spreading the energy over a wide frequency range. the amount of emi reduction is directly related to the switching frequency variation, which is limited internally. the switching frequency is determined randomly by external feedback voltage and an internal free-running oscillator at every switching instant. this random frequency fluctuation scatters the emi noise around typical switching frequency (67khz) effectively and can reduce the cost of the input filter in cluded to meet the emi requirements (e.g. en55022). figure 26. random frequency fluctuation
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 14 FSL117MRIN ? green-mode fairchild power switch (fps?) physical dimensions figure 27. 8-lead, dual inline package, 8dip. package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 5.08 max 0.33 min 2.54 7.62 0.56 0.355 1.65 1.27 3.683 3.20 3.60 3.00 6.67 6.096 9.83 9.00 7.62 9.957 7.87 0.356 0.20 notes: unless otherwise specified a) this package conforms to jedec ms-001 variation ba b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. d) dimensions and toleranc es per asme y14.5m-1994 8.255 7.61 e) drawing filename and revsion: mkt-n08frev2. (0.56)
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fsl117mrn ? rev.1.0.0 15 FSL117MRIN ? green-mode fairchild power switch (fps?)

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