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1/23 STLC5445 october 2002 n battery voltage up to 120v n supplies power for up to four digital telephone lines n programmable current limiting n longitudinal current cancellation n etsi etr80 compliant n output current up to 140 ma n status condition detection for each line n automatic thermal protection n auto power on sequence n output stage optimized for minimal output overvoltage protection n two external relay drivers per line n parallel or mpi control interface n hi-quad package 64 pin description the quad line feed controller provides a power source for up to four u line interfaces. the power source to the device is a local battery or a cen- tralized regulated power supply. each powered line is individually controlled and monitored by the device interface. a mpi or a simple parallel interface can be selected by a pin strap. each line can be individually powered and monitored: therefore overload and faults can easily be detected and localized even in a large system. the status con- ditions detected by the device are: current overload, thermal overload, open loop. if activated (by means of a dedicated pin strap), a self generated power on sequence avoids the thermal over stress when a simultaneous power on has been requested for more than one channel. the current limiting value can globally be programmed for the four channels by means of an external resistor. the device has two in- tegrated relay drivers per line to drive the test relays of the isdn system. hiquad-64 ordering number: STLC5445 quad line feed controller
STLC5445 2/23 block diagram relay driver 3b relay driver 3a relay driver 2b relay driver 2a relay driver 1b v cc wa0 codc0 wb0 wbp0 channel 3 channel 2 channel 1 v bat on / off & line current control old cod channel 0 cod & old generation logic interface ilim psc pbit ckilc resetn intn ale es0 (a0) es1 (csn) es2 (rdn) es3 (wrn) nack0 (d0) nack1 (d1) nack2 (d2) nack3 (d3) reference & biasing generation thermal monitoring 110c 130c 160c vo l t a g e and current biasing relay driver 1a relay driver 0b relay driver 0a erel0b rel0a rel0b rel1a rel1b rel2a rel2b rel3a rel3b erel0a erel1a erel1b erel2a erel2b erel3a erel3b vcc bgnd dgnd rgnd vbat v bat driving & output clamping i / o connections on channels 1, 2 and 3 are similar to those shown for channel 0 but have been omitted for clarity reasons. limiting current reference
3/23 STLC5445 pin connection (top view) pin function n pin name description 1 codc0 pin for connection of the external capacitor (100nf/6.3v) to gnd for cod signal filtering on channel 0. 2 codc1 pin for connection of the external capacitor (100nf/6.3v) to gnd for cod signal filtering on channel 1 4 ckilc external clock input pin for the internal power on sequencer 5 nack0(d0) logic pin: with psc = 0, line 0 status information output with psc = 1, line 0 i/o tristate data bus 6 nack1(d1) logic pin: with psc = 0, line 1 status information output with psc = 1, line 1 i/o tristate data bus 7 rel0a output of the 0a relay driver 8 *erel0a logic input pin: relay 0a output drivers on/off (high = on) 9 *erel0b logic input pin: relay 0b output drivers on/off (high = on) 10 rel0b output of the 0b relay driver 11 rel1a output of the 1a relay driver 1 2 3 5 6 4 7 8 9 10 27 11 28 29 30 31 32 59 58 57 56 55 54 53 47 46 45 43 42 44 52 51 50 48 49 nack1(d1) nack0(d0) ck_ilc codc1 codc0 rgnd rel1a rel0b *erel0b rel0a *erel0a vbat vbat wb2 wbp2 dgnd wa2 bgnd vbat vbat wb3 wbp3 ilim n.c. wa3 nack2(d2) rel3b *erel3b rel3a rel2b *erel3a n.c. bgnd nack3(d3) *reset d99tl437 26 60 wb0 61 wbp0 62 rgnd 63 wa0 64 bgnd wa1 n.c. v cc wbp1 wb1 21 22 23 24 25 41 40 38 37 39 *erel2b *erel2a *es2(rd) *es1(cs) *es3(wr) 12 13 14 15 16 pbit ale rel1b *erel1a *erel1b 36 34 33 35 *es0(a0) codc3 codc2 rgnd 17 18 19 20 n.c. bgnd intn psc rel2a *internal pull down to ground
STLC5445 4/23 12 *erel1a logic input pin: relay 1a output drivers on/off (high = on) 13 *erel1b logic input pin: relay 1b output drivers on/off (high = on) 14 rel1b output of the 1b relay driver 15 ale logic input pin: with psc = 0, dont care with psc = 1, address latch enable (active high) 16 pbit power on sequencer enable: pbit = 0: power on sequencer on pbit = 1: power on sequencer off 17 psc parallel or mpi mode input selection pin: 0 = parallel interface; 1 = mpi interface 18 intn logic output pin; open drain: with psc = 0 high impedance with psc = 1 interrupt (active low) 21 wa1 output feeders switch side of line 1; negative respect to wb1 23 vcc positive supply voltage. it is referred to dgnd 24 wbp1 internal protection diodes for line 1 25 wb1 output feeders resistive side of line 1; positive respect to wa1 28 wb2 output feeders resistive side of line 2; positive respect to wa2 29 wbp2 internal protection diodes for line 2 30 dgnd digital ground 31 wa2 output feeders switch side of line 2; negative respect to wb2 33 codc2 pin for connection of the external capacitor (100nf/6.3v) to gnd for cod signal filtering on channel 2 34 codc3 pin for connection of the external capacitor (100nf/6.3v) to gnd for cod signal filtering on channel 3 36 *es0(a0) logic input pin: with psc = 0, line 0 on/off request (high=on) with psc = 1, address bit for r/w operations 37 *es1(csn) logic input pin: with psc = 0, line 1 on/off request (high=on) with psc = 1, chip select (active low) 38 *es2(rdn) logic input pin: with psc = 0, line 2 on/off request (high=on) with psc = 1, read command (active low) 39 *es3(wrn) logic input pin: with psc = 0, line 3 on/off request (high=on) with psc = 1, write command (active low) 40 rel2a output of the 2a relay driver 41 *erel2a logic input pin: relay 2a output drivers on/off (high = on) 42 *erl2b logic input pin: relay 2b output drivers on/off (high = on) 43 rel2b output of the 2b relay driver 44 rel3a output of the 3a relay driver n pin name description pin function (continued)
5/23 STLC5445 * internal pull down to ground 45 *erel3a logic input pin: relay 3a output drivers on/off (high = on) 46 *erl3b logic input pin: relay 3b output drivers on/off (high = on) 47 rel3b output of the 3b relay driver 48 nack2 (d2) logic pin: with psc = 0, line 2 status information output with psc = 1, line 2 i/o tristate data bus 49 nack3 (d3) logic pin: with psc = 0 line 3 status information output with psc = 1 line 3 i/o tristate data bus 50 *resetn logic input pin: reset (active low) 53 wa3 output feeders switch side of line 3; negative respect towb3 55 ilim current limit programming input 56 wbp3 internal protection diodes for line 3 57 wb3 output feeders resistive side of line 3; positive respect to wa3 60 wb0 output feeders resistive side of line 0; positive respect to wa0 61 wbp0 internal protection diodes for line 0 0 wa0 output feeders switch side of line 0; negative respect to wb0 26 27 58 59 vbat negative battery supply voltage. it is referred to bgnd 19 32 51 64 bgnd battery ground 3 35 62 rgnd relay ground n pin name description pin function (continued)
STLC5445 6/23 absolute maximum ratings recommended operating condition symbol parameter value unit v dd voltage from digital input to dgnd C 0.5 to vcc + 0.5 v v cd voltage from vcc to dgnd C 0.4 to +7 v v bb voltage from vbat to bgnd C 143 to + 0.4 v v bd voltage from bgnd to dgnd C 3 to +0.5 v i wbn ac current into the wbn outputs (wbpn not connected to gnd 250 ma peak i neg negative current injected in the wan outputs (-40 to +85c) 50 ma t stg storage temperature C 60 to 150 c symbol parameter test condition min. typ. max. unit v cc v cc supply voltage 4.75 5.25 v v bat v bat supply voltage C 120 C 38 v v bgnd bgnd/dgnd voltage C 3 0.5 v i limt (1) programmable range of the current limiting function 20 140 ma i relay relay driver current 70 ma t a normal ambient temperature normal range 070c t a extended ambient temperature extended range C 40 85 c i loop max operating loop current 140 ma r min external, short circuit resistive load from wan to wbn 55 w
7/23 STLC5445 electrical characteristcs unless otherwise specified the below listed parameters' values are referred to the following conditions: v bat = C115v, v cc = 5v, r lim = 53.6 kw, codcn rc series = 100nf 10% and 510 w 1%, normal temperature range [0c to 70c]. the presence of an asterisk mark (*) indicates that the marked parameter must remain within the specified tolerance in the extended temperature range [-40c to 85c]. symbol parameter test condition min. typ. max. unit i vcc v cc supply current all the switches on n o load 2.5 ma i vbat v bat supply current all the switches on n o load 1.5 1.8 ma i limt current limiting value with transversal line current only i long = 0 42.5 50 57.5 ma i limtl current limiting value with added longitudinal line current see fig.1 37.5 50 62.5 ma i lim% current limiting accuracy in the range 20 to 140 ma (1) i long = 0 15 % i hz leakage current of each wan output to ground with output driver disabled 50* m a r wa resistance from wan to v bat i wa = 30ma 3.15 5.5 7.85 w r wb resistance from wbn to bgnd i wb = 30ma 3.5 5.5 7.5 w d r out absolute value of the difference between r wan and its related r wbn i wa = i wb = =30ma 0.7 1(*) w t j110 110c thermal monitoring threshold 11 0 c t j130 130c thermal monitoring threshold 130 c t j160 160c thermal monitoring threshold 160 c t hyst thermal monitoring hysteresis 10 c lv out (2) longitudinal output component of the fckilc clock signal see fig. 2 C 60 dbv v rel33 relay drivers output voltage all the relay drivers activated at a load current of 33ma. (3) 0.5 v v rel70 relay drivers output voltage all the relay drivers activated at a load current of 70ma. (3) 1.2 v i rleak relay driver leakage current erln = low 100 m a
STLC5445 8/23 notes: 1. our characterizations show that in the range 15ma - 20ma the accuracy is 20% over the 0c - 70c temperature range. 2. the longitudinal component of the signal detected by the spectrum analyzer must have an rms voltage value, in any 4khz equiv- alent bandwidth, averaged in any 1 second period, not greater of the specified value (C60dbv) over the 100hz - 150khz range (for details see etsi etr80 and ansi 601). 3. all the output lines activated at a line current of 35ma; no current limitation condition. rth(j-a) 20c/w please note that, in order to assure the frequency stability of the output drivers, a 1 m f capacitor must always be connected between wan and wbn or, as shown in fig. 6, immediately after the resistive protection elements used in the actual application. the r lim value can be calculated starting from the value of the needed current limitation threshold i limt : switching timing figure 1. i soc open circuit detector threshold 1.5 3 4 ma oldh open loop detector hysteresis 0.6 1.6 ma symbol parameter test condition min. typ. max. unit t enp output drivers enable time parallel interface mode 20 m s t disp output drivers disable time parallel interface mode 500 m s f ckilc frequency of ckilc duty cycle 60% max pulse width 500ns min 8 200 khz symbol parameter test condition min. typ. max. unit r lim 2664 i limit --------------- = 1.3k w 1% 25 w 0.01% i limtl STLC5445 output driver (one of four) wan wbn 8.5v rms 16.6hz 30 w 0.01% 20 m f 1% 25 w 0.01% 30 w 0.01% 20 m f 1% electrical characteristics (continued)
9/23 STLC5445 figure 2. static characteristics unless otherwise specified the below listed parameters values are referred to the following conditions: v cc = 5v, nor- mal temperature range. symbol parameter test condition min. typ. max. unit v il input low voltage 0.8 v v ih input high voltage 2 v v ol output low voltage i o = 1ma 0.4 v v oh output high voltage (open drain with psc = 0) i o = C1 ma 2.4 v i lh input high current 0 10 m a i ll input low current -10 0 m a i oz output current in high impedance state -10 10 m a STLC5445 output driver (one of four) wan wbn 100 w 1% 3.9k w 1% 67.5 w 0.01% 10 m f 1% 150nf 10% spectrum analyzer 67.5 w 0.01% 10 m f 1%
STLC5445 10/23 switching characteristics microprocessor write / read timing (refers to figures 3 and 4). unless otherwise specified the below listed parameters values are referred to the following conditions: vcc=5v, normal temperature range. symbol parameter test condition min. typ. max. unit t rlrh rdn, csn pulse width 260 ns t rhrl rdn, recovery time t amb = C 40 to 0c and +70c to +85c 200 220 ns t rlda rdn, csn low to data available 260 ns t rhdz rdn or csn high to data z t amb = C 40 to 0c and +70c to +85c 130 160 ns t ahal ale pulse width 100 ns t adal address setup time 60 ns t adaz address hold time 50 ns t azrl address z to rdn low 0 ns t azwl address z to wrn low 0 ns t adda address stable to data available t amb = C 40 to 0c and +70c to +85c 360 390 ns t wlwh wrn or csn pulse width 200 ns t whwl write recovery time 200 ns t dawh data setup time 100 ns t whdz data hold time t amb = C 40 to 0c and +70c to +85c 20 40 ns t resn reset pulse with 200 ns
11/23 STLC5445 figure 3. microprocessor write timing notes: 1. if tclwl is negative twlwh is measured from cs_ rather than fromwr_. 2. if twhch is negative, twhwl, twlwh, tdawh and twhdz are measured from cs_ rather than fromwr_. the propagation delay from the writing of the t/i bit to the effect on the int pin is approximately 1ms for both mask and enabl e operations. figure 4. microprocessor read timing notes: 1. if tclrl is negative, trhrl, trlrh, tazrl, and trlda are measured from cs_ rather than rd_. 2. if trhch is negative, trhrl, trlrh and trhdz are measured from cs_ rather than rd_. when a read from the ler immediately follows a write to the ler a minimum of 1ms is required between these operations t ahal t adal t adaz t clrl (note 1) t rhch (note 2) t azrl t rlrh t rhrl t rlda t rhdz read data data rd cs a o ale d94tl108a t adda t ahal t adal t adaz t clwl (note 1) t whch (note 2) t wlwh t whwl t dawh t whdz write data data wr cs a o ale d94tl109a int (note 3) t azwl
STLC5445 12/23 figure 5. typical application circuit external component list coponents description value c1, c2, c3, c4 & c5 power supply filter capacitance 100nf c6, c7, c8 & c9 signal filter capacitance 100nf r lin programmable limiting current resistor 53.6k w z 1 transil clamping protection 136v rgnd v cc c5 100nf c4 100nf c6 100nf c7 100nf c8 100nf c9 100nf 23 5,35,62 8 26 27 58 32 51 59 9 12 13 41 42 45 46 7 10 11 14 40 43 44 47 erel0a vbat vbat vbat vbat bgnd bgnd bgnd bgnd erel0b erel1a erel1b erel2a erel2b erel3a erel3b rel0a rel0b rel1a rel1b rel2a rel2b rel3a rel3b 20,22,52,54 53 31 21 63 57 28 25 60 56 29 24 61 49 n.c. codc0 codc1 codc2 codc3 34 33 2 1 ilim dgnd wbp_3 wb_0 wb_1 wb_2 wb_3 wa_0 wa_1 wa_2 wa_3 relays relays comand driver outputs digital control outputs clamping wbp_2 wbp_1 wbp_0 nack3(d3) 48 nack2(d2) 6 nack1(d1) 5 nack0(d0) 39 es3/wr 38 es2/rd 37 es1/cs 36 es0/a0 15 ale 16 pbit 17 psc 18 intn 4 ck_ilc 50 55 30 19 reset jp0 jp1 jp2 jp3 d99tl440 64 z1 2 x sm6t68a vbat c3 100nf c2 100nf c1 100nf
13/23 STLC5445 figure 6. typical protection diagram (only channel 0 and 1 shown) functional description wan (n=0-3) drivers (output pins). each wan output can sink up to 140ma. when the esn input is high and the activation request is approved by the internal control circuitry, the respective wan output is internally connected to vbat through a dmos switch and the low side sensing resistor. wbn (n=0-3) resistor to bgnd. each wbn output connects the wire b to ground through a 5w resistor used to perform the longitudinal balance and the high side current sensing function. wbpn (n=0-3) protection diodes connection (see the block diagram at page 3). each channel of the STLC5445 has two internal, back to back connected diodes, whose clamp- ing action can be used to protect the wbn outputs during lighting and power crossing events. the diodes' clamping action is normally disabled and can be activated by connecting the wbpn pin to bgnd. in this case however, if the line current exceeds 57.5ma the forward drop across the high side sensing resistor (and then across the diodes) reaches the diodes' conduction threshold, strongly degrading the current limiting action and the longitudinal balance. for line currents higher than 57.5ma external clamping elements must then be connected in place of the internal diodes or in series to them in order to increase the clamping voltage value. bgnd battery ground. dgnd digital ground. 1 m f 1 m f sm5908 2 x sm6t68a sm5908 16 w ptc 22 w 16 w ptc 22 w 16 w ptc 22 w 16 w ptc 22 w tip ring tip ring w bp1 w b1 w a1 w bat w bat b gnd w bp0 w b0 w a0 w bat b gnd channel's 1 output driver's stage channel's 0 output driver's stage d02tl549 note: the 1 m f capacitors are required for output driver's stability
STLC5445 14/23 rgnd ground connection of the relay drivers. ckilc logic input. external clock input for the power on sequencer embedded in the logic interface (see the block diagram at page 3). the power on sequencer controls (if activated) the power on se- quence of the lines. this will limit the chip's temperature increase that occurs, at channels switch on, due to the charging current of the capacitances used by the external isdn circuitry. if used, the power on sequencer is the only block of the circuit that needs an external clock sig- nal. esn (n=0-3) logic inputs. these pins have double names (see the block diagram at page 3) because they perform a dou- ble function: one in parallel mode ( psc = 0 ), and another in mpi mode ( psc = 1). in parallel mode esn acts as an activation or deactivation request for the respective line driver: esn = 0: line driver deactivation request. esn = 1: line driver activation request. in mpi mode the pins perform the following functions: a0: selects the source and destination locations for read and write operations on the data bus. a0 must be valid on the falling edge of ale or during rdn and wrn if ale is tied high. data transfer occurs over the d0-d3 lines. csn: this pin acts as a chip select. it must be low to enable the read or write opera- tions of the device. rdn: read command. the active low read signal is conditioned by csn and trans- fers internal information to the data bus. if a0 is a logical 0, the logic levels of the i ndirect a ddress r egister ( iar ) and of the thermal shutdown status bit will be transferred to d3-d0. if a0 is a logical 1, the data addressed by the iar will be transferred to d3-d0. wrn: write command. the active low write signal is conditioned by csn and trans- fers information from the data bus to one of the two internal registers selectable by a0: if a0 is a logical 1, d3-d0 is written into the l ine e nable r egister ( ler ); if a0 is a logical 0, d2-d0 are written into the i ndirect a ddress r egister ( iar ) and d3 is written as bit 3 and manages the generation of the interrupt signal for the external microprocessor. ler and iar are the only two writable registers in the device. resetn reset pin. it initializes the power on sequencer, the tor register and, in the mpi interface, the registers and the intn (interrupt output pin). when applied it leaves all the line drivers switched off. it has no effect in parallel interface mode if the power on sequencer is not used. when the supply voltages are applied to the circuit, an equivalent resetn pulse (power on reset) is automatically, internally generated. ale a ddress l atch e nable. ale is a logic input pin. it is used to strobe the address bit applied at the a0 pin, into the address latch. the address is latched on the high to low transition of ale. while ale is high the address latch is transparent. for a non multiplexed microprocessor bus, ale must be tied high. ilim the current limiting programming input, ilim, is used to program the current limit of the four drivers by means of an external resistor connected between this pin and dgnd. the voltage at ilim pin is a replica of the internal bandgap voltage (1.236v). when a line driver is in current limitation, its output current is 2155 times higher than the current flowing in the external current limiting programming resistor. intn the intn (interrupt) open drain type output can only be used in mpi interface mode. intn can be used to alerts an external microprocessor when a current overload condition occurs. it is not
15/23 STLC5445 latched and is active (low level) when at least one of the codn status detector bits is active (high level). when the four codn status detector bits are low, intn goes inactive (high). intn will also go inactive if (due to thermal overload) the qlfc automatically disables the output driv- er of the channel that caused the interrupt, or if the external microprocessor disables that line via the line enable register (ler). the interrupt function can be disabled (intn remains per- manently high) via the indirect address register (iar) or a low level on the resetn pin. nackn (n=0-3)logic i/o. these pins have double names (see the block diagram at page 3) because they perform a dou- ble function: one in parallel mode ( psc = 0 ), and another in mpi mode ( psc = 1). in parallel mode each nackn acts as an open drain output and gives the channel's status in- formation. the nackn bit goes in high impedance state (bit = 1 if a nackn pull up is provided) when at least one of these conditions is verified: the current on the relative line reaches the current limit programmed by the user. the chip's temperature reach the thermal alarm threshold. the line driver is in the power on phase. when the esn input is set low, the corresponding nackn is set to zero. in mpi mode the four pins become d3 - d0 and act as a bidirectional data bus with three state capability. the four bidirectional data bus lines are used to exchange information with an exter- nal microprocessor. d0 is the least significant bit and d3 is the most significant bit. an high lev- el on the data bus corresponds to a logical 1. when the chip select bit (csn) is low, these lines act as inputs when wrn is low and as outputs when rdn is low. when csn is high the d3 - d0 pins are in a high impedance state. psc logic input. this pin is used to select one of the two available logic interfaces. psc = 0: parallel mode. psc = 1: mpi mode. erln (n=0a-3b) logic inputs. each erln pin controls directly the respective relay driver's dmos: erln = 0 : switch off the relay driver. erln = 1 : switch on the relay driver. rln (n=0a-3b) relay drivers' output. each of the eight rln pins is connected to the drain of an internal dmos switch (see the block diagram at page 3) which acts as a driver for an external relay to be supplied from vcc. the relay drivers' current flows to ground through the rgnd pins. each output can sink up to 70 ma. an internal clamping circuit is provided, so no external kickback diodes are required. codcn (n=0-3) when a line over current condition exists, the output driver of the overloaded channel instanta- neously limits the line current at the value programmed by means of the external rlim resistor. in this condition the c urrent o verload d etector bit (cod) switches to a high logic level. when operating in mpi mode this bit can, for each of the four channels, be red by the external microprocessor in order to check which channel (if any) is overloaded. when in parallel mode each cod bit is internally or combined with two other bits in order to generate the nackn bit. since in the isdn application it can happens that the sum of the dc line current and the super- imposed signal peaks, easily exceeds the needed dc current limit, the cod generation circuitry has been arranged in such a way that the cod bit w ill be pus hed high only if the current over- load persists for at least 20ms: this eliminates any spurious high level cod / nack. the men-
STLC5445 16/23 tioned delaying function requires, for each of the four channels, one capacitor of 100nf has to be connected between each codcn and ground. operative description the device comprises three main blocks: the analog section , the logic section and the relay driver section . the analog section feeds the four lines and detects their status. the logic section allows to exchange information and commands between the qlfc and the external digital system. the relay driver section is completely independent: each relay command input is related to its own driver with- out any conditioning. analog section (see the block diagram at page 3) the analog section comprises the channel 0-channel 3 block, the reference & biasing generation block and the thermal monitoring block. as shown in the channel's card of the block diagram, the wbn and wan pins to which the line is connected are respectively routed to the battery ground and to the vbat line: wbn goes to bgnd through the upper side sens- ing resistor; wan goes to vbat through a power dmos and the lower side sensing resistor. the on/off con- trol for the power dmos comes from the outside world through the logic interface block. the implemented topology for the circuit used to cancel the longitudinal current effect is a dc coupled topology: it doesn't need external capacitors and its frequency band starts from dc. the qlfc has a double protection provided by its current limiting and thermal monitoring capabilities . the current limit threshold (ilimt) of the four channels is hardware programmable by means of a single, exter- nal resistor (rlim): . the protection implemented by the thermal monitoring is based on a three levels control system: a first temperature threshold controls the power on sequencer (see the logic section for a de- tailed description of its behaviour). when activated (pbit pin low), the power on sequencer manages the channels' activation requests received through the parallel (psc pin low) or the mpi (psc pin high) interface. the incoming channels' activation requests are stored in the power on sequencer and then satisfied, one at a time, only when the previously activated chan- nel leaves the current limiting condition that normally occurs at power on, due to the capacitive element that is part of the isdn load. however when the chip's internal temperature reaches 110c, only the already stored activation requests will be satisfied; the new, eventually incom- ing ones, will be rejected and will be processed when the internal temperature decreases down to 100c. a second temperature threshold is set at 130c. when this value is reached the channels that are in current limiting condition are switched off and their reactivation w ill only be possible when the chip's internal temperature has decreased down to 120c or, if the power on sequencer is activated, down to 100c. the third temperature threshold is set at 160c. when this temperature is reached the activated channels will all be switched off and their reactivation will only be possible when the chip's in- ternal temperature has decreased down to 150c. the user must however take into account that if (like in isdn application) the load seen by the channel has a high capacitive component, at channel's turn on a current limiting condition w ill always occur and the eventually reactivated channels w ill almost instant aneously be switched off by the 130c monitoring circuit, if the chip's internal temperature is still higher than 120c. more over (as explained at the previous point) if the power on sequencer is activated it w ill not be possible to switch on any c hannel until the chip has cooled down to 100c. i limit 1.236 2155 r lim -------------------------------- =
17/23 STLC5445 each of the four channels generates two status detector bits (see the block diagram at page 3): the cod bit ( c urrent o verload d etector) and the old bit ( o pen l oop d etector). the functions of the two bits are the follow- ing: the cod bit goes in a high logic state when its channel is in current limiting condition. since in the isdn application it can happens that the sum of the dc line current and the superimposed signal peaks, easily exceeds the needed dc current limit, the cod generation circuitry has been arranged in such a way that the cod bit w ill be pus hed high only if the current overload persists for at least 20ms: this eliminates any spurious high level cod. the mentioned delaying function requires, for each of the four channels, one capacitor of 100nf has to be connected between each codcn and ground. the old bit goes in a high state logic when the current that the channel supplies to the line falls below a typical value of 3ma, indicating a probable open line condition. as explained in the following pages, when operating in mpi mode the cod and old bits can, for each of the four channels, be red by an external microprocessor in order to check which channel (if any) is over or under loaded. when in parallel mode a single status bit (the nackn bit) is provided for each channel and is directly available on a dedicated pin. the nackn bit is internally generated by or combining the cod bit with two other bits (see the logic section for a more detailed explanation). logic section the logic section comprises the parallel interface , the mpi interface and the power on sequencer . in the block diagram shown at page 3 the three functions have been condensed in a single entity: the logic interface block. for each of the four channels, both types of the two provided interfaces use the cod, old and tor ( t hermal o verload r egister) status detector bits: the cod ( c urrent o verload d etector) bit is in a high logic state when its channel is in current limiting condition since at least 20ms. the old ( o pen l oop d etector) bit is in a high logic state when the current that the channel supplies to the line falls below a typical value of 3ma (isoc spec's parameter), indicating a pos- sible open line condition. each of the four output line drivers can be switched on, only if their corresponding tor bit is high. the tor bits are automatically set high by the internal power on reset when the chip is initially connected to its power supplies but can, however, also be globally set high by applying a reset pulse to the resetn pin. alternatively the tor bits that are latched in a low state can individ- ually be set high by applying to the selected interface the switch off command relative to their channel. the tor bits will go in a low state (determining the shut off of their relative c hannel's driver) in two cases: the activated channel is in current limiting condition and the chip's temperature reaches 130c. in this case the tor will be latched in low state. the chip's temperature reaches 160c: in this case the tor bits will all be set low but only the tor of the activated channels will be latched. power on sequencer when activated (pbit pin low), the power on sequencer manages the channels' activation requests received through the parallel (psc pin low) or the mpi (psc pin high) interface. the incoming channels' activation re- quests are stored in the power on sequencer and then satisfied, one at a time, only when the previously acti- vated channel exit the current limiting condition that normally occurs at power on, due to the capacitive element that is part of the isdn load. it must be noted that once a channel exits from the channel's turn on current limiting phase, the fact that it can for example because of a new line overload fall again in a current limiting condition
STLC5445 18/23 has no influence in the activation sequence of the next channels. the stored activation requests are satisfied starting from the lower index of the actually stored requests: if (for example) while channel 2 is in the activation phase, additional power on requests arrive for (in the order) channels 1, 3 and 0, when the channel's 2 activation phase w ill be concl uded the stored activation requests will be satisfied in the order 0, 1 and 3. it must be noted that the channels' deactivation requests are not conditioned by the power on sequencer. figure 7. power on sequence example notes: darn are the line d rivers' a ctivation r equest bits sent to the power on sequencer. they are internally generated starting from the activation requests coming from the outside world through the selected interface (parallel or mpi). pofn are the p ower o n f lags. each pofn goes high with its relative darn bit and returns to a low state when the current limiting condition ends: a pof high state indicates that the relative channel is in the power on phase. the figure 6 shows, for three of the four available channels, a typical power on sequence example. the codn pulse duration represents the time needed to charge the capacitive element that is part of the isdn load, with part of the constant current that each line driver provides with the actually programmed current limiting value. it must be realized that if (for example) has been required the activation of the lines 0, 2 and 3 but line 2 is over- loaded and cannot leave the current limiting condition, the activation sequence w ill remain blocked at the line 2 activation step. in this case the external software has to identify and shut off the overloaded line in order to allow the activation of the line 3. the previously mentioned resetn pin will also influence the power on sequencer: when resetn is pushed low the power on sequencer is reset, switching off the actually activated drivers. the power on sequencer is the only block of the circuit that needs an external clock signal to be applied at the ckilc pin. the clock frequency is not critical and has a nominal value of 8khz. when pbit=1 the power on sequencer is disabled and the incoming channels' activation requests will instan- taneously be satisfied. in this case the user as to take into account the actual operative condition (vbat, the programmed current limiting value, the load applied to the lines, the ambient temperature) and implement his own power on sequence in order to limit the chip's temperature increase induced by the channels' switch on transients. dar0 cod0 pof0 dar1 cod1 pof1 dar2 cod2 pof2
19/23 STLC5445 parallel interface mode in parallel interface mode (psc pin low), for each of the four output drivers a dedicated activation pin is pro- vided (es0-es3): each driver will unconditionally be switched off when its esn is pushed low. if the power on sequencer is not used, each driver w ill be switc hed on (under the supervision of the pre- viously described thermal monitoring block) when its esn is pushed high. if the power on sequencer is activated the drivers' activation requests coming from the esn inputs will (under the supervision of the previously described thermal monitoring block) be processed by the pow- er on sequencer block (see the previous power on sequencer's description). in parallel interface mode a single status bit is provided for each of the four channels at the open drain nack0 - nack3 output pins. the nackn bit is generated by or combining the three previously described status de- tector bits: codn, pofn and the complemented tor. this means that each nackn bit goes in high impedance state (bit=1 if a nackn pull up is externally provided) when at least one of these conditions is verified: the current on the relative line reaches the current limit programmed by the user (the nackn high state in this case will not be latched). the chip's temperature reaches 130c and the channel is in current limiting condition (the nackn high state will in this case be latched). the chip's temperature reaches 160c (in this case all the nackn will go in high state, but only the nackn of the activated channels will be latched). the line driver is in the power on phase (in this case the nackn w ill remain in high state only for the time during which its channel is in current limiting condition). when the esn input is set low, the corresponding nackn is always set to zero. in parallel interface mode the output pin intn and the input pin ale are not used (ale must in this case be tied high or low). mpi interface mode in mpi mode (psc pin high), the ale and intn pins become active and the pins nack0-nack3 and es0-es3 have a function that is completely different from that performed in parallel mode: the four nack0-nack3 pins become d0 -d3 and act as a bidirectional data bus with three state capa- bility. the four es0-es3 pins become respectively a0, csn, rdn and wrn. in mpi mode the above mentioned four bits data bus and three internal four bits registers, ler ( l ine e nable r egister), lec ( l ine e nable c ontrol) and iar ( i ndirect a ddress r egister) are used to perform the following op- erations: channels' output drivers switch on and switch off. enabling/disabling of the intn (interrupt) signal generation. status detector bits reading. t bit reading (this bit is high only when the internal chip's temperature exceeds 160c). the read/write operations on the data bus can only be performed when the csn (chip select) pin is low since when csn is high the data bus is inactive (high impedance state). the active low rdn and wrn signals are used to perform the read and write operations on the registers se- lected by the logic level applied at the a0 pin: a0=0 selects: the iar register if a write operation is performed (status detector bits type selection and enabling/disabling of the intn signal generation via the i bit). the reading of the bits actually written in the iar register if a read operation is performed. a0=1 selects: the ler register if a write operation is performed (switch on and switch off requests pro- gramming for the output drivers).
STLC5445 20/23 the status detector bits reading if a read operation is performed. a0 must be valid on the falling edge of the signal applied at the ale (address latch enable) pin or during the read and write operations if ale is tied high. note: a delay of at least 1ms is required between a ler writing and the next ler reading. subsequent ler reading operations do not have this constraint. the line output drivers' switch on or switch off requests are implemented by first selecting the ler register and then by writing in its d0-d3 bits a 1 (turn on request) or a 0 (turn off request). d0 controls channel 0, d1 channel 1 and so on. if the requests are accepted by the thermal monitoring block and (if activated) by the power on sequencer, the bits stored in the ler register are copied in the lec register whose status (1 = turn on; 0 = turn off) directly controls the output drivers' on/off condition. for each of the four channels, in mpi mode the following six status detector bits are available: the cod, old and tor bits whose function has already been described at the beginning of the logic section paragraph. the ler and the lec bits. the pof ( p ower o n s equencer) bit already described at the power on sequencer paragraph. the status detector bits reading is performed by first writing in the 2 - 0 bits of the iar register (via the d2-d0 bus lines) a three bits code used to select which of the six available status detector bits type has to be red. a0 must then to be set at 1 and the reading cycle has to be performed. the status detector bits' selection codes are listed in the following table. if (for example) a 010 code has been written in the iar, the output on the d0 - d3 lines at the end of the reading cycle will be the cod0 - cod3 bits. please, note that since the red data are not latched (apart from the tor status detector bits of the channels whose output drivers are switched on), the user should filter them (multiple samples) to ensure theirs integrity. as already explained the iar is a four bits register but only three bits (d2 - d0) are required to select one of the six available status detector bits types. the fourth iar bit (d3) is the i bit and is used to enable (1) or disable (0) the generation of the interrupt signal intn that, via the intn pin, can alerts an external microprocessor when a current overload condition occurs. intn is active (low level) when at least one of the codn status detector bits is active (high level). when the four codn status detector bits are low, intn goes inactive (high): this clearly means that intn will also go inactive if (due to thermal overload) the qlfc automatically disables the output driver of the channel that caused the interrupt or if the external microprocessor disables that line via the ler register. the interrupt function can also be disabled (intn remains permanently high) by applying a low level on the resetn pin. as previously explained, when a reading operation is performed while a0 = 0 the four bits actually written in the iar register can be read on the d3 - d0 bus lines. we already know that the d2 - d0 bits represent the status detector bits selection code. the d3 bit is the t bit: it is high only when the internal chip's temperature exceeds 160c. iar2 iar1 iar0 selected status detector bits type 000 pof 001 old 010 cod 0 1 1 lec 1 0 0 reserved 1 0 1 reserved 110 ler 1 1 1 tor
21/23 STLC5445 the iar bits' function has been summarized in the following table: the logic behaviour of the mpi's chip select and read/write operations has been summarized in the following table: bit symbol bit function 0 iar0 bit 0 of the status detector bits selection code 1 iar1 bit 1 of the status detector bits selection code 2 iar2 bit 2 of the status detector bits selection code 3 iar3: t (read) i (write) t bit (read only): logical 0 when chips temperature is below 160c logical 1 when chips temperature exceeds 160c i bit (write only): logical 0 to disable the interrupt generation logical 1 to enable the interrupt generation csn rdn wrn a0 performed operation 0100 write iar 0010read iar 0101 write ler 0011read the status detector bits types selected via the iar 1 x x x no access
STLC5445 22/23 hiquad-64 dim. mm inch min. typ. max. min. typ. max. a 3.15 0.124 a1 0 0.25 0 0.010 a2 2.50 2.90 0.10 0.114 a3 0 0.10 0 0.004 b 0.22 0.38 0.008 0.015 c 0.23 0.32 0.009 0.012 d 17.00 17.40 0.669 0.685 d1 (1) 13.90 14.00 14.10 0.547 0.551 0.555 d2 2.65 2.80 2.95 0.104 0.110 0.116 e 17.00 17.40 0.669 0.685 e1 (1) 13.90 14.00 14.10 0.547 0.551 0.555 e 0.65 0.025 e2 2.35 2.65 0.092 0.104 e3 9.30 9.50 9.70 0.366 0.374 0.382 e4 13.30 13.50 13.70 0.523 0.531 0.539 f 0.10 0.004 g 0.12 0.005 l 0.80 1.10 0.031 0.043 n10 (max.) s 0 (min.), 7?(max.) (1): "d1" and "e1" do not include mold flash or protusions - mold flash or protusions shall not exceed 0.15mm(0.006inch) per side c a a2 poqu64me e4 (slug lenght) 1 64 e1 gauge plane 0.35 l slug (bottom side) coplanarity g e b a n ? f ab m e3 21 33 53 b e2 d1 d e bottom view c a3 c seating plane s a1 e3 d2 (slug tail width) outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 23/23 STLC5445 esd - the stmicroelectronics internal quality standards set a target of 2kv that each pin of the device should withstand in a series of tests based on the human body model (mil-std 883 method 3015): with c = 100pf; r = 1500 w and performing 3 pulses for each pin versus v cc and gnd. device characterization showed that, in front of the stmicroelectronics internaly quality standards, all pins of STLC5445 withs tand at least 1500v. the above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in t he field. nonetheless they must be mentionned in connection with the applicability of the different sure 8 requirements to STLC5445.

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