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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. november 2009 doc id 16755 rev 1 1/67 67 SPEAR320 embedded mpu with arm926 core for factory automation and consumer applications features arm926ej-s 333 mhz core high-performance 8-channel dma dynamic power-saving features configurable peripheral functions multiplexed on 102 shared i/os memory: ? 32 kb rom and 8 kb internal sram ? lpddr-333/ddr2-666 external memory interface ? sdio/mmc card interface ? serial spi flash interface ? flexible static memo ry controller (fsmc) up to 16-bit data bus width, supporting nand flash ? external memory interface (emi) up to 16- bit data bus width, supporting nor flash and fpgas security ? c3 cryptographic accelerator connectivity ? 2 x usb 2.0 host ? 1 x usb 2.0 device ? 2 x fast ethernet mii/smii ports ? 2 x can interface ? 3 x spi ?2 x i 2 c ?1 x i 2 s ? 1 x fast irda interface ? 3 x uart interface ? 1 x standard parallel device port peripherals supported ? tft/stn lcd controller (resolution up to 1024 x 768 and up to 24 bpp) ? touchscreen support miscellaneous functions ? integrated real time clock, watchdog, and system controller ? 8-channel 10-bit adc, 1 msps ? 4 x pwm timers ? jpeg codec accelerator ? 6 x 16-bit general purpose timers with and programmable prescaler, 4 capture inputs ? up to 102 gpios with interrupt capability applications the SPEAR320 embedded mpu is configurable for a range industrial and consumer applications such as: programmable logic controllers factory automation printers table 1. device summary order code temp range, c package packing SPEAR320-2 -40 to 85 lfbga289 (15 x 15 mm, pitch 0.8 mm) tr ay lfbga289 (15 x 15 x 1.7 mm) www. s t.com
contents SPEAR320 2/67 doc id 16755 rev 1 contents description 5 1.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 cpu arm 926ej-s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 mobile ddr/ddr2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 external memory interface (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 multichannel dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 smii/mii ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 mii ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.10 can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.11 usb2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.12 usb2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.13 clcd controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.14 gpios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.15 parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.16 ssp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.17 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.18 i 2 s audio block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.19 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.19.1 uart0 with hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.19.2 uart1 and uart2 with software flow control . . . . . . . . . . . . . . . . . . . . 17 2.20 jpeg codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.21 cryptographic co-processor (c3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.22 8-channel adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.23 system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.23.1 power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.23.2 clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPEAR320 contents doc id 16755 rev 1 3/67 2.24 vectored interrupt controller (vic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.25 general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.26 pwm timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.27 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.28 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 re q uired external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 shared i/o pins (pl_gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.1 absolute minimum and maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2 maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4 overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.5 general purpose i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.6 lpddr and ddr2 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.6.1 ddr2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.7 clcd timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.7.1 clcd timing characteristics direct clock . . . . . . . . . . . . . . . . . . . . . . . . 44 5.7.2 clcd timing characteristics divided clock . . . . . . . . . . . . . . . . . . . . . . . 45 5.8 i 2 c timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.9 fsmc timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.9.1 8-bit nand flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.9.2 16-bit nand flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.10 ether mac 10/100/1000 mbps (gmac-univ) timing characteristics . . . . 52 5.10.1 gmii transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.10.2 mii transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.10.3 gmii-mii receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.10.4 mdio timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.11 smi - serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.12 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
contents SPEAR320 4/67 doc id 16755 rev 1 5.12.1 spi master mode timings (clock phase = 0) . . . . . . . . . . . . . . . . . . . . . 60 5.12.2 spi master mode timings (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . 61 5.13 uart (universal asynchronous receiver/transmitter) . . . . . . . . . . . . . . . 63 5.14 power up se q uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.15 power on reset (mreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SPEAR320 description doc id 16755 rev 1 5/67 1 description the SPEAR320 is a member of the spear fa mily of embedded mpus, optimized for industrial automation and consumer applications. it is based on the powerful arm926ej-s processor (up to 333 mhz), widely used in applications where high computation performance is re q uired. in addition, SPEAR320 has an mmu that allows virtual memo ry management -- making the system compliant with linux operating system. it also offers 16 kb of data cache, 16 kb of instruction cache, jtag and etm (embedded trace macrocell ? ) for debug operations. a full set of peripherals allows the system to be used in many applications, some typical applications being factory automation, printer and consumer applications. figure 1. functional block diagram

description SPEAR320 6/67 doc id 16755 rev 1 1.1 main features arm926ej-s 32-bit risc cpu, up to 333 mhz ? 16 kbytes of instruction cache, 16 kbytes of data cache ? 3 instruction sets: 32-bit for high performance, 16-bit (thumb) for efficient code density, byte java mode (jazelle?) for direct execution of java code. ? tightly coupled memory ? amba bus interface 32-kbyte on-chip bootrom 8-kbyte on-chip sram external dram memory interface: ? 8/16-bit (mobile ddr@166 mhz) ? 8/16-bit (ddr2@333 mhz) serial memory interface sdio interface supporting spi, sd1, sfd4 and sd8 modes 8/16-bits nand flash controller (fsmc) external memory interface (emi) for connecting nor flash or fpgas boot capability from nand flas h, serial/parallel nor flash boot and field upgrade capability from usb high performance 8-channel dma controller 2x ethernet mac 10/100 mbps with mii/smii phy interface two usb2.0 host (high- full-low speed) with in tegrated phy transceiver one usb2.0 device (high-full speed) with integrated phy transceiver 2x can 2.0 interfaces up to 102 gpios with interrupt capability up to 4 pwm outputs 3x spi master/slave (supporting motorola, texas instruments, national semiconductor protocols) up to 41.5 mbps standard parallel port (spp device implementation) i 2 s input-output for voice or modem interfaces 2x i 2 c master/slave interface (slow- fast-high speed, up to 1.2mb/s) 3x uart: uart1 with hardware flow control (up to 460.8 kbaud), uart2 and uart3 with software flow control (baud rate > 6 mbps) adc 10-bit, 1 msps 8 inputs/1-bit dac jpeg codec accelerator 1 clock/pixel color lcd interface (up to 1024x768, 24-bits clcd controller, tft and stn panels) touchscreen support c3 crypto accelerato r (des/3des/aes/sha1) advanced power saving features ? normal, slow, doze and sleep modes cpu clock with software-programmable fre q uency ? enhanced dynamic power-domain management ? clock gating functionality
SPEAR320 description doc id 16755 rev 1 7/67 ?low fre q uency operating mode ? automatic power saving controlled from application activity demands vectored interrupt controller system and peripheral controller ? 3 pairs of 16-bit general purpose timers with programmable prescaler ? rtc with separate power supply allowing battery connection ? watchdog timer ? miscellaneous registers array for embedded mpu configuration programmable pll for cpu and system clocks jtag ieee 1149.1 boundary scan etm functionality multiplexed on primary pins supply voltages ? 1.2 v core, 1.8 v/2.5 v ddr, 2.5 v plls and 3.3 v i/os operating temperature: - 40 to 85 c lfbga289 (15 x 15 mm, pitch 0.8 mm)
architecture overview SPEAR320 8/67 doc id 16755 rev 1 2 architecture overview the SPEAR320 internal architec ture is based on several s hared subsystem logic blocks interconnected through a multilayer interconnection matrix. the switch matrix structure allows different subsystem dataflow to be executed in parallel improving the core platform efficiency. high performance master agents are directly interconnected with the memory controller reducing the memory access latency. the overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted round- robin arbitration mechanism. figure 2. typical system architecture using SPEAR320 2.1 cpu arm 926ej-s the core of the SPEAR320 is an arm926ej reduced instruct ion set computer (risc) processor. it supports the 32-bit arm and 16-bit thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of java byte codes. the arm cpu and is clocked at a fre q uency up to 333 mhz. it has a 16-kbyte instruction cache, a 16-kbyte data cache, and features a memory management unit (mmu) which makes it fully compliant with linux and vxworks operating systems.

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SPEAR320 architecture overview doc id 16755 rev 1 9/67 it also includes an embedded trace module (etm medium+) for real-time cpu activity tracing and debugging. it supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode, with normal or half-rate clock. 2.2 embedded memory units 32 kbytes of bootrom 8 kbytes of sram 2.3 mobile ddr/ddr2 memory controller SPEAR320 integrates a high performance multi- channel memory contro ller able to support low power mobile ddr and ddr2 double data rate memory devices. the multi-port architecture ensures memory is shared efficiently among different high-bandwidth client modules. it has 6 internal ports. one of them is reserved for register access during the controller initialization while the other five are used to access the external memory. it also includes the physical layer (phy) and dlls for fine tuning the timing parameters to maximize the data valid windows at different fre q uencies. 2.4 serial memory interface SPEAR320 provides a serial memory interface (smi), acting as an ahb slave interface (32-, 16- or 8-bit) to spi-compatible off-chip memories. these serial memories can be used either as data storage or for code execution. main features: supports the following spi-comp atible flash and eeprom devices: ? stmicroelectronics m25pxxx, m45pxxx ? stmicroelectronics m95xxx, except m95040, m95020 and m95010 ?atmel at25fxx ?ymc y25fxx ? sst sst25lfxx acts always as a spi master and up to 2 spi slave memory devices are supported (with separate chip select signals), with up to 16 mb address space each smi clock signal (smiclk) is generated by smi (and input to all slaves) using a clock provided by the ahb bus smiclk can be up to 50 mhz in fast read mode (or 20 mhz in normal mode). it can be controlled by a programmable 7-bit prescaler allowing up to 127 different clock fre q uencies. 2.5 external memory interface (emi) the emi controller provide a simple external memory interface that can be used for example to connect to nor flash memory or fpga devices.
architecture overview SPEAR320 10/67 doc id 16755 rev 1 main features: emi bus master 16 and 8-bit transfers can access 4 different peripherals using cs#, one at a time. supports single asynchronous transfers. supports peripherals which use byte lane procedure 2.6 flexible static memory controller (fsmc) SPEAR320 provides a flexible static memory controller (fsmc) whic h interfaces the ahb bus to external parallel nand flash memories. provides an interface between ahb system bus and external nand flash memory devices. 8/16-bit wide data path fsmc performs only one access at a time and only one external device is accessed supports little-endian and big-endian memory architectures ahb burst transfer handling to reduce access time to external devices supplies an independent configuration for each memory bank programmable timings to support a wide range of devices ? programmable wait states (up to 31) ? programmable bus turnaround cycles (up to 15) ? programmable output enable and write enable delays (up to 15) independent chip select control for each memory bank shares the address bus and the data bus with all the external peripherals only chips selects are uni q ue for each peripheral external asynchronous wait control boot memory bank configurable at reset using external control pins 2.7 multichannel dma controller within its basic subs ystem, SPEAR320 provides an dma controller (dmac) able to service up to 8 independent dma channels for serial data transfers between single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and peripheral-to-peripheral). each dma channel can support a unidirectional transfer, with internal four-word fifo per channel. 2.8 smii/mii ethernet controller SPEAR320 features two ethernet macs, one suppor ting smii and one supporting smii and mii. each mac channel has dedicated tx/rx signals while synchronization and clock signals are common for phy connection.
SPEAR320 architecture overview doc id 16755 rev 1 11/67 the figure 3 shows the typical smii configuration (a generic example with four ports): figure 3. typical smii system each ethernet port provides the following features: compatible with ieee standard 802.3 10 and 100 mbit/s operation full and half duplex operation statistics counter registers for rmon/mib interrupt generation to signal receive and transmit completion automatic pad and crc generation on transmitted frames automatic discard of frames received with errors address checking logic supports up to four specific 48-bit addresses supports promiscuous mode where all valid received frames are copied to memory hash matching of unicast and multicast destination addresses external address matching of received frames physical layer management through mdio interface supports serial network interface operation half duplex flow control by forc ing collisions on incoming frames full duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause frames support for 802.1q vlan tagging with recognition of incoming vlan and priority tagged frames multiple buffers per receive and transmit frame wake on lan support jumbo frames of up to 10240 bytes supported configurable endianess for the dma interface (ahb master) 8 port mac quad phy quad phy clock 4 4 tx rx sync 4 4 tx rx sync 8 port mac quad phy quad phy clock 4 4 tx rx sync 4 4 tx rx sync 8 port mac quad phy quad phy clock 4 4 tx rx sync 4 4 4 4 tx rx sync 4 4 tx rx sync 4 4 4 4 tx rx sync
architecture overview SPEAR320 12/67 doc id 16755 rev 1 2.9 mii ethernet controller SPEAR320 provides an ethernet mac 10/100 universal (commo nly referred to as mac- univ), enabling to transmit and receive data over ethernet in compliance with the ieee 802.3-2002 standard. main features: supports the default media independent interface (mii) defined in the ieee 802.3 specifications. supports 10/100 mbps data transfer rates local fifo available (4 kbyte rx, 2 kbyte tx) supports both half-duplex and full-duplex operation. in half-duplex operation, csma/cd protocol is provided programmable frame length to support both standard and jumbo ethernet frames with size up to 16 kbytes 32/64/128-bit data transfer interface on system-side. a variety of flexible addresses filtering modes are supported a set of control and status registers (csrs) to control gmac core operation native dma with single-channel transmit and receive engines, providing 32/64/128-bit data transfers dma implements dual-buffer (ring) or linked-list (chained) descriptor chaining an ahb slave acting as programming interface to access all csrs, for both dma and gmac core subsystems an ahb master for data transfer to system memory 32-bit ahb master bus width, supporting 32, 64, and 128-bit wide data transactions it supports both big-endian and little-endian. 2.10 can controller SPEAR320 has two can controllers fo r interfacing can 2.0 networks. main features: supports can protocol version 2.0 part a and b bit rates up to 1 mbit/s 32 message objects(136 x 32 message ram) each message object has its own identifier mask maskable interrupt programmable loop-back mode for self-test operation disabled automatic retransmission mode for time triggered can applications
SPEAR320 architecture overview doc id 16755 rev 1 13/67 2.11 usb2 host controller SPEAR320 has two fully independent usb 2.0 ho sts. each consists of 5 major blocks: ehci capable of managing high-speed transfers (hs mode, 480 mbps) ohci that manages the full and the low speed transfers (12 and 1.5 mbps) local 2-kbyte fifo local dma integrated usb2 transceiver (phy) both hosts can manage an external power switch, providing a control line to enable or disable the power, and an input line to sense any over-current condition detected by the external switch. one host controller at time can perform high speed transfer. 2.12 usb2 device controller main features: supports the 480 mbps high-speed mode (hs) for usb 2.0, as well as the 12 mbps full-speed (fs) and the low-speed (ls modes) for usb 1.1 supports 16 physical endpoints, configurable as different logical endpoints integrated usb transceiver (phy) local 4 kbyte fifo shared among all the endpoints dma mode and slave-only mode are supported in dma mode, the udc supports descriptor-based memory structures in application memory in both modes, an ahb slave is provided by udc-ahb, acting as programming interface to access to memory-mapped control and status registers (csrs) an ahb master for data transfer to system memory is provided, supporting 8, 16, and 32-bit wide data transactions on the ahb bus a usb plug (upd) detects the connection of a cable.
architecture overview SPEAR320 14/67 doc id 16755 rev 1 2.13 clcd controller SPEAR320 has a color li q uid crystal display controller (c lcdc) that provides all the necessary control signals to interface directly to a variety of color and monochrome lcd panels. main features: resolution programmable up to 1024 x 768 16-bpp true-color non-palletized, for color stn and tft 24-bpp true-color non-palletized, for color tft supports single and dual panel mono super twisted nematic (stn) displays with 4 or 8- bit interfaces supports single and dual-panel color and monochrome stn displays supports thin film transistor (tft) color displays 15 gray-level mono, 3375 color stn, and 32 k color tft support 1, 2, or 4 bits per pixel (bpp) palletized displays for mono stn 1, 2, 4 or 8-bpp palletized color displays for color stn and tft programmable timing for different display panels 256 entry, 16-bit palette ram, arranged as a 128 x 32-bit ram physically frame, line and pixel clock signals ac bias signal for stn and data enable si gnal for tft panels patented gray scale algorithm supports little and big-endian 2.14 gpios a maximum of 102 gpios are available when part of the embedded or customizations ips are not needed (see "pin description" table). within its basic subs ystem, SPEAR320 provides a base general purpose input/output (gpio) block (basgpio). the base gpio block provides 6 programmable inputs or outputs. each input/output can be controlled in two distinct modes: software mode, through an apb interface. hardware mode, through a hardware control interface. main features of the base gpio block are: six individually programmable input/output pins (default to input at reset) an apb slave acting as control interface in "software mode" programmable interrupt generation capability on any number of pins. hardware control capability of gpio lines for differ ent system configurations. bit masking in both read and write operation through address lines. other gpio blocks are present in the reconfigurable array subsystem (ras).
SPEAR320 architecture overview doc id 16755 rev 1 15/67 2.15 parallel port main features: slave mode device interface for standard parallel port host supports unidirectional 8-bit data transfer from host to slave supports 9th bit for parity/data/command etc. maskable interrupts for data, device reset, auto line feed apb input clock fre q uency re q uired is 83 mhz for acknowledgement timings conforms to amba-apb specifications 2.16 ssp SPEAR320 provides one sync hronous serial port (ssp) block that offers a master or slave interface to enables synchronous serial communication with slave or master peripherals main features: master or slave operation. programmable clock bit rate and prescale. separate transmit and receive first-in, first-out memory buffers, 16-bits wide, 8 locations deep. programmable choice of interface operation: ? spi (motorola) ? microwire (national semiconductor) ? ti synchronous serial. programmable data frame size from 4 to 16-bits. independent masking of transmit fifo, receive fifo, and receive overrun interrupts. internal loopback test mode available. dma interface
architecture overview SPEAR320 16/67 doc id 16755 rev 1 2.17 i2c the SPEAR320 has 2 i2c interfaces; main features: compliance to the i 2 c bus specification (philips) supports three modes: ? standard (100 kbps) ? fast (400 kbps) ? high-speed (3.4 mbps) clock synchronization master and slave mode configuration possible multi-master mode (bus arbitration) 7-bit or 10-bit addressing 7-bit or 10-bit combined format transfers slave bulk transfer mode ignores cbus addresses (predessor to i2c that used to share the i2c bus) transmit and receive buffers interrupt or polled-mode operation handles bit and byte waiting at all bus speeds digital filter for the re ceived sda and scl lines handles component parameters for configurable software driver support supports apb data bus widths of 8, 16 and 32-bits. 2.18 i 2 s audio block the SPEAR320 has one i2s interface. main features: conversion of ahb protocol to i 2 s protocol. supports 2.0 audio outputs (master mode only) supports 32 (16l + 16r) and 64-bit (32l + 32r) of raw pcm data length 48 khz audio sampling rate mic/line-in recording (master/slave modes) the the i2s audio blocks can be used to prov ide "audio play" and "audio record" capability. the audio play function works in master mode only but audio record can be used in both master and slave modes. in master mode, it outputs clock and ws signals in addition to stereo data. in slave mode, the clock and the ws signal has to be provided externally. 2.19 uarts the SPEAR320 has 2 uarts featuring software flow control and 1 uart featuring hardware and/or software flow control.
SPEAR320 architecture overview doc id 16755 rev 1 17/67 2.19.1 uart0 with hardware flow control main features: separate 16 x 8 (16 locations deep x 8-bit wide) transmit and 16 x 12 receive fifos to reduce cpu interrupts speed up to 3 mbps hardware and/or software flow control 2.19.2 uart1 and uart2 with software flow control main features: separate 16 x 8 (16 location deep x 8-bit wide) transmit and 16x12 receive fifos to reduce cpu interrupts speed up to 5 mbps. 2.20 jpeg codec SPEAR320 provides a jpeg codec with header processing (jpgc), able to decode (or encode) image data co ntained in the SPEAR320 ram, from the jpeg (or bmp) format to the bmp (or jpeg) format. main features: compliance with the baseline jpeg standard (iso/iec 10918-1) single-clock per pixel encoding/decoding support for up to four channels of component color 8-bit/channel pixel depths programmable q uantization tables (up to four) programmable huffman tables (two ac and two dc) programmable minimum coded unit (mcu) configurable jpeg header processing support for restart marker insertion use of two dma channels and of two 8 x 32-bits fifo's (local to the jpeg) for efficient transferring and buffering of encoded/decoded data from/to the codec core. 2.21 cryptographic co-processor (c3) SPEAR320 has an embedd ed channel control coprocessor (c3). c3 is a high-performance instruction driven dma based co-processor. it executes instruction flows generated by the host processor. after it has been set-up by the host it runs in a completely autonomous way (dma data in, data processing, dma data out), until the completion of all the re q uested operations. c3 has been used to accelerate the processing of cryptographic, security and network security applications. it can be used for other types of data intensive applications as well.
architecture overview SPEAR320 18/67 doc id 16755 rev 1 hardware cryptographic co-processor features are listed below: supported cryptographic algorithms: ? advanced encryption sta ndard (aes) cipher in ecb, cbc, ctr modes. ? data encryption standard (des) cipher in ecb and cbc modes. ? sha-1, hmac-sha-1, md5, hmac-md5 digests. instruction driven dma based programmable engine. ahb master port for data access from/to system memory. ahb slave port for co-processor regi ster accesses and in itial engine-setup. the co-processor is fully autonomous (dma input reading, cryptographic operation execution, dma output writing) after being set up by the host processor. the co-processor executes programs written by the host in memory, it can execute an unlimited list of programs. the co-processor supports hardware chaining of cryptographic blocks for optimized execution of data-flow re q uiring multiple algorithms processing over the same set of data (for example encryption + hashing on the fly). 2.22 8-channel adc main features: successive approximatio n conversion method 10-bit resolution @1 msps hardware supporting up to 13.5 bits resolution at 8 ksps by oversampling and accumulation eight analog input (ain) channels, ranging from 0 to 2.5 v inl 1 lsb, dnl 1 lsb programmable conversion speed, (min. conversion time is 1 s) programmable averaging of results from 1 (no averaging) up to 128 programmable auto scan for all the eight channels. 2.23 system controller the system controller provides an interface for controllin g the operation of the overall system. main features: power saving system mode control crystal oscillator and pll control configuration of system response to interrupts reset status capture and soft reset generation watchdog and timer module clock enable
SPEAR320 architecture overview doc id 16755 rev 1 19/67 2.23.1 power saving system mode control using three mode control bits, the system controller switch th e SPEAR320 to any one of four different modes: doze, sleep, slow and normal. sleep mode : in this mode the system clocks, hclk and clk, are disabled and the system controller clock sclk is driven by a low speed oscillator (n ominally 32768 hz). when either a fiq or an irq interrupt is generated (through the vic) the system enters doze mode. additionally, the operating mode setting in the system control register automatically changes from sleep to doze. doze mode : in this mode the system clocks , hclk and clk, and the system controller clock sclk are driven by a lo w speed oscillator. t he system controller moves into sleep mode from doze mode on ly when none of th e mode control bits are set and the processor is in wait-for-interrupt state. if slow mode or normal mode is re q uired the system moves into the xtal co ntrol transition stat e to initialize the crystal oscillator. slow mode : during this mode, both the system clocks and the system controller clock are driven by the crystal oscillator. if normal mode is selected, the system goes into the "pll control" transition state. if neither the slow nor the normal mode control bits are set, the system goes into the "switch from xtal" transition state. normal mode : in normal mode, both the system clocks and the system controller clock are driven by the pll output. if the normal mode control bit is not set, then the system goes into the "switch from pll" transition state. 2.23.2 clock and reset system the clock system is a fully programmable bloc k that generates all the clocks necessary to the chip. the default operating clock fre q uencies are: clock @ 333 mhz for the cpu. clock @ 166 mhz for ahb bus and ahb peripherals. clock @ 83 mhz for, apb bus and apb peripherals. clock @ 333 mhz for ddr memory interface. the default values give the maximum allowed clock fre q uencies. the clock fre q uencies are fully programmable through dedicated registers. the clock system consists of 2 main parts: a multi clock generator bl ock and two internal plls. the multi clock generator block, takes a reference signal (which is usually delivered by the pll), generates all clocks for the ips of SPEAR320 accordi ng to dedicated programmable registers. each pll uses an oscillator input of 24 mhz to generate a clock signal at a fre q uency corresponding at the highest of the group. this is the reference signal used by the multi clock generator block to obtain all the other re q uested clocks for the group. its main feature is electromagnetic interfer ence reduction capability. the user can set up the pll in order to modulate the vco with a triangular wave. the resulting signal has a spectrum (and power) spread over a small programmable range of fre q uencies centered on f0 (the vco fre q uency), obtaining minimum electromagnetic emissions. this method replaces all the other traditional methods of emi reduction, such as
architecture overview SPEAR320 20/67 doc id 16755 rev 1 filtering, ferrite beads, chokes, adding power layers and ground planes to pcbs, metal shielding and so on. this gives the customer appreciable cost savings. in sleep mode the SPEAR320 runs with the pll disabled so the available fre q uency is 24 mhz or a sub-multiple (/2, /4, /8). 2.24 vectored interrupt controller (vic) the vic allows the os interrupt handler to q uickly dispatch interrupt service routines in response to peripheral interrupts. there are 32 interrupt lines and the vic uses a separate bit position for each interrupt source. software controls each re q uest line to generate software interrupts. 2.25 general purpose timers SPEAR320 provides 6 general purpose timers (gpts) acting as apb slaves. each gpt consists of 2 channels, each one made up of a programmable 16-bit counter and a dedicated 8-bit timer clock prescaler. the programmable 8-bit prescaler performs a clock division by 1 up to 256, and different input fre q uencies can be chosen through configuration registers (a fre q uency range from 3.96 hz to 48 mhz can be synthesized). two different modes of operation are available : auto-reload mode, an interrupt source is activated, the counter is automatically cleared and then it restarts incrementing. single-shot mode, an interrupt source is activated, the counter is stopped and the gpt is disabled. 2.26 pwm timers SPEAR320 provides 4 pwm timers. main features: prescaler to define the input clock fre q uency to each timer programmable duty cycle from 0% to 100% programmable pulse length apb slave interface for register programming 2.27 watchdog timer the arm watchdog module consists of a 32-bit down counter with a programmable timeout interval that has the capability to generate an interrupt and a reset signal on timing out. the watchdog module is intended to be used to apply a reset to a system in the event of a software failure.
SPEAR320 architecture overview doc id 16755 rev 1 21/67 2.28 rtc oscillator the rtc provides a 1-second resolution clock. this keeps time when the system is inactive and can be used to wake the system up when a programmed alarm time is reached. it has a clock trimming feature to compensate for the accuracy of the 32.768 khz crystal and a secured time update. main features: tme-of-day clock in 24 hour mode calendar alarm capability isolation mode, allowing rtc to work even if power is not supplied to the rest of the device.
pin description SPEAR320 22/67 doc id 16755 rev 1 3 pin description the following tables describe the pinout of the SPEAR320 listed by functional block. list of abbreviations: pu = pull up pd = pull down 3.1 required external components 1. ddr_comp_1v8: place an external 121 k resistor between ball p4 and ball r4 2. usb_tx_rtune: connect an external 43.2 k pull-down resistor to ball k5 3. digital_rext: place an external 121 k resistor between ball g4 and ball f4. 3.2 dedicated pins table 2. master clock, rtc, reset and 3.3 v comparator pin descriptions group signal name ball direction function pin type master clock mclk_xi p1 input 24 mhz (typical) crystal in oscillator 2.5 v capable mclk_xo p2 output 24 mhz (typical) crystal out rtc rtc_xi e2 input 32 khz crystal in oscillator 1v capable rtc_xo e1 output 32 khz crystal out reset mreset# m17 input main reset ttl schmitt trigger input buffer, 3.3 v tolerant, pu 3.3 v comp. digital_rext g4 output configuration analog, 3.3 v capable digital_gnd_r ex f4 power power power table 3. power supply pin description group signal name ball value digital ground gnd g6 g7 g8 g9 g10 g11 h6 h7 h8 h9 h10 h11 j6 j7 j8 j9 j10 j11 k6 k7 k8 k9 k10 k11 l6 l7 l8 l9 l10 m8 m9 m10 0 v analog ground agnd f2, g1, j2, l1, l3, l5, n2, n4, p3, r3, n12 0 v i/o v dd 3v3 f5 f6 f7 f10 f11 f12 g5 j12 k12 l12 m12 3.3 v
SPEAR320 pin description doc id 16755 rev 1 23/67 core v dd f8 f9 g12 h5 h12 j5 l11 m6 m7 m11 1.2 v usb host0 phy host0_v dd bc l2 2.5 v host0_v dd b3 k4 3.3 v usb host1 phy host1_v dd bc k3 2.5 v host1_v dd b3 j1 3.3 v usb device phy device_v dd bc n1 2.5 v device_v dd b3 n3 3.3 v host_v dd bs m3 1.2 v osci (master clock) mclk_v dd r1 1.2 v mclk_v dd 2v5 r2 2.5 v pll1 dith1_av dd g2 2.5 v pll2 dith2_av dd m4 2.5 v ddr i/o sstl_v dd e m5 n5 n6 n7 n8 n9 n10 n11 1.8 v adc adc_av dd n13 2.5 v osci rtc rtc_v dd f1 1.5 v table 3. power supply pin description group signal name ball value
pin description SPEAR320 24/67 doc id 16755 rev 1 table 4. debug pin descriptions group signal name ball direction function pin type debug test_0 k16 input test configuration ports. for functional mode, they have to be set to zero. ttl input buffer, 3.3 v tolerant, pd test_1 k15 test_2 k14 test_3 k13 test_4 j15 boot_sel j14 ntrst l16 input test reset input ttl schmitt trigger input buffer, 3.3 v tolerant, pu tdo l15 output test data output ttl output buffer, 3.3 v capable 4 ma tck l17 input test clock ttl schmitt trigger input buffer, 3.3 v tolerant, pu tdi l14 input test data input tms l13 input test mode select table 5. serial memory interface (smi) pin description group signal name ball direction function pin type smi smi_datain m13 input serial flash input data ttl input buffer 3.3 v tolerant, pu smi_dataout m14 output serial flash output data ttl output buffer 3.3 v capable 4 ma smi_clk n17 i/o serial flash clock smi_cs_0 m15 output serial flash chip select smi_cs_1 m16 table 6. usb pin descriptions group signal name ball direction function pin type usb dev dev_dp m1 i/o usb device d+ bidirectional analog buffer 5 v tolerant dev_dm m2 usb device d- dev_vbus g3 input usb device vbus ttl input buffer 3.3 v tolerant, pd host1_dp h1 i/o usb host1 d+ bidirectional analog buffer 5 v tolerant host1_dm h2 usb host1 d-
SPEAR320 pin description doc id 16755 rev 1 25/67 usb host host1_vbus h3 output usbhost1 vbus ttl output buffer 3.3 v capable, 4ma host1_ovrc j4 input usb host1 over-current ttl input buffer 3.3 v tolerant, pd host0_dp k1 i/o usb host0 d+ bidirectional analog buffer 5 v tolerant host0_dm k2 usb host0 d- host0_vbus j3 output usb host0 vbus ttl output buffer 3.3 v capable, 4ma host0_ovrc h4 input usb host0 over-current ttl input buffer 3.3 v tolerant, pd usb_txrtune k5 output reference resistor analog usb_analog_t est l4 output analog test output analog table 7. adc pin description group signal name ball direction function pin type adc ain_0 n16 input adc analog input channel analog buffer 2.5 v tolerant ain_1 n15 ain_2 p17 ain_3 p16 ain_4 p15 ain_5 r17 ain_6 r16 ain_7 r15 adc_vrefn n14 adc negative voltage reference adc_vrefp p14 adc positive voltage reference table 6. usb pin descriptions (continued) group signal name ball direction function pin type
pin description SPEAR320 26/67 doc id 16755 rev 1 table 8. ddr pin description group signal name ball direction function pin type ddr ddr_add_0 t2 output address line sstl_2/sstl_18 ddr_add_1 t1 ddr_add_2 u1 ddr_add_3 u2 ddr_add_4 u3 ddr_add_5 u4 ddr_add_6 u5 ddr_add_7 t5 ddr_add_8 r5 ddr_add_9 p5 ddr_add_10 p6 ddr_add_11 r6 ddr_add_12 t6 ddr_add_13 u6 ddr_add_14 r7 ddr_ba_0 p7 output bank select ddr_ba_1 p8 ddr_ba_2 r8 ddr_ras u8 output row add. strobe ddr_cas t8 output col. add. strobe ddr_we t7 output write enable ddr_clken u7 output clock enable ddr_clk_p t9 output differential clock differential sstl_2/sstl_18 ddr_clk_n u9
SPEAR320 pin description doc id 16755 rev 1 27/67 ddr ddr_cs_0 p9 output chip select sstl_2/sstl_18 ddr_cs_1 r9 ddr_odt_0 t3 i/o on-die termination enable lines ddr_odt_1 t4 ddr_data_0 p11 i/o data lines (lower byte) ddr_data_1 r11 ddr_data_2 t11 ddr_data_3 u11 ddr_data_4 t12 ddr_data_5 r12 ddr_data_6 p12 ddr_data_7 p13 ddr_dqs_0 u10 output lower data strobe differential sstl_2/sstl_18 ddr_ndqs_0 t10 ddr_dm_0 u12 output lower data mask sstl_2/sstl_18 ddr_gate_0 r10 i/o lower gate open ddr_data_8 t17 i/o data lines (upper byte) ddr_data_9 t16 ddr_data_10 u17 ddr_data_11 u16 ddr_data_12 u14 ddr_data_13 u13 ddr_data_14 t13 ddr_data_15 r13 ddr_dqs_1 u15 i/o upper data strobe differential sstl_2/sstl_18 ddr_ndqs_1 t15 ddr_dm_1 t14 i/o upper data mask sstl_2/sstl_18 ddr_gate_1 r14 upper gate open ddr_vref p10 input reference voltage analog ddr_mem_com p_gnd r4 power return for ext. resistors power ddr_mem_com p_rext p4 power ext. resistor analog ddr2_en j13 input configuration ttl input buffer 3.3 v tolerant, pu table 8. ddr pin description (continued) group signal name ball direction function pin type
pin description SPEAR320 28/67 doc id 16755 rev 1 3.3 shared i/o pins (pl_gpios) the 98 pl_gpio and 4 pl_clk pins have the following characteristics: ? output buffer: ttl 3.3 v capable up to 10 ma ? input buffer: ttl, 3.3 v tolerant, select able internal pull up/pull down (pu/pd) configuration modes the following modes can be selected by programming the ras control registers. mode 1: smii automation networking mode mode 2: mii automation networking mode mode 3: expanded automation mode mode 4: printer mode the peripherals available are shown in table 9: available peripheral s in each configuration mode . details of each pl_gpio pin are given in table 10: pl_gpio pin de s cription on page 29 mode 1 is the default mode for SPEAR320. boot pins the status of the boot pins is read at startup by the bootrom. refer to the description of the boot register in the SPEAR320 user manual. alternate functions other peripheral functions are listed in the alternate functions column of ta bl e 1 0 : pl_gpio pin de s cription and can be individually enabled/disabled via ras control register 1. refer to the user manual for the register descriptions. table 9. available peripherals in each configuration mode modes fsmc nand interface emi nor interface sdio/mmc data lines no. of ethernet ports clcd touchscreen no of can interfaces std. parallel portr no. of pwm outputs i2s no. of i2c interfaces no. of spi interfaces no. of uarts 18-bit 82 smii1 1 2 411 (1) 3 (2) 3 (3) 28-bit 82 mii (4) 2 411 (1) 3 (2) 3 (3) 3 16-bit 16-bit 1 smii 2 3 2 (1) 1 (2) 3 (3) 48-bit 82 smii 14 2 (2) 3 (3) 1. assuming i2c0 alternate functi ons are enabled on pl5 and pl4 (see table 10 ) 2. assuming that ssp0alternate functi ons are enabled on pl9 thru pl6 (see table 10 ) 3. assuming that uart0 alternate functi ons are enabled on pl3 and pl3 and optionally on pl42-37 if hardware flow control is used (see table 10 ) 4. assuming that mii0 alternate functions are enabled on pl27 thru 10 (see table 10 )
SPEAR320 pin description doc id 16755 rev 1 29/67 table 10. pl_gpio pin description pl / pin number boot pins alternate function (enabled by ras register 1) configuration mode (enabled by ras register 2) function in ras gpio mode function in debug trace mode (etm) 12 3 4 97/h16 cld0 mii1_txclk emi_a0 0 gpio_97 arm_trace_c lk 96/h15 cld1 mii1_txd0 emi_a1 0 gpio_96 arm_trace_p kta[0] 95/h14 cld2 mii1_txd1 emi_a2 0 gpio_95 arm_trace_p kta[1] 94/h13 cld3 mii1_txd2 emi_a3 0 gpio_94 arm_trace_p kta[2] 93/g17 cld4 mii1_txd3 emi_a4 0 gpio_93 arm_trace_p kta[3] 92/g16 cld5 mii1_txen emi_a5 0 gpio_92 arm_trace_p ktb[0] 91/g15 cld6 mii1_txer emi_a6 0 gpio_91 arm_trace_p ktb[1] 90/g14 cld7 mii1_rxclk emi_a7 0 gpio_90 arm_trace_p ktb[2] 89/f17 cld8 mii1_rxdv emi_a8 0 gpio_89 arm_trace_p ktb[3] 88/f16 cld9 mii1_rxer emi_a9 0 gpio_88 arm_trace_s ynca 87/g13 cld10 mii1_rxd0 emi_a10 0 gpio_87 arm_trace_s yncb 86/e17 cld11 mii1_rxd1 emi_a11 0 gpio_86 arm_pipestat a[0] 85/f15 cld12 mii1_rxd2 emi_a12 spp_data0 gpio_85 arm_pipestat a[1] 84/d17 cld13 mii1_rxd3 emi_a13 spp_data1 gpio_84 arm_pipestat a[2] 83/e16 cld14 mii1_col emi_a14 spp_data2 gpio_83 arm_pipestat b[0] 82/e15 cld15 mii1_crs emi_a15 spp_data3 gpio_82 arm_pipestat b[1] 81/c17 cld16 mii1_mdio emi_a16 spp_data4 gpio_81 arm_pipestat b[2] 80/d16 cld17 mii1_mdc emi_a17 spp_data5 gpio_80 arm_trace_p kta[4] 79/f14 cld18 0 emi_a18 spp_data6 gpio_79 arm_trace_p kta[5] 78/d15 cld19 0 emi_a19 spp_data7 gpio_78 arm_trace_p kta[6] 77/b17 cld20 0 emi_a20 spp_strbn gpio_77 arm_trace_p kta[7] 76/f13 cld21 0 emi_a21 spp_ackn gpio_76 arm_trace_p ktb[4] 75/e14 cld22 0 emi_a22 spp_busy gpio_75 arm_trace_p ktb[5] 74/c16 cld23 0 emi_a23 spp_perror gpio_74 arm_trace_p ktb[6]
pin description SPEAR320 30/67 doc id 16755 rev 1 73/a17 clac 0 emi_d8/ fsmc_d8 spp_select gpio_73 arm_trace_p ktb[7] 72/b16 clfp 0 emi_d9/ fsmc_d9 spp_autofdn gpio_72 71/d14 cllp 0 emi_d10/ fsmc_d10 spp_faultn gpio_71 70/c15 clle 0 emi_d11/ fsmc_d11 spp_initn gpio_70 69/a16 clpower 0 emi_wait spp_selinn gpio_69 68/b15 fsmc_d0 fsmc_d0 emi_d0/ fsmc_d0 fsmc_d0 gpio_68 67/c14 fsmc_d1 fsmc_d1 emi_d1/ fsmc_d0 fsmc_d1 gpio_67 66/e13 fsmc_d2 fsmc_d2 emi_d2/ fsmc_d2 fsmc_d2 gpio_66 65/b14 fsmc_d3 fsmc_d3 emi_d3/ fsmc_d3 fsmc_d3 gpio_65 64/d13 fsmc_d4 fsmc_d4 emi_d4/ fsmc_d4 fsmc_d4 gpio_64 63/c13 fsmc_d5 fsmc_d5 emi_d5/ fsmc_d5 fsmc_d5 gpio_63 62/a15 h7 fsmc_d6 fsmc_d6 emi_d6/ fsmc_d6 fsmc_d6 gpio_62 61/e12 h6 fsmc_d7 fsmc_d7 emi_d7/ fsmc_d7 fsmc_d7 gpio_61 60/a14 h5 fsmc_addr_ le fsmc_addr_ le fsmc_addr_le fsmc_addr_l e gpio_60 59/b13 h4 fsmc_we fsmc_we emi_we/ fsmc_we fsmc_we gpio_59 58/d12 h3 fsmc_re fsmc_re emi_oe/ fsmc_re fsmc_re gpio_58 57/e11 h2 fsmc_cmd_ le fsmc_cmd_ le fsmc_cmd_le fsmc_cmd_le gpio_57 56/c12 h1 fsmc_rdy /bsy fsmc_rdy/ bsy fsmc_rdy/bsy fsmc_rdy/ bsy gpio_56 55/a13 h0 fsmc_cs0 fsmc_cs0 emi_ce0/ fsmc_cs0 fsmc_cs0 gpio_55 54/e10 b3 fsmc_cs1 fsmc_cs1 emi_ce1/ fsmc_cs1 fsmc_cs1 gpio_54 53/d11 b2 fsmc_cs2 fsmc_cs2 emi_ce2/ fsmc_cs2 fsmc_cs2 gpio_53 52/b12 b1 fsmc_cs3 fsmc_cs3 emi_ce_3/ fsmc_cs3 fsmc_cs3 gpio_52 51/d10 b0 sd_cd sd_cd emi_byten0 sd_cd gpio_51 50/a12 tmr_cptr4 sd_dat7 sd_dat7 emi_byten1 sd_dat7 gpio_50 49/c11 tmr_cptr3 sd_dat6 sd_dat6 emi_d12/ fsmc_d12 sd_dat6 gpio_49 table 10. pl_gpio pin description (continued) pl / pin number boot pins alternate function (enabled by ras register 1) configuration mode (enabled by ras register 2) function in ras gpio mode function in debug trace mode (etm) 12 3 4
SPEAR320 pin description doc id 16755 rev 1 31/67 48/b11 tmr_cptr2 sd_dat5 sd_dat5 emi_d13/ fsmc_d13 sd_dat5 gpio_48 47/c10 tmr_cptr1 sd_dat4 sd_dat4 emi_d14/ fsmc_d14 sd_dat4 gpio_47 46/a11 tmr_clk4 sd_dat3 sd_dat3 emi_d15/ fsmc_d15 sd_dat3 gpio_46 45/b10 tmr_clk3 sd_dat2 sd_dat2 uart1_dcd sd_dat2 gpio_45 44/a10 tmr_clk2 sd_dat1 sd_dat1 uart1_dsr sd_dat1 gpio_44 43/e9 tmr_clk1 sd_dat0 sd_dat0 uart1_rts sd_dat0 gpio_43 42/d9 uart0_dtr i2s_rx i2s_rx 0 0 gpio_42 41/c9 uart0_ri i2s_tx i2s_tx 0 0 gpio_41 40/b9 uart0_dsr i2s_lr i2s_lr 0 0 gpio_40 39/a9 uart0_dcd i2s_clk i2s_clk 0 0 gpio_39 38/a8 uart0_rts pwm0 pwm0 0 0 gpio_38 37/b8 uart0_cts pwm1 pwm1 0 0 gpio_37 36/c8 ssp0_cs4 touch screen x 0 uart1_cts uart1_cts gpio_36 35/d8 ssp0_cs3 i2s_audio sample 0 uart1_dtr uart1_dtr gpio_35 34/e8 ssp0_cs2 sd_led / pwm2 sd_led / pwm2 uart1_ri uart1_ri gpio_34 33/e7 basgpio5 can0_tx can0_tx can0_tx uart1_dcd gpio_33 32/d7 basgpio4 can0_rx can0_rx can0_rx uart1_dsr gpio_32 31/c7 basgpio3 can1_tx can1_tx can1_tx uart1_rts gpio_31 30/b7 basgpio2 can1_rx can1_rx can1_rx gpio_30 29/a7 basgpio1 uart1_tx uart1_tx uart1_tx uart1_tx gpio_29 28/a6 basgpio0 uart1_rx uart1_rx uart1_rx uart1_rx gpio_28 27/b6 mii0_txclk smii0_tx 0 smii0_tx smii0_tx gpio_27 26/a5 mii0_txd0 smii0_rx 0 smii0_rx smii0_rx gpio_26 25/c6 mii0_txd1 smii1_tx 0 0 smii1_tx gpio_25 24/b5 mii0_txd2 smii1_rx 0 0 smii1_rx gpio_24 23/a4 mii0_txd3 smii_sync 0 smii_sync smii_sync gpio_23 22/d6 mii0_txen smii_clkout 0 smii_clkout smii_clkout gpio_22 21/c5 mii0_txer smii_clkin 0 smii_clkin smii_clkin gpio_21 20/b4 mii0_rxclk ssp1_mosi 0 0 ssp1_mosi gpio_20 19/a3 mii0_rxdv ssp1_clk 0 0 ssp1_clk gpio_19 18/d5 mii0_rxer ssp1_ss0 0 0 ssp1_ss0 gpio_18 17/c4 mii0_rxd0 ssp1_miso 0 0 ssp1_miso gpio_17 16/e6 mii0_rxd1 ssp2_mosi 0 0 0 gpio_16 table 10. pl_gpio pin description (continued) pl / pin number boot pins alternate function (enabled by ras register 1) configuration mode (enabled by ras register 2) function in ras gpio mode function in debug trace mode (etm) 12 3 4
pin description SPEAR320 32/67 doc id 16755 rev 1 15/b3 mii0_rxd2 ssp2_clk 0 pwm0 pwm0 gpio_15 14/a2 mii0_rxd3 ssp2_ss0 0 pwm1 pwm1 gpio_14 13/a1 mii0_col ssp2_mido 0 pwm2 pwm2 gpio_13 12/d4 mii0_crs pwm3 0 pwm3 pwm3 gpio_12 11/e5 mii0_mdc smii_mdio 0 smii_mdio smii_mdio gpio_11 10/c3 mii0_mdio smii_mdc 0 smii_mdc smii_mdc gpio_10 9/b2 ssp0_mosi 0 0 0 0 gpio_9 8/c2 ssp0_clk 0 0 0 0 gpio_8 7/d3 ssp0_ss0 0 0 0 0 gpio_7 6/b1 ssp0_miso 0 0 0 0 gpio_6 5/d2 i2c0_sda 0 0 0 0 gpio_5 4/c1 i2c0_scl 0 0 0 0 gpio_4 3/d1 uart0_rx 0 0 0 0 gpio_3 2/e4 uart0_tx 0 0 0 0 gpio_2 1/e3 irda_rx uart2_tx uart2_tx uart2_tx uart2_tx gpio_1 0/f3 irda_tx uart2_rx uart2_rx uart2_rx uart2_rx gpio_0 ck1/k17 pl_clk1 clcp 0 i2c1_sda sd_led gpio_98 ck2/j17 pl_clk2 sd_clk sd_clk i2c1_scl sd_clk gpio_99 ck3/j16 pl_clk3 sd_wp sd_wp 0 sd_wp gpio_100 ck4/h17 pl_clk4 sd_cmd sd_cmd 0 sd_cmd gpio_101 table 10. pl_gpio pin description (continued) pl / pin number boot pins alternate function (enabled by ras register 1) configuration mode (enabled by ras register 2) function in ras gpio mode function in debug trace mode (etm) 12 3 4
SPEAR320 pin description doc id 16755 rev 1 33/67 notes/legend for ta bl e 1 0 : emi_ : external memory interface (for nor flash or fpga) signals fsmc_ : flexible static me mory controller (for nand flash) signals gpio (general purpose i/o) : basgpio : base gpios in the base subsystem gpio_102 to gpio_0 : gpios in the ras subsystem mii0_ : mii signals from the mii cont roller in the high speed subsystem mii1_ : mii signals from the smii controller in the ras subsystem working in mii mode smii0_ , smii1_ : signals from the 2 smii controllers in the ras subsystem working in smii mode spp_ : standard parallel port signals ssp_ : spi interface signals from the synchronous serial peripheral tmr_ : general purpose timer signals note: 1 ta bl e 1 0 cell s filled with 0 or 1 are unu s ed and unle ss otherwi s e configured a s alternate function or gpio, the corre s ponding pin i s held at low or high level re s pectively by the internal logic. 2pin s s hared by emi and fsmc: depending on the ahb addre ss to be acce ss ed the pin s are u s ed for emi or fsmc tran s fer s . table shading: fsmc fsmc pins: nand flash clcd color lcd controller pins
memory map SPEAR320 34/67 doc id 16755 rev 1 4 memory map table 11. SPEAR320 main memory map start address end address peripheral description 0x0000.0000 0x3fff.ffff external dram low power ddr or ddr2 0x4000.0000 0xbfff.ffff - ras (see ta bl e 1 2 ) 0xc000.0000 0xcfff.ffff - reserved 0xd000.0000 0xd007.ffff uart0 0xd008.0000 0xd00f.ffff adc 0xd010.0000 0xd017.ffff spi0 0xd018.0000 0xd01f.ffff i2c0 0xd020.0000 0xd07f.ffff - reserved 0xd080.0000 0xd0ff.ffff jpeg codec 0xd100.0000 0xd17f.ffff irda 0xd180.0000 0xd1ff.ffff - reserved 0xd280.0000 0xd7ff.ffff sram static ram shared memory (8 kbytes) 0xd800.0000 0xe07f.ffff - reserved 0xe080.0000 0xe0ff.ffff e thernet controller mac 0xe100.0000 0xe10f.ffff usb 2.0 device fifo 0xe110.0000 0xe11f.ffff usb 2.0 de vice configuration registers 0xe120.0000 0xe12f.ffff usb 2.0 device plug detect 0xe130.0000 0xe17f.ffff - reserved 0xe180.0000 0xe18f.ffff usb2.0 ehci 0-1 0xe190.0000 0xe19f.ffff usb2.0 ohci 0 0xe1a0.0000 0xe20f.ffff - reserved 0xe210.0000 0xe21f.ffff usb2.0 ohci 1 0xe220.0000 0xe27f.ffff - reserved 0xe280.0000 0xe28f.ffff ml u sb arb configuration register 0xe290.0000 0xe7ff.ffff - reserved 0xe800.0000 0xefff.ffff - reserved 0xf000.0000 0xf00f.ffff timer0 0xf010.0000 0xf10f.ffff - reserved 0xf110.0000 0xf11f.ffff itc primary 0xf120.0000 0xf7ff.ffff - reserved 0xf800.0000 0xfbff.ffff serial flash memory 0xfc00.0000 0xfc1f.ffff serial flash controller
SPEAR320 memory map doc id 16755 rev 1 35/67 0xfc20.0000 0xfc3f.ffff - reserved 0xfc40.0000 0xfc5f.ffff dma controller 0xfc60.0000 0xfc7f.ffff dram controller 0xfc80.0000 0xfc87.ffff timer 1 0xfc88.0000 0xfc8f.ffff watchdog timer 0xfc90.0000 0xfc97.ffff real time clock 0xfc98.0000 0xfc9f.ffff basgpio 0xfca0.0000 0xfca7.f fff system controller 0xfca8.0000 0xfcaf.ffff miscellaneous registers 0xfcb0.0000 0xfcb7.ffff timer 2 0xfcb8.0000 0xfcff.ffff - reserved 0xfd00.0000 0xfeff.ffff - reserved 0xff00.0000 0xffff.ffff bootrom table 12. reconfigurable array subsystem (ras) memory map start address end address peripheral description 0x4000_0000 0x47ff_ffff emi 0x4800_0000 0x4bff_ffff reserved 0x4c00_0000 0x5fff_ffff fsmc 0x6000_0000 0x6fff_ffff i2s 0x7000_0000 0x7f ff_ffff sdio 0x8000_0000 0x8000_3fff boot memory 0x8000_4000 0x8fff_ffff reserved 0x9000_0000 0x9fff_ffff clcd 0xa000_0000 0xa0ff_ffff parallel port 0xa100_0000 - 0xa1ff_ffff can0 0xa200_0000 - 0xa2ff_ffff can1 0xa300_0000 - 0xa3ff_ffff uart1 0xa400_0000 - 0xa4ff_ffff uart23 0xa500_0000 0xa5ff_ffff spi1 0xa600_0000 0xa6ff_ffff spi2 0xa700_0000 0xa7ff_ffff i2c1 0xa800_0000 0xa8ff_ffff quad pwm timer 0xa900_0000 0xa9cf_ffff gpio 0xa9d0_0000 0xa9ff_ffff reserved table 11. SPEAR320 main memory map (continued) start address end address peripheral description
memory map SPEAR320 36/67 doc id 16755 rev 1 0xaa00_0000 0xaaff_ffff smii0 0xab00_0000 0xabff_ffff smii1/mii 0xac00_0000 0xb2ff_ffff reserved 0xb300_0000 0xbfff_ffff ahb interface table 12. reconfigurable array subsystem (ras) memory map (continued) start address end address peripheral description
SPEAR320 electrical characteristics doc id 16755 rev 1 37/67 5 electrical characteristics 5.1 absolute minimum and maximum ratings this product contains devices to protect the in puts against damage due to high/low static voltages. however it is advisable to take normal precaution to avoid application of any voltage higher/lower than the specified maximum/minimum rated voltages. the absolute minimum and maximum rating is the maximum stress that can be applied to a device without causing permanent damage. however, extended exposure to minimum/maximum ratings may affe ct long-term device reliability. the average chip-junction temperature, t j , can be calculated using the following e q uation: t j = t a + (p d ? ja ) where: t a is the ambient temperature in c ja is the package junction-to-ambient thermal resistance, which is 34 c/w p d = p int + p port ? p int is the chip internal power ? p port is the power dissipation on input and output pins, user determined if p port is neglected, an approximate relationship between p d is: p d = k / (t j + 273 c) and, solving first e q uations: k = p d ? (t a + 273 c) + ja x p d 2 k is a constant for the particular case, which can be determined through last e q uation by measuring p d at e q uilibrium, for a known t a . using this value of k, the value of p d and t j can be obtained by solving first and second e q uation, iteratively for any value of t a . table 13. absolute minimum and maximum ratings symbol parameter minimum value maximum value unit v dd 1.2 supply voltage for the core - 0.3 1.6 v v dd 3.3 supply voltage for the i/os - 0.3 4.8 v v dd 2.5 supply voltage for the analog blocks - 0.3 4.8 v v dd 1.8 supply voltage for the dram interface - 0.3 4.8 v t j junction temperature -40 125 c t stg storage temperature -55 150 c
electrical charac teristics SPEAR320 38/67 doc id 16755 rev 1 5.2 maximum power consumption note: the s e value s take into con s ideration the wor s t ca s e s of proce ss variation and voltage range and mu s t be u s ed to de s ign the power s upply s ection of the board. the maximum current and power values listed above are not guaranteed to be the highest obtainable. these values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages. your specific application can produce significantly different results. 1.2 v current and power are primarily dependent on the applications running and the use of internal chip functions (dma, usb, ethernet, and so on). 3.3 v current and power are primarily dependent on the capacitive loading, fre q uency, and utilization of the external buses. 5.3 dc electrical characteristics the recommended operating conditions are listed in the following table: table 14. maximum power consumption symbol description max unit v dd 1.2 supply voltage for the core (1) 1. peak current with cpu at maximum speed in asynchronous mode with ddr at maximum speed. 420 ma v dd 1.8 supply voltage for the dram interface (2) 2. peak current with linux memory test (50% write and 50% read) plus dma reading memory. 160 ma v dd 2.5 supply voltage for the analog blocks 35 ma v dd 3.3 supply voltage for the i/os (3) 3. with 30 logic channels connected to the dev ice and simultaneously switching at 10 mhz. 15 ma p d maximum power consumption 930 mw table 15. recommended operating conditions symbol parameter min typ max unit v dd core supply voltage for the core 1.14 1.2 1.26 v v dd i/o supply voltage for the i/os 3 3.3 3.6 v v dd pll pll supply voltage 2.25 2.5 2.75 v v dd osc oscillator supply voltage 2.25 2.5 2.75 v v dd 1.8 supply voltage for dram interface 1.7 1.8 1.9 v
SPEAR320 electrical characteristics doc id 16755 rev 1 39/67 5.4 overshoot and undershoot this product can support the following values of overshoot and undershoot. table 1. if the amplitude of the overshoot/undershoo t increases (decreases), the ratio of overshoot/undershoot width to the pulse width decreases (increases). the formula relating the two is: amplitude of os/us = 0.75*(1- ratio of os (or us) duration with respect to pulse width) note: the value of over s hoot/under s hoot s hould not exceed the value of 0.5 v. however, the duration of the over s hoot/under s hoot can be increa s ed by decrea s ing it s amplitude. 5.5 general purpose i/o characteristics the 3.3 v i/os are compliant with jedec standard jesd8b v dd rtc rtc supply voltage 1.2 1.5 1.8 v t a operating temperature -40 85 c table 15. recommended operating conditions (continued) symbol parameter min typ max unit table 16. overshoot and undershoot specifications parameter 3v3 i/os 2v5 i/os 1v8 i/os amplitude 500 mv 500 mv 500 mv ratio of overshoot (or unders hoot) duration with respect to pulse width 1/3 1/3 1/3 table 17. low voltage ttl dc input specification (3 v< v dd <3.6 v) symbol parameter min max unit v il low level input voltage 0.8 v v ih high level input voltage 2 v v hyst schmitt trigger hysteresis 300 800 mv table 18. low voltage ttl dc output specification (3 v< v dd <3.6 v) symbol parameter test condition min max unit v ol low level output voltage i ol = x ma (1) 1. for the max current value (x ma) refer to section 3: pin de s cription . 0.3 v v oh high level output voltage i oh = -x ma (1) v dd - 0.3 v
electrical charac teristics SPEAR320 40/67 doc id 16755 rev 1 5.6 lpddr and ddr2 pin characteristics 5.6.1 ddr2 timing characteristics the characterization timing is done considering an output load of 10 pf on all the ddr pads. the operating conditions are in worst case v = 0.90 v t a = 125 c and in best case v=1.10 v t a = 40 c. table 19. pull-up and pull-down characteristics symbol parameter test condition min max unit r pu e q uivalent pull-up resistance v i = 0 v 29 67 k r pd e q uivalent pull-down resistance v i = v dde 3v3 29 103 k table 20. dc characteristics symbol parameter test condition min max unit v il low level input voltage sstl2 -0.3 v ref -0.15 v sstl18 -0.3 v ref -0.125 v v ih high level input voltage sstl2 v ref +0.15 v dde 2v5+0.3 v sstl18 v ref +0.125 v dde 1v8+0.3 v v hyst input voltage hysteresis 200 mv table 21. driver characteristics symbol parameter min typ max unit r o output impedance 45 table 22. on die termination symbol parameter min typ max unit rt1* termination value of resistance for on die termination 75 rt2* termination value of resistance for on die termination 150 table 23. reference voltage symbol parameter min typ max unit v refin voltage applied to core/pad 0.49 * v dde 0.500 * v dde 0.51 * v dde v
SPEAR320 electrical characteristics doc id 16755 rev 1 41/67 ddr2 read cycle timings figure 4. read cycle waveforms figure 5. read cycle path table 24. read cycle timings frequency t4 max t5 max t5 max 333 mhz 1.24 ns -495 ps -495 ps 266 mhz 1.43 ns -306 ps -306 ps 200 mhz 1.74 ns 4 ps 4 ps 166 mhz 2.00 ns 260 ps 260 ps 133 mhz 2.37 ns 634 ps 634 ps t4 t5 t5 t4 t4 dqs dq t3 t1 t2 dll d q q clr set dq dqs
electrical charac teristics SPEAR320 42/67 doc id 16755 rev 1 ddr2 write cycle timings figure 6. write cycle waveforms figure 7. write cycle path table 25. write cycle timings frequency t4 max t5 max unit 333 mhz 1.36 -1.55 ns 266 mhz 1.55 -1.36 ns 200 mhz 1.86 -1.05 ns 166 mhz 2.11 - 794 ns 133 mhz 2.49 -420 ns t6 t6 t6 t4 t5 t4 t5 t4 t5 clk dqs dq
SPEAR320 electrical characteristics doc id 16755 rev 1 43/67 ddr2i command timings figure 8. command waveforms figure 9. command path 5.7 clcd timing characteristics the characterization timing is done considering an output load of 10 pf on all the outputs.the operating conditions are in worst case v=0.90 v t=125 c and in best case v =1.10 v t= 40 c. the clcd has a wide variety of configurations and setting and the parameters change accordingly. two main scenarios will be consid ered, one with direct cl ock to output (166 mhz), setting bcd bit to '1', and the second one with the clock passing through a clock divider (83 mhz), setting bcd bit to '0'. table 26. command timings frequency t4 max t5 max unit 333 mhz 1.39 1.40 ns 266 mhz 1.77 1.78 ns 200 mhz 2.39 2.40 ns 166 mhz 2.90 2.91 ns 133 mhz 3.65 3.66 ns t4 t5 clk address, strobes, and control lines
electrical charac teristics SPEAR320 44/67 doc id 16755 rev 1 5.7.1 clcd timing charact eristics direct clock figure 10. clcd waveform with clcp direct figure 11. clcd block diagram with clcp direct note: 1 t stable = t clock direct max - (t max + t min ) 2for t ma x the maximum value i s taken from the wor s t ca s e and be s t ca s e, while for t min the minimum value i s taken from the wor s t ca s e and be s t ca s e. 3clcp s hould be delayed by {t max + [t clock direct max - (t max + t min )]/2} = 4.7915 n s table 27. clcd timings with clcp direct parameter value frequency t clock direct max (t clock ) 6 ns 166 mhz t clock direct max rise (t r ) 0.81 ns t clock direct max (t f ) 0.87 ns t min -0.04 ns t max 3.62 ns t stable 2.34 ns tmin tmax clcp cld[23:0],clac,clle,cllp, clfp ,c lpow er tc loc k tr tf tstable q q set cl r d t2 t3 clcp cld[23:0],clac,clle, cllp,clfp,clpower clcdclk t1
SPEAR320 electrical characteristics doc id 16755 rev 1 45/67 5.7.2 clcd timing char acteristics divided clock figure 12. clcd waveform with clcp divided figure 13. clcd block diagram with clcp divided table 105. note: 1 t stable = t clock direct max - (tmax + tmin) 2for t max the maximum value i s taken from the wor s t ca s e and for t min the minimum value i s taken from the be s t ca s e. 3clcp s hould be delayed by {t max + [t clock direct max - (t max + t min )]/2} = 6.945 n s table 28. clcd timings with clcp divided parameter value frequency t clock divided max 12 ns 83.3 mhz t clock divided max rise (t r ) 0.81 ns t clock divided max (t f ) 0.87 ns t min -0.49 ns t max 2.38 ns t stable 9.13 ns tmin tmax clcp cld[23:0],clac,clle,cllp, clfp ,c lpow er tc loc k tr tf tstable q q set cl r d t2 clcp cld[23:0],clac,clle, cllp,clfp,clpower clcdclk t1 q q set cl r d t3
electrical charac teristics SPEAR320 46/67 doc id 16755 rev 1 5.8 i 2 c timing characteristics the characterization timing is done using primetime considering an output load of 10 pf on scl and sda. the operating conditions are v = 0.90 v, t a =125 c in worst case and v =1. 10 v, t a = 40 c in best case. figure 14. i 2 c output pins figure 15. i 2 c input pins the flip-flops used to capture the incoming si gnals are re-synchronized with the ahb clock: so, no input delay calculation is re q uired. those values are referred to the common internal source clock which has a period of: t hclk = 6 ns. table 29. output delays for i 2 c signals parameter min max unit t hclk -> sclh 8.1067 11.8184 ns t hclk -> scll 7.9874 12.6269 ns t hclk -> sdah 7.5274 11.2453 ns t hclk -> sdal 7.4081 12.0530 ns set q q d clr set q q d clr hclk scl sda
SPEAR320 electrical characteristics doc id 16755 rev 1 47/67 figure 16. output signal waveforms for i 2 c signals the timing of high and low level of scl (t sclhigh and t scllow ) are programmable. table 30. time characteristics for i 2 c in high-speed mode parameter min unit t su-sta 157.5897 ns t hd-sta 325.9344 t su-dat 314.0537 t hd-dat 0.7812 t su-sto 637.709 t hd-sto 4742.1628 table 31. time characteristics for i 2 c in fast speed mode parameter min unit t su-sta 637.5897 ns t hd-sta 602.169 t su-dat 1286.0537 t hd-dat 0.7812 t su-sto 637.709 t hd-sto 4742.1628 table 32. time characteristics for i 2 c in standard speed mode parameter min unit t su-sta 4723.5897 ns t hd-sta 3991.9344 t su-dat 4676.0537 t hd-dat 0.7812 t su-sto 4027.709 t hd-sto 4742.1628
electrical charac teristics SPEAR320 48/67 doc id 16755 rev 1 note: 1 the timing s s hown in figure 16. depend on the programmed value of t sclhigh and t scllow, s o the value s pre s ent in the three table s here above have been calculated u s ing the minimum programmable value s of : ic_hs_scl_hcnt=19 and ic_hs_scl_lcnt=53 regi s ter s (for high-speed mode); ic_fs_scl_hcnt=99 and ic _fs_scl_lcnt=215 regi s ter s (for fa s t-speed mode); ic_ss_scl_hcnt=664 and ic_ss_scl_lcnt=780 regi s ter s (for standard-speed mode). the s e minimum value s depend on the ahb clock frequency, which i s 166 mhz. 2 a device may internally requi re a hold time of at lea s t 300 n s for the sda s ignal (referred to the v ihmin of the scl s ignal) to bridge the undefined region of t he falling edge of scl (plea s e refer to the i 2 c bu s specification v3-0 jun 2007). however, the sda data hold time in the i 2 c controller of SPEAR320 i s one-clock cycle ba s ed (6 n s with the hclk clock at 166 mhz). thi s time may be in s ufficient for s ome s lave device s . a few s lave device s may not receive the valid addre ss due to the lack of sda hold ti me and will not acknowledge even if the addre ss i s valid. if the sda data hold time i s in s ufficient, an error may occur. 3 workaround: if a device need s more sda data hold time than one clock cycle, an rc delay circuit i s needed on the sda line a s illu s trated in the following figure: figure 17. rc delay circuit for example, r=k and c = 200 pf. 5.9 fsmc timing characteristics the characterization timing is done using prim etime considering an output load of 3pf on the data, 15pf on nf_ce, nf_re and nf_we and 10pf on nf_ale and nf_cle. the operating conditions are v=0.90v, t=125c in worst case and v=1.10v, t= 40c in best case.
SPEAR320 electrical characteristics doc id 16755 rev 1 49/67 5.9.1 8-bit nand flash configuration figure 18. output pads for 8-bit nand flash configuration figure 19. input pads for 8-bit nand flash configuration figure 20. output command si gnal waveforms for 8-bit nand flash configuration set q q d clr set q q d clr hclk nfcle nfce nfwe nfre nfrwprt nfale nfio_0..7 set q q d clr set q q d clr nfrb nfio_0..7 clpower cllp clle clfp clcp clac cld_23..22 (nfio_8..15) hclk nfcle nf ce nfwe nfio command t cle t we t io
electrical charac teristics SPEAR320 50/67 doc id 16755 rev 1 figure 21. output address signal waveforms for 8-bit nand flash configuration figure 22. in/out data address signal waveforms for 8-bit nand flash configuration note: value s in ta b l e 3 3 are referred to the common internal s ource clock which ha s a period of thclk = 6 n s . table 33. time characteristics fo r 8-bit nand flash configuration parameter min max tcle -16.85 ns -19.38 ns tale -16.84 ns -19.37 ns twe (s=1) 11.10 ns 13.04 ns tre (s=1) 11.18 ns 13.05 ns tio (h=1) 3.43 ns 8.86 ns nf ale nfc e nfwe nfio address t ale t we t io nfce nfwe nf i o (out ) data out t io nf i o (i n) nfre t re? io t we t re t read t nfio? ffs
SPEAR320 electrical characteristics doc id 16755 rev 1 51/67 5.9.2 16-bit nand flash configuration figure 23. output pads for 16 -bit nand flash configuration figure 24. input pads for 16-bit nand flash configuration figure 25. output command signal waveforms 16-bit nand flash configuration set q q d clr set q q d clr hclk nfcle nfce nfwe nfre nfrwprt nfale nfio_0..7 clpower cllp clle clfp clcp clac cld_23..22 (nfio_8..15) set q q d clr set q q d clr nfrb nfio_0..7 clpower cllp clle clfp clcp clac cld_23..22 (nfio_8..15) hclk nfcle nf ce nfwe nfio command t cle t we t io
electrical charac teristics SPEAR320 52/67 doc id 16755 rev 1 figure 26. output address signal waveforms 16-bit nand flash configuration figure 27. in/out data si gnal waveforms for 16-bit nand flash configuration note: value s in ta b l e 3 4 are referred to the common internal s ource clock which ha s a period of thclk = 6 n s . 5.10 ether mac 10/100/1000 mbps (gmac-univ) timing characteristics the characterization timing is given for an output load of 5 pf on the gmii tx clock and 10 pf on the other pads. the operating conditions are in worst case v=0.90 v t=125 c and in best case v=1.10 v t= 40 c. table 34. time characteristics for 16-bit nand flash configuration parameter min max tcle -16.85 ns -19.38 ns tale -16.84 ns -19.37 ns twe (s=1) 11.10 ns 13.04 ns tre (s=1) 11.18 ns 13.05 ns tio (h=1) 3.27 ns 11.35 ns nfale nf ce nfwe nfio address t al e t we t io nfce nfwe nfio (out) data out t io nfio (in) nfre t re? io t we t re t r ead t nfio? ffs
SPEAR320 electrical characteristics doc id 16755 rev 1 53/67 5.10.1 gmii transmit timing specifications figure 28. gmii tx waveforms figure 29. block diagram of gmii tx pins note: to calculate the t setup value for the phy you have to con s ider the next t clk ri s ing edge, s o you have to apply the following formula: t setup = t clk - t max table 35. gmii tx timing parameter value using gmii [t clk period = 8 ns 125 mhz] t rise (t r ) <1 ns t fall (t f ) <1 ns t max = t2 max - t3 min 2.8 ns t min = t2 min - t3 max 0.4 ns t setup 5.19 ns tm in tm ax gmiitx _clk txd0-txd3 , gmiitx_d4-gmiitx _d7, tx_en , tx_er tclock tr tf q q set cl r d t2 t3 gmiitx_clk tx[0..3], gmii_tx[4..7], tx_en, tx_er clk tx[0..3], gmii_tx[4..7], tx_en, tx_er
electrical charac teristics SPEAR320 54/67 doc id 16755 rev 1 5.10.2 mii transmit timing specifications figure 30. mii tx waveforms figure 31. block diagram of mii tx pins note: to calculate the t setup value for the phy you have to con s ider the next t clk ri s ing edge, s o you have to apply the following formula: t setup = t clk - t max table 36. mii tx timings parameter value using mii 10 mb [t clk period = 40 ns 25 mhz] value using mii 100 mb [t clk period = 400 ns 2.5 mhz] t max = t2 max - t3 min 6.8 ns 6.8 ns t min = t2 min - t3 max 2.9 ns 2.9 ns t setup 33.2 ns 393.2 ns tm in tm ax tx_c lk txd0 -t xd 3 tclock tr tf q q set cl r d t2 t3 tx_clk txd[0..3] tx[0..3]
SPEAR320 electrical characteristics doc id 16755 rev 1 55/67 5.10.3 gmii-mii receive timing specifications figure 32. gmii-mii rx waveforms figure 33. block diagram of gmii-mii rx pins note: the input s tage i s the s ame for all the interface s (gmii and mii10/100) s o t setup and t hold value s are equal in all the ca s e s . the receive path i s optimized for the gmii interface: thi s al s o en s ure s correct capture of data for the mii10/100 interface. 5.10.4 mdio timing specifications figure 34. mdc waveforms ts th rx _c lk rxd0-rxd3, gm iirx_d 4- gm iir x_d7, rx_er, rx_d v tc loc k tr tf t1 q q set cl r d t2 rx[0.. 3], gmii_ rx[4.. 7] , rx_er, rx_dv rx_clk input thold mdc mdio tc loc k tr tf ou tp ut tsetup tmin tmax
electrical charac teristics SPEAR320 56/67 doc id 16755 rev 1 figure 35. paths from mdc/mdio pads note: when mdio i s u s ed a s output the data are launched on the falling edge of the clock a s s hown in figure 34 . table 37. mdc/mdio timing parameter value frequency t clk period 614.4 ns 1.63 mhz t clk fall (t f ) 1.18 ns t clk rise (t r ) 1.14 ns output t max = ~t clk /2 307 ns t min = ~t clk /2 307 ns input t setupmax = t1 max - t3 min 6.88 ns t holdmin = t1 min - t3 max -1.54 ns q q set cl r d t2 t3 clk md io t1 q q set cl r d md c input output
SPEAR320 electrical characteristics doc id 16755 rev 1 57/67 5.11 smi - serial memory interface figure 36. smidatain data path figure 37. smidataout/smicsn data paths table 38. smidatain timings signal parameter value smi_datain t d_max t smidatain_arrival_max - t input_delay t d_min t smidatain_arrival_min - t input_delay t cd_min t smi_clk_i_arrival_min t cd_max t smi_clk_i_arrival_max t setup_max t s + t d_max -t cd_min t hold_min t h - t d_min + t cd_max hclk smi_clk smi_datain smi_clk_i t smidatain arrival t input_delay t d t h t s t cd hclk hclk output smiclk
electrical charac teristics SPEAR320 58/67 doc id 16755 rev 1 figure 38. smidataout timings figure 39. smicsn fall timings table 39. smidatain timings signal parameter value smi_dataout t delay_max t arrivalsmidataout_max - t arrival_smi_clk_min t delay_min t arrivalsmidataout_min - t arrival_smi_clk_max table 40. smicsn fall timings signal parameter value smi_csn fall t delay_max t arrivalsmicsn_max_fall - t arrival_smi_clk_min_fall t delay_min t arrivalsmicsn_min_fall - t arrival_smi_clk_max_fall smi_clk smidataout(fast) t delay_min t arrival smidataout(slow) t delay_max
SPEAR320 electrical characteristics doc id 16755 rev 1 59/67 figure 40. smicsn rise timings 5.12 spi this module provides a programmable le ngth shift register which allows serial communication with other spi devices through a 3 or 4 wire interface (spi_sck, miso, mosi and spi_csn). table 41. smicsn rise timings signal parameter value smi_csn rise t delay_max t arrivalsmicsn_max_rise - t arrival_smi_clk_min_fall t delay_min t arrivalsmicsn_min_rise - t arrival_smi_clk_max_fall table 42. timing requirements for smi parameter input setup-hold/output delay max min smi_clk fall time 1.8209 1.4092 rise time 1.6320 1.1959 smidatain input setup time 8.27482 input hold time -2.595889 smidataout output valid time 2.039774 smics_0 output valid time fall 1.922779 rise 1.69768 smics_1output valid time fall 1.7898169 rise 1.638069
electrical charac teristics SPEAR320 60/67 doc id 16755 rev 1 figure 41. spi_clk timings 5.12.1 spi master mode timings (clock phase = 0) figure 42. spi master mode external timing (clock phase =0) table 43. spi timing requirements (all modes) no. parameters min max unit 1t c(clk) cycle time, spi_sck 24 ns 2t w(clkh) pulse duration, spi_sck high 0.49*t c(clk) - 0.51*t c(clk) ns 3t w(clkl) pulse duration, spi_sck low 0.51t c(clk) - 0.49*t c(clk) ns
SPEAR320 electrical characteristics doc id 16755 rev 1 61/67 5.12.2 spi master mode timings (clock phase = 1) figure 43. spi master mode external timing (clock phase = 1) table 44. timing requirements for spi master mode [clock phase = 0] no. parameters max. unit 4t su(div-clkl) setup time, miso (input) valid before spi_sck (output) falling edge clock polarity = 0 11.832 ns 5t su(div-clkh) setup time, miso (input) valid before spi_sck (output) rising edge clock polarity = 1 11.950 ns 6t h(clkl-div) hold time, miso (input)valid after spi_sck (output) falling edge clock polarity = 0 -7.690 ns 7t h(clkh-div) hold time, miso (input) valid after spi_sck (output) rising edge clock polarity = 1 -7.958 ns table 45. switching characteristics over recommen ded operating conditions for spi master mode (clock phase = 0) no. parameters max unit 8t d(clkh-dov) delay time, spi_sck (output) rising edge to mosi (output) transition clock polarity = 0 1.960 ns 9t d(clkl-dov) delay time, spi_sck (output) falling edge to mosi (output) transition clock polarity = 1 21.75 ns 10 t d(enl-clkh/l) delay time, spi_csn (output) falling edge to first spi_sck (output) rising or falling edge tns 11 t d(clkh/l-enh) delay time, spi_sck (output) rising or falling edge to spi_csn (output) rising edge t/2 ns
electrical charac teristics SPEAR320 62/67 doc id 16755 rev 1 table 46. timing requirements for spi master mode (clock phase = 1) no. parameters max unit 12 t su(div-clkl) setup time, miso (input) valid before spi_sck (output) rising edge clock polarity = 0 11.950 ns 13 t su(div-clkh) setup time, miso (input) valid before spi_sck (output) falling edge clock polarity = 1 11.832 ns 14 t h(clkl-div) hold time, miso (input) valid after spi_sck (output) rising edge clock polarity = 0 -7.958 ns 15 t h(clkh-div) hold time, miso (input) valid after spi_sck (output) falling edge clock polarity = 1 -7.690 ns table 47. switching characteristics over recommended oeprating conditions for spi master mode (clock phase =1 ) no. parameters max unit 16 t d(clkh-dov) delay time, spi_sck (output) rising edge to mosi (output) transition clock polarity = 0 1.960 ns 17 t d(clkl-dov) delay time, spi_sck (output) falling edge to mosi (output) transition clock polarity = 1 2.175 ns 18 t d(enl- clkh/l) delay time, spi_csn (output) falling edge to first spi_sck (output) rising or falling edge t/2 ns 19 td(clkh/l- enh) delay time, spi_sck (output) rising or falling edge to spi_csn (output) rising edge tns
SPEAR320 electrical characteristics doc id 16755 rev 1 63/67 5.13 uart (universal asynchro nous receiver/transmitter) figure 44. uart transmit and receive timings where (1) b = uart baud rate 5.14 power up sequence the only re q uirement is that the various power supplies reach the correct range in less than 10 ms. 5.15 power on reset (mreset) the mreset must remain active for at least 10 ms after all the power supplies are in the correct range and should become active in no more than 10 s when one of the power supplies goes out of the correct range. table 48. uart transmit timing characteristics s.no. parameters min max unit 1 uart maximum baud rate 3 mbps 2 uart pulse duration transmit data (txd) 0.99b (1) b (1) ns 3 uart transmit start bit 0.99b (1) b (1) ns table 49. uart receive timing characteristics s.no. parameters min max units 4 uart pulse duration receive data (rxd) 0.97b (1) 1.06b (1) ns 5 uart receive start bit 0.97b (1) 1.06b (1) ns
package information SPEAR320 64/67 doc id 16755 rev 1 6 package information in order to meet environmental re q uirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www. s t.com . ecopack ? is an st trademark. table 50. lfbga289 (15 x 15 x 1.7 mm) mechanical data dim. mm inches min. typ. max. min. typ. max. a 1.700 0.0669 a1 0.270 0.0106 a2 0.985 0.0387 a3 0.200 0.0078 a4 0.800 0.0315 b 0.450 0.500 0.550 0.0177 0.0197 0.0217 d 14.850 15.000 15.150 0.5846 0.5906 0.5965 d1 12.800 0.5039 e 14.850 15.000 15.150 0.5846 0.5906 0.5965 e1 12.800 0.5039 e 0.800 0.0315 f 1.100 0.0433 ddd 0.200 0.0078 eee 0.150 0.0059 fff 0.080 0.0031
SPEAR320 package information doc id 16755 rev 1 65/67 figure 45. lfbga289 package dimensions
revision history SPEAR320 66/67 doc id 16755 rev 1 7 revision history table 51. document revision history date revision changes 12-nov-2009 1 initial release.
SPEAR320 doc id 16755 rev 1 67/67 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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