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december 2011 doc id 022529 rev 2 1/51 51 l6474 easyspin ? fully integrated microstepping motor driver features operating voltage: 8 - 45 v 7.0 a output peak current (3.0 a r.m.s.) low r dson power mosfets programmable power mos slew-rate up to 1/16 microstepping current control with adaptive decay non dissipative current sensing spi interface low quiescent and standby currents programmable non dissipative overcurrent protection on all power mos two-level overtemperature protection application bipolar stepper motor description the l6474, realized in analog mixed signal technology, integrates a dual low r dson dmos full bridge with all power switches equipped with an accurate on-chip current sensing circuitry suitable for non dissipative current control and overcurrent protections. thanks to a new current control, a 1/16 microstepping is achieved through an adaptive decay mode which outperforms traditional implementations. all data registers, including those used to set analogue values (i.e. current control value, current protection trip point, dead time, etc.) are sent through a standard 5 mbit/s spi. a very rich set of protections (thermal, low bus voltage, overcurrent) makes the l6474 ?bullet proof? as required by the most demanding motor control applications. htssop28 powerso36 table 1. device summary order codes package packing l6474h htssop28 tube L6474HTR htssop28 tape and reel l6474pd powerso36 tube l6474pdtr powerso36 tape and reel www.st.com
contents l6474 2/51 doc id 022529 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 device power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 logic i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5 absolute position counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6 step sequence control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.7 enable and disable commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.8 internal oscillator and oscillator driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.8.1 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.8.2 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.9 overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.10 undervoltage lock-out (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.11 thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.12 reset and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.13 programmable dmos slew-rate, dead-time and blanking-time . . . . . . . . 24 6.14 integrated analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.15 internal voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
l6474 contents doc id 022529 rev 2 3/51 6.16 sync pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.17 flag pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 phase current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 peak current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 auto-adjusted decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3 auto-adjusted fast decay during the falling steps . . . . . . . . . . . . . . . . . . . 28 7.4 torque regulation (output current amplitude regulation) . . . . . . . . . . . . . . 29 8 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 registers and flags description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1.1 abs_pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.2 el_pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.3 mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.4 tval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.5 t_fast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.6 ton_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.7 toff_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.8 adc_out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1.9 ocd_th . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1.10 step_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.11 alarm_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.12 config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.13 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2 application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.1 command management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.2 nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2.3 setparam (param, value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2.4 getparam (param) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2.5 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2.6 disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2.7 getstatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
list of tables l6474 4/51 doc id 022529 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. typical application values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8. cl values according to external oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. registers map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. el_pos register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 11. torque regulation by tval_hold, tval_acc, tval_dec and tval_run registers . 34 table 12. t_fast register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 13. maximum fast decay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. minimum on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. minimum off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16. adc_out value and torque regulation feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. overcurrent detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18. step_mode register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19. step mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 20. sync signal source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 21. alarm_en register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 22. config register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 23. oscillator management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 24. overcurrent event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 25. programmable power bridge output slew-rate values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 26. external torque regulation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 27. switching period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 28. status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 29. status register dir bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 30. application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 31. nop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 32. setparam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 33. getparam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 34. hardstop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 35. disable command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 36. getstatus command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 37. htssop28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 38. powerso36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 39. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
l6474 list of figures doc id 022529 rev 2 5/51 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. htssop28 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. powerso36 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. bipolar stepper motor control application using l6474 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. charge pump circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. normal mode and microstepping (16 microsteps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. oscin and oscout pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. internal 3 v linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. peak current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. adaptive decay - fast decay tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. adaptive decay - switch from normal to slow+fast decay mode and vice versa . . . . . . . . . 28 figure 12. fast decay tuning during the falling steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13. spi timings diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 14. daisy-chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15. command with three-byte argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 16. command with three-byte response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 figure 17. command response aborted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 18. htssop28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 19. powerso36 drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
block diagram l6474 6/51 doc id 022529 rev 2 1 block diagram figure 1. block diagram !-v 9 9rowdjh5hj $'& ([w2vfgulyhu &orfnjhq 0+] 2vfloodwru &kdujh sxps 9 '' 63, 5hjlvwhuv &rqwuro /rjlf &xuuhqw'$&v &rpsdudwruv 7hpshudwxuh vhqvlqj &xuuhqw vhqvlqj 67%<5(6 )/$* &6 &. 6'2 6', 6<1& ',5 67&. '*1' 9'' 26&,1 26&287 $'&,1 95(* &3 9%227 $*1' 3*1' 3*1' 96$ 96$ 287$ 287$ 96% 96% 287% 287% +6 $ /6 $ +6 $ /6 $ +6 % /6 % +6 % /6 % +6 $ /6 $ +6 $ /6 $ +6 % /6 % +6 % /6 % 9 '' 9 errw 9 errw 9 errw 9 errw
l6474 electrical data doc id 022529 rev 2 7/51 2 electrical data 2.1 absolute maximum ratings table 2. absolute maximum ratings symbol parameter test condition value unit v dd logic interface supply voltage 5.5 v v s motor supply voltage v sa = v sb = v s 48 v v gnd, diff differential voltage between agnd, pgnd and dgnd 0.3 v v boot bootstrap peak voltage 55 v v reg internal voltage regulator output pin and logic supply voltage 3.6 v v adcin integrated adc input voltage range (adcin pin) -0.3 to +3.6 v v osc oscin and oscout pin voltage range -0.3 to +3.6 v v out_diff differential voltage between v sa , out1 a , out2 a , pgnd and v sb , out1 b , out2 b , pgnd pins v sa = v sb = v s 48 v v logic logic inputs voltage range -0.3 to +5.5 v i out (1) r.m.s. output current 3 a i out_peak (1) pulsed output current t pulse < 1 ms 7 a t op operating junction temperature 150 c t s storage temperature range -55 to 150 c p tot total power dissipation (t a = 25 oc) (2) tbd w 1. maximum output current limit is related to metal connection and bonding characteristics. actual limit must satisfy maximum thermal dissipation constraints. 2. tbd.
electrical data l6474 8/51 doc id 022529 rev 2 2.2 recommended operating conditions 2.3 thermal data table 3. recommended operating conditions symbol parameter test condition value unit v dd logic interface supply voltage 3.3 v logic outputs 3.3 v 5 v logic outputs 5 v s motor supply voltage v sa = v sb = v s 8 45 v v out_diff differential voltage between v sa , out1 a , out2 a , pgnd and v sb , out1 b , out2 b , pgnd pins v sa = v sb = v s 45 v v reg,in logic supply voltage v reg voltage imposed by external source 3.2 3.3 v v adc integrated adc input voltage (adcin pin) 0 v reg v t j operating junction temperature -25 125 c table 4. thermal data symbol parameter package typ unit r thja thermal resistance junction-ambient htssop28 (1) 1. tbd. tbd c/w powerso36 (2) 2. tbd. tbd
l6474 electrical characteristics doc id 022529 rev 2 9/51 3 electrical characteristics v sa = v sb = 36 v; v dd = 3.3 v; internal 3 v regulator; t j = 25 c, unless otherwise specified. table 5. electrical characteristics symbol parameter test condition min. typ. max. unit general v sthon v s uvlo turn-on threshold 7.5 8.2 8.9 v v sthoff v s uvlo turn-off threshold 6.6 7.2 7.8 v v sthhyst v s uvlo threshold hysteresis 0.7 1 1.3 v i q quiescent motor supply current internal oscillator selected; v reg = 3.3 v ext; cp floating 0.5 0.65 ma t j(wrn) thermal warning temperature 130 c t j(sd) thermal shutdown temperature 160 c charge pump v pump voltage swing for charge pump oscillator 10 v f pump,min minimum charge pump oscillator frequency (1) 660 khz f pump,max maximum charge pump oscillator frequency (1) 800 khz i boot average boot current f sw,a = f sw,b = 15.6 khz pow_sr = ?10? 1.1 1.4 ma output dmos transistor r ds(on) high side switch on resistance t j = 25 c, i out = 3a 0.37 ? t j = 125 c, (2) i out = 3a 0.51 low side switch on resistance t j = 25 c, i out = 3a 0.18 t j = 125 c, (2) i out = 3a 0.23 i dss leakage current out = v s 3.1 ma out = gnd -0.3 t r rise time (3) pow_sr = '00', i out = +1a 100 ns pow_sr = '00', i out = -1a 80 pow_sr = ?11?, i out = 1a 100 pow_sr = ?10?, i out = 1a 200 pow_sr = ?01?, i out = 1a 300
electrical characteristics l6474 10/51 doc id 022529 rev 2 t f fall time (3) pow_sr = '00'; i out = +1a 90 ns pow_sr = '00'; i out = -1a 110 pow_sr = ?11?, i out = 1a 110 pow_sr = ?10?, i out = 1a 260 pow_sr = ?01?, i load = 1a 375 sr out_r output rising slew-rate pow_sr = '00', i out = +1a 285 v/s pow_sr = '00', i out = -1a 360 pow_sr = ?11?, i out = 1a 285 pow_sr = ?10?, i out = 1a 150 pow_sr = ?01?, i out = 1a 95 sr out_f output falling slew-rate pow_sr = '00', i out = +1a 320 v/s pow_sr = '00', i out = -1a 260 pow_sr = ?11?, i out = 1a 260 pow_sr = ?10?, i out = 1a 110 pow_sr = ?01?, i out = 1a 75 dead time and blanking t dt dead time (1) pow_sr = '00' 250 ns pow_sr = ?11?, f osc = 16 mhz 375 pow_sr = ?10?, f osc = 16 mhz 625 pow_sr = ?01?, f osc = 16 mhz 875 t blank blanking time (1) pow_sr = '00' 250 ns pow_sr = ?11?, f osc = 16 mhz 375 pow_sr = ?10?, f osc = 16 mhz 625 pow_sr = ?01?, f osc = 16 mhz 875 source-drain diodes v sd,hs high side diode forward on voltage i out = 1 a 1 1.1 v v sd,ls low side diode forward on voltage i out = 1 a 1 1.1 v t rrhs high side diode reverse recovery time i out = 1 a 30 ns t rrls low side diode reverse recovery time i out = 1 a 100 ns table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
l6474 electrical characteristics doc id 022529 rev 2 11/51 logic inputs and outputs v il low logic level input voltage 0.8 v v ih high logic level input voltage 2 v i ih high logic level input current (4) v in = 5 v 1 a i il low logic level input current (5) v in = 0 v -1 a v ol low logic level output voltage (6) v dd = 3.3 v, i ol = 4 ma 0.3 v v dd = 5 v, i ol = 4 ma 0.3 v oh high logic level output voltage v dd = 3.3 v, i oh = 4 ma 2.4 v v dd = 5 v, i oh = 4 ma 4.7 r pu r pd cs pull-up and stby pull-down resistors cs = gnd; stby/rst = 5 v 335 430 565 k ? r pudir dir input pull-up resistance dir = gnd 60 85 110 k ? i logic internal logic supply current 3.3 v v reg externally supplied, internal oscillator 3.7 4.3 ma i logic,stby standby mode internal logic supply current 3.3 v v reg externally supplied 2 2.5 a f stck step clock input frequency 2 mhz internal oscillator and external oscillator driver f osc,i internal oscillator frequency t j = 25 c, v reg = 3.3 v -3% 16 +3% mhz f osc,e programmable external oscillator frequency 8 32 mhz v oscouth oscout clock source high level voltage internal oscillator 3.3 v v reg externally supplied; i oscout = 4 ma 2.4 v v oscoutl oscout clock source low level voltage internal oscillator 3.3 v v reg externally supplied; i oscout = 4 ma 0.3 v t roscout t foscout oscout clock source rise and fall time internal oscillator 20 ns t extosc internal to external oscillator switching delay 3 ms t intosc external to internal oscillator switching delay 1.5 s spi f ck,max maximum spi clock frequency (7) 5 mhz t rck t fck spi clock rise and fall time (7) c l = 30 pf 25 ns t hck t lck spi clock high and low time (7) 75 ns t setcs chip select set-up time (7) 350 ns table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
electrical characteristics l6474 12/51 doc id 022529 rev 2 t holcs chip select hold time (7) 10 ns t discs deselect time (7) 800 ns t setsdi data input set-up time (7) 25 ns t holsdi data input hold time (7) 20 ns t ensdo data output enable time (7) 38 ns t dissdo data output disable time (7) 47 ns t vsdo data output valid time (7) 57 ns t holsdo data output hold time (7) 37 ns current control i step,max max. programmable reference current 4 a i step,min min. programmable reference current 31 ma overcurrent protection i ocd,max maximum programmable overcurrent detection threshold ocd_th = ?1111? 6 a i ocd,min minimum programmable overcurrent detection threshold ocd_th = ?0000? 0.375 a i ocd,res programmable overcurrent detection threshold resolution 0.375 a t ocd,flag ocd to flag signal delay time di out /d t = 350a/s 650 1000 ns t ocd,sd ocd to shut down delay time di out /d t = 350a/s pow_sr = '10' 600 s standby i qstby quiescent motor supply current in standby conditions v s = 8 v 26 34 a v s = 36 v 30 36 t stby,min minimum standby time 10 s t logicwu logic power-on and wake-up time 38 45 s t cpwu charge pump power-on and wake-up time power bridges disabled, c p = 10 nf, c boot = 220 nf 650 s internal voltage regulator v reg voltage regulator output voltage 2.9 3 3.2 v i reg voltage regulator output current 40 ma v reg, drop voltage regulator output voltage drop i reg = 40 ma 50 mv i reg,stby voltage regulator standby output current 10 ma integrated analog to digital converter n adc analog to digital converter resolution 5 bit table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
l6474 electrical characteristics doc id 022529 rev 2 13/51 v adc,ref analog to digital converter reference voltage v reg v f s analog to digital converter sampling frequency f osc / 512 khz 1. accuracy depends on oscillator frequency accuracy. 2. tested at 25 c in a restricted range and guaranteed by characterization. 3. rise and fall time depends on motor supply voltage value. refer to sr out values ( table 5 ) in order to evaluate the actual rise and fall time. 4. not valid for stby/rst pins which have internal pull-down resistor. 5. not valid for sw and cs pins which have internal pull-up resistor. 6. flag and sync open drain outputs included. 7. see figure 13 ? spi timings diagram for details. table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
pin connection l6474 14/51 doc id 022529 rev 2 4 pin connection figure 2. htssop28 pin connection (top view) figure 3. powerso36 pin connection (top view) rst dir 1(/% 065" 065" 74" 74" 45#:345 48 "%$*/ 04$*/ 04$065 065# "(/% $1 7#005 74# 74# 73&( 065# 065" 065" 74" 74" 45$, '-"( $4 #64:=4:/$ &1"% %(/% 4%* 065# $, 4%0 7%% 74# 74# 1(/% 065#
l6474 pin connection doc id 022529 rev 2 15/51 4.1 pin list table 6. pin description n. name type function 17 vdd power logic outputs supply voltage (pull-up reference) 6 vreg power internal 3 v voltage regulator output and 3.3 v external logic supply 7 oscin analog input oscillator pin 1. to connect an external oscillator or clock source. if this pin is unused, it should be left floating. 8 oscout analog output oscillator pin 2. to connect an external oscillator. when the internal oscillator is used this pin can supply 2/4/8/16 mhz. if this pin is unused, it should be left floating. 10 cp output charge pump oscillator output 11 vboot supply voltage bootstrap voltage needed for driving the high side power dmos of both bridges (a and b) 5 adcin analog input internal analog to digital converter input 2 vsa power supply full bridge a power supply pin. it must be connected to vsb 26 12 vsb power supply full bridge b power supply pin. it must be connected to vsa 16 27 pgnd ground power ground pin 13 1 out1a power output full bridge a output 1 28 out2a power output full bridge a output 2 14 out1b power output full bridge b output 1 15 out2b power output full bridge b output 2 9 agnd ground analog ground 4 dir logical input direction input 21 dgnd ground digital ground 22 sync open drain output synchronization signal. 18 sdo logic output data output pin for serial interface 20 sdi logic input data input pin for serial interface 19 ck logic input serial interface clock 23 cs logic input chip select input pin for serial interface 24 flag open drain output status flag pin. an internal open drain transistor can pull the pin to gnd when a programmed alarm condition occurs (step loss, ocd, thermal pre-warning or shutdown, uvlo, wrong command, non performable command) 3 stby\rst logic input standby and reset pin. low logic level resets the logic and puts the device into standby mode. if not used, should be connected to vdd
pin connection l6474 16/51 doc id 022529 rev 2 25 stck logic input step clock input epad exposed pad ground internally connected to pgnd, agnd and dgnd pins table 6. pin description (continued) n. name type function
l6474 typical applications doc id 022529 rev 2 17/51 5 typical applications figure 4. bipolar stepper motor control application using l6474 table 7. typical application values name value c vs 220 nf c vspol 100 f c reg 100 nf c regpol 47 f c dd 100 nf c ddpol 10 f d1 charge pump diodes c boot 220 nf c fly 10 nf r pu 39 k ? r sw 100 ? c sw 10 nf /54! !$#). 6"//4 #0 63" 63! 6$$ 62%' 0'.$ !'.$ $'.$ /54" /54" /54! #+ 34#+ 3$/ 3$) /3#). /3#/54 $)2 #3 39.# &,!' -otor 34"9 # &,9 # 63 # "//4 # 630/, # $$ # $$0/, 2 05 2 05 6 3 , 6 6 $ (/34 30) '0)/
functional description l6474 18/51 doc id 022529 rev 2 6 functional description 6.1 device power-up at power-up end, the device state is the following: registers are set to default internal logic is driven by internal oscillator and a 2 mhz clock is provided by the oscout pin bridges are disabled (high z) uvlo bit in status register is forced low (fail condition) flag output is forced low. during power-up the device is under reset (all logic io disabled and power bridges in high impedance state) until the following conditions are satisfied: v s is greater than v sthon v reg is greater than v regth = 2.8 v typical internal oscillator is operative. 6.2 logic i/o pins cs , ck, sdi, stck, dir and stby\rst are ttl/cmos 3.3 v-5 v compatible logic inputs. pin sdo is a ttl/cmos compatible logic output. vdd pin voltage sets the logic output pin voltage range; when it is connected to vreg or 3.3 v external supply voltage, the output is 3.3 v compatible. when vdd is connected to a 5 v supply voltage, sdo is 5 v compatible. vdd is not internally connected to v reg , an external connection is always needed. a 10 f capacitor should be connected to the vdd pin in order to obtain a proper operation. pins flag and sync are open drain outputs. 6.3 charge pump to ensure the correct driving of the high side integrated mosfets, a voltage higher than the motor power supply voltage needs to be applied to the vboot pin. the high side gate driver supply voltage vboot is obtained through an oscillator and a few external components realizing a charge pump (see figure 5 ).
l6474 functional description doc id 022529 rev 2 19/51 figure 5. charge pump circuitry 6.4 microstepping the driver is able to divide the single step into up to 16 microsteps. stepping mode can be programmed by step_sel parameter in step_mode register (see ta bl e 1 9 ). step mode can only be changed when bridges are disabled. every time the step mode is changed, the electrical position (i.e. the point of microstepping sinewave that is generated) is reset to the first microstep and the absolute position counter value (see section 6.5 ) becomes meaningless. figure 6. normal mode and microstepping (16 microsteps)
functional description l6474 20/51 doc id 022529 rev 2 6.5 absolute position counter an internal 22 bit register (abs_pos) takes memory of motor motion according to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). the position range is from -2 21 to +2 21 -1 () steps (see section 9.1.1 ). 6.6 step sequence control the motor movement is defined by the step clock signal applied to the stck pin. at each step clock rising edge, the motor is moved by one microstep in the direction selected by dir input (high for forward direction and low for reverse direction) and absolute position is consequently updated. 6.7 enable and disable commands the power stage of the device can be enabled and disabled through the respective spi commands. the enable command turns on the power outputs and starts the current control algorithm. the phase currents are controlled according to present el_pos value. if a fault condition requires the power stage to be disabled, the command is ignored. the disable command immediately forces the power outputs in a high impedance condition.
l6474 functional description doc id 022529 rev 2 21/51 6.8 internal oscillator and oscillator driver the control logic clock can be supplied by the internal 16 mhz oscillator, an external oscillator (crystal or ceramic resonator) or a direct clock signal. these working modes can be selected by ext_clk and osc_sel parameters in the config register (see ta bl e 2 3 ). at power-up the device starts using the internal oscillator and provides a 2 mhz clock signal on the oscout pin. attention: in any case, before changing clock source configuration, a hardware reset is mandatory. switching to different clock configurations during operation could cause unexpected behavior. 6.8.1 internal oscillator in this mode the internal oscillator is activated and oscin is unused. if oscout clock source is enabled, the oscout pin provides a 2, 4, 8 or 16 mhz clock signal (according to osc_sel value); otherwise it is unused (see figure 7 ). 6.8.2 external clock source two types of external clock source can be selected: crystal/ceramic resonator or direct clock source. four programmable clock frequencies are available for each external clock source: 8, 16, 24 and 32 mhz. when an external crystal/resonator is selected, the oscin and oscout pins are used to drive the crystal/resonator (see figure 7 ). the crystal/resonator and load capacitors (cl) must be placed as close as possible to the pins. refer to ta bl e 8 for the choice of the load capacitor value according to the external oscillator frequency. if a direct clock source is used, it must be connected to the oscin pin and the oscout pin supplies the inverted oscin signal (see figure 7 ). table 8. cl values according to external oscillator frequency crystal/resonator freq. (1) 1. first harmonic resonance frequency. cl (2) 2. lower esr value allows driving greater load capacitors. 8 mhz 25 pf (esr max = 80 ? ) 16 mhz 18 pf (esr max = 50 ? ) 24 mhz 15 pf (esr max = 40 ? ) 32 mhz 10 pf (esr max = 40 ? )
functional description l6474 22/51 doc id 022529 rev 2 figure 7. oscin and oscout pin configurations note: when oscin is unused, it should be left floating. when oscout is unused it should be left floating. 6.9 overcurrent detection when the current in any of the power mosfets exceeds a programmed overcurrent threshold, the status register ocd flag is forced low until the overcurrent event has expired and a getstatus command is sent to the ic (see paragraphs 9.1.13 and 9.1.9 ). overcurrent event expires when all the power mosfet currents fall below the programmed overcurrent threshold. the overcurrent threshold can be programmed through the ocd_th register in one of 16 available values ranging from 375 ma to 6 a with steps of 375 ma (see ta b l e 9 , paragraph 9.1.9 ). it is possible to set whether or not an overcurrent event causes the mosfet turn-off (bridges in high impedance status) acting on the oc_sd bit in the config register (see paragraph 9.1.12 ). the ocd flag in the status register is raised anyway (see ta b l e 2 8 , paragraph 9.1.13 ). when the ic outputs are turned off by an ocd event, they cannot be turned on until the ocd flag is released by a getstatus command.
l6474 functional description doc id 022529 rev 2 23/51 attention: the overcurrent shutdown is a critical protection feature. it is not recommended to disable it. 6.10 undervoltage lock-out (uvlo) the l6474 provides a motor supply uvlo protection. when the motor supply voltage falls below the vsthoff threshold voltage, the status register uvlo flag is forced low. when a getstatus command is sent to the ic, and the undervoltage condition has expired, the uvlo flag is released (see paragraphs 9.1.13 and 9.2.7 ). undervoltage condition expires when the motor supply voltage goes over the vsthon threshold voltage. when the device is in undervoltage condition no motion can be performed. the uvlo flag is forced low by logic reset (power-up included) even if no uvlo condition is present. 6.11 thermal warning and thermal shutdown an internal sensor allows the l6474 to detect when the device internal temperature exceeds a thermal warning or an overtemperature threshold. when the thermal warning threshold (t j(wrn) ) is reached, the th_wrn bit in the status register is forced low (see paragraph 9.1.13 ) until the temperature decreases below t j(wrn) and a getstatus command is sent to the ic (see paragraphs 9.1.13 and 9.2.7 ). when the thermal shutdown threshold (t j(off) ) is reached, the device goes into thermal shutdown condition: the th_sd bit in the status register is forced low, the power bridges are disabled, bridges in high impedance state and the hiz bit in the status register are raised (see paragraph 9.1.13 ). thermal shutdown condition only expires when the temperature goes below the thermal warning threshold (t j(wrn) ). on exiting thermal shutdown condition, the bridges are still disabled (hiz flag high). 6.12 reset and standby the device can be reset and put into standby mode through a dedicated pin. when the stby \rst pin is driven low, the bridges are left open (high z state), the internal charge pump is stopped, the spi interface and control logic are disabled, and the internal 3 v voltage regulator maximum output current is reduced to i reg,stby ; as a result the l6474 heavily reduces the power consumption. at the same time the register values are reset to default and all protection functions are disabled. stby\rst input must be forced low at least for tstby, min. in order to ensure the complete switch to standby mode. on exiting standby mode, as well as for ic power-up, a delay of up to tlogicwu must be given before applying a new command to allow proper oscillator and logic startup and a delay of up to tcpwu must be given to allow the charge pump startup. on exiting standby mode the bridges are disabled (hiz flag high).
functional description l6474 24/51 doc id 022529 rev 2 attention: it is not recommended to reset the device when outputs are active. the device should be switched to high impedance state before being reset. 6.13 programmable dmos slew-rate, dead-time and blanking-time using the pow_sr parameter in the config register, it is possible to set the commutation speed of the power bridges output (see ta b l e 2 5 , paragraph 9.1.17 ). 6.14 integrated analog to digital converter the l6474 integrates a n adc bit ramp-compare analog to digital converter with a reference voltage equal to vreg. the analog to digital converter input is available through the adcin pin and the conversion result is available in the adc_out register (see paragraph 9.1.13 ). sampling frequency is equal to the clock frequency divided by 512. the adc_out value can be used for the torque regulation or is at the user?s disposal. 6.15 internal voltage regulator the l6474 integrates a voltage regulator which generates a 3 v voltage starting from the motor power supply (vsa and vsb). in order to make the voltage regulator stable, at least 22 f should be connected between the vreg pin and ground (suggested value is 47 f). the internal voltage regulator can be used to supply the vdd pin in order to make the device digital output range 3.3 v compatible ( figure 8 ). a digital output range 5 v compatible can be obtained connecting the vdd pin to an external 5 v voltage source. in both cases, a 10 f capacitance should be connected to the vdd pin in order to obtain a correct operation. the internal voltage regulator is able to supply a current up to i reg,max , internal logic consumption included (i logic ). when the device is in standby mode the maximum current that can be supplied is i reg , stby , internal consumption included (i logic , stby ). if an external 3.3 v regulated voltage is available, it can be applied to the vreg pin in order to supply all the internal logic and avoid power dissipation of the internal 3 v voltage regulator ( figure 8 ). the external voltage regulator should never sink current from the vreg pin.
l6474 functional description doc id 022529 rev 2 25/51 figure 8. internal 3 v linear regulator 6.16 sync pin this pin works as a synchronization signal: the output status is an echo of one of the bits of the el_pos register according to a sync_sel and step_sel parameter combination (see paragraph 9.1.10 ). 6.17 flag pin by default, an internal open drain transistor pulls the flag pin to ground when at least one of the following conditions occurs: power-up or standby/reset exit overcurrent detection thermal warning thermal shutdown uvlo switch turn-on event wrong command non performable command. it is possible to mask one or more alarm conditions by programming the alarm_en register (see paragraph 9.1.11 , ta bl e 2 1 ). if the corresponding bit of the alarm_en register is low, the alarm condition is masked and it does not cause a flag pin transition; all other actions imposed by alarm conditions are performed anyway. in case of daisy-chain configuration, flag pins of different ics can be or-wired to save host controller gpios. 6 2%' 6 $$ 6 3! 6 3" !'.$ $'.$ 6 $$ m # )# 6 s 6 6 2%' 6 $$ 6 3! 6 3" !'.$ $'.$ )# 6 2%' 6 s 6 "!4 ,ogigsuppliedb y ).4%2.!, v oltageregulator ,ogigsuppliedb y %84%2.!, v oltageregulator
phase current control l6474 26/51 doc id 022529 rev 2 7 phase current control the l6474 performs a peak current control technique described in detail in section 7.1 . furthermore, the l6474 automatically selects the best decay mode in order to follow the current profile. current control algorithm parameters can be programmed by t_fast, ton_min, toff_min and config registers (see paragraphs 9.1.5 , 9.1.6 , 9.1.7 and 9.1.12 for details). the current amplitude can be set through the tval register (see paragraph 9.1.4 ). the output current amplitude can also be regulated by adcin voltage value (see paragraph 6.14 ). each bridge is driven by an independent control system that shares with the other bridge the control parameters only. 7.1 peak current control the l6474 implements a peak current control algorithm with fixed off time. the control cycle begins in the on state: the opposite high side dmos low side dmos of the power bridges are turned on according to the required current direction. in this way, the phase current is increased according to the electrical model of the motor. when the target current value is reached (this value is internally generated according to the present value of the el_pos register), the device switches to the off state in order to make the phase current decay. during the off state both slow and fast decay can be performed; the better decay combination is automatically selected by l6472 as described in section 7.2 . the t off value sets through the toff parameter of the config register and the value of the toff_min register. if toff is greater than toff_min, it defines the off time of the system. otherwise the toff_min value is used. figure 9. peak current control
l6474 phase current control doc id 022529 rev 2 27/51 7.2 auto-adjusted decay mode during the current control, the device automatically selects the best decay mode in order to follow the current profile reducing the current ripple. at reset, the off time is performed by turning on both the low side mos of the power stage and the current recirculates in the lower half of the bridge (slow decay). if, during a pwm cycle, the target current threshold is reached in a time shorter than the ton_min value, a fast decay of toff_fast/8 (t_fast register) is immediately performed, turning on the opposite mos of both half bridges and the current recirculates back to the supply bus. after this time, the bridge returns to the on state: if the time needed to reach the target current value is still less than ton_min, a new fast decay is performed with a period twice the previous one. otherwise, the normal control sequence is followed as described in section 7.1. the maximum fast decay duration is set by toff_fast value. figure 10. adaptive decay - fast decay tuning when two or more fast decays are performed with present target current, the control system adds a fast decay at the end of every off time, keeping the off state duration constant (t off is split into t off,slow and t off,fast ). when the current threshold is increased by a micro-step change (rising step), the system returns to normal decay mode (slow decay only) and the t fast value is halved. reaching the current sinewave zero crossing causes the current control system to return to the reset state. referencecurrent st fastdeca y 4fast4/&&?&!34 nd fastdeca y
4fast4/&&?&!34
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phase current control l6474 28/51 doc id 022529 rev 2 7.3 auto-adjusted fast decay during the falling steps when the target current is decreased by a micro-step change (falling step), the device performs a fast decay in order to reach the new value as fast as possible. anyway, exceeding the fast duration could cause a strong ripple on the step change. the l6474 automatically adjusts these fast decays reducing the current ripple. at reset, the fast decay value (t fall ) is set to fall_step/4 (t_fast register). the t fall value is doubled every time, within the same falling step, an extra fast decay is necessary to obtain an on time greater than ton_min. the maximum t fall value is equal to fall_step. at the next falling step, the system uses the last t fall value of the previous falling step. stopping the motor or reaching the current sinewave zero crossing causes the current control system to return to the reset state. figure 11. adaptive decay - switch from normal to slow+fast decay mode and vice versa time time reference current 1 st fast decay target current is increased (raising step) 2 nd fast decay system returns to slow decay mode and t fast value is halved switch to fast + slow decay mode t fast t off,fast t off,slow t off t off reference current
l6474 phase current control doc id 022529 rev 2 29/51 figure 12. fast decay tuning during the falling steps 7.4 torque regulation (output current amplitude regulation) the output current amplitude can be regulated in two ways: writing the tval register or varying the adcin voltage value. the en_tqreg bit (config register) sets the torque regulation method. if this bit is high, adc_out prevalue is used to regulate output current amplitude (see paragraph 9.1.8 ). otherwise the internal analog to digital converter is at the user?s disposal and the output current amplitude is managed by the tval register (see paragraph 9.1.4 ). the voltage applied to the adcin pin is sampled at fs frequency and converted in an nadc bit digital signal. the analog to digital conversion result is available in the adc_out register. &allingstep st fastdeca y t &!,, &!,,?34%0 &allingstep st fastdeca y t &!,, &!,,?34%0 nd fastdeca y t &!,, &!,,?34%0 4ime referencecurrent
serial interface l6474 30/51 doc id 022529 rev 2 8 serial interface the integrated 8-bit serial peripheral interface (spi) is used for a synchronous serial communication between the host microprocessor (always master) and the l6474 (always slave). the spi uses chip select (cs ), serial clock (ck), serial data input (sdi) and serial data output (sdo) pins. when cs is high, the device is unselected and the sdo line is inactive (high-impedance). the communication starts when cs is forced low. the ck line is used for synchronization of data communication. all commands and data bytes are shifted into the device through the sdi input, most significant bit first. the sdi is sampled on the rising edges of the ck. all output data bytes are shifted out of the device through the sdo output, most significant bit first. the sdo is latched on the falling edges of the ck. when a return value from the device is not available, an all zero byte is sent. after each byte transmission, the cs input must be raised and be kept high for at least tdiscs in order to allow the device to decode the received command and put the return value into the shift register. all timing requirements are shown in figure 13 (see respective section 3: electrical characteristics for values). multiple devices can be connected in a daisy-chain configuration, as shown in figure 14 . figure 13. spi timings diagram
l6474 serial interface doc id 022529 rev 2 31/51 figure 14. daisy-chain configuration
programming manual l6474 32/51 doc id 022529 rev 2 9 programming manual 9.1 registers and flags description the following is a map of the user registers available (detailed description in respective paragraphs): table 9. registers map address [hex] register name register function len. [bit] reset hex reset value remarks (1) h01 abs_pos current position 22 000000 0 r, wr h02 el_pos electrical position 9 000 0 r, wr h03 mark mark position 22 000000 0 r, wr h04 reserved reserved address 24 h05 reserved reserved address 16 h06 reserved reserved address 16 h07 reserved reserved address 16 h08 reserved reserved address 16 h15 reserved reserved address 16 r, wr h09 tval reference current 7 29 1.3125 a r, wr h0a reserved reserved address 8 h0b reserved reserved address 8 h0c reserved reserved address 8 h0d reserved reserved address 16 h0e t_fast fast decay/fall step time 8 19 1 s / 5 s r, wh h0f ton_min minimum on time 7 29 20.5 s r, wh h10 toff_min minimum off time 7 29 20.5 s r, wh h11 reserved reserved address 8 h12 adc_out adc output 5 xx (2) r h13 ocd_th ocd threshold 4 8 3.38a r, wr h14 reserved reserved address 8 h16 step_mode step mode 8 7 16 microsteps, no synch r, wh h17 alarm_en alarms enables 8 ff all alarms enabled r, wr h18 config ic configuration 16 2e88 internal oscillator, 2 mhz oscout clock, supply voltage compensation disabled, overcurrent shutdown enabled, slew- rate = 290 v/s toff = 40 s r, wh
l6474 programming manual doc id 022529 rev 2 33/51 9.1.1 abs_pos the abs_pos register contains the current motor absolute position in agreement to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). the value is in 2's complement format and it ranges from -2 21 to +2 21 -1. at power-on the register is initialized to ?0? (home position). 9.1.2 el_pos the el_pos register contains the current electrical position of the motor. the two msbits indicate the current step and the other bits indicate the current microstep (expressed in step/128) within the step. when the el_pos register is written by the user the new electrical position is instantly imposed. when the el_pos register is written its value must be masked in order to match with the step mode selected in the step_mode register in order to avoid a wrong microstep value generation (see paragraph 9.1.10 ); otherwise the resulting microstep sequence is incorrect. any attempt to write the register when the outputs are enabled causes the command to be ignored and the notperf_cmd flag to rise (see paragraph 9.1.13 ). 9.1.3 mark the mark register contains an absolute position called mark, according to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). it is in 2's complement format and it ranges from -2 21 to +2 21 -1. 9.1.4 tval the tval register contains the current value that is assigned to the torque regulation dac. the available range is from 31.25 ma to 4 a with a resolution of 31.25 ma, as shown in ta b l e 2 . h19 status status 16 xxxx (2) high impedance state, uvlo/reset flag set. r h1a reserved reserved address h1b reserved reserved address 1. r: readable, wh: writable only when outputs are in high impedance, wr: always writable. 2. according to startup conditions. table 9. registers map (continued) address [hex] register name register function len. [bit] reset hex reset value remarks (1) table 10. el_pos register bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 step microstep
programming manual l6474 34/51 doc id 022529 rev 2 9.1.5 t_fast the t_fast register contains the maximum fast decay time (toff_fast) and the maximum fall step time (fall_step) used by the current control system (see sections 7.2 and 7.3 for details): table 12. t_fast register the available range for both parameters is from 0.5 s to 8 s. any attempt to write to the register when the outputs are enabled causes the command to be ignored and the notperf_cmd to rise (see section 9.1.13 ). 9.1.6 ton_min the ton_min register contains the minimum on time value used by the current control system (see section 7.2 ). the available range for both parameters is from 0.5 s to 64 s. table 11. torque regulation register tval [6..0] output current amplitude 0 0 0 0 0 0 0 31.25 ma 0 0 0 0 0 0 1 62.5 ma ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 3.969 a 1 1 1 1 1 1 1 4 a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 toff_fast fast_step table 13. maximum fast decay times toff_fast [3..0] fast_step[3..0] fast decay time 0 0 0 0 0.5 s 0 0 0 1 1 s ? ? ? ? ? 1 1 1 0 7.5 s 1 1 1 1 8 s
l6474 programming manual doc id 022529 rev 2 35/51 any attempt to write to the register when the outputs are enabled causes the command to be ignored and the notperf_cmd to rise (see section 9.1.13 ). 9.1.7 toff_min the toff_min register contains the minimum off time value used by the current control system (see section 7.1 for details).this parameter imposes the off time of the current control system only if its value is greater than the tsw one. the available range for both parameters is from 0.5 s to 64 s. any attempt to write to the register when the outputs are enabled causes the command to be ignored and the notperf_cmd to rise (see section 9.1.13 ). table 14. minimum on time time 0 0 0 0 0 0 0 0.5 s 0 0 0 0 0 0 1 1 s ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 63.5 s 1 1 1 1 1 1 1 64 s table 15. minimum off time time 0 0 0 0 0 0 0 0.5 s 0 0 0 0 0 0 1 1 s ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 63.5 s 1 1 1 1 1 1 1 64 s
programming manual l6474 36/51 doc id 022529 rev 2 9.1.8 adc_out the adc_out register contains the result of the analog to digital conversion of the adcin pin voltage. any attempt to write to the register causes the command to be ignored and the notperf_cmd flag to rise (see section 9.1.13 ). 9.1.9 ocd_th the ocd_th register contains the overcurrent threshold value (see section 6.9 for details). the available range is from 375 ma to 6 a, steps of 375 ma as shown in ta bl e 1 7 . table 16. adc_out value and torque regulation feature vadcin/ vreg adc_out [4..0] output current amplitude 0 0 0 0 0 0 125 ma 1/32 0 0 0 0 1 250 ma ? ? ? ? ? ? ? 30/32 1 1 1 1 0 3.875 a 31/32 1 1 1 1 1 4 a table 17. overcurrent detection threshold ocd_th [3..0] overcurrent detection threshold 0 0 0 0 375 ma 0 0 0 1 750 ma ? ? ? ? ? 1 1 1 0 5.625 a 1 1 1 1 6 a
l6474 programming manual doc id 022529 rev 2 37/51 9.1.10 step_mode the step_mode register has the following structure: the step_sel parameter selects one of five possible stepping modes: every time the step mode is changed, the electrical position (i.e. the point of microstepping sinewave that is generated) is reset to the first microstep. warning: every time step_sel is changed the value in abs_pos register loses meaning and should be reset. any attempt to write the register when the outputs are enabled causes the command to be ignored and the notperf_cmd flag to rise (see paragraph 9.1.13 ). the sync output provides a synchronization signal according to sync_sel parameter. table 18. step_mode register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 sync_sel 1 (1) 1. when the register is written this bit should be set to 1. step_sel table 19. step mode selection step_sel[2..0] step mode 0 0 0 full step 0 0 1 half step 0 1 0 1/4 microstep 0 1 1 1/8 microstep 1 x x 1/16 microstep
programming manual l6474 38/51 doc id 022529 rev 2 the synchronization signal is obtained starting from electrical position information (el_pos register) according to ta b l e 1 0 : table 20. sync signal source sync_sel[2..0] source 0 0 0 el_pos[7] 0 0 1 el_pos[6] 0 1 0 el_pos[5] 0 1 1 el_pos[4] 1 0 0 el_pos[3] 1 0 1 unused (1) 1. when this value is selected the busy output is forced low. 1 1 0 unused (1) 1 1 1 unused (1)
l6474 programming manual doc id 022529 rev 2 39/51 9.1.11 alarm_en the alarm_en register allows to select which alarm signals are used to generate the flag output. if the respective bit of the alarm_en register is set high, the alarm condition forces the flag pin output down. 9.1.12 config the config register has the following structure: table 21. alarm_en register alarm_en bit alarm condition 0 (lsb) overcurrent 1 thermal shutdown 2 thermal warning 3 undervoltage 4 reserved 5 reserved 6 switch turn-on event 7 (msb) wrong or not performable command table 22. config register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0 toff pow_sr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oc_sd reserved en_tqreg 0 ext_clk osc_sel
programming manual l6474 40/51 doc id 022529 rev 2 the osc_sel and ext_clk bits set the system clock source: the oc_sd bit sets whether or not an overcurrent event causes the bridges to turn off; the ocd flag in the status register is forced low anyway: the pow_sr bits set the slew rate value of power bridge output: table 23. oscillator management ext_clk osc_sel[2..0] clock source oscin oscout 0 0 0 0 internal oscillator: 16 mhz unused unused 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 internal oscillator: 16 mhz unused supplies a 2 mhz clock 1 0 0 1 internal oscillator: 16 mhz unused supplies a 4 mhz clock 1 0 1 0 internal oscillator: 16 mhz unused supplies a 8 mhz clock 1 0 1 1 internal oscillator: 16 mhz unused supplies a 16 mhz clock 0 1 0 0 external crystal or resonator: 8 mhz crystal/resonator driving crystal/resonator driving 0 1 0 1 external crystal or resonator: 16 mhz crystal/resonator driving crystal/resonator driving 0 1 1 0 external crystal or resonator: 24 mhz crystal/resonator driving crystal/resonator driving 0 1 1 1 external crystal or resonator: 32 mhz crystal/resonator driving crystal/resonator driving 1 1 0 0 ext. clock source: 8 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal 1 1 0 1 ext. clock source: 16 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal 1 1 1 0 ext. clock source: 24 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal 1 1 1 1 ext. clock source: 32 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal table 24. overcurrent event oc_sd overcurrent event 1 bridges shut down 0 bridges do not shut down
l6474 programming manual doc id 022529 rev 2 41/51 the tqreg bit sets if the torque regulation (see section 7.4 ) is performed through the adcin voltage (external) or tval register (internal): the toff time is used by current control system. if its value is lower than the toff_min one, the off time is equal to toff_min. any attempt to write the config register when the outputs are enabled causes the command to be ignored and the notperf_cmd flag to rise (see section 9.1.13 ). 9.1.13 status when hiz flag is high, it indicates that the bridges are in high impedance state. enable command makes the device exit from high z state unless error flags forcing a high z state are active. table 25. programmable power bridge output slew-rate values pow_sr [1..0] output slew-rate (1) [v/s] (1) 1. see srout_r and srout_f parameters in the electrical characteristics table 5 for details. 0 0 180 0 1 180 1 0 290 1 1 530 table 26. external torque regulation enable tqreg external torque regulation enable 0 internal registers 1 adc input table 27. off time toff [4..0] off time 0 0 0 0 0 4 s 0 0 0 0 1 4 s 0 0 0 1 0 8 s ? ? ? ? ? ? 1 1 1 1 1 124 s table 28. status register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1 1 1 ocd th_sd th_wrn uvlo wrong_cmd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notperf_cmd 0 0 dir 0 0 1 hiz
programming manual l6474 42/51 doc id 022529 rev 2 the uvlo flag is active low and is set by an undervoltage lock-out or reset events (power- up included). the th_wrn, th_sd, ocd flags are active low and indicate, respectively, thermal warning, thermal shutdown and overcurrent detection events. the notperf_cmd and wrong_cmd flags are active high and indicate, respectively, that the command received by spi can't be performed or does not exist at all. the uvlo, th_wrn, th_sd, ocd, notperf_cmd and wrong_cmd flags are latched: when the respective conditions make them active (low or high), they remain in that state until a getstatus command is sent to the ic. the dir bit indicates the current motor direction: any attempt to write to the register causes the command to be ignored and the notperf_cmd to rise (see paragraph 9.1.13 ). 9.2 application commands the commands summary is given in ta b l e 3 0 . 9.2.1 command management the host microcontroller can control motor motion and configure the l6474 through a complete set of commands. all commands are composed of a single byte. after the command byte, some bytes of arguments should be needed (see figure 15 ). argument length can vary from 1 to 3 bytes. table 29. status register dir bit dir motor direction 1 forward 0 reverse table 30. application commands command mnemonic command binary code action [7..5] [4] [3] [2..1] [0] nop 000 0 0 00 0 nothing setparam(param,value) 000 [param] writes value in param register enable 101 1 1 00 0 enable the power stage disable 101 0 1 00 0 puts the bridges in high impedance status immediately getstatus 110 1 0 00 0 returns the status register value reserved 111 0 1 01 1 reserved command reserved 111 1 1 00 0 reserved command
l6474 programming manual doc id 022529 rev 2 43/51 figure 15. command with three-byte argument by default, the device returns an all zeroes response for any received byte, the only exceptions are getparam and getstatus commands. when one of these commands is received, the following response bytes represent the related register value (see figure 16 ). response length can vary from 1 to 3 bytes. figure 16. command with three-byte response during response transmission, new commands can be sent. if a command requiring a response is sent before the previous response is completed, the response transmission is aborted and the new response is loaded into the output communication buffer (see figure 17 ). figure 17. command response aborted when a byte that does not correspond to a command is sent to the ic it is ignored and the wrong_cmd flag in the status register is raised (see section 9.1.13 ). 9.2.2 nop nothing is performed. table 31. nop command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 0 0 from host
programming manual l6474 44/51 doc id 022529 rev 2 9.2.3 setparam (param, value) the setparam command sets the param register value equal to value; param is the respective register address listed in ta b l e 1 6 . the command should be followed by the new register value (most significant byte first). the number of bytes composing the value argument depends on the length of the target register (see ta b l e 1 6 ). some registers cannot be written (see ta b l e 1 6 ); any attempt to write one of those registers causes the command to be ignored and the wrong_cmd flag to rise at the end of command byte, the same is true when an unknown command code is sent (see section 9.1.13 ). some registers can only be written in particular conditions (see ta bl e 1 6 ); any attempt to write one of those registers when the conditions are not satisfied causes the command to be ignored and the notperf_cmd flag to rise at the end of last argument byte (see section 9.1.13 ). any attempt to set an inexistent register (wrong address value) causes the command to be ignored and the wrong_cmd flag to rise at the end of command byte, the same is true when an unknown command code is sent. 9.2.4 getparam (param) this command reads the current param register value; param is the respective register address listed in ta b l e 1 6 . the command response is the current value of the register (most significant byte first). the number of bytes composing the command response depends on the length of the target register (see ta b l e 1 6 ). the returned value is the register one at the moment of getparam command decoding. if register values change after this moment the response is not accordingly updated. all registers can be read anytime. table 32. setparam command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 param from host value byte 2 (if needed) value byte 1 (if needed) value byte 0 table 33. getparam command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 param from host ans byte 2 (if needed) to host ans byte 1 (if needed) to host ans byte 0 to host
l6474 programming manual doc id 022529 rev 2 45/51 any attempt to read an inexistent register (wrong address value) causes the command to be ignored and the wrong_cmd flag to rise at the end of command byte, the same is true when an unknown command code is sent. 9.2.5 enable the enable command turns on the power stage of the device. when the motor is in high-impedance state, an enable command forces the bridges to exit from high impedance state. this command can be given anytime and is immediately executed. 9.2.6 disable the disable command immediately disables the power bridges (high-impedance state) and raises the hiz flag. this command can be given anytime and is immediately executed. 9.2.7 getstatus the getstatus command returns the status register value. the getstatus command resets the status register warning flags. the command forces the system to exit from any error state. the getstatus command does not reset the hiz flag. table 34. hardstop command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0 1 1 1 0 0 0 from host table 35. disable command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0 1 0 1 0 0 0 from host table 36. getstatus command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 1 0 1 0 0 0 0 from host status msbyte to host status lsbyte to host
package mechanical data l6474 46/51 doc id 022529 rev 2 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 37. htssop28 mechanical data dim mm min. typ. max. a 1.2 a1 0.15 a2 0.8 1.0 1.05 b 0.19 0.3 c 0.09 0.2 d (1) 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs do not exceed 0.15 mm per side. 9.6 9.7 9.8 d1 5.5 e 6.2 6.4 6.6 e1 (2) 2. dimension ?e1? does not include interlead flash or prot rusions. interlead flash or protrusions do not exceed 0.25 mm per side. 4.3 4.4 4.5 e2 2.8 e 0.65 l 0.45 0.6 0.75 l1 1.0 k 0 8 aaa 0.1
l6474 package mechanical data doc id 022529 rev 2 47/51 figure 18. htssop28 mechanical data
package mechanical data l6474 48/51 doc id 022529 rev 2 table 38. powerso36 mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.60 0.1417 a1 0.10 0.30 0.003 0.0118 a2 3.30 0.1299 a3 0 0.10 0 0.0039 b 0.22 0.38 0.008 0.0150 c 0.23 0.32 0.009 0.0126 d (1) 15.80 16.00 0.622 0.6299 d1 9.40 9.80 0.370 0.3858 e 13.90 14.50 0.547 0.5709 e1 (1) 10.90 11.10 0.429 0.4370 e2 2.90 0.1142 e3 5.8 6.2 0.228 0.2441 e 0.65 0.025 e3 11.05 0.435 g 0 0.10 0.000 0.0039 h 15.50 15.90 0.610 0.6260 h 1.10 0.0433 l 0.80 1.10 0.031 0.0433 n 10 10 s 0 8 0 8
l6474 package mechanical data doc id 022529 rev 2 49/51 figure 19. powerso36 drawings h d $ ( d 3620(& '(7$,/$ ' ( ( k[? '(7$,/$ ohdg voxj d 6 *djh3odqh / '(7$,/% '(7$,/% &23/$1$5,7< *& & 6($7,1*3/$1( h f 1 1 0 $% e % $ + ( ' %277209,(:
revision history l6474 50/51 doc id 022529 rev 2 11 revision history table 39. document revision history date revision changes 02-dec-2011 1 initial release. 22-dec-2011 2 deleted previous chapter 6.4.1 automatic full-step mode. minor text changes.
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