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integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 recommended application: db1900gs/gso with 15:4 output grouping features: power up default is all outputs in 1:1 mode dif_(14:0) can be ?gear-shifted? from the input cpu host clock dif_(18:15) can be ?gear-shifted? from the input cpu host clock spread spectrum compatible supports output clock frequencies up to 400 mhz 8 selectable smbus addresses smbus address determines pll or bypass mode key specifications: dif output cycle-to-cycle jitter < 50ps dif output-to-output skew < 100ps within a group frequency generator for cpu, pcie gen 1, pcie gen 2 & fbd other names and brands may be claimed as the property of others. 72-pin mlf pin configuration smb_a2_pllbyp# clk_in# clk_in oe_17_18# dif_18# dif_18 dif_17# dif_17 gnd vdd dif_16# dif_ 16 oe_15_16# dif_15# dif_15 ckpwrgd/pd# dif_14# dif_14 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 iref 1 54 oe14# gnda 2 53 dif_13# vdda 3 52 dif_13 high_bw# 4 51 oe13# fs_a_410 5 50 dif_12# dif_0 6 49 dif_12 dif_0# 7 48 oe12# dif_1 8 47 vdd dif_1# 9 46 gnd gnd 10 45 dif_11# vdd 11 44 dif_11 dif_2 12 43 oe11# dif_2# 13 42 dif_10# dif_3 14 41 dif_10 dif_3# 15 40 oe10# dif_4 16 39 dif_9# dif_4# 17 38 dif_9 oe_01234# 18 37 oe9# 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 smbclk smbdat oe5# dif_5 dif_5# oe6# dif_6 dif_6# vdd gnd oe7# dif_7 dif_7# oe8# dif_8 dif_8# smb_a0 smb_a1 ics9fg1904-1 functionality at power up (pll mode) fs_a_410 1 clk_in (cpu fsb) mhz dif_(18:0) mhz 1 100 <= clk_in < 200 clk_in 0 200<= clk_in <= 400 clk_in 1. fs_a_410 is a low-threshold input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. power down functionality outputs ckpwrgd/ pd# clk_in/ clk_in# dif/dif# 1 running running on 0x hi-z off pll state inputs
2 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 pin description pin # pin name pin type description 1 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the a pp ro p riate current. 475 ohms is the standard value. 2 gnda pwr ground pin for the pll core. 3 vdda pwr 3.3v power for the pll core. 4high_bw# in 3.3v input for selecting pll band width 0 = hi g h, 1= low 5 fs_a_410 in 3.3v tolerant low threshold input for cpu frequency selection. this pin requires ck410 fsa. refer to input electrical characteristics for vil_fs and vih_fs threshold values. 6 dif_0 out 0.7v differential true clock output 7 dif_0# out 0.7v differential complement clock output 8 dif_1 out 0.7v differential true clock output 9 dif_1# out 0.7v differential complement clock output 10 gnd pwr ground pin. 11 vdd pwr power supply, nominal 3.3v 12 dif_2 out 0.7v differential true clock output 13 dif_2# out 0.7v differential complement clock output 14 dif_3 out 0.7v differential true clock output 15 dif_3# out 0.7v differential complement clock output 16 dif_4 out 0.7v differential true clock output 17 dif_4# out 0.7v differential complement clock output 18 oe_01234# in active low input for enabling dif pairs 0, 1, 2, 3 and 4. 1 = tri-state outputs, 0 = enable outputs 19 smbclk in clock pin of smbus circuitr y , 5v tolerant 20 smbdat i/o data pin of smbus circuitr y , 5v tolerant 21 oe5# in active low input for enabling dif pair 5. 1 = tri-state outputs, 0 = enable outputs 22 dif_5 out 0.7v differential true clock output 23 dif_5# out 0.7v differential complement clock output 24 oe6# in active low input for enabling dif pair 6. 1 = tri-state outputs, 0 = enable outputs 25 dif_6 out 0.7v differential true clock output 26 dif_6# out 0.7v differential complement clock output 27 vdd pwr power supply, nominal 3.3v 28 gnd pwr ground pin. 29 oe7# in active low input for enabling dif pair 7. 1 = tri-state outputs, 0 = enable outputs 30 dif_7 out 0.7v differential true clock output 31 dif_7# out 0.7v differential complement clock output 32 oe8# in active low input for enabling dif pair 8. 1 = tri-state outputs, 0 = enable outputs 33 dif_8 out 0.7v differential true clock output 34 dif_8# out 0.7v differential complement clock output 35 smb_a0 in smbus address bit 0 (lsb) 36 smb_a1 in smbus address bit 1
3 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 pin description (continued) pin # pin name pin type description 37 oe9# in active low input for enabling dif pair 9. 1 = tri-state outputs, 0 = enable outputs 38 dif_9 out 0.7v differential true clock output 39 dif_9# out 0.7v differential complement clock output 40 oe10# in active low input for enabling dif pair 10. 1 = tri-state outputs, 0 = enable outputs 41 dif_10 out 0.7v differential true clock output 42 dif_10# out 0.7v differential complement clock output 43 oe11# in active low input for enabling dif pair 11. 1 = tri-state outputs, 0 = enable outputs 44 dif_11 out 0.7v differential true clock output 45 dif_11# out 0.7v differential complement clock output 46 gnd pwr ground pin. 47 vdd pwr power suppl y , nominal 3.3v 48 oe12# in active low input for enabling dif pair 12. 1 = tri-state outputs, 0 = enable outputs 49 dif_12 out 0.7v differential true clock output 50 dif_12# out 0.7v differential complement clock output 51 oe13# in active low input for enabling dif pair 13. 1 = tri-state outputs, 0 = enable outputs 52 dif_13 out 0.7v differential true clock output 53 dif_13# out 0.7v differential complement clock output 54 oe14# in active low input for enabling dif pair 14. 1 = tri-state outputs, 0 = enable outputs 55 dif_14 out 0.7v differential true clock output 56 dif_14# out 0.7v differential complement clock output 57 ckpwrgd/pd# in a rising edge samples latched inputs and release power down mode, a low puts the part into power down mode and tristates all outputs. 58 dif_15 out 0.7v differential true clock output 59 dif_15# out 0.7v differential complement clock output 60 oe_15_16# in active low input for enabling dif pair 15 and 16. 1 = tri-state outputs, 0 = enable outputs 61 dif_ 16 out 0.7v differential true clock output 62 dif_16# out 0.7v differential complement clock output 63 vdd pwr power suppl y , nominal 3.3v 64 gnd pwr ground pin. 65 dif_17 out 0.7v differential true clock output 66 dif_17# out 0.7v differential complement clock output 67 dif_18 out 0.7v differential true clock output 68 dif_18# out 0.7v differential complement clock output 69 oe_17_18# in active low input for enabling dif pair 17, 18. 1 = tri-state outputs, 0 = enable outputs 70 clk_in in input for reference clock. 71 clk_in# in "complementary" reference clock input. 72 smb_a2_pllbyp# in smbus address bit 2. when low, the part operates as a fanout buffer with the pll bypassed. when high, the part operates as a zero-delay buffer (zdb) with the pll operating. 0 = fanout mode (pll bypassed), 1 = zdb mode (pll used)
4 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 clk_in clk_in# dif(14:0) control logic high_bw# smb_a2_pllbyp# smbdat smbclk ckpwrgd/pd# spread compatible gearing pll 15 iref oe(14:5)#, oe_01234# 11 smb_a0 smb_a1 fs_a_410 dif(18:15) 4 oe_17_18# oe_15_16# spread compatible 1:1 pll 2 ththe ics9fg1904-1 follows the intel db1900gs differential buffer specification, except for the output groupings and gear table. the gear table is a blend of the gs and gso gearing. this buffer provides 19 output clocks for cpu host bus, pci- express, or fully buffered dimm applications. the outputs are configured with two groups. both groups, dif_(14:0) and dif_(18:15) can be equal to or have a gear ratio to the input clock. a differential cpu clock from a ck410b+ main clock generator, such as the ics932s421, drives the ics9fg1904-1 . the ics9fg1904-1 can provide outputs up to 400mhz. general description block diagram power groups vdd gnd 3 2 main plls, analog 11,27,47,63 10,28,46,64 dif clocks description pin number
5 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 ics 9fg1904b-1 programmable gear ratios clk_in (cpu fsb) mhz geared dif outputs mhz mn gear ratio n/m (fs_a_410#) byte 0, bit 4 fs4 byte 0, bit 3 fs3 byte 0, bit 2 fs2 byte 0, bit 1 fs1 byte 0, bit 0 fs0 notes 100.00 133.33 3 4 1.333 0 0000 100.00 166.67 3 5 1.667 0 0001 100.00 200.00 1 2 2.000 0 0010 100.00 266.67 3 8 2.667 0 0011 100.00 333.33 3 10 3.333 0 0100 100.00 400.00 1 4 4.000 0 0101 133.33 166.67 4 5 1.250 0 01101 133.33 200.00 2 3 1.500 0 01111 133.33 266.67 1 2 1.250 0 1000 133.33 333.33 2 5 1.500 0 1001 133.33 100.00 4 3 0.750 0 1010 166.67 133.33 5 4 0.800 0 1011 1,3 166.67 200.00 5 6 1.200 0 11001 166.67 266.67 5 8 1.600 0 1101 160/ 166.67 320/ 333.33 122.000 0 11101,2 166.67 400.00 5 12 2.400 0 1111 200.00 133.33 3 2 0.667 1 00001 200.00 166.67 6 5 0.833 1 00011 200.00 266.67 3 4 1.333 1 00101 200.00 333.33 3 5 1.667 1 00111 200.00 400.00 1 2 2.000 1 01001 266.67 133.33 2 1 0.500 1 01011 266.667/ 320.00 166.67/ 200.00 850.625 1 01101, 6 266.67 200.00 4 3 0.750 1 01111 333.33 133.33 5 2 0.400 1 10001 320/ 333.33 160/ 166.67 210.500 1 10011,5 333.33 200.00 5 3 0.600 1 10101 400.00 133.33 3 1 0.333 1 1011 1,4 400.00 160.00 5 2 0.400 1 11001 400.00 166.67 12 5 0.417 1 11011 400.00 320.00 5 4 0.800 1 11101 400.00 333.33 6 5 0.833 1 11111 notes: 1. targetted input/output frequency pairs 2. this gear is also used for 160mhz/320 mhz. 3. gear ratio 5/4 is power up default for fs_a_410 = 1 4. gear ratio 3/1 is power up default for fs_a_410 = 0 5. this gear is also used for 400mhz/200mhz 6. this gear is also used for 320mhz/200mhz
6 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 byte 9, bit 2 fsc byte9, bit 1 fsb byte 9, bit 0 fs_a_410 clk_in (cpu fsb) mhz 1:1 dif outputs mhz notes 101 100.00 100.00 3 001 133.33 133.33 3 011 166.67 166.67 1 010 200.00 200.00 3 000 266.67 266.67 3 100 333.33 333.33 3 110 400.00 400.00 2 111 notes:fs_a_410 = 1 1. powerup default for fs_a_410 = 1 2. powerup default for fs_a_410 = 0 3. setting the exact fsb frequency after power is required for best phase noise performance. reserved ics 9fg1904b-1 1:1 pll programming desired decimal value binary value to write to register 20000 30001 50010 70011 40100 60101 10 0110 14 0111 81000 12 1001 20 1010 28 1011 16 1100 24 1101 40 1110 56 1111 out p ut divider ratios
7 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 absolute max parameter symbol conditions min typ max units notes 3.3v core supply voltage vdd_a gnd - 0.5 v dd + 0.5v v 1 3.3v logic supply voltage vdd_in gnd - 0.5 v dd + 0.5v v 1 storage temperature ts -65 150 c 1 ambient operating temp tambient 0 70 c 1 case temperature tcase 115 c 1 input esd protection esd prot human body model 2000 v 1 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v d d = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v d d -5 5 ua input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ua low threshold input- high voltage v ih_fs 3.3 v +/-5%, applies to fs_a_410 pin 0.7 v dd + 0.3 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5%, applies to fs_a_410 pin v ss - 0.3 0.35 v 1 operating current i dd3. 3op all outputs driven 500 ma 1 powerdown current i dd3. 3p d all differential pairs tri-stated 30 ma 1 input frequency f i v d d = 3.3 v 100 400 mhz 3 pin inductance l p in 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 2.5 pf 1 clk stabilization t stab from v dd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 modulation frequency triangular modulation 30 33 khz 1 tdrive_pd# dif output enable after pd# de-assertion 300 us 1 tfall_pd# pd# fall time of 5 ns 1 trise_pd# pd# rise time of 5 ns 2 smbus voltage v max maximum input voltage 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 4ma1 sclk/sdata clock/data rise time t ri 2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi 2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 input capacitance
8 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 electrical characteristics - dif 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , ref = 475 ? parameter symbol conditions min typ max units notes current source output im p edance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 850 1,3 voltage low vlow -150 150 1,3 max volta g e vovs 1150 1 min volta g e vuds -300 1 crossing voltage (abs) vcross(abs) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all edges 140 mv 1 lon g accurac y pp msee t p eriod min-max values 0 0 pp m1,2,7 400mhz nominal 2.4993 2.5008 ns 2 400mhz s p read 2.4993 2.5133 ns 2 333.33mhz nominal 2.9991 3.0009 ns 2 333.33mhz s p read 2.9991 3.016 ns 2 266.66mhz nominal 3.7489 3.7511 ns 2 266.66mhz s p read 3.7489 3.77 ns 2 200mhz nominal 4.9985 5.0015 ns 2 200mhz s p read 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz s p read 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz s p read 7.4978 7.5400 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz s p read 9.9970 10.0533 ns 2 400mhz nominal/s p read 2.4143 ns 1,2 333.33mhz nominal/s p read 2.9141 ns 1,2 266.66mhz nominal/s p read 3.6639 ns 1,2 200mhz nominal/s p read 4.8735 ns 1,2 166.66mhz nominal/s p read 5.8732 ns 1,2 133.33mhz nominal/s p read 7.3728 ns 1,2 100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 t jcyc-cyc pll mode, from differential wavefrom 50 ps 1,4,5 t jbyp bypass mode as additive jitter 50 ps 1,4 notes: 1.guaranteed by design and characteri zation, not 100% tested in production. 3.iref = vdd/(3xrr). for rr = 475 ? (1%), iref = 2.32ma. ioh = 6 x iref and voh = 0.7v @ zo=50 ? . 4. measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding input . 5. measured from differential cross- point to differential cross-point 6. all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 7. this device does not introduce any ppm errors to the input clock. jitter, cycle to cycle 2. all long term accuracy and clock period specifications are guaranteed assuming that the input frequency meets ck410 accuracy requirements absolute min period t absmin statistical measurement on single ended signal using oscilloscope math function. mv average period tperiod measurement on single ended signal using absolute value. mv
9 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 electrical characteristics - skew and differential jitter parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% group parameter description min max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode (1:1 only), nominal value @ 25c, 3.3v -500 500 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode (1:1 only), nominal value @ 25c, 3.3v 2.5 4.5 ns 1,2,3,5 clk_in, dif [x:0] ? t spo_pll input-to-output skew variation in pll mode (over specified voltage / temperature operating ranges) |350| ps 1,2,4,5,6, 10 clk_in, dif [x:0] ? t pd_byp input-to-output skew variation in bypass mode (over specified voltage / temperature operating ranges) |500| ps 1,2,3,4,5, 6,10 dif[14:0] t skew_g15 output-to-output skew group of 15 ( common to b yp ass and pll mode ) 100 ps 1,2 dif[18:15] tskew_g4 output-to-output skew group of 4 (common to bypass and pll mode ) 50 ps 1.2 dif[18:0] t skew_a19 output-to-output skew across all 19 outputs (common to bypass and pll mode - all outputs at same gear) 150 ps 1,2,3 dif[18:0] t jph differential phase jitter (rms value) 10 ps 1,4,7 dif[18:0] t ssterror differential spread spectrum tracking error (peak to peak) 80 ps 1,4,9 notes: 8. t is the period of the input clock 10. this parameter is an absolute value. it is not a double-sided figure. 9. differential spread spectrum tracking error is the difference in spread spectrum tracking between two ics9fg1900 devices th is parameter is measured at the outputs of two separate ics9fg1900 devices driven by a single ck410b in spread spectrum mode. the ics9fg1900's must be set to high bandwidth. the spread spectrum characteristics are: maximum of 0.5%, 30-33khz modulation frequency, linear profile. 5. measured with scope averaging on to find mean value. 6. long-term variation from nominal of input-to-output skew over temperature and voltage for a single device. 7. this parameter is measured at the outputs of two separate ics9fg1900 devices driven by a single ck410b. the ics9fg1900's mu st be set to high bandwidth. differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the a ffects of spread spectrum). target ran g es of consideration are a g ents with bw of 1-22mhz and 11-33mhz. 1. measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding i nput. 2. measured from differential cross-point to differential cross-point 3. all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 4. this parameter is deterministic for a given device electrical characteristics - phase jitter parameters ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, when driven by 932s421b or equivalent parameter s y mbol conditions min t yp ma x units notes t jp hpcie1 pcie gen 1 108 ps (p-p) 1,2 t jphpcie2lo pcie gen 2 10khz < f < 1.5mhz 3ps (rms)1,2 t jphpcie2hi pcie gen 2 1.5mhz < f < nyquist (50mhz) 3.1 ps (rms) 1,2 t jphfbd1_3.2g fbd1 3.2/4g 11mhz to 33mhz 3ps (rms)1,2 t jphfbd1_4.0g fbd1 4.8g 11mhz to 33mhz 2.5 ps (rms) 1,2 notes: 1 guaranteed b y desi g n and characterization, not 100% tested in production. jitter, phase 2 see http://www.pcisig.com for complete specs
10 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 programming the 9fg1904b-1 the 9fg1904b-1 uses advanced power saving features to detect when only geared outputs or only 1:1 outputs are needed. it then shuts down the unused pll. at power up all outputs are coming from the 1:1 pll and the gear pll is shut down. this power saving feature requires a little care when configuring the gear outputs in the device. configuring gear outputs of the 9fg1904b-1 selecting pre-configured gear ratios byte 0 contains both the bits that enable the gear ratio outputs (bits 7 and 6), and the bits that select the actual gear ratio (bits (4:0)). it is tempting to enable the gearing outputs and select the gear ratio at the same time. however, this can result in the inability to obtain the proper output frequency. due to the power saving feature, it is necessary to perform this operation as two steps: 1. first, enable outputs to the gear ratio pll, which actually powers up the gear ratio pll (set byte 0, bits 7 and 6) 2. then select the desired gear ratio in a separate write to byte 0 (set byte 0, bits (4:0) the actual order of the two operations is unimportant, so steps 1 and 2 could be reversed if desired. programming gear ratios that are not pre-configured most applications using the 9fg1904b-1 can obtain the desired output frequencies from the selections built into the gear table. there are two gear tables defined for these devices. there is the original gs gear set indicated by the dbxxxxgs yellow cover designation and the newer optimized gso gear set indicated by dbxxxxgso yellow cover designation. the 9fg1904b-1 contains a gear set that is a combination of the gs and gso gear sets. the differences between the gs and gso gear sets are highlighted in figure 1 gs versus gso versus 9fg1904b-1 gear ratios. any gear in the gs or the gso table that is not pre-configured in the 9fg1904b-1, and virtually any other input/output combination can be obtained by use of m/n programming. note that care must be used or the jitter/bandwidth characteristics of the pll can be compromised. the values provided later in this document have been verified to preserve the pll performance of the device. refer to the section using m/n programming to obtain other gear ratios for additional details.
11 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 clk_in (cpu fsb) mhz geared dif outputs mhz mn gear ratio n/m clk_in (cpu fsb) mhz geared dif outputs mhz mn gear ratio n/m clk_in (cpu fsb) mhz geared dif outputs mhz mn gear ratio n/m 1 100.00 133.33 3 4 1.33 100.00 133.33 3 4 1.33 100.00 133.33 3 4 1.33 2 100.00 166.67 3 5 1.67 100.00 166.67 3 5 1.67 100.00 166.67 3 5 1.67 3 100.00 200.00 1 2 2.00 100.00 200.00 1 2 2.00 100.00 200.00 1 2 2.00 4 100.00 266.67 3 8 2.67 100.00 266.67 3 8 2.67 100.00 266.67 3 8 2.67 5 100.00 333.33 3 10 3.33 100.00 333.33 3 10 3.33 100.00 333.33 3 10 3.33 6 100.00 400.00 1 4 4.00 133.33 100.00 4 3 0.75 100.00 400.00 1 4 4.00 7 133.33 166.67 4 5 1.25 133.33 166.67 4 5 1.25 133.33 166.67 4 5 1.25 8 133.33 200.00 2 3 1.50 133.33 200.00 2 3 1.50 133.33 200.00 2 3 1.50 9 133.33 266.67 1 2 1.25 133.33 266.67 1 2 2.00 133.33 266.67 1 2 1.25 10 133.33 333.33 2 5 1.50 133.33 333.33 2 5 2.50 133.33 333.33 2 5 1.50 11 133.33 400.00 1 3 3.00 133.33 400.00 1 3 3.00 133.3 3 100.0 0 4 3 0.7 5 12 166.67 133.33 5 4 0.80 166.67 133.33 5 4 0.80 166.67 133.33 5 4 0.80 13 166.67 200.00 5 6 1.20 166.67 200.00 5 6 1.20 166.67 200.00 5 6 1.20 14 166.67 266.67 5 8 1.60 166.67 266.67 5 8 1.60 166.67 266.67 5 8 1.60 15 160 / 166.67 320 / 333.33 1 2 2.00 166.67 333.33 1 2 2.00 160 / 166.67 320 / 333.33 12 2.00 16 166.67 400.00 5 12 2.40 166.67 400.00 5 12 2.40 166.67 400.00 5 12 2.40 17 200.00 133.33 3 2 0.67 200.00 133.33 3 2 0.67 200.00 133.33 3 2 0.67 18 200.00 166.67 6 5 0.83 200.00 166.67 6 5 0.83 200.00 166.67 6 5 0.83 19 200.00 266.67 3 4 1.33 200.00 266.67 3 4 1.33 200.00 266.67 3 4 1.33 20 200.00 333.33 3 5 1.67 200.00 333.33 3 5 1.67 200.00 333.33 3 5 1.67 21 200.00 400.00 1 2 2.00 200.00 400.00 1 2 2.00 200.00 400.00 1 2 2.00 22 266.67 133.33 2 1 0.50 266.67 133.33 2 1 0.50 266.67 133.33 2 1 0.50 23 266.667 / 320 166.67/ 200 8 5 0.63 266.67 166.67 8 5 0.63 266.667 / 320.00 166.67/ 200.00 85 0.63 24 266.67 200.00 4 3 0.75 266.67 200.00 4 3 0.75 266.67 200.00 4 3 0.75 25 333.33 133.33 5 2 0.40 333.33 133.33 5 2 0.40 333.33 133.33 5 2 0.40 26 320 / 333.33 160 / 166.67 2 1 0.50 333.33 166.67 2 1 0.50 320 / 333.33 160 / 166.67 21 0.50 27 333.33 200.00 5 3 0.60 333.33 200.00 5 3 0.60 333.33 200.00 5 3 0.60 28 400.00 133.33 3 1 0.33 400.00 133.33 3 1 0.33 400.00 133.33 3 1 0.33 29 400.00 160.00 5 2 0.40 400.00 166.67 12 5 0.42 400.00 160.00 5 2 0.40 30 400.00 166.67 12 5 0.42 400.00 200.00 2 1 0.50 400.00 166.67 12 5 0.42 31 400.00 320.00 5 4 0.80 400.00 266.67 6 4 0.67 400.00 320.00 5 4 0.80 32 400.00 333.33 6 5 0.83 400.00 333.33 6 5 0.83 400.00 333.33 6 5 0.83 gso gear ratios gs gear ratios 9fg1904-1 gear ratios fi g ure 1 gs versus gso versus 9fg1904b-1 gear ratios
12 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 using m/n programming to obtain other gear ratios m/n programming can be used to obtain input output frequency combinations that are not preconfigured in the 9fg1904b-1. refer to figure 2 pll block diagram. the internal architecture of the 9fg1904b-1 is standard pseudo-zdb architecture with internal feedback. this means that the ref divider, the output divider and the feedback divider all play a role in determining the output frequency. the output frequency is given by the equation: output frequency = (input frequency x n x output div)/m the dbxxxxgso input/output combinations that are not in the 9fg1904b-1 gear table are shown in table 1 dbxxxxgso gears not present in the 9fg1904b-1 . this table also gives the values needed to program the gearing pll to provide the desired input/output combination. input clock ref (m) div fbk (n) div vco output div buffers output clocks figure 2 pll block diagram setting the 1:1 pll operating point after configuring the gearing outputs, it is also necessary to set the 1:1 pll operating point by writing the input frequency value to byte 9 bits (2:0). the input frequency is usually the cpu hclk frequency. note before the m/n programming can be accomplished, byte 10, bit 7 (the m/n_enable bit) must be set to a ?1?. the values provided in the table above have been verified to meet the specified performance of the 9fg1901b-1. performance is not guaranteed for any other values that have not been pre-approved by idt. contact your local idt representative for other values not mentioned here. 1:1 pll bytes byte 17 byte 18 byte 19 gear pll bytes byte 11 byte 12 byte 13 line fs_a_410# input frequency (fref) output frequency decimal m value decimal n value decimal post divider gear ref m div (hex) vco n div (hex) output div (hex) 1 0 133.33 400.00 4 12 2 3.000 2 a 0 2 1 400.00 200.00 12 6 4 0.500 a 4 4 3 1 400.00 266.67 12 8 3 0.667 a 6 1 table 1 dbxxxxgso gears not present in the 9fg1904b-1
13 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 9fg1904-1 smbus address mapping when using ck410/ck410b, 9fg1200, and 9db401/801 smb adr: dc 9db401/801 (db400/800) smb adr: d2 954101 932s401 (ck410/410b) pll bypass mode smb_a2_pllbyp# = 0 p l l z d b m o d e s m b _ a 2 _ p l l b y p # = 1 smb_a(2:0) = 100 smb adr: d8 smb_a(2:0) = 101 smb adr: da smb_a(2:0) = 110 smb adr: dc smb_a(2:0) = 111 smb adr: de smb_a(2:0) = 000 smb adr: d0 9fg1904-1 (db1900gs) smb_a(2:0) = 001 smb adr: d2 smb_a(2:0) = 010 smb adr: d4 smb_a(2:0) = 011 smb adr: d6 smb_a(2:0) = 100 smb adr: d8 9fg1200-1 (db1200gs) smb_a(2:0) = 101 smb adr: da 9fg1200-1 (db1200gs) smb_a(2:0) = 110 smb adr: dc 9fg1200-1 (db1200gs) smb_a(2:0) = 111 smb adr: de 9fg1200-1 (db1200gs) smb_a(2:0) = 000 smb adr: d0 9fg1200-1 (db1200gs) smb_a(2:0) = 001 smb adr: d2 9fg1200-1 (db1200gs) smb_a(2:0) = 010 smb adr: d4 9fg1200-1 (db1200gs) smb_a(2:0) = 011 smb adr: d6 9fg1200-1 (db1200gs) or or or or or or or or or or ` 9fg1904-1 (db1900gs) 9fg1904-1 (db1900gs) 9fg1904-1 (db1900gs) 9fg1904-1 (db1900gs) 9fg1904-1 (db1900gs) 9fg1904-1 (db1900gs) 9fg1904-1 (db1900gs)
14 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 general smbus serial interface information for the ICS9FG1904B-1 how to write: ? controller (host) sends a start bit. controller (host) sends the write address *d0 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address *d0 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address *d1 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address *d0 (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address *d1 (h) index block read operation slave address *d0 (h) beginning byte = n ack ack * the smbus address of this device is programmable. see the preceding page for details on how to set the smbus address.
15 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 smbustable: gear ratio select register pin # name control function t yp e0 1pwd bit 7 rw gear ratio 1:1 1 bit 6 rw gear ratio 1:1 1 bit 5 rw 1 bit 4 rw latch bit 3 rw 1 bit 2 rw 0 bit 1 rw 1 bit 0 rw 1 smbustable: output control register pin # name control function t yp e0 1pwd bit 7 dif_7 output control rw hi-z enable 1 bit 6 dif_6 output control rw hi-z enable 1 bit 5 dif_5 output control rw hi-z enable 1 bit 4 dif_4 output control rw hi-z enable 1 bit 3 dif_3 output control rw hi-z enable 1 bit 2 dif_2 output control rw hi-z enable 1 bit 1 dif_1 output control rw hi-z enable 1 bit 0 dif_0 output control rw hi-z enable 1 smbustable: output and pll bw control register pin # name control function t yp e0 1pwd bit 7 rw high bw low bw 1 bit 6 rw bypass pll 1 bit 5 dif_13 output control rw hi-z enable 1 bit 4 dif_12 output control rw hi-z enable 1 bit 3 dif_11 output control rw hi-z enable 1 bit 2 dif_10 output control rw hi-z enable 1 bit 1 dif_9 output control rw hi-z enable 1 bit 0 dif_8 output control rw hi-z enable 1 note: bit 7 is wired or to the high_bw# input, any 0 selects high bw note: bit 6 is wired or to the smb_a2_pllbyp# input, any 0 selects fanout bypass mode smbustable: output enable readback register pin # name control function t yp e0 1pwd bit 7 r x bit 6 r x bit 5 r x bit 4 r x bit 3 r x bit 2 r x bit 1 r x bit 0 r x 72 readback readback - oe5# input readback - oe6# input readback readback readback - oe8# input readback readback readback - oe7# input readback - oe9# input see note pll_bw# adjust see note bypass# test mode / pll 8 b y te 1 - - - - b y te 0 dif(14:0) dif(18:15) gear ratio fs4 (inverse of fs_a_410 input!) - - group of 15 gear ratio enable group of 4 gear ratio enable reserved b y te 3 readback readback - oe_01234# input readback - smb_a2_pll byp# in readback readback - high_bw# in readback b y te 2 gear ratio fs3 gear ratio fs2 gear ratio fs1 see ics9fg1904-1 programmable gear ratios table gear ratio fs0
16 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 smbustable: output enable readback register pin # name control function t yp e0 1pwd bit 7 r x bit 6 r x bit 5 x bit 4 r x bit 3 r x bit 2 r x bit 1 r x bit 0 r x smbustable: vendor & revision id register pin # name control function t yp e0 1pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id pin # name control function t yp e0 1pwd bit 7 rw 1 bit 6 rw 0 bit 5 rw 0 bit 4 rw 1 bit 3 rw 0 bit 2 rw 1 bit 1 rw 0 bit 0 rw 0 smbustable: byte count register pin # name control function t yp e0 1pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 - - - 54 51 48 43 - - - - - reserved readback readback readback reserved device id 1 reserved writing to this register configures how many bytes will be read back. - - - device id 2 device id 3 device id 4 60 - - 40 - b y te 4 reserved device id 6 reserved device id 7 (msb) readback - oe12# input vendor id readback - oe11# input readback - - b y te 5 - b y te 6 69 - reserved readback b y te 7 - - - - - - reserved revision id readback readback - oe10# input readback - oe14# input device id 5 readback - oe13# input readback - oe15_16# input readback - oe17_18# input readback reserved device id 0 reserved
17 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 smbustable: control pin readback register pin # name control function t yp e0 1pwd bit 7 r x bit 6 x bit 5 x bit 4 dif_18 output control rw hi-z enable 1 bit 3 dif_17 output control rw hi-z enable 1 bit 2 dif_16 output control rw hi-z enable 1 bit 1 dif_15 output control rw hi-z enable 1 bit 0 dif_14 output control rw hi-z enable 1 smbustable: 1:1 pll operating set point register pin # name control function t yp e0 1pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 rw x bit 1 rw 1 bit 0 rw latch smbus table: m/n programming & watchdog safe register pin # name control function t yp e0 1pwd bit 7 m/n_en gear and 1:1 pll m/n pro g rammin g enable rw disable enable 0 bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x smbus table: gear pll frequency control register pin # name control function t yp e0 1pwd bit 7 x bit 6 x bit 5 gear pll m div5 rw x bit 4 gear pll m div4 rw x bit 3 gear pll m div3 rw x bit 2 gear pll m div2 rw x bit 1 gear pll m div1 rw x bit 0 gear pll m div0 rw x reserved reserved reserved reserved reserved reserved reserved frequenc y select c frequency select b fs_a_410 see ics9fg1904 1:1 pll programming table reserved reserved reserved reserved reserved see m/n programming section of the data sheet 5 b y te 8 - m divider - - - - - b y te 11 b y te 10 - reserved - - - reserved b y te 9 readback - fs_a_410 readback reserved reserved
18 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 smbus table: gear pll frequency control register pin # name control function t yp e0 1pwd bit 7 gear pll n div7 rw x bit 6 gear pll n div6 rw x bit 5 gear pll n div5 rw x bit 4 gear pll n div4 rw x bit 3 gear pll n div3 rw x bit 2 gear pll n div2 rw x bit 1 gear pll n div1 rw x bit 0 gear pll n div0 rw x smbustable: reserved register pin # name control function t yp e0 1pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 gear pll out div 3 gear pll output divider rw x bit 2 gear pll out div 2 gear pll output divider rw x bit 1 gear pll out div 1 gear pll output divider rw x bit 0 gear pll out div 0 gear pll output divider rw x smbustable: reserved register pin # name control function t yp e0 1pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: reserved register pin # name control function t yp e0 1pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved reserved reserved see output divider ratios table reserved b y te 14 b y te 15 reserved reserved reserved reserved - b y te 13 reserved b y te 12 - n divider see m/n programming section of the data sheet - - - - - - reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
19 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 smbustable: reserved register pin # name control function t yp e0 1pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: 1:1 pll frequency control register pin # name control function t yp e0 1pwd bit 7 x bit 6 x bit 5 1:1 pll m div5 rw x bit 4 1:1 pll m div4 rw x bit 3 1:1 pll m div3 rw x bit 2 1:1 pll m div2 rw x bit 1 1:1 pll m div1 rw x bit 0 1:1 pll m div0 rw x smbus table: 1:1 pll frequency control register pin # name control function t yp e0 1pwd bit 7 1:1 pll n div7 rw x bit 6 1:1 pll n div6 rw x bit 5 1:1 pll n div5 rw x bit 4 1:1 pll n div4 rw x bit 3 1:1 pll n div3 rw x bit 2 1:1 pll n div2 rw x bit 1 1:1 pll n div1 rw x bit 0 1:1 pll n div0 rw x smbustable: reserved register pin # name control function t yp e0 1pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 1:1 pll out div 3 1:1 pll output divider rw x bit 2 1:1 pll out div 2 1:1 pll output divider rw x bit 1 1:1 pll out div 1 1:1 pll output divider rw x bit 0 1:1 pll out div 0 1:1 pll output divider rw x - b y te 16 - - - b y te 17 - - - - - - b y te 19 - - - b y te 18 - reserved n divider programming b(7:0) reserved see m/n programming section of the data sheet reserved reserved reserved reserved reserved reserved see output divider ratios table reserved reserved reserved reserved m divider programming bits see m/n programming section of the data sheet reserved reserved
20 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 smbustable: reserved register pin # name control function t yp e0 1pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: test byte register test t yp epwd bit 7 rw 0 bit 6 rw 0 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 0 bit 0 rw 0 note: do not write to bit 21. erratic device operation will result! ics only test `ics only test b y te 21 test function reserved reserved test result ics only test reserved ics only test reserved reserved ics only test reserved ics only test reserved reserved ics only test reserved ics only test reserved reserved reserved reserved reserved b y te 20 reserved reserved
21 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 ordering information ics 9fg1904bk-1lft example: designation for tape and reel packaging lead free, rohs compliant (optional) variation number package type k = mlf revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) ics xxxx b k - v lf t e top view or anvil singulation a3 l n (ref.) e e e e (ref. ) (ref. ) (ref. ) (typ.) if a1 even e2 d2 d2 2 a c 0.08 c e2 2 2 2 1 sawn singulation index area seating plane are even thermal base odd b (n - 1)x n 1 chamfer 4x 0.6 x 0.6 max optional d d & & n d n d n e n e & n d n e (n - 1)x e dimensions a 0.8 1.0 n 72 a1 0 0.05 n d 18 a3 n e 18 b 0.18 0.3 d x e basic 10.00 x 10.00 e d2 min. / max. 5.75 / 6.15 e2 min. / max. 5.75 / 6.15 l min. / max. 0.30/ 0.50 ics 72l tolerance thermally enhanced, very thin, fine pitch quad flat / no lead plastic package dimensions symbol min. max. symbol 0.25 reference 0.50 basic
22 integrated circuit systems, inc. ICS9FG1904B-1 1255b?08/03/07 revision history rev. issue date description page # a 05/04/07 1. added output divider table. 2. added phase jitter table to electrical characteristics. 3. added m/n programming information. 4. chan g ed part number to reference 9fg1904b-1. various b 08/03/07 release to final. -

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