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high speed difference amplifier with input short - to - battery protection data sheet ada4830 - 1 / ada4830 - 2 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor fo r any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 C 2012 analog devices, inc. all rights reserved. features input over voltage (short - to - battery) protection of up to 18 v short - to - battery output flag for wire diagnostics wide input common - mode range with single 5 v supply high performance video amplifier with 0.5 0 v/v gain ?3 db bandwidth of 84 mhz 2 5 0 v /s slew rate (2 v step) excellent video specifications 0.1 db flatness to 28 mhz snr of 73 db to 15 mhz differential gain/phase of 0.1% /0.1 wide supply range: 2.9 v to 5.5 v enable / o utput disable mode space saving 3 mm 3 mm lfcsp package wide operating temperature range: ?40 c to +125c qualified for automotive applications applications automotive vision systems automotive infotainment surveillance systems general description the ada4830 - 1 (single) and ada4830 - 2 (dual) are monolithic , high speed difference amplifiers that integrate input overvoltage (short - to - battery) protection of up to 18 v with a wide input common - mode voltage range and excellent esd robustne ss. they are intended for use as receivers for differential or pseudo differential cvbs and other high speed video signals in harsh, noisy environments such as automotive infotainment and vision systems. the ad a4830 - 1 and ada4830 - 2 combine high speed and precision, which allows for accurate reproduction of cvbs video signals, yet rejects unwanted common - mode error voltages. the short - to - battery protection that is integrated into the ada4830 - 1 and ada4830 - 2 employs fast switching circuitry to clamp and hold internal voltage nodes at a safe level when an input overvoltage co ndition is detected. this protection allows the inputs of the ada4830 - 1 and ada4830 - 2 to be directly connected to a remote video source, such as a rearview camera , without the need for large expensive series capacitors. the ada4830 - 1 and ada4830 - 2 can withstand direct short - to - battery voltages as high as 18 v on their inpu t pins. the ada4830 - 1 and ada4830 - 2 are designed to operate at supply voltages as low as 2.9 v and as high as 5.5 v, using only 6.8 ma of supply current per chann el. these devices provide true single - supply capability, allowing the input signal to extend 8.5 v functional block dia gram stb ena +vs gnd +vs r/2 r r/2 r inn inp vref 1 vout ada4830-1 10020-001 figure 1. stb1 ena1 +vs1 stb2 ena2 +vs2 gnd2 gnd1 +vs r/2 r r/2 r inn1 inp1 vref1 1 vout1 vout2 ada4830-2 +vs 10020-102 r r/2 r inn2 inp2 vref2 1 r/2 figure 2. below ground rail and to 8.5 v above ground on a single 5 v supply. at the output, the amplifier can swing to within 250 mv of either supply rail into a 150 load. the ada4830 - 1 and ada4830 - 2 present a gain of 0.5 0 v/v at their output. this is designed to keep the video signal within the allowed range of the video decoder, which is typically 1 v p - p or less. the ada4830 - 1 w and ada4830 - 2 w are automotive grade version, qualified for automotive applications. see the automotive products section for more details. the ada4830 - 1 and ada4830 - 2 are available in 3 mm 3 mm lfcsp packages, 8 - lead and 16 - lead, respectively, and are specified for operation over the automotive temperature range of ?40 c to +125 c.
ada4830- 1 /ada4830- 2 data sheet rev. c | page 2 of 22 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 5 v operation ............................................................................... 3 3.3 v operation ............................................................................ 4 absolute maximum ratings ....................................................... 6 thermal resistance ...................................................................... 6 maximum power dissipation ..................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 13 core amplifier ............................................................................ 13 overvoltage (short - to - battery) protection ............................. 13 short - to - battery out put flag ................................................... 13 esd protection ........................................................................... 13 power supply pins ( ada4830 - 2 ) .............................................. 13 a pplications information .............................................................. 14 methods of transmission .......................................................... 14 voltage reference (vref pin) ................................................. 14 input common - mode range ................................................... 15 short - to - battery output flag pin ............................................ 15 enable/disable modes (ena pin) ........................................... 15 pcb layout ................................................................................. 15 exposed paddle (epad) connection ...................................... 15 using the ada4830 - 2 as a low cost video switch ............... 16 driving capacitive loads .......................................................... 17 typical applications circuits ........................................................ 18 fully dc - coupled transmission line .................................... 20 packaging and ordering information ......................................... 21 outline dimensions ................................................................... 21 ordering guide .......................................................................... 21 automotive products ................................................................. 22 revision history 6 /12 rev. b to rev. c added ada4830 - 2 w ......................................................... u niversal changes to features ................................ ................................ ..................... 1 changes to ordering guide ................................ ................................ ..... 21 4 /12 rev. a to rev. b changes to features section and generation description section . 1 changes to table 1 ................................ ................................ ....................... 3 changes to table 2 ................................ ................................ ....................... 4 changes to table 4 ................................ ................................ ....................... 6 changes to figure 28 ................................ ................................ ................. 12 changes to esd protec tion section ................................ ....................... 13 changes to ordering guide ................................ ................................ ..... 21 added automotive products section ................................ .................... 22 1/1 2 rev. 0 to rev. a added ada4830 - 2 ............................................................. universal changes to features section and figure 1 ..................................... 1 added figure 2; renumbered sequentially .................................. 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 added supply voltage delta parameter, table 3 ; renumbered sequentially ....................................................................................... 5 added figure 5 and table 6 ............................................................. 7 changes to typical performance characteristics section ........... 8 added figure 23 ............................................................................. 10 added figure 2 4 to figure 2 9 ....................................................... 11 changes to pseudo differential mode (unbalan ced source termination) section , fully differential mode section , and voltage reference (vref pin) section ....................................... 13 changes to input common - mode range section, table 7 , short - to - battery output flag pin section , and table 9 ............ 14 added figure 34 ............................................................................. 15 added driving cap acitive loads section and figure 35 to figure 38 .......................................................................................... 16 changes to figure 3 9 and figure 40 ............................................. 17 changes typical application circuits section and figure 41 ......... 1 8 added fully dc - coupled transmission line section ..................... 19 changes to figure 42 ................................ ................................ ................. 19 updated outline dimensions ....................................................... 2 0 changes to ordering guide .......................................................... 20 10 /11 revision 0 : initial version
data sheet ada4830- 1/ada4830 - 2 rev. c | page 3 of 22 specifications 5 v operation t a = 25 c, +v s = 5 v, r l = 1 k ?, v ref = 2.5 v (floating), v incm = +v s /2, r stb = 5 k ? to +v s , unless otherwise specified . table 1 . pa rameter test conditions /comments min typ max unit dynamic performance ?3 db large signal bandwidth v out = 0.5 v p -p , r l = 150 ? 64 71 mhz ada4830 - 1 w / ada4 830- 2 w only t min to t max 56 mhz v out = 0.1 v p - p, r l = 1 k? 84 mhz v out = 0.1 v p - p, r l = 150 ? 65 74 mhz ada4830 - 1 w/ ada4830 - 2 w only t min to t max 60 mhz bandwidth for 0.1 db flatness v out = 0.5 v p - p, r l = 150 ? 28 mhz slew rate (t r /t f ) v out = 2 v step 196/200 250/300 v/s ada4830 - 1 w/ ada4830 - 2 w only t min to t max 164/220 v/s settling time to 0.1% v out = 2 v step 25 ns noise/distortion performance output voltage noise f = 1 mhz 28 nv/hz differential gain error (ntsc) r l = 150 ?, v in = 1 v p -p 0.1 % differential phase error (ntsc) r l = 150 ?, v in = 1 v p -p 0.1 degrees signal -to - noise ratio f = 100 khz to 15 mhz, v out = 0.5 v p -p 73 db dc performance nominal gain v in to v out 0.49 0.50 0.51 v/v ada4830 - 1 w/ ada4830 - 2 w only t min to t max 0.49 0.51 v/v output bias voltage 2.45 2.50 2.55 v ada4830 - 1 w/ ada4830 - 2 w only t min to t max 2.44 2 .56 v input characteristics input resistance (differential mode) 6.7 k? input resistance (common mode) 2 k? input common - mode voltage range v ref voltage adjusted to optimized range ?10 +9.5 v ada4830 - 1 w/ ada4830 - 2 w only t min to t max ?10 +9.5 v common - mode rejection (cmr) v in = 5 v 42 65 db ada4830 - 1 w/ ada4830 - 2 w only t min to t max 42 db short - to - battery characteristics i nput current v in = 18 v (short - to - battery) 4.1 ma protected input voltage range ?9 +20 v ada4830 - 1 w/ ada4830 - 2 w only t min to t max ? 9 +20 v short - to - batte ry output flag trigger level minimum v in needed to signal an input fault condition 9.8 10.3 10.8 v ada4830 - 1 w/ ada4830 - 2 w only t min to t max 9.8 10.8 v v o ltage reference input input voltage range 0.2 to 3.9 v input resistance 20 k? gain v ref to v out 1 v/v logic output/input characteristics stb v oh v in 9.8 v (normal operation) 5.0 v stb v ol v in 10.8 v (fault condition), ada4830 - 1 / ada4830 - 2 110/253 mv ena v ih voltage to enable device 3.0 v ena v il voltage to disable device 1.0 v
ada4830- 1 /ada4830- 2 data sheet rev. c | page 4 of 22 pa rameter test conditions /comments min typ max unit output characteristics output voltage swing r l = 150 ? to ground 0.01 to 4.75 v linear output current <1% thd at 100 k hz 125 ma short - circuit current sourcing/sinking 248/294 ma capacitive load drive peaking 3 db 47 pf power supply operating range operation outside of this range results in performance degradation 2.9 5.5 v quiescent current per amplifier enabled (ena = 5 v), no load 6.8 10 ma ada4830 - 1 w/ ada4830 - 2 w only t min to t max 10.4 ma disabled (ena = 0 v) , no load 90 a v in = 18 v (short - to - battery) , no l oad 5.3 ma power supply rejection ratio (psrr) +v s = 4.5 v to 5.5 v, v ref is forced to 2.5 v 53 db operating temperature range ?40 +125 c 3.3 v operation t a = 25 c, +v s = 3.3 v, r l = 1 k ?, v ref = 1.65 v (floating), v incm = +v s /2, r stb = 5 k? to +vs, unless otherwise specified . table 2 . parameter test conditions /comments min typ max unit dynamic perfor mance ?3 db large signal bandwidth v out = 0.5 v p -p , r l = 150 ? 63 73 mhz ada4830 - 1 w/ ada4830 - 2 w only t min to t max 58 mhz v out = 0. 1 v p - p, r l = 1 k? 89 mhz v out = 0. 1 v p - p, r l = 150 ? 64 7 8 mhz ada4830 - 1 w/ ada4830 - 2 w only t min to t max 59 mhz bandwidth for 0.1 db flatness v out = 0.5 v p - p, r l = 150 ? 2 0 mhz slew rate (t r /t f ) v out = 1 v step 147/155 165 /180 v/s ada4830 - 1 w/ ada4830 - 2 w only t min to t max 136/145 v/s settling time to 0.1% v out = 1 v st ep 25 ns noise/distortion performance output voltage noise f = 1 mhz 28 nv/hz differential gain error (ntsc) r l = 150 ?, v in = 1 v p -p 0.1 % differential phase error (ntsc) r l = 150 ?, v in = 1 v p -p 0.1 d egrees signal - to - noise ratio f = 100 khz to 15 mhz , v out = 0.5 v p - p 73 db dc performance nominal gain v in to v out 0.49 0.50 0.51 v/v ada4830 - 1 w/ ada4830 - 2 w only t min to t max 0.49 0.51 v/v output bias voltage 1.60 1.65 1.70 v ada4830 - 1 w/ ada4830 - 2 w only t min to t max 1.59 1.71 v input characteristics input resistance (differentia l mode) 6. 7 k? input resistance (common mode) 2 k? input common - mode voltage range v ref voltage adjusted to optimized range ? 8 + 6 v ada4830 - 1 w/ ada4830 - 2 w only t min to t max ?8 +6 v common - mode rejection (cmr) v in = 3.3 v 41 54 db ada4830 - 1 w/ ada4830 - 2 w only t min to t max 40 db short - to - battery characterist ics input current v in = 18 v (short - to - battery) 4.4 ma protected input voltage range ?9 +20 v ada4830 - 1 w/ ada4830 - 2 w only t min to t max ?9 +20 v sho rt - to - battery output flag trigger level minimum vin needed to signal an input fault condition 7.4 7.8 8.2 v ada4830 - 1 w/ ada4830 - 2 w only t min to t max 7.4 8.2 v
data sheet ada4830- 1/ada4830 - 2 rev. c | page 5 of 22 parameter test conditions /comments min typ max unit voltage reference input input voltage range 0.2 to 2.2 v input resistance 20 k? gain v ref to v out 1 v/v logic output/input characteristics stb v oh v in 7.4 v (normal operation) 3.3 v stb v ol v in 8.2 v (fault condition), ada4830 - 1 / ada4830 - 2 85/178 mv ena v ih voltage to enable device 1.8 v ena v il voltage to disable device 0.8 v output characteristics output voltage swing r l = 150 ? to ground 0.01 to 3.08 v linear output current <1% thd at 100 k hz 50 ma short - circuit current sourcing/sinking 85/180 ma capacitive load drive peaking 4 db 47 pf power supply operating range operation outside of this range results in performance degradation 2.9 5.5 v quiescent current per amplifier enabled (en a = 3.3 v), no load 5.5 8.0 ma ada4830 - 1 w/ ada4830 - 2 w only t min to t max 8.4 ma disabled (ena = 0 v), no load 60 a v in = 18 v (short - to - battery), no load 4.3 ma power supply rejection ratio (psrr) +v s = 3.0 v to 3.6 v, v ref forced to 1.65 v 42 db operating temperature range ?40 +125 c
ada4830- 1 /ada4830- 2 data sheet rev. c | page 6 of 22 absolute maximum rat ings table 3 . parameter rating supply voltage (+vs p in) 6 v supply voltage delta +vs1 to +vs2, ada4830 - 2 only 0.5 v input voltage positive dir ection (inn x , inp x ) 22 v input voltage negative direction (inn x , inp x ) ? 10 v reference voltage (vref x p in) +v s + 0.3 v power dissipation see figure 3 storage temperature range ?65c to +1 5 0 c operating temperature range ?40 c to +125c lead temperature (soldering, 10 sec) 260c junction temperature 150c s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y . thermal resistance ja is specified for the device and its exposed paddle is soldered to a high thermal conductivity , 4 - layer (2s2p) circuit board, as described in eia/ jesd 51 - 7. table 4 . package type ja jc unit 8 - lead lfcsp 50 5 c/w 16- lead lfcsp 54 6 c/w maximum power dissip ation the maximum safe power dissipation in the ada4830 - 1 and ada4830 - 2 package s is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. exceeding a junct ion temperature of 150c for an extended time can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the supply voltage ( + v s ) times the quiescent current (i s ). the power dissipated due to load drive depends on the particular application. the power due to load drive is calculated by multiplying the lo ad current by the associated voltage drop across the device. rms voltages and currents must be used in these calculations. airflow increases heat dissipation, effectively reducing ja . figure 3 shows the maximum power dissipation in the package vs. the ambient temperature for the 8 - lead lfcsp ( 116c/w) and the 16 - lead lfcsp (54c/w) o n a jedec standard 4 - layer board. ja values are approximate. 10020-050 0 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40 50 60 70 80 90 100 maximum power dissi pa tion (w) ambient temper a ture (c) 16-lead lfcsp 8-lead lfcsp figure 3 . maximum power dissipation vs. ambient temperature for a 4 - layer board esd caution
data sheet ada4830- 1/ada4830 - 2 rev. c | page 7 of 22 pin configuration s and function descrip tions notes 1. exposed pad on bottom side of package. not connected electrically, but should be soldered to a metalized area on the pcb to minimize thermal resistance. 3 inn 4 gnd 1 vref 2 inp 6 vout 5 stb 8 +vs 7 ena ada4830-1 top view (not to scale) 10020-003 figure 4. ada4830 - 1 pin configuration table 5 . ada4830 - 1 pin function descriptions pin no. mnemonic description 1 vref voltage reference inpu t. sets the output dc bias voltage. internally biased to +v s /2 when left floating. see the applications information section . 2 inp positive input. 3 inn negative i nput . 4 gnd power supply ground p in . 5 stb short - to - battery indicator output pi n. a logic low indicates an overvoltage condition ( short - to - battery ), wh ereas a logic high indicates normal operation. an open - drain configuration requires external pull - up resistor. 6 vout amplifier output. 7 ena e nable pi n . connect to +v s or float for normal operation. connect to ground for device disable. 8 +vs positive power supply pin . bypass this pin with a 0.1 f capacitor to ground . epad exposed p ad . the exposed pad is located on the bottom side of the package. th e pad is not connected electrically but should be soldered to a metalized area on the printed circuit board (pcb) to minimize thermal resistance.
ada4830- 1 /ada4830- 2 data sheet rev. c | page 8 of 22 10020-004 12 11 10 1 3 4 vout1 notes 1. exposed pad on bottom side of package. not connected electrically, but should be soldered to a metalized area on the pcb to minimize thermal resistance. stb1 stb2 9 vout2 inp1 inn2 2 inn1 inp2 6 gnd2 5 vref2 7 +vs2 8 ena2 16 vref1 15 gnd1 14 +vs1 13 ena1 top view ada4830-2 figure 5. ada4830 - 2 pin c onfiguration table 6 . ada4830 - 2 pin function descriptions pin no. mnemonic description 1, 4 inp 1, inp2 positive i nput s. 2, 3 inn 1, inn2 negative i nput s. 5, 16 vref 2, vref1 voltag e reference input s . sets the output dc bias voltage. internally biased to +v s /2 when left floating. see the applications information section. 6, 15 gnd 2, gnd1 power supply ground pin s. 7, 14 +vs 2, +vs1 positive power supply p in s . these pins must be connected together, to the same voltage. bypass th e s e pin s with a 0.1 f capacitor to ground . 8, 13 ena 2, ena1 e nable p in s . connect to +v s or float for normal operation and to ground for device disable . 9, 12 vout 2, vout1 amplifier output s. 10, 11 stb2, stb1 short - to - battery indicator output pins . a logic low indicates an overvoltage condition ( short - to - battery ), wh ereas a logic high indicates normal operation. an o pen - drain configuration requires an external pull - up resistor. e pad exposed pad. the exposed pad is located on the bottom side of the package. the pad is n ot connected electrically, but should be soldered to a metalized area on the pcb to minimize thermal resistance.
data sheet ada4830- 1/ada4830 - 2 rev. c | page 9 of 22 typical performance characteristics t a = 25 c, +v s = 5 v, r l = 1 k?, v ref = 2.5 v (floating), v incm = +v s /2, r st b = 5 k to +v s , unless otherwise specified . 3 0 ?3 ?6 ?9 ?12 ?15 ?18 0.1 1 10 100 frequency (mhz) normalized gain (db) 10020-005 v in = 200mv p-p r l = 150? r l = 1k? figure 6. small signal frequency response for various load s 3 0 ?3 ?6 ?9 ?12 ?15 ?18 0.1 1 10 100 frequency (mhz) normalized gain (db) 10020-006 v in = 200mv p-p +v s = 3.3v +v s = 5v figure 7. small signal freque ncy response for various supply voltages 3 0 ?3 ?6 ?9 ?12 ?15 ?18 ?21 ?24 1 10 100 frequency (mhz) normalized gain (db) 10020-008 +125c +25c ?40c v in = 200mv p-p figure 8. small signal frequency response for various temperatures 3 0 ?3 ?6 ?9 ?12 ?15 ?18 0.1 1 10 100 frequency (mhz) normalized gain (db) 10020-010 v in = 1v p-p r l = 150? r l = 1k? figure 9. large signal frequency response for various loads 3 0 ?3 ?6 ?9 ?12 ?15 ?18 0.1 1 10 100 frequency (mhz) normalized gain (db) 10020-0 1 1 v in = 1v p-p +v s = 3.3v +v s = 5v figure 10 . large signal frequency response for various supply voltage s 3 0 ?3 ?6 ?9 ?12 ?15 ?18 ?21 ?24 1 10 100 frequency (mhz) normalized gain (db) 10020-013 +25c +125c ?40c +v s = 3.3v v in = 1v p-p r l = 150? figure 11 . large signal frequency response for various temperatures
ada4830- 1 /ada4830- 2 data sheet rev. c | page 10 of 22 7 6 5 4 3 2 1 0 ?1 ?2 ?3 0.1 1 10 100 frequency (mhz) normalized gain (db) 10020-012 v in = 1v p-p r l = 150? c l = 0pf c l = 68pf no series output resistor c l = 47pf c l = 22pf c l = 10pf figure 12 . large signal frequency response for various ca p acitor loads 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0.1 1 10 100 frequency (mhz) normalized gain (db) 10020-014 v in = 1v p-p r l = 150? figure 13 . 0.1 db flatness ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 0.1 1 10 100 common-mode rejection (db) frequenc y (mhz) 10020-042 v in = 1v p-p v incm = ?8v v incm = +8v v incm = 0v figure 14 . cm r frequency response for various input common - mode voltage s ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 common-mode rejection (db) input common-mode vo lt age (v) v in = 200mv p-p f = 5mhz +v s = 3.3v +v s = 5.0v 10020-017 figure 15 . small signal cmr vs. v incm for various su pply voltage s ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.1 1 10 100 gain (db) frequenc y (mhz) 10020-019 v in = 1v p-p ena = 0v figure 16 . input - to - output isolation with device disabled 6 3 0 ?3 ?6 ?9 ?12 ?15 0.1 1 10 100 frequency (mhz) normalized gain (db) 10020-009 v ref = 200mv p-p +v s = 5.0v r l = 1k? +v s = 3.3v r l = 150? +v s = 5.0v r l = 150? +v s = 3.3v r l = 1k? figure 17 . v ref to v out frequency response
data sheet ada4830- 1/ada4830 - 2 rev. c | page 11 of 22 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 0 10 20 30 40 50 60 70 80 output vo lt age (v) time (ns) 10020-020 +v s = 3.3v v out = 1v p-p r l = 1k r l = 150 figure 18 . pulse response at +v s = 3.3 v ?2 0 2 4 6 8 10 12 14 16 0 50 100 150 200 250 300 350 500 400 450 volt age (v) time (ns) 10020-022 inp r stb = 500 ? r stb = 1k ? c stb = 1 1pf r stb = 5k ? figure 19 . short - to - battery output flag response for various r stb , ada4830 - 1 6 5 4 3 2 1 0 ?1 100 0 200 300 400 500 600 time (ns) voltage (v) 10020-024 ena v out figure 20 . enable turn - on/turn - off time ?2 0 ?1 0 0 1 0 2 0 3 0 4 0 ?1 2 ?1 0 ? 8 ? 6 ? 4 ? 2 0 2 4 6 8 1 0 1 2 1 4 output offset vo lt age (mv) i n pu t c o mmo n -mo d e vo l t a g e (v) 10020-033 +v s = 3 . 3 v +v s = 5 v figure 21 . ou tput offset voltage (v out ? v ref ) vs. input common - mode voltage 0 1 2 3 4 5 6 7 8 9 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supp l y current (ma) enable vo lt age (v) v inp, v inn = floating +v s = 3.3v +v s = 5v 10020-134 figure 22 . supply current vs. enable voltage 0 20 40 60 80 100 120 140 46 51 56 61 66 71 76 81 86 91 count cmr (db) 10020-045 figure 23 . typical distribution of common - mode rejection
ada4830- 1 /ada4830- 2 data sheet rev. c | page 12 of 22 10020-046 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 0.1 1 10 100 cross t alk (db) frequenc y (mhz) v in = 2v p-p figure 24 . crosstalk (out put - to- output) vs. frequency, ada4830 - 2 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 10 20 30 40 50 60 70 80 90 100 v out (v) time (ns) v in = 4v p-p c l = 0pf c l = 22pf c l = 10pf 10020-047 figure 25 . pulse response for various capacitor loads 10 100 1k 10k 10 100 1k 10k 100k 1m 10m 100m volt age noise (nv/hz) frequenc y (hz) 10020-048 figure 26 . total output voltage noise vs. frequency 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 supp l y current (ma) temper a ture (c) 10020-051 figure 27 . supply current vs. temperature 10020-028 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 0.01 0.1 1 10 distortion (dbc) frequency (mhz) v out = 1v p-p single-ended input hd2 single-ended input hd3 differential input hd2 differential input hd3 figure 28 . harmonic distortion vs frequency ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 100 1k 10k 100k 1m 10m psr (db) frequenc y (hz) 10020-029 +v s ripple = 100mv p-p c vref = 0.1f c vref = 10f c vref = 4.7f figure 29 . psr v s. frequency for various vref bypass capacitors
data sheet ada4830- 1/ada4830 - 2 rev. c | page 13 of 22 theory of oper ation core amplifier at the core of the ada4830 - 1 and ada4830 - 2 are high speed , rail - to - rail op amp s that are built on a 0.35 m cmos process. toge th er with the core amplifier, t he ada4830 - 1 and ada4830 - 2 combine four h ighly matched on - chip resistors into a difference amplifier function. com mon - mode range extension at its inputs is achieved by employing a resistive attenuator . the closed - loop differential to single - ended gain of the video channel is internally fixed at 0.5 0 v/v ( ? 6 db) to ensure compatibility with video decoders whose input range is constrained to 1 v p - p or less. the transfer function of the ada4830 - 1 and ada4830 - 2 is ref inn inp out v v v v + ? = 2 w here : v out is the voltage at the output pin , vout . v in p and v in n are th e input voltages at the inp and inn pins , respectively . v ref i s the voltage at the vref pin. overvoltage ( short - to - b attery ) protection robust inputs guarantee that sensitive internal circuitry is not subjected to extreme voltages or currents during a stre ssful event. a short - to - battery condition usually consists of a voltage o n either input (or both inputs) that is significantly higher than the power supply voltage of the amplifier . duration may vary from a short transient to a continuous fault. the ada4830 - 1 and ada4830 - 2 can withstand voltages of up to 18 v on the inputs. critical internal nodes are protected from exposure to high voltages by circuitry that cl am ps the inputs at a safe level and limits internal currents. this protection is available whether the device is enabled or disabled, even when the supply voltage is removed. short - to - b attery output flag the short - to - battery output flag (stb pin) is functio nally independent of the short - to - battery protection. its purpose is to indicate an overvoltage condition on either input. because protection is provided passively, it is always available; the flag merely indicates the presence or absence of a fault condit ion. esd protection all pins on the ada4830 - 1 and ada4830 - 2 are protected with in ternal esd protection structures connected to the po wer supply pins (+v s and gnd) . these structures provide protection during the handling and manufacturing process. the inputs (inn and inp) of the ada4830 - 1 and ada4830 - 2 can be exposed to dc voltages well above the supply voltage ; therefore, conventional esd structure protection can not be used. the ada4830 - 1 and ada4830 - 2 employ analog devices, inc., proprietary esd devices at the input pins (inn, inp) to allow for a wide common - mode voltage range and esd protection well beyond the handling and manufacturing requirements. the inputs of the ada4830 - 1 and ada4830 - 2 are esd protected to survive 8 kv human body model (hbm) power supply pins ( ada4830 - 2 ) as indicated in the ab solute maximum ratings section , the voltage differen ce between the +vs1 and +vs2 pins of the ada4830 - 2 cannot exceed 0.5 v. to ensure compliance with the absolute maximum ratings, it is recommended that these supply pins be connected together to the same power supply source .
ada4830- 1 /ada4830- 2 data sheet rev. c | page 14 of 22 applications informa tion methods of transmiss ion pseudo differential mode (unbalanced source termination) the ada4830 - 1 and ada4830 - 2 can be operated in a pseudo differential configuration with an unbalanced input signal. this allows the receiver to be driv en by a single - ended source. pseudo differential mode uses a single conductor to carry a n unbalanced signal and connects the negative input terminal to the ground reference of the source. use t he positive wire or coax ial center conductor to connect the source output to the positive input (inp) of the ada4830 - 1 or ada4830 - 2 . next, connect t he negative wire or coax ial shield from the negative input (inn) back to a ground reference on the source pri nted circuit board ( pcb ). the input termination sh ould match the source impedance and be referenced to the remote ground. an example of this configuration is shown in figure 30. inn inp ada4830-1 75 ? ? + 75 ? positive wire negative wire driver pcb single-ended amplifier 10020-034 figure 30 . pseudo d ifferential mode pseudo d ifferential mode (balanced source i mpedance) pseudo differential signaling is typically implemented using unbalance d source termination , as shown in figure 30 . with this arrangement, however, common - mode signals on the positive and negative inputs r eceive different attenuation due to unbalance d termination at the source. this effectively converts some of the common - mode signal into differential mode signal , degrading the overall common - mode rejection of the system. system common - mode rejection can be improved by balancing the output impedance of the driver , as shown in figure 31. splitting the source termination resistance evenly between the hot and cold conductors results in matched attenuation of the common - mode signals, ensuring maximum rejection. inn inp ada4830-1 75 ? ? + 37.5 ? 37.5 ? positive wire negative wire driver pcb 10020-035 single-ended amplifier figure 31 . pseudo d ifferential mode with balanced source impedance fully differential mode the differential inputs of the ada4830 - 1 and ada4830 - 2 allow full balanced transmission using a differential source. in this configuration, the differential input termination is equal to twice the so urce impedance of each output. for example, a source wi th 37.5 ? back termination resistors in each leg should be terminated with a diff erential resistance of 75 ?. an illustration of this arrangement is shown in figure 32. inn inp ada4830-1 75 ? ? + 37.5 ? 37.5 ? positive wire negative wire driver pcb 10020-036 differential amplifier figure 32 . fully d ifferential mode voltage reference (v ref pin) an internal reference level (v ref ) determines the output voltage when the differential input voltage is zero. a resistor divider connected between the supply rails sets the v ref voltage . built with a pair of matched 40 k? res istors, the divider set s this voltage to +v s /2. the voltage reference pin (vref) normally float s at its default value of +v s /2. however, it can be used to vary the output reference level from this default value. a voltage applied to vref appear s at the ou tput with unity gain, within the bandwidth limit of the internal reference buffer. figure 17 shows the frequency response of the vref input. any noise on the +v s supply rail appear s at the output with only 6 db of attenuation (the divide - by - two provided by the reference divider). even when this pin is floating, it is recommended that an external capacitor be connected from the reference node to ground to provide further attenuation of noise on the power supply line. a 4.7 f capaci tor combined with the internal 40 k? resistor set s the low - pass corner at under 1 hz and result s in better than 40 db of supply noise attenuation at 100 hz.
data sheet ada4830- 1/ada4830 - 2 rev. c | page 15 of 22 input common - mode range in a standard four resistor difference amplifier with 0.5 0 v/v gain, the input common - mode (cm) ra nge is three times the cm range of the core amplifier. in the ada4830 - 1 and ada4830 - 2 , however, the input cm range h as been extended to more than 18 v (with a 5 v supply). the input cm range can be approximated by using the following formulas: for the m aximum cm voltage , 5( +v s ? 1.25) ? 4 v ref v incm(max) 9.5 v for the m inimum cm voltage , ? 10 v v incm(min) ? (1 + 4 v ref ) approximate minimum and maximum cm voltages are shown in table 7 for several common supply voltages. table 7 . input common -m ode range examples +v s (v) v ref (v) v incm(min) (v) v incm(max) (v) 3.0 1.5 1 C 7.0 2. 8 3.0 0.97 C 4.9 4.9 3.3 1.65 1 C 7.6 3. 6 3.3 1.15 C 5.6 5. 6 3.6 1.8 1 C 8.2 4.5 3.6 1.34 C 6.4 6.4 5.0 2.5 1 C 10 8. 7 5.0 2.22 C 9.9 9. 5 1 floating (default condition) . ?1 5 ?1 0 ? 5 0 5 1 0 1 5 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 6 . 0 input common-mode vo lt age (v) s u pp l y vo l t a g e (v) v i ncm (m a x ) v i ncm (m i n ) vref p i n flo a t i n g 10020-037 figure 33 . input common - mode range vs. supply voltage short - to - b attery output flag pin the flag output (stb) is an active low, open - drain logic configuration . a low level on this output indicates that an overvoltage event has been detected on either the positive or the negative input or both . flags from multiple chips can be wire - or 'ed to form a single fault detection signal. the output is driven by a grounded source nmos device, capable of sinking approximately 10 m a while pulling within a few hundred millivolts above ground. the output high level is set with an external pull - up resistor connected to the supply voltage of the logic family that is used to monitor the state of the flag. in the falling direction, t he s peed with which the flag output responds primarily depend s on the external ca pacitance attached to this node and the sink current that can be provided. for example, if the load is 10 pf, and the external pull - up voltage is 3.3 v, the fall time is a few nan oseconds. in the rising direction, the speed is determined by external capacitance and the magnitude of the pull - up resistor. for the case of 10 pf of external capacitance and a pull - up of 5 k?, the time constant of the rising edge is approximately 50 ns. table 8 . stb pin function stb pin output device state high (logic 1) normal operation low (logic 0) stb fault condition enable/disable modes (e na pin) the power - down, or enable/disable (ena) pin, is internally pulled up to +v s through a 250 k? resistor. when the voltage on this pin is high, the amplifier is enabled; pulling ena low disables the channel. with no external connection, this pin float s high, enabling the amplifier channel. table 9 . ena pin function ena pin input device state high (logic 1) enabled low (logic 0) disabled hi gh - z (floating) normal operation pcb layout as with all high speed applications, atten tion to pcb layout is of paramount importance. adhere to s tandard high speed layout practices in design s using the ada4830 - 1 and ada4830 - 2 . a solid ground plane i s recommended, and placing a 0.1 f surface - mount, ceramic power supply, decoupling capacitor as close as possible to the supply pin (s) is recommended . connect t he gnd pin(s) to the ground plane with a trace that is as short as possible. in cases where th e ada4830 - 1 and ada4830 - 2 drive transmission lines, series terminate the outputs and use c ontrolled impedance traces of the shortest length possible to connect to the signal i/o pins , which should not pass over any voids in the ground plane. exposed paddle (epad ) connection the ada4830 - 1 and ada4830 - 2 have an exposed ther mal pad ( e pa d ) on the bottom of the package. this pad is not electrically connected to the die and can be left floating or connected to the ground plane. should heat dissipation be a concern, thermal resistance can be minimized by soldering the epad to a m etalized pad on the pcb. connect t his pad to the ground plane with multiple vias. note that the thermal resistance ( ja ) of the device is specified with the epad soldered to the pcb.
ada4830- 1 /ada4830- 2 data sheet rev. c | page 16 of 22 using the ada4830 - 2 as a low cost video switch figure 34 shows a video multiplexer/switch using the ada4830 - 2 , dual, high speed difference amplifier. this circuit allows the user to input tw o remote video sources into a single channel of a video decoder, such as the adv7180 . traditional cmos multiplexers and switches suffer several disadvantages at video frequencies where their on - resistance introd uces distortion, degrades differential gain and phase performance, and interacts with the termination resistor to attenuate the incoming video signal and affect the luminance. system designers generally address these issues by adding external buffers to ad d gain and increase drive capability. video multiplexing can be simplified by using high speed video amplifiers with a disable/enable function (sometimes called power - down). when the amplifier is disabled, its output stage goes into a high impedance state , allowing several amplifier output s to be wired together. high speed video op amps have all the key features required to make them ideal for this function. their high input impedance does not affect the characteristic impedance of the transmission line, t hus allowing back termination. they also have inherently good video specifications, including differential gain and phase, slew rate, bandwidth, and 0.1 db flatness. each channel of the ada4830 - 2 is a high sp eed difference amplifier circuit that eliminates common - mode noise and phase noise caused by ground potential differences between the incoming video signal and the receiver. the ada4830 - 2 also offers integrate d short - to - battery protection and heightened esd tolerance in a small foot print. the fault detection output ( the stb pins ) of the ada4830 - 2 allows for proactive wire diagnostics when connected to a microcontr oller or video decoder and are used to generate an interrupt during a fault condition. ada4830-2 inp1 gnd2 vref2 +vs2 0.1f ena2 enable2 (input) +v s 4.7f 4.7f vref1 +vs1 gnd1 ena1 vout1 vout2 stb1 stb2 5k ? 5k ? +v s +v s 1 2 3 4 6 7 8 5 12 11 10 9 15 14 13 16 75 75 75 differential input 1 75 75 differential input 2 connect to video decoder 75 inn1 inn2 inp2 stb flags (outputs) 2.2f 0.1f + enable1 (input) 10020-049 figure 34 . low cost video switch u sing the ada4830 - 2
data sheet ada4830- 1/ada4830 - 2 rev. c | page 17 of 22 driving capacitive l oads the ada4830 - 1 and ada4830 - 2 are capable of driving large capacitive loads while maintaining its rated performance. several performance curves vs . capacitive load are shown in figure 12 and figure 25. capacitive loads interact with an op amps output impedance to create an extra delay in the feedback path. this reduces circuit stability and can cause unwanted ringing and oscillation. the capacitive load drive of the ada4830 - 1 and ada4830 - 2 c an be increased by adding a low valued resistor , r s , in series with the capacitive load. figure 35 shows the test circuit. ada4830-1 + ? c l = 47pf r s = 49.9? r l = 1k? 10020-052 figure 35 . r s test circuit introducing a series resistor tends to isolate the capacitive load from the feedback loop, thereby diminishing its influence. one drawback to this approach is a slight loss of signal amplitude. figure 36 shows the effects of a series resistor on the capacitive drive. for very large capacitive loads, the frequency response of the amplifier is dominated by the roll - off of the series resistor and capacitive load. 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 50 100 150 200 250 v out (v) time (ns) 10020-135 +v s = 5v r l = 1k c l = 47pf no r s r s = 49.9 ? figure 36 . pulse response w ith and w ithout series resistor another method of reducing the resonant peaking cause d by d riving large capacitive load s at the output of the ada4830 - 1 and ada4830 - 2 is with the u se of a r - c sh unt circuit or a snubber circuit . this method acts to resist ively load the amplifier output , thus reducing frequency response peaking. one drawback to this approach is a slight loss of signal bandwidth. figure 37 shows a simple circuit representation of the implementation o f the r - c snubb er circuit with r snt and c snt . figure 38 shows the effects of a r - c snubber circuit driving 47 pf, where r snt = 73.2 ? and c snt = 0.1 f. ada4830-1 + ? c l = 47pf c snt = 0.1uf r l = 1k? r snt = 73.2? 10020-053 figure 37 . r - c test circuit 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 50 100 150 200 250 v out (v) time (ns) 10020-137 +v s = 5v r l = 1k c l = 47pf no snubber circuit r snt = 73.2 c snt = 0.1 f figure 38 . pulse response w ith and w ithout r - c s nubber circuit
ada4830- 1 /ada4830- 2 data sheet rev. c | page 18 of 22 typical application s circuits inn vout to video decoder gnd inp vref ada4830-1 75 ? ? + 75 ? positive wire negative wire driver pcb + stb ena +vs single ended amplifier 4.7f 0.1f +vs enable (input) stb flag (output) 2.2f 0.1f +v s (2.9v to 5.5v) 5k ? 1 10020-038 figure 39 . typical applicati on with pseudo d ifferential input inn vout to video decoder gnd inp ada4830-1 75 ? ? + 37.5 ? 37.5 ? driver pcb stb ena +vs 4.7f 0.1f +vs + enable (input) stb flag (output) 2.2f 0.1f 5k ? 1 +v s (2.9v to 5.5v) vref differential amplifier 10020-039 figure 40 . typical application with fully differential input
data sheet ada4830- 1/ada4830 - 2 rev. c | page 19 of 22 ? + adv7180 inn vout gnd inp ada4830-1 75 ? + stb ena +vs 4.7f 0.1f 0.1f 21 25 24 23 19 3 14 30 22 18 a in 1 a in 2 a in 3 20 13 11 32 1 31 4 12 26 28 17 82nf 10nf 2 29 elpf 27 alsb sclk sclk dgnd dgnd sda sdata xtal1 xtal 0.1f +vs enable (input) stb flag (output) 2.2f 0.1f 5k ? +v s (2.9v to 5.5v) vref d vddio 0.1 f 10 nf a vdd _1.8v 0.1 f 10 nf 0.1 f 10 nf d vdd _1.8v d vdd _3.3v d vddio p vdd _1.8v p vdd _1.8v d vdd _1.8v a vdd _1.8v 0.1 f 10 nf keep vrefn and vrefp capacitors as close as possible to the adv7180 and on the same side of the pcb as the adv7180. locate close to, and on the same side as, the adv7180 alsb tied hi i 2 c address = 0x42 alsb tied low i 2 c address = 0x40 reset reset p0 p1 p2 p3 p4 p5 p6 p7 p0 ycrcb 8-bit 656 data p[0:7] p1 p2 p3 p4 p5 p6 p7 16 15 10 9 8 7 6 5 vrefn dvddio dvdd dvdd avdd pvdd vrefp 28.63636mhz 47pf 47pf 1m ? 4k ? llc 1.69k ? intrq sfl vs/field external loop filter keep close to the adv7180 and on the same side of pcb as the adv7180. hs llc intrq sfl vs/field hs 10020-040 1 figure 41 . ada4830 - 1 d riving an adv7180 video decoder the ada4830 - 1 and ada4830 - 2 are differential receivers whose overall performance is independent of the transmitter ic used and whether the transmission line is ac - coupled or dc - coupled. the ada4830 - 1 and ada4830 - 2 are specifically designed to perform as differential line receiver s . the circuit in figure 41 sh ows a detailed schematic of the ada4830 - 1 and the adv7180 configured for this function. the signal is received differentially relative to the common of the source circuitry , and that voltage is exactly reproduced with an attenuating gain of 0.5 0 v/v . this is designed to keep the video signal within the allowed range of the video decoder, which is typically 1 v p - p or less. the common - mode rejection vs . frequency, shown in figure 14, typically 6 5 db at low frequencies , enables the recovery of video signals in the presence of large common - mode noise. the hig h input impedance permits the ada4830 - 1 and ada4830 - 2 to operate as a bridging amplifier across low impedance terminations with negligible loading.
ada4830- 1 /ada4830- 2 data sheet rev. c | page 20 of 22 f ully dc - co upled transmission line the wide input common - mode range and high input impedance of the ada4830 - 1 and ada4830 - 2 allow them to be used in fully dc - coupled tr ansmission line applications in which there m ay be a significant discrepanc y between voltage levels at the ground pins of the driver and receiver. as long as the voltage difference between reference levels at the transmitter and receiver is within the comm on - mode range of the receiver, very little current flow result s, and no image degradation should be anticipated. figure 42 shows an example configuration of a completely dc - coupled transmission using a low impedan ce differential d river. r t +v s inn vout to video decoder gnd inp ada4830-1 75 ? ? + gnd lpf lpf + + stb ena +vs 4.7f 0.1f +vs enable (input) stb flag (output) 2.2f 0.1f 5k ? +v s (2.9v to 5.5v) stb ena +vs enable (input) stb flag (output) 2.2f 0.1f +v s (2.7v to 3.6v) vref +in ?in ?out +out ? + 75 ? twisted pair 37.5 ? 37.5 ? from imager or video encoder 1 10020-041 figure 42 . differential video filter driver and ada4830 - 1 difference amplifier
data sheet ada4830- 1/ada4830 - 2 rev. c | page 21 of 22 packaging and orderi ng information outline dimensions 2.44 2.34 2.2 4 t op view 8 1 5 4 0.30 0.25 0.20 b o t t o m v i e w pin 1 index are a sea ting plane 0.80 0.75 0.70 1.70 1.60 1.50 0.203 ref 0.05 max 0.02 nom 0.50 bsc e x p o s e d p a d 3.10 3.0 0 sq 2.90 pin 1 indica t or (r 0.15) for proper connection of the exposed pad, refe r to the pin confi gurat ion and funct ion descr iptio ns secti on of this data sheet. copla narit y 0.08 0.50 0.40 0.30 complian t t o jedec stand ards mo-229-wee d 01-24-201 1-b figure 43 . 8- lead lead frame chip scale package [lfcsp _wd] 3 mm 3 mm body, very very thin, dual lead (cp - 8 - 11) dimensions shown in millimeters 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 0.50 0.40 0.30 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. figure 44 . 16 - lead lead frame chip scale package [lfcsp _wq ] 3 mm 3 mm body, very very thin quad (cp - 16 - 22) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option branding ordering quantity ada4830 - 1bcp - ebz evaluation board ada4830 - 1bcpz -r7 ?40c to +125c 8 - lead lead frame chip scale package [lfcsp _wd ] cp -8 -11 h30 1 500 ada4830 - 1wbcpz - r7 ?40c to +125c 8 - lead lead frame chip scale package [lfcsp _wd ] cp - 8 - 11 4h1 1500 ada4830 - 1bcpz -r2 ?40c to +125c 8 - lead lead frame chip scale package [lfcsp _wd ] cp -8 -11 h30 250 ada4830 - 2bcpz -r7 ?40 c to +125c 16- lead lead frame chip scale package [lfcsp _wq ] cp -16-22 h31 1500 ada4830 - 2bcpz -r2 ?40c to +125c 16- lead lead frame chip scale package [lfcsp _wq ] cp -16-22 h31 250 ada4830 -2 w bcpz -r7 ?40c to +125c 16- lead lead frame chip scale package [lfc sp_wq] cp -16-22 4h2 1500 1 z = rohs compliant part. 2 w = qualified for automotive applications.
ada4830- 1 /ada4830- 2 data sheet rev. c | page 22 of 22 automotive products the ada4830 - 1 w and ada4830 - 2 w model s are available with controlled manufacturing to support the quality and reliabi lity requirements of automotive applications. note that th e s e automotive model s may have specifications that differ from the commercial model; therefore, designers should review the specifications section of this data sheet carefu lly. only the automotive grade product s shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for th e s e model s. ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10020 - 0- 6/12(c) www.analog.com/ ada4830 - 1/ada4830 - 2

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