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tle42694 low dropout fixed voltage regulator data sheet, rev. 1.1, october 2008 automotive power
pg-dso-8 pg-dso-14 pg-ssop-14 exposed pad type package marking TLE42694G pg-dso-8 42694g TLE42694Gm pg-dso-14 42694gm tle42694e pg-ssop-14 exposed pad 42694e data sheet 2 rev. 1.1, 2008-10-07 tle42694 low dropout fixed voltage regulator 1overview features ? output voltage 5 v 2% ? ouput current up to 150 ma ? very low current consumption ? early warning ? power-on and undervoltage reset with programmable delay time ? reset low down to v q = 1 v ? adjustable reset threshold ? very low dropout voltage ? output current limitation ? reverse polarity protection ? overtemperature protection ? suitable for use in automotive electronics ? wide temperature range from -40 c up to 150 c ? input voltage range from -42 v to 45 v ? integrated pull-up resistors at logic outputs ? green product (rohs compliant) ? aec qualified description the tle 42694 is a monolithic integrated low dropout voltage regulator, especially designed for au tomotive applicat ions. an input voltage up to 45 v is regulated to an output voltage of 5.0 v. the component is able to drive loads up to 150 ma. it is short-circuit proof by the implemented output current limitation and has an integrated overtemperature shutdown. a reset signal is generated for an output voltage v q,rt of typically 4.65 v. this threshold can be decreased by an external resistor divider. the power-on reset delay time can be programmed by the external delay capacitor. the additional sense comparator provides an early warning function: any voltage (e.g. the input voltage) can be monitored, an under-voltage condition is indicated by setting the comparator?s output to low. the reset and sense output are internally connected to the output q via a pull-up resistor. if these integrated resistors are not desired, the tle42794 can be used instead of the tle42694.
data sheet 3 rev. 1.1, 2008-10-07 tle42694 overview dimensioning information on external components the input capacitor c i is recommended for compensation of line influences. the output capacitor c q is necessary for the stability of the control loop. circuit description the control amplifier compares a reference voltage to a volta ge that is proportional to th e output voltage and drives the base of the series transistor via a buffer. saturation control as a function of the load current prevents any oversaturation of the power element. the component also has a number of internal circuits for protection against: ? overload ? overtemperature ? reverse polarity
tle42694 block diagram data sheet 4 rev. 1.1, 2008-10-07 2block diagram aeb01669 control saturation current and reference trimming 20 k ?? k 20 amplifier error reference d radj si q ro so & gnd figure 1 block diagram
data sheet 5 rev. 1.1, 2008-10-07 tle42694 pin configuration 3 pin configuration 3.1 pin assignment pg-dso-8 pg-dso-8 gnd ro so d5 6 7 radj 8 4 3 2 1 aep01668 q s , ? ? , c q and esr in ?functional range? on page 9
tle42694 pin configuration data sheet 6 rev. 1.1, 2008-10-07 3.3 pin assignment pg-dso-14 pg-dso-14 aep02248 q gnd si gnd ro gnd 10 9 gnd gnd 1 2 3 4 5 gnd 6 7so 14 13 12 11 d gnd 8 radj figure 3 pin configuration (top view) 3.4 pin definitions an d functions pg-dso-14 table 2 pin symbol function 1 radj reset threshold adjust connect an external voltage divi der to adjust reset threshold; connect to gnd for using internal threshold 2 d reset delay timing connect a ceramic capacitor to gnd for adjusting the reset delay time; leave open if the reset function is not needed 3, 4, 5, 6 gnd ground all pins must be connected to gnd 7 ro reset output open collector output; internally linked to the output via a 20k ? ? , c q and esr in the table ?functional range? on page 9 10, 11, 12 gnd ground all pins must be connected to gnd 13 i input for compensating line influences, a capacito r to gnd close to the ic terminals is recommended 14 si sense input connect the voltage to be monitored; connect to q if the sense comparator is not needed
data sheet 7 rev. 1.1, 2008-10-07 tle42694 pin configuration 3.5 pin assignment pg -ssop-14 exposed pad 3lq&rqiljb6623yvg 5$'- 6, qf ' *1' qf qf 52 , qf 4 qf qf 62 figure 4 pin configuration (top view) 3.6 pin definitions and functi ons pg-ssop-14 exposed pad table 3 pin symbol function 1 radj reset threshold adjust connect an external voltage divi der to adjust reset threshold; connect to gnd for using internal threshold 2, 5, 6 n.c. not connected 3 d reset delay timing connect a ceramic capacitor to gnd for adjusting the reset delay time; leave open if the reset function is not needed 4 gnd ground all pins must be connected to gnd 7 ro reset output open collector output; internally linked to the output via a 20k ? ? , , , c q and esr in the table ?functional range? on page 7 13 i input for compensating line influences, a capacito r to gnd close to the ic terminals is recommended 14 si sense input connect the voltage to be monitored; connect to q if the sense comparator is not needed
tle42694 general product characteristics data sheet 8 rev. 1.1, 2008-10-07 4 general product characteristics 4.1 absolute maximum ratings -40 c , v i , v si -40 45 v ? voltage v q , v ro , v so , v d -0.3 7 v ? voltage v radj -0.3 7 v ? current i radj -10 10 ma ? junction temperature t j -40 150 t stg -50 150 , , , , ,
data sheet 9 rev. 1.1, 2008-10-07 tle42694 general product characteristics 4.2 functional range pos. parameter symbol limit values unit conditions min. max. input voltage v i 5.5 45 v ? output capacitor?s requirements for stability c q 10 ? f 1) the minimum output capacitance requirement is appl icable for a worst case capacitance tolerance of 30% ? 1) esr(c q ) ? 3 ? f = 10 khz junction temperature t j -40 150
tle42694 general product characteristics data sheet 10 rev. 1.1, 2008-10-07 4.3 thermal resistance pos. parameter symbol limit value unit conditions min. typ. max. junction to soldering point 1) not subject to production test, specified by design 1) r thjsp ? 80 ? k/w measured to pin 5 junction to ambient 1) r thja ? 113 ? k/w 2) specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm3 boar d with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. ? 170 ? k/w footprint only 3) specified r thja value is according to jedec jesd 51-3 at nat ural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 r thjsp ? 27 ? k/w measured to group of pins 3, 4, 5, 10, 11, 12 junction to ambient 1) r thja ? 63 ? k/w 2) ? 104 ? k/w footprint only 3) ? 73 ? k/w 300mm 2 heatsink area on pcb 3) ? 65 ? k/w 600mm 2 heatsink area on pcb 3) junction to soldering point 1) r thjsp ? 10 ? k/w measured to pin 5 junction to ambient 1) r thja ? 47 ? 2) ? 145 ? k/w footprint only 3) ? 63 ? k/w 300mm 2 heatsink area on pcb 3) ? 53 ? k/w 600mm 2 heatsink area on pcb 3) 3) 2) TLE42694G (pg-dso-8) 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 TLE42694Gm (pg-dso-14) 4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 tle42694e (pg-ssop-14 exposed pad) 4.3.14 4.3.15 4.3.16 4.3.17 4.3.18
data sheet 11 rev. 1.1, 2008-10-07 tle42694 block description and electrical characteristics 5 block description and el ectrical characteristics 5.1 voltage regulator the output voltage v q is controlled by comparing a portion of it to an internal reference and driving a pnp pass transistor accordingly. th e control loop stability depe nds on the outpu t capacitor c q , the load current, the chip temperature and the poles/zeros introduced by the integr ated circuit. to ensure stable operation, the output capacitor?s capacitance and its equivalent series resistor esr requirements given in the table ?functional range? on page 9 have to be maintained. for details see also the typical performance graph ?output capacitor series resistor esr(cq) versus output current iq? on page 14 . as the output capacitor also has to buffer load steps it should be sized according to the application?s needs. an input capacitor c i is strongly recommended to compensate line in fluences. connect the capacitors close to the component?s terminals. a protection circuitry prevents the ic as well as the application from destruction in case of catastrophic events. these safeguards contain an output current limitation, a reverse polarity protection as well as a thermal shutdown in case of overtemperature. in order to avoid excessive power dissipation that coul d never be handled by the pass element and the package, the maximum output current is de creased at input voltages above v i = 22 v. the thermal shutdown circuit prevents the ic from imme diate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. after the chip has cooled down, the regulator restarts. this leads to an oscillatory behaviour of the output volt age until the fault is remo ved. however, junction temperatures above 150 c are outside the maximum ratings and ther efore significantly re duce the ic?s lifetime. the tle 42694 allows a negative supply voltage. in this fault condition, small currents are flowing into the ic, increasing its junction temperature. this has to be considered for the thermal design, respecting that the thermal protection circuit is not operating during reverse polarity conditions. bandgap reference gnd q i blockdiagram_voltageregulator.vsd saturation control curr ent lim itation tem peratur e shutdown c q load supply c i regulated output voltage i q i i figure 5 voltage regulator
electrical characteristics voltage regulator v i = 13.5 v, -40 c t j 150 c, all voltages with respect to groun d, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. output voltage v q 4.9 5.0 5.1 v 100 a < i q < 100 ma 6 v < v i < 18 v output current limitation i q,max 150 200 500 ma v q = 4.8v load regulation steady-state ? q,load -30 -15 ? mv i q = 5 ma to 100 ma i = 6 v line regulation steady-state ? q,line ? 10 40 mv v i = 6 v to 32 v q = 5 ma dropout voltage 1) measured when the output voltage v q has dropped 100mv from the nominal value obtained at v i = 13.5v 1) dr = v i - v q v dr ? 250 500 mv i q = 100 ma overtemperature shutdown threshold t j,sd 151 ? 200 c t j increasing 2) not subject to production test, specified by design overtemperature shutdown threshold hysteresis t j,sdh ? 15 ? c t j decreasing 2) power supply ripple rejection 2) psrr ? 70 ? db f ripple = 100 hz ripple = 0.5 vpp 2) tle42694 block description and electrical characteristics data sheet 12 rev. 1.1, 2008-10-07 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8
01_vq_tj.vsd 4,6 4,7 4,8 4,9 5 5,1 5,2 -40 0 40 80 120 160 t j [c] v q [v] i q = 5 ma v i = 13.5 v data sheet 13 rev. 1.1, 2008-10-07 tle42694 block description and electrical characteristics typical performance characteristics voltage regulator output voltage v q versus junction temperature t j output current i q versus input voltage v i power supply ripple rejection psrr versus ripple frequency f r line regulation ? v q,line versus input voltage change ? v i 02_iq_vi.vsd 0 50 100 150 200 250 300 0 10203040 v i [v] i q,max [ma] v q = 4.8 v t j = -40 c t j = 25 c t j = 150 c 03_psrr_fr.vsd 0 10 20 30 40 50 60 70 80 90 0,01 0,1 1 10 100 1000 f [khz] psrr [db] t j =25c i q = 10 ma c q =10f ceramic 04_dvq_dvi.vsd 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 010203040 v i [v] ? v q,line [mv] i q = 5 ma t j = -40 c t j = 25 c t j = 150 c
07_vdr_iq.vsd 0 50 100 150 200 250 300 0 20406080100 i q [ma] v dr [mv] t j = 150 c t j = 25 c t j = -40 c tle42694 block description and electrical characteristics data sheet 14 rev. 1.1, 2008-10-07 load regulation ? v q,load versus output current change ? i q output capacitor series resistor esr ( c q ) versus output current i q dropout voltage v dr versus output current i q dropout voltage v dr versus junction temperature t j typical performance characteristics voltage regulator 05_dvq_diq.vsd -14 -12 -10 -8 -6 -4 -2 0 0 20406080100 i q [ma] ? v q,load [mv] v i = 13.5 v t j = -40 c t j = 25 c t j = 150 c 06_esr_iq.vsd 0,01 0,1 1 10 100 0 50 100 150 i q [ma] esr(c q ) [ ? ] c q = 10 f v i = 13.5 v stable region unstable region 08_vdr_tj.vsd 0 50 100 150 200 250 300 -40 0 40 80 120 160 t j [c] v dr [mv] i q = 100 ma i q = 25 ma i q = 5 ma i q = 100 a
data sheet 15 rev. 1.1, 2008-10-07 tle42694 block description and electrical characteristics 5.2 current consumption electrical characteristics current consumption v i = 13.5 v, -40 c t j , pos. parameter symbol limit values unit conditions min. typ. max. current consumption i q = i i - i q i q ? 210 280 a i q = 100 a t j = 25 c ? 240 300 a i q = 100 a t j i q = 10 ma ? 3.5 8 ma i q = 50 ma 5.2.1 5.2.2 5.2.3 5.2.4
current consumption i q versus i q ( i q low) 09_iq_iq_iqlow.vsd 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 0 5 10 15 20 25 i q [ma] i q [ma] v i = 13.5 v t j =25c 10_iq_iq.vsd 0 2 4 6 8 10 12 0 20 40 60 80 100 120 i q [ma] i q [ma] v i = 13.5 v t j = 25 c current consumption i q versus i q 11_iq_vi.vsd 0 1 2 3 4 5 6 0 10203040 v i [v] i q [ma] r load = 100 ? load = 50 k ? i q versus v i tle42694 block description and electrical characteristics data sheet 16 rev. 1.1, 2008-10-07 typical performance characteristics current consumption
data sheet 17 rev. 1.1, 2008-10-07 tle42694 block description and electrical characteristics 5.3 reset function the reset function provides several features: output undervoltage reset: an output undervoltage condition is indicated by setting the reset output ro to ?low?. this signal might be used to reset a microcontroller during low supply voltage. power-on reset delay time: the power-on reset delay time t rd allows a microcontoller and oscillator to st art up. this delay time is the time frame from exceeding the reset switching threshold v rt until the reset is released by switching the reset output ?ro? from ?low? to ?high?. the power-on reset delay time t rd is defined by an external delay capacitor c d connected to pin d charged by the delay capacitor charge current i d,ch starting from v d = 0 v. if the application needs a power-on reset delay time t rd different from the value given in item 5.3.8 , the delay capacitor?s value can be derived from the specified values in item 5.3.8 and the desired power-on delay time: c d t rd new , t rd ---------------- 100nf = with ? c d : capacitance of the delay capacitor to be chosen ? t rd,new : desired power-on reset delay time ? t rd : power-on reset delay time specified in this datasheet for a precise calculation also take the dela y capacitor?s tolerance into consideration. reset reaction time: the reset reaction time avoids that short undervoltage spikes trigger an unwanted reset ?low? signal. the reset reaction rime t rr considers the intern al reaction time t rr,int and the discharge time t rr,d defined by the external delay capacitor c d (see typical performance graph for details). hence, the total reset reaction time becomes: t rr t rd int , t rr d , + = with ? t rr : reset reaction time ? t rr,int : internal reset reaction time ? t rr,d : reset discharge optional reset output pull-up resistor r ro,ext : the reset output ro is an open co llector output with an integrated pull-up resistor. to improve the emc behaviour of the component, an external pull-up resistor to the output v q can be added. in table ?electrical characteristics reset function? on page 21 a minimum value for the external resistor r ro,ext is given.
tle42694 block description and electrical characteristics data sheet 18 rev. 1.1, 2008-10-07 reset adjust function the undervoltage reset switching threshold can be adjuste d according to the application?s needs by connecting an external voltage divider ( r adj1 , r adj2 ) at pin radj. for selecting the defa ult threshold connect pin radj to gnd. when dimensioning the volta ge divider, take into consid eration that there will be an add itional current constantly flowing through the resistors. with a voltage divider connected, the reset switching threshold v rt,new is calculated as follows: v rt new , r adj 1 , r + adj 2 , r adj 2 , ------------------------------------------ v radj th , = with ? v rt,new : the desired new reset switching threshold ? r adj1 , r adj2 : resistors of the external voltage divider ? v radj,th : reset adjust switchin g threshold given in table ?electrical characteristics reset function? on page 21
gnd q i blockdiagram_resetadjust.vsd or supply ro v dst in t. supply i d, ch i d, dch v radj, t h radj control d c d reset optional optional c q vdd micro- controller gnd r adj,1 r adj,2 r ro i ro i radj r ro, ext data sheet 19 rev. 1.1, 2008-10-07 tle42694 block description and electrical characteristics figure 6 block diagram reset function
v i t v q t v rt v ro timingdiagram_reset.v s t v ro,low 1 v 1v t rr,total t rd therm al shutdown input voltage dip t r r ,to ta l t rd t rd t < t r r ,to ta l t rd under - voltage spike at output over- load t rr,total v drl v du t v d tle42694 block description and electrical characteristics data sheet 20 rev. 1.1, 2008-10-07 figure 7 timing diagram reset
electrical characteristics reset function v i = 13.5 v, -40 c t j 150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. default output undervoltage reset switching thresholds v rt 4.5 4.65 4.8 v v q decreasing reset adjust switching threshold v radj,th 1.26 1.35 1.44 v 3.5 v v q < 5 v reset adjust ment range 1) v rt is scaled linearly, in case the reset switching threshold is modified 1) v rt,range 3.50 ? 4.65 v ? reset output low voltage v ro,low ? 0.1 0.4 v 1 v v q v rt no external r ro,ext reset output internal pull-up resistor to v q r ro 10 20 40 k ? ? optional reset output external pull-up resistor to v q r ro,ext 20 ? ? k ? 1 v v q v rt ; v ro 0.4 v delay pin output voltage v d ? ? 5 v ? power on reset delay time t rd 17 28 39 ms c d = 100 nf upper delay switching threshold v du ? 1.8 ? v ? lower delay switching threshold v dl ? 0.45 ? v ? delay capacitor charge current i d,ch ? 6.5 ? a v d = 1 v delay capacitor reset discharge current i d,dch ? 70 ? ma v d = 1 v delay capacitor discharge time t rr,d ? 1.9 3 s calculated value: t rr,d = c d *( v du - v dl )/ i d,dch c d = 100 nf internal reset reaction time t rr,int ? 3 7 s c d = 0 2) parameter not subject to production test; specified by design reset reaction time t rr,total ? 4.9 10 s calculated value: t rr,total = t rr,int + t rr,d c d = 100 nf nf 2) data sheet 21 rev. 1.1, 2008-10-07 tle42694 block description and electrical characteristics output undervoltage reset 5.3.1 output undervoltage reset threshold adjustment 5.3.2 5.3.3 reset output ro 5.3.4 5.3.5 5.3.6 reset delay timing 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 5.3.14 5.3.15
power on reset delay time t rd c d 13_trd_cd.vsd 0 10 20 30 40 50 60 70 0 50 100 150 200 250 c d [nf] t rd [m s] t j = 25 c tle42694 block description and electrical characteristics data sheet 22 rev. 1.1, 2008-10-07 typical performanc e characteristics power on reset delay time t rd t j 12_trd_tj.vsd 0 5 10 15 20 25 30 35 -40 0 40 80 120 160 t j [c] t rd [ms] c d = 100 nf
data sheet 23 rev. 1.1, 2008-10-07 tle42694 block description and electrical characteristics 5.4 early warning function the additional sense comparator provides an early warnin g function: any voltage (e.g. the input voltage) can be monitored, an undervoltage condition is indicat ed by setting the comparator?s output to low. aed03049 t sense t si, high v si, low v input voltage high low output sense figure 8 sense timing diagram electrical characteristics early warning function v i = 13.5 v, -40 c t j , , pos. parameter symbol limit values unit conditions min. typ. max. sense comparator input 5.4.1 sense threshold high v si,high 1.24 1.31 1.38 v ? 5.4.2 sense threshold low v si,low 1.16 1.22 1.28 v ? 5.4.3 sense switching hysteresis v si,hy 20 90 160 mv ? 5.4.4 sense input current i si -1 -0.1 1 a ?
tle42694 block description and electrical characteristics data sheet 24 rev. 1.1, 2008-10-07 sense comparator output 5.4.5 sense output low voltage v so,low ? 0.1 0.4 v v si < v si,low i > 5.5 v no external r so,ext 5.4.6 sense output in ternal pull-up resistor to v q r so,int 10 20 40 k ? ? 5.4.7 optional sense output external pull-up resistor to v q r so,ext 20 ? ? k ? i > 5.5 v so 0.4 v electrical characteristics early warning function v i = 13.5 v, -40 c t j 150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max.
data sheet 25 rev. 1.1, 2008-10-07 tle42694 package outlines 6 package outlines +0.06 0.19 0.35 x 45? 1) -0.2 4 c 8 max. 0.64 ?.2 6 ?.25 0.2 8x m c 1.27 +0.1 0.41 0.2 m a -0.06 1.75 max. (1.45) ?.07 0.175 b 8x b 2) index marking 5 -0.2 1) 4 1 85 a 1) does not include plastic or metal protrusion of 0.15 max. per side 2) lead width can be 0.61 max. in dambar area gps01181 0.1 figure 9pg-dso-8 you can find all of our packages, so rts of packing and others in our http://www.infineon.com/products . dimensions in mm
1) does not include plastic or metal protrusion of 0.15 max. per side 2) lead width can be 0.61 max. in dambar area -0.2 8.75 1) 0.64 0.19 +0.06 index marking 1.27 +0.10 0.41 0.1 1 14 2) 7 14x 8 0.175 (1.47) 0.07 ?.2 6 0.35 x 45? -0.2 1.75 max. 4 1) ?.25 8?max. -0.06 0.2 m ab m 0.2 c c b a gps01230 tle42694 package outlines data sheet 26 rev. 1.1, 2008-10-07 figure 10 pg-dso-14
pg-ssop-14-1,-2,-3-po v02 1 7 14 8 14 17 8 14x 0.25 ?.05 2) m 0.15 d c a-b 0.65 c stand off 0 ... 0.1 (1.45) 1.7 max. 0.08 c a b 4.9 ?.1 1) a-b c 0.1 2x 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include dambar protrusion bottom view ?.2 3 ?.2 2.65 0.2 ?.2 d 6 m d 8x 0.64 ?.25 3.9 ?.1 1) 0.35 x 45? 0.1 cd +0.06 0.19 8 ? max. index marking exposed diepad data sheet 27 rev. 1.1, 2008-10-07 tle42694 package outlines figure 11 pg-ssop-14 exposed pad green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. gree n products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). you can find all of our packages, so rts of packing and others in our http://www.infineon.com/products . dimensions in mm
tle42694 revision history data sheet 28 rev. 1.1, 2008-10-07 7 revision history revision date changes 1.1 2008-10-07 package version tle42694e in pg-ssop-14 exposed pad and all related information added in ?overview? on page 2 package graphic for pg-ssop-14 exposed pad and product name ?tle42694e? added in chapter 3 ?pin assignment pg-ssop-14 exposed pad? on page 7 and ?pin definitions and functions pg-ssop-14 exposed pad? on page 7 added in ?thermal resistance? on page 10 values for tle42694e added in ?package outlines? on page 25 outlines for tle4269e added 1.0 2008-08-25 initial version data sheet
edition 2008-10-07 published by infineon technologies ag 81726 munich, germany ? 2008 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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