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order number: 311998-006 6-sep-2006 intel ? ss72 nand flash memory JS29F02G08AANB3, js29f04g08banb3, js29f08g08fanb3 datasheet product features intel ? nand flash technology provides a cost-effective solution for applications requiring high- density solid-state storage. intel ? JS29F02G08AANB3 devices are 2gb nand flash memory devices. the js29f04g08banb3 devices are 4gb devices. the js29f08g08fanb3 devices are four-die stacks that operate as two independent 4gb devices, providing a total storage capacity of 8gb in a single, space-saving package. these devices include standard nand features as well as new features designed to enhance system-level performance. intel ? nand flash devices use a highly multiplexed 8- or 16-bit bus (i/o[7:0] or i/o[15:0]) to transfer data, addresses, and instructions. the five command signals (cle, ale, ce#, re#, we#) implement the nand command bus interface protocol. two additional signals control hardware write protection (wp#), and monitor device status (r/b#). this hardware interface creates a low-signal-count device with a standard interface that is the same from one density to another, supporting future upgrades to higher densities without board redesign. intel ? JS29F02G08AANB3 and js29f04g08banb3 devices contain 2,048 and 4,096 erasable blocks respectively. each block is subdivided into 64 programmable pages. each page consists of 2,112 bytes organization: page size: x8: 2,112 bytes (2,048 + 64 bytes); x16: 1,056 words (1,024 + 32 words) block size: 64 pages (128k + 4k bytes) device size: 2gb: 2,048 blocks; 4gb: 4,096 blocks; 8gb: 8,192 blocks read performance: random read: 25s sequential read: 30ns (3v x8 only) write performance: page program: 300s (typ) block erase: 2ms (typ) endurance: 100,000 program/erase cycles data retention: 10 years first block: block address 00h: guaranteed valid without ecc (up to 1,000 program/erase cycles) vcc: 1.70vC1.95v 2.7vC3.6v automated program and erase basic nand flash command set: page read, read for internal data move, random data read, read id, read status, program page, random data input, program page cache mode, program for internal data move, block erase, reset new commands: page read cache mode one-time programmable (otp), including: otp data program, otp data protect, otp data read read unique id (contact factory) read id2 (contact factory) ready/busy# (r/b#) pin provides a hardware method for detecting program or erase cycle completion wp# signal: hardware write protect operating temperature: commercial (0 c to 70 c) extended (C40 c to +85 c)
intel ? ss72 nand flash memory datasheet 6-sep-2006 2 order number: 311998-006 (x8) or 1,056 words (x16). the pages are further divided into a 2,048-byte data storage region with a separate 64-byte area on the x8 device; and on the x16 device, separate 1,024-word and 32-word areas. the 64-byte and 32-word areas are typically used for error management functions. the contents of each 2,112-byte page can be programmed in 300s, and an entire 132k-byte/66k-word block can be erased in 2ms. on-chip control logic automates program and erase operations to maximize cycle endurance. erase/program endurance is specified at 100k cycles when using appropriate error correcting code (ecc) and error management. leg al li nes and dis clai mers information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear fac ility appli cations. intel may make changes to specifications and product descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . intel and intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2006, intel corporation. all rights reserved.
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 3 intel ? ss72 nand flash memory contents 1.0 functional overview .................................................................................................. 7 1.1 architecture........................................................................................................ 7 1.2 memory map and addressing ................................................................................ 8 1.2.1 memory map and array addressing (x8 device) ............................................ 9 1.2.2 memory map and array addressing (x16 device) ........................................ 11 2.0 signal assignments and descriptions ...................................................................... 13 3.0 package information ............................................................................................... 15 4.0 electrical characteristics ......................................................................................... 16 4.1 maximum ratings and operating conditions.......................................................... 16 4.2 vcc power cycling ............................................................................................. 16 5.0 nand flash bus operations ..................................................................................... 21 5.1 control signals ................................................................................................. 21 5.2 commands ....................................................................................................... 21 5.3 address input ................................................................................................... 21 5.4 data input ....................................................................................................... 22 5.5 reads ............................................................................................................. 22 5.6 ready/busy#.................................................................................................... 22 6.0 command definitions .............................................................................................. 26 6.1 read operations............................................................................................... 26 6.1.1 page read 00h-30h............................................................................... 26 6.1.2 random data read 05h-e0h ................................................................. 27 6.1.3 page read cache mode start 31h; page read cache mode start last 3fh 28 6.1.4 read id 90h ......................................................................................... 29 6.1.5 read status 70h ................................................................................. 30 6.2 program operations ........................................................................................ 31 6.2.1 program page 80h-10h ........................................................................ 31 6.2.2 serial data input 80h ......................................................................... 32 6.2.3 random data input 85h....................................................................... 32 6.2.4 program page cache mode 80h-15h..................................................... 32 6.3 internal data move............................................................................................ 33 6.3.1 read for internal data move 00h-35h ................................................ 34 6.3.2 program for internal data move 85h-10h ........................................... 34 6.4 block erase operation .................................................................................... 35 6.4.1 block erase 60h-d0h........................................................................... 35 6.5 one time programmable (otp) area.................................................................... 36 6.5.1 otp data program a0h-10h.................................................................. 36 6.5.2 otp data protect a5h-10h ................................................................... 38 6.5.3 otp data read afh-30h ........................................................................ 39 6.6 reset operation ............................................................................................... 40 6.6.1 reset ffh ............................................................................................ 40 6.7 write protect operation ................................................................................. 41 7.0 error management ................................................................................................... 43 8.0 timing diagrams ..................................................................................................... 44 9.0 ordering information .............................................................................................. 54
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 4 order number: 311998-006 figures 1 intel ? ss72 nand flash memory functional block diagram ............................................ 8 2 intel ? ss72 nand flash memory memory map (x8)....................................................... 9 3 intel ? ss72 nand flash memory array organization (x8)..............................................10 4 intel ? ss72 nand flash memory memory map (x16) ....................................................11 5 intel ? ss72 nand flash memory array organization (x16) ......................................... ...12 6 48-pin tsop type 1 pin assignment top view ..............................................................13 7 tsop type 1 package ...............................................................................................15 8 ac waveforms during power transitions......................................................................17 9 minimum r p .............................................................................................................23 10 ready/busy# open drain.........................................................................................23 11 t fall and t rise ............................................................................................................24 12 i ol vs. r p ................................................................................................................24 13 page read operation ...............................................................................................27 14 random data read operation .................................................................................27 15 page read cache mode..........................................................................................28 16 read id operation ...................................................................................................29 17 status register operation ....................................................................................... ...31 18 program and read status operation ......................................................................32 19 random data input ...............................................................................................32 20 program page cache mode example.......................................................................33 21 internal data move ..............................................................................................34 22 internal data move with random data input........................................................35 23 block erase operation ...........................................................................................36 24 otp data program (1.8v part) ................................................................................37 25 otp data program (3.3v part) ................................................................................38 26 otp data protect..................................................................................................39 27 otp data read.......................................................................................................40 28 reset operation ......................................................................................................41 29 erase enable ..........................................................................................................41 30 erase disable .........................................................................................................42 31 program enable .....................................................................................................42 32 program disable.....................................................................................................42 33 command latch cycle ............................................................................................44 34 address latch cycle..............................................................................................44 35 input data latch ..................................................................................................45 36 serial access cycle after read...............................................................................45 37 read status cycle..................................................................................................46 38 page read .............................................................................................................46 39 page read operation with ce# dont care..................................................................47 40 random data read ................................................................................................47 41 page read cache mode timing diagram (part 1 of 2).................................................48 42 page read cache mode timing diagram (part 2 of 2).................................................48 43 page read cache mode timing without r/b# (part 1 of 2) ..........................................49 44 page read cache mode timing without r/b# (part 2 of 2) ..........................................49 45 read id operation ...................................................................................................50 46 program page operation.........................................................................................50 47 program page operation with ce# dont care ...........................................................51 48 program page operation with random data input ..................................................51 49 internal data move ..............................................................................................52 50 program page cache mode ...................................................................................52 51 program page cache mode ending on 15h ..............................................................52 52 block erase operation ...........................................................................................53 53 reset operation ......................................................................................................53 54 decoder ..................................................................................................................54
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 5 intel ? ss72 nand flash memory tables 1 intel ? ss72 nand flash memory operational example (x8) ............................................ 9 2 intel ? ss72 nand flash memory array addressing (x8)................................................ 10 3 intel ? ss72 nand flash memory operational example (x16)......................................... 11 4 intel ? ss72 nand flash memory array addressing (x16) .............................................. 12 5 signal descriptions................................................................................................... 13 6 absolute maximum ratings by device: voltage on any pin relative to vss ....................... 16 7 recommended operating conditions........................................................................... 16 8 dc and operating characteristics ............................................................................... 17 9 valid blocks............................................................................................................. 18 10 capacitance ............................................................................................................ 18 11 test conditions........................................................................................................ 18 12 ac characteristics: command, data, and address input................................................ 19 13 ac characteristics: normal operation ......................................................................... 19 14 program/erase characteristics ............................................................................... 20 15 mode selection ........................................................................................................ 25 16 command set ......................................................................................................... 26 17 device id and configuration codes............................................................................. 30 18 status register bit definition ..................................................................................... 31 19 status register contents after reset operation .......................................................... 41 20 intel? nand flash memory ordering information ........................................................ 54
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 6 order number: 311998-006 revision history revision date revision description 29-aug-06 006 ? first production datasheet revision ? removed the pre signal due to low customer demand. ? clarified in figure 6 48-pin tsop type 1 pin assignment top view on page 13 that pin 38 can be either dnu or vss. 18-aug-06 005 ? updated with new product naming convention, and document title change. 29-jun-06 004 ? added x16 page size content throughout document. ? added operating temperature to the product features section, on page 1 . 3-may-06 003 ? updated graphics and ordering information. 31-mar-06 002 ? revised for 4 and 8 gbit parts. 10-mar-06 001 ? initial release.
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 7 intel ? ss72 nand flash memory 1.0 functional overview this section provides an overview of the device in the following sections: ? section 1.1, architecture on page 7 ? section 1.2, memory map and addressing on page 8 this section provides an overview of the device architecture, addressing, and memory map. 1.1 architecture these devices use nand flash electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins. this provides a memory device with a low signal count. the internal memory array is accessed on a page basis. when doing reads, a page of data is copied from the memory array into the data register. once copied to the data register, data is output sequentially, byte by byte on x8 devices, or word by word on x16 devices. the memory array is programmed on a page basis. after the starting address is loaded into the internal address register, data is sequentially written to the internal data register up to the end of a page. after all of the page data has been loaded into the data register, array programming is started. in order to increase programming bandwidth, this device incorporates a cache register. in the cache programming mode, data is first copied into the cache register and then into the data register. once the data is copied into the data register, programming begins. after the data register has been loaded and programming started, the cache register becomes available for loading additional data. loading the next page of data into the cache register takes place while page programming is in process. the internal data move command also uses the internal cache register. normally, moving data from one area of external memory to another uses a large number of external memory cycles. by using the internal cache register and data register, array data can be copied from one page and then programmed into another without using external memory cycles.
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 8 order number: 311998-006 1.2 memory map and addressing nand flash devices do not contain dedicated address signals. addresses are loaded using a five-cycle sequence as shown in table 2, intel ? ss72 nand flash memory array addressing (x8) on page 10 for the x8 device and in table 4, intel ? ss72 nand flash memory array addressing (x16) on page 12 for the x16 device. figure 1. intel ? ss72 nand flash memory functional block diagram address register data register cache register status register command register ce# v cc v ss cle ale we# re# wp# pre (3v i/o only) i /o [7:0] i /o [15:0] control logic i/o control r/b# row decode column decode
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 9 intel ? ss72 nand flash memory 1.2.1 memory map and array addressing (x8 device) the 12-bit column address is capable of addressing from 0 to 4,095 words on x8 devices; however, only words 0 through 2,111 are valid. words 2,112 through 4,095 of each page are out of bounds, do not exist in the device, and cannot be addressed. note: as shown in ta b l e 2 , i n t e l ? ss72 nand flash memory array addressing (x8) on page 10 , the high nibble of address cycle 2 has no assigned address bits; however, these 4 bits must be held low during the address cycle to ensure that the address is interpreted correctly by the nand flash device. these extra bits are accounted for in address cycle 2 even though they do not have address bits assigned to them. figure 2. intel ? ss72 nand flash memory memory map (x8) table 1. intel ? ss72 nand flash memory operational example (x8) block page min address in page max address in page out of bounds addresses in page 0 0 0x0000000000 0x000000083f 0x0000000840C0x0000000fff 0 1 0x0000010000 0x000001083f 0x0000010840C0x0000010fff 0 2 0x0000020000 0x000002083f 0x0000020840C0x0000020fff 2,046 62 0x01fffe0000 0x01fffe083f 0x01fffe0840C0x01fffe0fff 2,047 63 0x01ffff0000 0x01ffff083f 0x01ffff0840C0x01ffff0fff ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b locks b a[16:6] p ages p a[5:0] b ytes c a[11:0] 012 012 63 0 1 2 2,047 ? ? ? 2,11 1 2,047 spare area
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 10 order number: 311998-006 notes: 1. block address concatenated with page address = actual page address. cax = column address; pax = page address, bax = block address. 2. if ca11 = 1 then ca[10:6] must be 0. figure 3. intel ? ss72 nand flash memory array organization (x8) table 2. intel ? ss72 nand flash memory array addressing (x8) cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low ca11 2 ca10 ca9 ca8 third ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low low ba16 c ache register data register 2,048 blocks per device 1 block 64 2,048 64 2,048 2,112 bytes i/o 7 i/o 0 64 pages = 1 block (128k + 4k) bytes 1 page = (2k + 64) bytes 1 block = (2k + 64) bytes x 64 pag es = (128k + 4k) bytes 1 device = (2k + 64) bytes x 64 page s x 2,048 blocks = 2,112mb
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 11 intel ? ss72 nand flash memory 1.2.2 memory map and array addressing (x16 device) the 11-bit column address is capable of addressing from 0 to 2,047 words on x16 devices; however, only words 0 through 1,055 are valid. words 1,056 through 2,048 of each page are out of bounds, do not exist in the device, and cannot be addressed. note: as shown in table 4, intel ? ss72 nand flash memory array addressing (x16) on page 12 , the upper five bits of address cycle 2 have no assigned address bits; however, these 5 bits must be held low during the address cycle to ensure that the address is interpreted correctly by the nand flash device. these extra bits are accounted for in address cycle 2 even though they do not have address bits assigned to them. figure 4. intel ? ss72 nand flash memory memory map (x16) table 3. intel ? ss72 nand flash memory operational example (x16) block page min address in page max address in page out of bounds addresses in page 0 0 0x0000000000 0x000000041f 0x0000000420C0x0000000fff 0 1 0x0000010000 0x000001041f 0x0000010420C0x0000010fff 0 2 0x0000020000 0x000002041f 0x0000020420C0x0000020fff 2,046 62 0x01fffe0000 0x01fffe041f 0x01fffe0420C0x01fffe0fff 2,047 63 0x01ffff0000 0x01ffff041f 0x01ffff0420C0x01ffff0fff ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b locks b a[16:6] p ages p a[5:0] w ords c a[10:0] 012 012 63 0 1 2 1,023 ? ? ? 1,05 5 2,047 spare area
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 12 order number: 311998-006 notes: 1. if ca10 = 1 then ca[9:5] must be 0. 2. block address concatenated with page address = actual page address. cax = column address; pax = page address, bax = block address. 3. i/o[15:8] are not used during the addressing sequence and should be driven low. figure 5. intel ? ss72 nand flash memory array organization (x16) table 4. intel ? ss72 nand flash memory array addressing (x16) cycle i/o[15:8] i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first low ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low low low ca10 1 ca9 ca8 third low ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth low ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low low low ba16 c ache register data register 2,048 blocks per device 1 block 32 1,024 32 1,024 1,056 words i/o 15 i/o 0 64 pages = 1 block (64k + 2k) words 1 page = (1k + 32) words 1 block = (1k + 32) words x 64 pag es = (64k + 2k) words 1 device = (1k + 32) words x 64 page s x 2,048 blocks = 2,112mb
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 13 intel ? ss72 nand flash memory 2.0 signal assignments and descriptions notes: 1. r/b2# and ce2# are only available on 8gb devices. these pins are nc for other configurations. figure 6. 48-pin tsop type 1 pin assignment top view x8 nc nc nc nc nc r/b2# 1 r/b# re# ce# ce2# 1 nc v cc v ss nc nc cle ale we# wp# dnu dnu dnu nc nc x16 nc nc nc nc nc r/b2# 1 r/b# re# ce# ce2# 1 nc v cc v ss nc nc cle ale we# wp# dnu dnu dnu nc nc x16 v ss i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 nc dnu or vss v cc nc nc nc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 v ss x8 nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc dnu or vss v cc v ss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc 1 l 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 table 5. signal descriptions symbol type description ale input address latch enable: during the time ale is high, address information is transferred from i/o[7:0] into the on-chip address register upon a low-to- high transition on we# . when address information is not being loaded, the ale pin should be driven low. ce#, ce2# input chip enable: this gates transfers between the host system and the nand flash device. once the device starts a program or erase operation, the chip enable pin can be de-asserted. for the 8gb configuration, ce# controls the first 4gb of memory; ce2# controls the second 4gb. see section 5.0, nand flash bus operations on page 21 for additional operational details. in the 8gb configuration, r/b# is for the 4gb of memory enabled by ce#; r/b2# is for the 4gb of memory enabled by the ce2#. cle input command latch enable: when cle is high, information is transferred from i/o[7:0] to the on-chip command register on the rising edge of we#. when command information is not being loaded, cle should be driven low. re# input read enable: this gates transfers from the nand flash device to the host system. we# input write enable: this gates transfers from the host system to the nand flash device. wp# input write protect: pin protects against inadvertent program and erase operations. all program and erase operations are disabled when the wp# pin is low.
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 14 order number: 311998-006 i/o[7:0] (8-bit bus width) i/o[15:0] (16-bit bus width) i/o data inputs/outputs: the bidirectional i/o pins transfer address, data, and instruction information. data is output only during read operations; at other times the i/o pins are inputs. r/b#, r/b2# output ready/busy: an open-drain, active-low output that uses an external pull- up resistor, the pin is used to indicate when the chip is processing a program or erase operation. the pin is also used during a read operation to indicate when data is being transferred from the array into the serial data register. when these operations have completed, the r/b# returns to the high-z state. v cc supply v cc : power supply. v ss supply v ss : ground connection. nc C no connect: nc pins are not internally connected. these pins can be driven or left unconnected. dnu C do not use: these pins must be left unconnected. table 5. signal descriptions symbol type description
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 15 intel ? ss72 nand flash memory 3.0 package information note: all dimensions in millimeters, min/max, or typical, as noted. figure 7. tsop type 1 package 1.20 max 0.15 +0.03 -0.02 0.20 0.05 see detail a 0.50 typ 18.40 0.08 20.00 0.25 12.00 0.08 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 p in #1 index plated lead finish: 90% sn, 10% pb or 100%s n plastic package material: novolac epoxy package width and length do not include mold protrusion. allowable protrusion is 0.25 per side.
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 16 order number: 311998-006 4.0 electrical characteristics 4.1 maximum ratings and operating conditions stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods may affect reliability. 4.2 v cc power cycling intel ? nand flash devices are designed to prevent data corruption during power transitions. v cc is internally monitored. when v cc goes below approximately 1.1v (1.8v device), or 2.0v (3v device), program and erase functions are disabled. wp# provides additional hardware protection. wp# should be kept at v il during power cycling. when v cc reaches 1.5v (1.8v device) or 2.5v (3v device), a minimum of 10s should be allowed for the flash to initialize before executing any commands. table 6. absolute maximum ratings by device: voltage on any pin relative to vss parameter/condition symbol min max unit voltage input JS29F02G08AANB3 vin C0.6 +4.6 v js29f04g08banb3 js29f08g08fanb3 voltage input (1.8v version) vin -0.6 +2.4 v v cc supply voltage JS29F02G08AANB3 v cc C0.6 +4.6 v js29f04g08banb3 js29f08g08fanb3 v cc supply voltage (1.8v version) vin -0.6 +2.4 v storage temperature t stg C65 +150 c short circuit output current, i/os 5 ma table 7. recommended operating conditions parameter/condition symbol min typ max unit operating temperature commercial t a 0+70 o c extended C40 +85 o c v cc supply voltage JS29F02G08AANB3 v cc 2.7 3.3 3.6 v js29f04g08banb3 js29f08g08fanb3 v cc supply voltage (1.8v version) vcc 1.70 1.8 1.95 v ground supply voltage vss 0 0 0 v
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 17 intel ? ss72 nand flash memory figure 8. ac waveforms during power transitions w e# r /b# w p# vcc 10s high 3v device: 2.5v 1.8v device: 1.5v 3v device: 2.5v 1.8v device: 1.5 v undefine d don?t care table 8. dc and operating characteristics parameter conditions symbol min typ max unit sequential read current t rc = 30ns, ce# = v il , i out = 0ma icc1 C 15 30 ma program current C i cc 2 C 15 30 ma erase current C i cc 3 C 15 30 ma standby current (ttl) ce# = v ih , wp# = 0v/v cc i sb 1 CC1ma standby current (cmos) JS29F02G08AANB3 ce# = v cc C 0.2v, wp# = 0v/v cc i sb 2 C 1050a js29f04g08banb3 C 20 100 a js29f08g08fanb3 C 40 200 a input leakage current JS29F02G08AANB3 v in = 0v to v cc i li CC10a js29f04g08banb3 C C 20 a js29f08g08fanb3 C C 40 a output leakage current JS29F02G08AANB3 v out = 0v to v cc i lo CC10a js29f04g08banb3 C C 20 a js29f08g08fanb3 C C 40 a input high voltage i/o[7:0], i/o[15:0] ce#, cle, ale, we#, re#, wp#, r/b# v ih 0.8 x v cc C v cc + 0.3 v input low voltage (all inputs) Cv il C0.3 C 0.2 x v cc v output high voltage i oh = C400a v oh 2.4CCv output low voltage i ol = 2.1ma v ol CC0.4v output low current (r/b#) v ol = 0.4v i ol (r/b#) 8 10 C ma
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 18 order number: 311998-006 notes: 1. invalid blocks are blocks that contain one or more bad bits. the device may contain bad blocks upon shipment. additional bad blocks may develop over time; however, the total number of available blocks will not drop below n vb during the endurance life of the device. do not erase or program blocks marked invalid by the factory. 2. block 00h (the first block) is guaranteed to be valid and does not require error correction up to 1k program/erase cycles. 3. the number of invalid blocks in each 4gb section will not exceed 80. notes: 1. these parameters are verified in device characterization and are not 100 percent tested. 2. test conditions: t c = 25c; f = 1 mhz; v in = 0v. notes: 1. verified in device characterization; not 100 percent tested. table 9. valid blocks parameter symbol device min max unit notes valid block number n vb JS29F02G08AANB3 2,008 2,048 blocks 1, 2 js29f04g08banb3 4,016 4,096 js29f08g08fanb3 8,032 8,192 3 table 10. capacitance description symbol device max unit notes input capacitance c in JS29F02G08AANB3 10 pf 1, 2 js29f04g08banb3 20 js29f08g08fanb3 40 input/output capacitance (i/o) c io JS29F02G08AANB3 10 pf 1, 2 js29f04g08banb3 20 js29f08g08fanb3 40 table 11. test conditions parameter value notes input pulse level JS29F02G08AANB3 0.0v to v cc (2.7vC3.6v) js29f04g08banb3 js29f08g08fanb3 input pulse level (1.8v version) 0.0v to v cc (1.70vC1.95v) input rise and fall times 5ns input and output timing levels v cc /2 output load v cc = 3.0v 10% 1 ttl gate and cl = 50pf 1 v cc = 3.3v 10% 1 ttl gate and cl = 100pf 1 output load vcc = 1.70vC1.95v 1 ttl gate and cl = 30pf 1
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 19 intel ? ss72 nand flash memory notes: 1. timing for t adl begins in the address cycle, on the final rising edge of we#, and ends with the first rising edge of we# for data input. 2. for page read cache mode and program page cache mode operations, the 3v x16 ac characteristics apply for 3v x8 devices. table 12. ac characteristics: command, data, and address input parameter symbol 3v x16 3v x8 unit notes min max min max ale to data start t adl 100 100 ns 1 ale hold time t alh 10 5 ns 2 ale setup time t als 25 10 ns 2 ce# hold time t ch 10 5 ns 2 cle hold time t clh 10 5 ns 2 cle setup time t cls 25 10 ns 2 ce# setup time t cs 35 15 ns 2 data hold time t dh 10 5 ns 2 data setup time t ds 20 10 ns 2 write cycle time t wc 45 30 ns 2 we# pulse width high t wh 15 10 ns 2 we# pulse width t wp 25 15 ns 2 wp# setup time t ww 30 30 ns table 13. ac characteristics: normal operation (sheet 1 of 2) parameter symbol 3v x16 3v x8 unit notes min max min max ale to re# delay t ar 10 C 10 ns ce# access time t cea C 45 C 23 ns 1 ce# high to output high-z t chz C 20 C 20 ns 2 cle to re# delay t clr 10 C 10 C ns cache busy in page read cache mode (first 31h) t dcbsyr1 C 3 C 3 s cache busy in page read cache mode (next 31h and 3fh) t dcbsyr2 t dcbsyr1 25 t dcbsyr1 25 s output high-z to re# low t ir 0 C 0 C ns 1 data output hold time t oh 15 C 15 C ns data transfer from nand flash array to data register t rC25C25s read cycle time t rc 50 C 30 C ns 1 re# access time t rea C 30 C 18 ns 1 re# high hold time t reh 15 C 10 C ns 1 re# high to output high-z t rhz C 30 C 30 ns 2 re# pulse width t rp 25 C 15 C ns 1 ready to re# low t rr 20 C 20 C ns
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 20 order number: 311998-006 notes: 1. for page read cache mode and program page cache mode operations, the 3v x16 ac characteristics apply for 3v x8 devices. 2. transition is measured 200mv from steady-state voltage with load. this parameter is sampled and not 100 percent tested. 3. if reset (ffh) command is loaded at ready state, the device goes busy for maximum 5s. 4. do not issue a new command during t wb, even if r/b# is ready. notes: 1. eight total to the same page. 2. t cbsy max time depends on timing between internal program completion and data in. 3. t lprog = t prog (last page) + t prog (last C 1 page) C command load time (last page) C address load time (last page) C data load time (last page). reset time (read/ program/erase) t rst C 5/10/ 500 C 5/10/ 500 s 3 we# high to busy t wb C 100 C 100 ns 3, 4 we# high to re# low t whr 60 C 60 C ns table 13. ac characteristics: normal operation (sheet 2 of 2) parameter symbol 3v x16 3v x8 unit notes min max min max table 14. program/erase characteristics parameter description typ max unit notes nop number of partial page programs 8 cycles 1 t bers block erase time 2 3 ms t cbsy busy time for cache program 3 700 s 2 t lprog last page program time 3 t prog page program time 300 700 s
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 21 intel ? ss72 nand flash memory 5.0 nand flash bus operations the bus on the 8-bit bus width intel ? ss72 nand flash memory device is multiplexed. data i/o, addresses, and commands all share the same pins. i/o pins i/o[15:8] are used only for data in the x16 configuration. addresses and commands are always supplied on i/o[7:0]. the command sequence normally consists of a command latch cycle, an address latch cycle, and a data cycleeither read or write. 5.1 control signals ce#, we#, re#, cle, ale and wp# control nand flash device read and write operations. on the 8gb js29f08g08fanb3, ce# and ce2# each control independent 4gb arrays. ce2# functions the same as ce# for its own array; all operation described for ce# also apply to ce2#. ce# is used to enable the device. when ce# is low and the device is not in the busy state, the nand flash memory will accept command, data, and address information. when the device is not performing an operation, the ce# pin is typically driven high and the device enters standby mode. the memory will enter standby if ce# goes high while data is being transferred and the device is not busy. this helps reduce power consumption. see figure 39, page read operation with ce# dont care on page 47 and figure 47, program page operation with ce# dont care on page 51 for examples of ce# dont care operations. the ce# dont care operation enables the nand flash to reside on the same asynchronous memory bus as other flash or sram devices. other devices on the memory bus can then be accessed while the nand flash is busy with internal operations. this capability is important for designs that require multiple nand devices on the same bus. one device can be programmed while another is being read. a high cle signal indicates that a command cycle is taking place. a high ale signal signifies that an address input cycle is occurring. 5.2 commands commands are written to the command register on the rising edge of we# when: ? ce# and ale are low, and ? cle is high, and ? the device is not busy. the exceptions to this are the read status and reset commands when busy. see figure 34, address latch cycle on page 44 for detailed timing requirements. commands are input on i/o[7:0] only. for devices with a x16 interface, i/o[15:8] must be written with zeros when issuing a command. 5.3 address input addresses are written to the address register on the rising edge of we# when: ? ce# and cle are low, and ? ale is high, and ? the device is not busy.
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 22 order number: 311998-006 addresses are input on i/o[7:0] only; bits not part of the address space must be low. for devices with a x16 interface, i/o[15:8] must be written with zeros when issuing an address. the number of address cycles required for each command varies. refer to the command descriptions to determine addressing requirements ( table 16, command set on page 26 ). 5.4 data input data is written to the data register on the rising edge of we# when: ? ce#, cle, and ale are low, and ? the device is not busy. data is input on i/o[7:0] for x8 devices, and i/o[15:0] on x16 devices. see figure 35, input data latch on page 45 for additional data input details. 5.5 reads after a read command is issued, data is transferred from the memory array to the data register from the rising edge of we#. r/b# goes low for t r and transitions high after the transfer is complete. when r/b# goes high, data is available in the data register, and is clocked out of the part by toggling re#. see figure 38, page read on page 46 for detailed timing information. the read status (70h) command or the r/b# signal can be used to determine when the device is ready. see section 6.1.5, read status 70h on page 30 for details. 5.6 ready/busy# the r/b# output provides a hardware method of indicating the completion of program, erase, and read operations. the signal requires a pull-up resistor for proper operation. the signal is typically high, and transitions to low after the appropriate command is written to the device. the signal pins open-drain driver enables multiple r/b# outputs to be or-tied. the read status command can be used in place of r/b#. typically r/b# is connected to an interrupt pin on the system controller (see figure 10, ready/busy# open drain on page 23 ). on the 8gb js29f08g08fanb3, r/b# provides a status indication for the 4gb section enabled by ce#, and r/b2# does the same for the 4gb section enabled by ce2#. r/b# and r/b2# can be tied together, or they can be used separately to provide independent indications for each 4gb section. the combination of r p and capacitive loading of the r/b# circuit determines the rise time of the r/b# pin. the actual value used for r p depends on the system timing requirements. large values of r p cause r/b# to be delayed significantly. at the 10 to 90 percent points on the r/b# waveform, rise time is approximately two time constants (tc). tc = r * c where r = r p (resistance of pull-up resistor), and c = total capacitive load the fall time of the r/b# signal is determined mainly by the output impedance of the r/b# pin and the total load capacitance.
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 23 intel ? ss72 nand flash memory refer to figure 11, t fall and t rise on page 24 , and figure 12, i ol vs. r p on page 24 , which depict approximate r p values using a circuit load of 100pf. the minimum value for r p is determined by the output drive capability of the r/b# signal, the output voltage swing, and v cc . figure 9. minimum r p where i l is the sum of the input currents of all devices tied to the r/b# pin. r p (min, 1.8v part) = v cc (max) ? v ol (max) i ol + i l = 1.85v 3ma + i l r p (min, 3.3v part) = v cc (max) ? v ol (max) i ol + i l = 3.2v 8ma + i l figure 10. ready/busy# open drain rp r/b# open drain outp ut v cc gnd device i ol
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 24 order number: 311998-006 notes: 1. t fall and t rise calculated at 10 percentC90 percent points. 2. t rise dependent on external capacitance, and resistive loading and output-transistor impedance. 3. t rise primarily dependent on external pull-up resistor and external capacitive loading. 4. t fall 10ns at 3.3v; t fall 7ns at 1.8v. 5. see tc values in figure 12, i ol vs. r p on page 24 for approximate r p value and tc. figure 11. t fall and t rise 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 6 t fall t rise vcc 3.3 vcc 1.8 tc v figure 12. i ol vs. r p 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2,000 4,000 6,000 8,000 10,000 12,000 rp ( ) t (s) i ol at 3.60v (ma) i ol at 1.95v (ma)
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 25 intel ? ss72 nand flash memory notes: 1. wp# should be biased to cmos high or low for standby. 2. mode selection settings for this table: h = logic level high; l = logic level low; x = v ih or v il . table 15. mode selection cle ale ce# we# re# wp# 1 mode hl l hx read mode command input l h l h x address input hl l hh write mode command input l h l h h address input lll hh data input l l l h x sequential read and data output l l l h h x during read (busy) xxxxxh during program (busy) xxxxxh during erase (busy) xxxxxl write protect x x h x x 0v/vcc standby
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 26 order number: 311998-006 6.0 command definitions notes: 1. indicates required data cycles between command cycle 1 and command cycle 2. 2. do not cross die boundaries when using read for internal data move and program for internal data move. 3. random data read command limited to use within a single page. 4. random data input command limited to use within a single page. 6.1 read operations 6.1.1 page read 00h-30h on initial power up, the device defaults to read mode. to enter the read mode while in operation, write the 00h command to the command register, then write five address cycles followed by the 30h command. to determine the progress of the data transfer from the nand flash array to the data register ( t r), monitor the r/b# signal; or alternately, issue a read status (70h) command. if the read status command is used to monitor the data transfer, the user must re-issue the read (00h) command to receive data output from the data register. see figure 43, page read cache mode timing without r/b# (part 1 of 2) on page 49 and figure 44, page read cache mode timing without r/b# (part 2 of 2) on page 49 for examples. after the read command has been re-issued, pulsing the re# line will result in outputting data, starting from the initial column address. table 16. command set operation command cycle 1 number of address cycles data cycles required 1 command cycle 2 valid during busy notes page read 00h 5 no 30h no page read cache mode start 31h no no page read cache mode start last 3fh no no read for internal data move 00h 5 no 35h no 2 random data read 05h 2 no e0h no 3 read id 90h 1 no no read status 70h no yes program page 80h 5 yes 10h no program page cache mode 80h 5 yes 15h no program for internal data move 85h 5 optional 10h no 2 r and om d ata inp ut 8 5h 2 ye s no 4 block erase 60h 3 no d0h no reset ffh no yes otp data program a0h 5 yes 10h no otp data protect a5h 5 no 10h no otp data read afh 5 no 30h no
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 27 intel ? ss72 nand flash memory a serial page read sequence outputs a complete page of data. after 30h is written, the page data is transferred to the data register, and r/b# goes low during the transfer. when the transfer to the data register is complete, r/b# returns high. at this point, data can be read from the device. starting from the initial column address to the end of the page, read the data by repeatedly pulsing re# at the maximum t rc rate. 6.1.2 random data read 05h-e0h the random data read command enables the user to specify a new column address so the data at single or multiple addresses can be read. the random read mode is enabled after a normal page read (00h-30h) sequence. random data can be output after the initial page read by writing an 05h-e0h command sequence along with the new column address (two cycles). the random data read command can be issued without limit within the page. only data on the current page can be read. pulsing the re# pin outputs data sequentially. figure 13. page read operation d out n d out n + 1 d out m w e# ce# ale cle re# r /b# i/ox t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz don?t care col add 1 col add 2 row add 1 row add 2 row add 3 figure 14. random data read operation re# i/ox 00h address (5 cycles) data output data output 30h 05h address (2 cycles) e0h r /b# t r
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 28 order number: 311998-006 6.1.3 page read cache mode start 31h; page read cache mode start last 3fh intel ? nand flash devices have a cache register that can be used to increase the read operation speed when accessing sequential pages in a block. first, a normal page read (00h-30h) command sequence is issued. the r/b# signal goes low for t r during the time it takes to transfer the first page of data from the memory to the data register. after r/b# returns to high, the page read cache mode start (31h) command is latched into the command register. r/b# goes low for t dcbsyr1 while data is being transferred from the data register to the cache register. once the data register contents are transferred to the cache register, another page read is automatically started as part of the 31h command. data is transferred from the next sequential page of the memory array to the data register during the same time data is being read serially (pulsing of re#) from the cache register. if the total time to output data exceeds t r, then the page read is hidden. the second and subsequent pages of data are transferred to the cache register by issuing additional 31h commands. r/b# will stay low up to t dcbsyr2. this time can vary, depending on whether the previous memory-to-data-register transfer was completed prior to issuing the next 31h command. see table 13, ac characteristics: normal operation on page 19 for timing parameters. if the data transfer from memory to the data register is not completed before the 31h command is issued, r/b# stays low until the transfer is complete. it is not necessary to output a whole page of data before issuing another 31h command. r/b# will stay low until the previous page read is complete and the data has been transferred to the cache register. to read out the last page of data, the page read cache mode start last (3fh) command is issued. this command transfers data from the data register to the cache register without issuing another page read . figure 15. page read cache mode re# ce# ale cle i/ox 00h address (5 cycles) 31h 30h 31h 3fh r /b# w e# t r t dcbsyr1 t dcbsyr2 t dcbsyr2 don?t care data output (serial access) data output (serial access) data output (serial access)
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 29 intel ? ss72 nand flash memory 6.1.4 read id 90h the read id command is used to read the 4 bytes of identifier codes programmed into the devices. the read id command reads a 4-byte table that includes manufacturer id, device configuration, and part-specific information (see table 17, device id and configuration codes on page 30 ). writing 90h to the command register puts the device into the read id mode. the command register stays in this mode until another valid command is issued (see figure 16, read id operation on page 29 ). note: see table 17, device id and configuration codes on page 30 for byte definitions. figure 16. read id operation w e# ce# ale cle re# i/ox address, 1 cycle 90h 00h byte 2 byte 0 byte 1 byte 3 t ar t rea t whr
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 30 order number: 311998-006 notes: 1. b = binary, h = hex. 2. device ids for these configurations are provided for reference only. 3. the js29f08g08fanb3 device id code reflects the configuration of each 4gb section. 6.1.5 read status 70h these nand flash devices have an 8-bit status register that the software can read during device operation. on the x16 device, i/o[15:8] are 0 when reading the status register. table 18 describes the status register. after a read status command, all read cycles will be from the status register until a new command is issued. changes in the status register will be seen on i/o[7:0] as long as ce# and re# are low; it is not necessary to start a new read status cycle to see these changes. while monitoring the read status to determine when the t r (transfer from nand flash array to data register) is complete, the user must re-issue the read (00h) command to make the change from status mode to data mode. after the read command has been re-issued, pulsing the re# line will result in outputting data, starting from the initial column address. table 17. device id and configuration codes options i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 value 1 notes byte 0 manufacturer id intel ? 00101100 2ch byte 1 device id JS29F02G08AANB3 2gb, x8, 3v 1 1 0 1 1 0 1 0 dah js29f04g08banb3 4gb, x8, 3v 11011100 dch js29f08g08fanb3 8gb, x8, 3v 11011100 dch 3 byte 2 byte value dont care xxxxxxxx xxh byte 3 page size 2kb 0 101b spare area size (bytes) 64 0 101b block size (w/o spare) 128kb 0 1 01b organization x8 00b reserved 00b byte value x8 00010101 15h
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 31 intel ? ss72 nand flash memory notes: 1. status register bit 5 is 0 during the actual programming operation. if cache mode is used, this bit will be 1 when all internal operations are complete. 2. status register bit 6 is 1 when the cache is ready to accept new data. r/b# follows bit 6. see figure 15, page read cache mode on page 28 , and figure 20, program page cache mode example on page 33 . 6.2 program operations 6.2.1 program page 80h-10h intel ? nand flash devices are inherently page-programmed devices. pages must be programmed consecutively within a block from the least significant page address to the most significant page address (for instance, 0, 1, 2, ..., 63). random page address programming is prohibited. table 18. status register bit definition sr bit page program program page cache mode page read page read cache mode block erase definition 0 pass/fail pass/fail (n) pass/fail 0 = successful program/erase 1 = error in program/ erase 1 pass/fail (n- 1) 0 = successful program/erase 1 = error in program/ erase 20 30 40 5 ready/ busy ready/busy 1 ready/busy ready/busy 1 ready/busy 0 = busy 1 = ready 6 ready/ busy ready/busy cache 2 ready/busy ready/busy cache 2 ready/busy 0 = busy 1 = ready 7 wr ite protect write protect write protect write protect write protect 0 = protected 1 = not protected [15:8 ] 0 figure 17. status register operation 70h ce# cle w e# re# i/ox status output t rea t clr
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 32 order number: 311998-006 intel ? nand flash devices also support partial-page programming operations. this means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned such that a maximum of eight programming operations are allowed before an erase is required. 6.2.2 serial data input 80h program page operations require loading the serial data input (80h) command into the command register, followed by five address cycles, then the data. serial data is loaded on consecutive we# cycles starting at the given address. the program (10h) command is written after the data input is complete. the control logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operation. write verification only detects 1s that are not successfully written to 0s. r/b# goes low for the duration of array programming time, t prog. the read status (70h) command and the reset (ffh) command are the only commands valid during the programming operation. bit 6 of the status register will reflect the state of r/b#. when the device reaches ready, read bit 0 of the status register to determine if the program operation passed or failed (see figure 18, program and read status operation on page 32 ). the command register stays in read status register mode until another valid command is written to it. 6.2.3 random data input 85h after the initial data set is input, additional data can be written to a new column address with the random data input (85h) command. the random data input command can be used any number of times in the same page prior to issuing the page write (10h) command. see figure 19, random data input on page 32 for the proper command sequence. 6.2.4 program page cache mode 80h-15h cache programming is actually a buffered programming mode of the standard program page command. programming is started by loading the serial data input (80h) command to the command register, followed by five cycles of address, and a full or partial page of data. the data is initially copied into the cache register, and the cache write (15h) command is then latched to the command register. data is figure 18. program and read status operation i/ox 80h address (5 cycles) 10h 70h r /b# t prog status i/o 0 = 0 program successful i/o 0 = 1 program error d in figure 19. random data input i/ox 80h address (5 cycles) 85h address (2 cycles) 10h 70h r /b# t prog d in d in status
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 33 intel ? ss72 nand flash memory transferred from the cache register to the data register on the rising edge of we#. r/b# goes low during this transfer time. after the data has been copied into the data register and r/b# returns to high, memory array programming begins. when r/b# returns to high, new data can be written to the cache register by issuing another cache program command sequence. the time that r/b# stays low will be controlled by the actual programming time. the first time through equals the time it takes to transfer the cache register contents to the data register. on the second and subsequent programming passes, transfer from the cache register to the data register is held off until current data register content has been programmed into the array. bit 6 (cache r/b#) of the status register can be read by issuing the read status (70h) command to determine when the cache register is ready to accept new data. the r/b# pin always follows bit 6. bit 5 (r/b#) of the status register can be polled to determine when the actual programming of the array is complete for the current programming cycle. if just the r/b# pin is used to determine programming completion, the last page of the program sequence must use the program page (10h) command instead of the cache program (15h) command. if the cache program (15h) command is used every time, including the last page of the programming sequence, status register bit 5 must be used to determine when programming is complete. bit 0 of the status register returns the pass/fail for the previous page when bit 6 of the status register is a 1 (ready state). the pass/fail status of the current program operation is returned with bit 0 of the status register when bit 5 of the status register is a 1 (ready state). notes: 1. see note 3, table 14, program/erase characteristics on page 20 . 2. check i/o[6:5] for internal ready/busy. check i/o[1:0] for pass fail. re# can stay low or pulse multiple times after a 70h command. 6.3 internal data move an internal data move requires two command sequences. issue a read for internal data move (00h-35h) command first, then the program for internal data move (85h-10h) command. data moves are only supported within the die from which data is read. figure 20. program page cache mode example t cbsy address/ data input 80h 15h address/ data input 80h 15h address/ data input 80h 15h address/ data input 80h 10h t lprog 1 address/ data input 80h 15h address/ data input 80h 10h status output 2 70h t lprog 1 status output 2 70h a: without status reads b: with status reads t cbsy t cbsy t cbsy r /b# i /ox r /b# i /ox
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 34 order number: 311998-006 6.3.1 read for internal data move 00h-35h the read for internal data move (00h-35h)command is used in conjunction with the program for internal data move (85h-10h) command. first (00h) is written to the command register, then the internal source address is written (five cycles). after the address is input, the read for internal data move (35h) command writes to the command register. this transfers a page from memory into the cache register. the written column addresses are ignored even though all five address cycles are required. the memory device is now ready to accept the program for internal data move command. please refer to the description of this command in the following section. 6.3.2 program for internal data move 85h-10h after the read for internal data move (00h-35h) command has been issued and r/b# goes high, the program for internal data move (85h-10h) command can be written to the command register. this command transfers the data from the cache register to the data register and programming of the new destination page begins. the sequence: 85h, destination address (five cycles), then 10h, is written to the device. after 10h is written, r/b# goes low while the control logic automatically programs the new page. the read status command can be used instead of the r/b# line to determine when the write is complete. when status register bit 6 = 1, bit 0 indicates if the operation was successful. the random data input (85h) command can be used during the program for internal data move command sequence to modify a word or multiple words of the original data. first, data is copied into the cache register using the 00h-35h command sequence, then the random data input (85h) command is written along with the address of the data to be modified next. new data is input on the external data pins. this copies the new data into the cache register. when 10h is written to the command register, the original data plus the modified data is transferred to the data register, and programming of the new page is started. the random data input command can be issued as many times as necessary before starting the programming sequence with 10h. because internal data move operations do not use external memory, ecc cannot be used to check for errors before programming the data to a new page. this can lead to a data error if the source page contains a bit error due to charge loss or charge gain. in the case that multiple internal data move operations are performed, these bit errors may accumulate without correction. for this reason, it is highly recommended that systems using internal data move operations also use a robust ecc scheme that can correct two or more bits per sector. figure 21. internal data move i/ox 00h address (5 cycles) 35h 85h address (5 cycles) 10h 70h r /b# t prog t r status
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 35 intel ? ss72 nand flash memory 6.4 block erase operation 6.4.1 block erase 60h-d0h erasing occurs at the block level. for example, the JS29F02G08AANB3 device has 2,048 erase blocks organized into 64 pages per block, 2,112 bytes per page (2,048 + 64 bytes). each block is 132k bytes (128k + 4k bytes). the block erase command operates on one block at a time. three cycles of addresses ba[17:6] and pa[5:0] are required. although page addresses pa[5:0] are loaded, they are dont care and are ignored for block erase operations. see table 2, intel ? ss72 nand flash memory array addressing (x8) on page 10 for addressing details. the actual command sequence is a two-step process. the erase setup (60h) command is first written to the command register. then three cycles of addresses are written to the device. next, the erase confirm (d0h) command is written to the command register. at the rising edge of we#, r/b# goes low and the control logic automatically controls the timing and erase-verify operations. r/b# stays low for the entire t bers erase time. the read status (70h) command can be used to check the status of the block erase operation. when bit 6 = 1 the erase operation is complete. bit 0 indicates a pass/fail condition where 0 = pass (see figure 17, status register operation on page 31 , and table 18, status register bit definition on page 31 ). figure 22. internal data move with random data input i/ox 00h address (5 cycles) 35h 85h address (5 cycles) data data 85h address (2 cycles) unlimited number of repetitions 10h 70h status r /b# t prog t r
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 36 order number: 311998-006 6.5 one time programmable (otp) area this intel ? nand flash device offers a protected, one-time programmable nand flash memory area. ten full pages (2,112 bytes or 1,056 words per page) of otp data is available on the device, and the entire range is guaranteed to be good from the factory. the otp area is accessible only through the otp commands. customers can use the otp area any way they desire; typical uses include programming serial numbers or other data for permanent storage. in intel ? nand flash devices, the otp area leaves the factory in a non-written state (all bits are 1s). programming or partial-page programming enables the user to program only 0 bits in the otp area. the otp area cannot be erased, even if it is not protected. protecting the otp area simply prevents further programming of the otp area. while the otp area is referred to as one-time programmable, intel provides a unique way to program and verify databefore permanently protecting it and preventing future changes. otp programming and protection are accomplished in two discrete operations. first, using the otp data program (a0h-10h) command, an otp page is programmed entirely in one operation, or in up to four partial-page programming sequences. second, the otp area is permanently protected from further programming using the otp data protect (a5h-10h) command. the pages within the otp area can always be read using the otp data read (afh-30h) command, whether or not it is protected. 6.5.1 otp data program a0h-10h the otp data program (a0h-10h) command is used to write data to the pages within the otp area. an entire page can be programmed at one time, or the page can be partially programmed up to four times. there is no erase operation for the otp pages. figure 23. block erase operation re# ce# ale cle i/ox 60h address input (3 cycles) status d0h 70h r /b# w e# t bers don?t car e i/o 0 = 0 erase successful i/o 0 = 1 erase error
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 37 intel ? ss72 nand flash memory the otp data program enables programming into an offset of an otp page, using the two bytes of column address (ca[11:0]). the command is not compatible with the random data input (85h) command. the otp data program command will not execute if the otp area has been protected. to use the otp data program command, issue the a0h command. then issue five address cycles: the first two address cycles are the column address. for a vcc=1.7v-1.95v part the otp page # is repeated in the third and fourth address cycles, and the fifth address cycle is 00h. for a vcc=2.7v-3.6v part the third cycle is the otp page #, and the fourth and fifth address cycles are 00h-00h. see figure 24 on page 37 and figure 25 on page 38 for details. next, write the data: from 1 to 2,112 bytes (x8 device), or from 1 to 1,056 words (x16 device). after data input is complete, issue the 10h command. the internal control logic automatically executes the proper programming algorithm and controls the necessary timing for programming and verification. program verification only detects 1s that are not successfully written to 0s. r/b# goes low during the duration of the array programming time (tprog). the read status (70h) command is the only command valid during the otp data program operation. bit 5 of the status register will reflect the state of r/b#. if bit 7 is 0, the otp area has been protected; otherwise, it is not protected. when the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see table 18, status register bit definition on page 31 ). it is possible to program the otp page a maximum of four times. note: the otp page must be within the 02hC0bh range. figure 24. otp data program (1.8v part) w e# ce# ale cle re# r /b# i/ox don?t care otp data written (following "good" status confirmatio n) t wc t wb t prog otp dat a input command progr am command read sta tus command 1 up to m b ytes serial input x8 devic e: m = 2,112 byt es x16 devic e: m = 1,056 wor ds a0h col add 1 col add 2 otp page 1 d in n d in m 00h 10h 70h statu s otp page 1
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 38 order number: 311998-006 note: the otp page must be within the 02hC0bh range. 6.5.2 otp data protect a5h-10h the otp data protect (a5h-10h) command is used to protect the data in the otp area. after the data is protected it cannot be programmed further. when the otp area is protected, the pages within the area are no longer programmable and cannot be unprotected. to use the otp data protect command, issue the a5h command. next, issue the following five address cycles: 00h-00h-01h-00h-00h. finally, issue the 10h command. r/b# goes low while the otp area is being protected. the protect command duration is similar to a normal page programming operation, t prog. the read status (70h) command is the only command valid during the otp data protect operation. bit 5 of the status register will reflect the state of r/b#. when the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see table 18, status register bit definition on page 31 ). figure 25. otp data program (3.3v part) w e# ce# ale cle re# r /b# i/ox don?t care otp data written (following "good" status confirmatio n) t wc t wb t prog otp data input command program command read status command 1 up to m bytes serial input x8 device: m = 2,112 bytes x16 device: m = 1,056 words a0h col add 1 col add 2 otp page 1 d in n d in m 00h 00h 10h 70h status
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 39 intel ? ss72 nand flash memory note: otp data is protected following good status confirmation. 6.5.3 otp data read afh-30h the otp data read (afh-30h) command is used to read data from a page within the otp area. an otp page within the otp area is available for reading data whether or not the area is protected. to use the otp data read command, issue the afh command. then issue five address cycles: the first two address cycles are the column address, and for the remaining three cycles select a page in the range of 02h-00h-00h through 0bh-00h- 00h. finally, issue the 30h command. r/b# goes low ( t r) while the data is moved from the otp page to the data register. the read status (70h) command and the reset (ffh) command are the only commands valid during the otp data read operation. bit 5 of the status register will reflect the state of r/b#. for details, refer to table 18, status register bit definition on page 31 . normal read operation timings apply to otp read accesses. additional pages within the otp area can be selected by repeating the otp data read command. figure 26. otp data protect w e# ce# ale cle re# r /b# i/ox don?t car e t wc t wb t prog otp data protect command otp data protected 1 program command read status command a5h col 00h col 00h 10h 70h status 01h 00h 00h
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 40 order number: 311998-006 note: the otp page must be within the 02hC0bh range. 6.6 reset operation 6.6.1 reset ffh the reset command is used to put the memory device into a known condition and to abort a command sequence in progress. read, program, and erase commands can be aborted while the device is in the busy state. the contents of the memory location being programmed or the block being erased are no longer valid. the data may be partially erased or programmed, and is invalid. the command register is cleared and is ready for the next command. the data register and cache register contents are marked invalid. the status register contains the value e0h when wp# is high; otherwise it is written with a 60h value. r/b# goes low for t rst after the reset command is written to the command register. figure 27. otp data read w e# ce# ale cle re# r /b# i/ox busy d out n afh 00h 00h 30h don?t ca re otp page 1 col add 2 col add 1 d out n + 1 d out m t r
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 41 intel ? ss72 nand flash memory 6.7 write protect operation it is possible to enable and disable program and erase commands using the wp# pin. the following figures illustrate the setup time ( t ww) required from wp# toggling until a program or erase command is latched into the command register. after command cycle 1 is latched, the wp# pin must not be toggled until the command is complete and the device is ready (status register bit 5 is 1). figure 28. reset operation cle ce# w e# r /b# i/ox t rst t wb ffh reset command table 19. status register contents after reset operation condition status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex wp# highready 11100000e0h wp# low ready and write protected 0110000060h figure 29. erase enable t ww 60h d0h w e# i /ox w p# r /b#
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 42 order number: 311998-006 figure 30. erase disable t ww 60h d0h w e# i /ox w p# r /b# figure 31. program enable t ww 80h 10h w e# i /ox w p# r /b# figure 32. program disable t ww 80h 10h w e# i /ox w p# r /b#
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 43 intel ? ss72 nand flash memory 7.0 error management intel ? nand flash devices are specified to have a minimum of 2,008 (n vb ) valid blocks out of every 2,048 total available blocks. this means the devices may have blocks that are invalid when they are shipped. an invalid block is one that contains one or more bad bits. additional bad blocks may develop with use. however, the total number of available blocks will not fall below n vb during the endurance life of the product. although nand flash memory devices may contain bad blocks, they can be used quite reliably in systems that provide bad-block mapping, bad-block replacement, and error correction algorithms. this type of software environment ensures data integrity. internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the flash device. the first block (physical block address 00h) for each ce# is guaranteed to be free of defects (up to 1,000 program/erase cycles) when shipped from the factory. this provides a reliable location for storing boot code and critical boot information. before nand flash devices are shipped from intel, they are erased. the factory identifies invalid blocks before shipping by programming data other than ffh (x8) or ffffh (x16) into the first spare location (column address 2,048 for x8 devices, or column address 1,024 for x16 devices) of the first or second page of each bad block. system software should check the first spare address on the first two pages of each block prior to performing any erase or programming operations on the nand flash device. a bad block table can then be created, allowing system software to map around these areas. factory testing is performed under worst-case conditions. because blocks marked bad may be marginal, it may not be possible to recover this information if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over the life of the nand flash device, certain precautions must be taken, such as: ? always check status after a program, erase, or data move operation. ? use some type of error detection and correction algorithm to recover from single- bit errors per 528 bytes of data. ? use a bad-block replacement algorithm.
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 44 order number: 311998-006 8.0 timing diagrams note: x16: i/o[15:8] must be set to 0. note: x16: i/o [15:8] must be set to 0. figure 33. command latch cycle w e# ce# ale cle i/ox command t wp t ch t cs t alh t dh t ds t als t clh t cls don?t car e figure 34. address latch cycle t alh w e# ce# ale cle i/ox col add 1 t wp t wh t cs t dh t ds t als t cls col add 2 row add 1 row add 2 row add 3 don?t care undefined t wc
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 45 intel ? ss72 nand flash memory note: d in final = 2,111 (x8) or 1,055 (x16). figure 35. input data latch w e# ce# ale cle i/ox t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in 1 d in final 1 don?t car e t wc d in 0 figure 36. serial access cycle after read ce# re# i/ox t reh t rp t rr t rc t cea t rea t rea t rea don?t car e t rhz t chz t rhz t oh r /b# t oh d out d out d out
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 46 order number: 311998-006 figure 37. read status cycle re# ce# w e# cle i/ox t rhz t wp t whr t clr t ch t cls t cs t clh t dh t oh t rp t chz t ds t rea t oh t ir 70h status output don?t car e t cea figure 38. page read d out n d out n + 1 d out m w e# ce# ale cle re# r /b# i/ox t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz don?t care col add 1 col add 2 row add 1 row add 2 row add 3
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 47 intel ? ss72 nand flash memory figure 39. page read operation with ce# dont care re# ce# t rea t cea re# ce# ale cle i/ox i/ox out r /b# w e# data output t r don?t care address (5 ccycles) 00h 30h figure 40. random data read w e# ce# ale cle re# r /b# i/ox busy col add 1 col add 2 row add1 row add 2 row add 3 00h t r t wb t ar t rr don?t care t rc d out m d out m + 1 col add 1 col add 2 05h e0h t rea t clr d out n d out n + 1 30h t whr column address n column address m
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 48 order number: 311998-006 figure 41. page read cache mode timing diagram (part 1 of 2) t t wc w e# ce# ale cle re# r /b# i/ox column address 0 1 d out t cea t ds t clh t cls t cs t ch t dh don?t care undefined t rr t wb t wb t wb t r column address 0 continued to 1 of next page t rc t rea 30h d out 0 d out 0 d out 1 31h 31h col add 1 col add 2 row add 1 row add 2 row add 3 00h page address m page address m column address 00h page addre ss m + 1 t dcbsyr1 t dcbsyr2 figure 42. page read cache mode timing diagram (part 2 of 2) cle ce# w e# ale re# i/ox r /b# 1 page address m + 1 don?t care undefine d page address m + 2 column address 0 continued from 1 of previous page page address m + x column address 0 t clh t ch t rea t cea t ds t dh t rr t wb t wb column address 0 d out 1 d out 0 d out 1 d out 0 d out 1 t cls t cs t rc t dcbsyr2 d out 0 31h t wb 31h 3fh t dcbsyr2 t dcbsyr2
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 49 intel ? ss72 nand flash memory figure 43. page read cache mode timing without r/b# (part 1 of 2) t wc w e# ce# ale cle re# i/ox 30h 70h status d out 0 column address 0 1 d out 0 d out 1 d out column address 00h page address m page address m t cea t ds t clh t cls t cs t ch t dh don?t care 31h 31h column address 0 70h status i/o 6 = 0, cache busy = 1, cache ready i/o 5 = 0, busy = 1, ready continued to 1 of next page col add 1 col add 2 row add 1 row add 2 row add 3 00h 00h 00h t rc t rea 70h status i/o 6 = 0, cache busy = 1, cache ready page addres s m + 1 figure 44. page read cache mode timing without r/b# (part 2 of 2) w e# ce# ale cle re# i/ox 1 page address m + 1 don?t care page address m + 2 column address 0 continued from 1 of previous page page address m + x column address 0 t rea t cea t ds t dh column address 0 d out 0 d out 1 d out 31h d out 0 d out 3fh d out 1 d out d out 1 d out 0 t rc d out 31h 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 00h 00h 00h t clh t ch t cls t cs
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 50 order number: 311998-006 note: see table 17, device id and configuration codes on page 30 . figure 45. read id operation w e# ce# ale cle re# i/ox address, 1 cycle 90h 00h byte 2 byte 0 byte 1 byte 3 t ar t rea t whr figure 46. program page operation w e# ce# ale cle re# r /b# i/ox t wc t adl serial data input command x8 device: m = 2,112 byte x16 device: m = 1,056 byte program command read status command 1 up to m bytes serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in m 70h status 10h t prog t wb don?t care
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 51 intel ? ss72 nand flash memory figure 47. program page operation with ce# dont care cle ce# w e# ale i/ox address (5 cycles) data input 10h we# ce# t wp t ch t cs don?t care data input 80h figure 48. program page operation with random data input w e# ce# ale cle re# r /b# i/ox t wc serial data input command serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in n+1 t adl t adl random data input command column address program command read status command serial input 85h t prog t wb don?t car e col add 1 col add 2 d in n d in n+1 70h statu s 10h
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 52 order number: 311998-006 figure 49. internal data move w e# ce# ale cle re# r /b# i/ox t wb t prog t wb busy busy t wc internal data move don?t care t adl t whr col add 2 row add 1 row add 2 70h 10h status data n row add 3 col add 1 00h 35h col add 2 row add 1 row add 2 row add 3 col add 1 85h data 1 t r read status command figure 50. program page cache mode w e# ce# ale cle re# r /b# i/ox 15h t cbsy t wb t wb t whr t lprog col add 1 80h 10h 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page - 1 last page serial input program program t wc don?t car e 80h t adl row add 3 serial data input figure 51. program page cache mode ending on 15h w e# ce# ale cle re# i/ox 15h col add 1 80h 15h 70h status 70h status 70h status col add 2 row add 2 row add 1 row add 3 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page last page ? 1 serial input program program t wc don?t care 80h poll status until: i/o6 = 1, ready to verify successful completion of the last 2 page s: i/o5 = 1, ready i/o0 = 0, last page program successful i/o1 = 0, last page ? 1 program successful t adl t whr t whr t adl serial data input
intel ? ss72 nand flash memory 6-sep-2006 datasheet order number: 311998-006 53 intel ? ss72 nand flash memory note: see table 17, device id and configuration codes on page 30 for actual values. figure 52. block erase operation w e# ce# ale cle re# r /b# i/ox auto block erase setup command erase command read status command busy row address 60h row add 1 row add 2 row add 3 70h status d0h t wc t bers t wb t whr don?t car e i/o0 = 0, pass i/o0 = 1, fail figure 53. reset operation cle ce# w e# r /b# i/ox t rst t wb ffh reset command
intel ? ss72 nand flash memory intel ? ss72 nand flash memory datasheet 6-sep-2006 54 order number: 311998-006 9.0 ordering information figure 54, decoder on page 54 provides the device part number decoder and table 20, intel? nand flash memory ordering information on page 54 provides the available combinations. for combinations not listed, please contact your local intel sales office. figure 54. decoder s 2 9 f 0 8 a n 3 2 g a b j 0 device configuration # of die # of ce # of r/b i/o a b c 1 1 1 common common common 1 2 2 1 1 2 group designator 29f = intel ? flash memory package designator js = 48-pin pb-free tsop density 01g = 1gb 02g = 2gb 04g = 4gb 08g = 8gb 16g = 16gb 32g = 32gb device bus width 08=8 bits 16 = 16 bits f 2 common 42 process identifier a = 90nm, b = 72 nm, c = 50 nm product generation / revisions 1-9 generations, e = engineering samples m = mechanical samples, q = qualification samples product technology type n = nand flash memory m = mlc nand flash memory operating voltage range a = 3.3 v (2.70 ? 3.60 v) b = 1.8 v (1.70 ? 1.95 v) table 20.intel ? nand flash memory ordering information im l1 part number marketing device # (1st mark line) mm # (2nd mark line) device nomenclature JS29F02G08AANB3 29f02g08aanb3 880202 2gb, x8, 1 die, 3.3 v, nand, 72 nm, 3rd gen intel si (1000pc t&r), pb-free) 880203 2gb, x8, 1 die, 3.3 v, nand, 72 nm, 3rd gen intel si (11 tray pack), pb-free) js29f04g08banb3 29f04g08banb3 884090 2gb, x8, 2 die, 3.3 v, nand, 72 nm, 3rd gen intel si (1000pc t&r), pb-free 884116 2gb, x8, 2 die, 3.3 v, nand, 72 nm, 3rd gen intel si (11 tray pack), pb-free js29f08g08fanb3 29f08g08fanb3 880197 2gb, x8, 4 die, 3.3 v, nand, 72 nm, 3rd gen intel si (1000pc t&r), pb-free) 880198 2gb, x8, 4 die, 3.3 v, nand, 72 nm, 3rd gen intel si (11 tray pack), pb-free) tbd tbd tbd 2gb, x16, 1 die, 3.3 v, nand, 72 nm, 3rd gen intel si (1000pc t&r), pb-free) 2gb, x16, 1 die, 3.3 v, nand, 72 nm, 3rd gen intel si (11 tray pack), pb-free)

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