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rev. 1.0 8/06 copyright ? 2006 by silicon laboratories si3016 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si3016 3.3 v e nhanced g lobal d irect a ccess a rrangement features complete daa includ es the following: applications description the si3016 is an integrated direct access arrangement (daa) line-side device with a programmable line interface to meet global telephone line interface requirements. available in a 16-pin small outline package, it eliminates the need for an analog front end (afe), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. the si3016 dramatically reduces the number of discrete components and cost required to achieve compliance with global regulatory requirements. the si3016 interfaces directly to a s ilicon laboratories integrated daa system-side interface. functional block diagram ? line voltage monitor ? loop current monitor ? 3.2 dbm transmit/receive levels ? parallel handset detection ? 7 a on-hook line monitor current ? overload protection ? programmable line interface z ac termination z dc termination z ring detect threshold z ringer impedance ? polarity reversal detection ? 84 db dynamic range tx/rx ? integrated analog front end (afe) and 2- to 4-wire hybrid ? integrated ring detector ? caller id support ? pulse dialing support ? billing tone detection ? 3.3 v or 5 v power supply ? direct interface to dsps ? up to 5000 v isolation ? proprietary isolation technology ? v.90 modems ? voice mail systems ? set-top boxes ? fax machines ? internet appliances ? voip systems silicon laboratories integrated daa interface isolation interface si3016 rx rng1 rng2 qb qe qe2 rext2 rext vreg2 vreg dct ref filt2 filt hybrid and dc termination ring detect off-hook u.s. patent #5,870,046 u.s. patent #6,061,009 other patents pending ordering information see page 46. pin assignments si3016 2 1 3 4 5 6 7 8 15 16 14 13 12 11 10 9 qe2 dct ignd c1b rng1 rng2 qb qe filt rx rext rext2 ref vreg2 vreg filt2
si3016 2 rev. 1.0
si3016 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.1. initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.2. power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 4.3. isolation barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.4. transmit/receive full scal e level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.5. parallel handset detecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6. line voltage/loop current s ensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7. off-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8. dc termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9. dc termination considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.10. ac termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11. ring detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4.12. ringer impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13. dtmf dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14. pulse dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.15. billing tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.16. billing tone filter (optional ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.17. on-hook line moni tor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.18. caller id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.19. overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.20. analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.21. gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.22. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.23. power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.24. calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.25. in-circuit testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 4.26. exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.27. revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 appendix a?ul1950 3rd edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 appendix b?cispr22 compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6. pin descriptions: si3016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8. package outline: soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
si3016 4 rev. 1.0 1. electrical specifications all si3016 electrical specificat ions are based on the assumption that all s pecifications listed in the data sheet of the host processor with the integrated system-side daa module are met. table 1. recommended operating conditions parameter 1 symbol test condition min 2 typ max 2 unit ambient temperature t a k-grade 0 25 70 c ambient temperature t a b-grade ?40 25 85 c notes: 1. the si3016 specifications are guarantee d when the typical application circuit (including component tolerance) and any system-side module and any si3016 are used. see figur e 6, ?si3016 typical application circuit,? on page 9. 2. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated.
si3016 rev. 1.0 5 figure 1. test circuit for loop characteristics table 2. loop characteristics (t a = 0 to 70 c for k-grade and ?40 to 85 c for b-grade, see figure 1) parameter symbol test condition min typ max unit dc termination voltage v tr i l = 20 ma, act = 1 dct = 11 (ctr21) ??7.5v dc termination voltage v tr i l = 42 ma, act = 1 dct = 11 (ctr21) ? ? 14.5 v dc termination voltage v tr i l = 50 ma, act = 1 dct = 11 (ctr21) ??40 v dc termination voltage v tr i l = 60 ma, act = 1 dct = 11 (ctr21) 40 ? ? v dc termination voltage v tr i l = 20 ma, act = 0 dct = 01 (japan) ??6.0v dc termination voltage v tr i l = 100 ma, act = 0 dct = 01 (japan) 9??v dc termination voltage v tr i l = 20 ma, act = 0 dct = 10 (fcc) ??7.5v dc termination voltage v tr i l = 100 ma, act = 0 dct = 10 (fcc) 9??v dc termination voltage v tr i l = 15 ma, act = 0 dct = 00 (low voltage) ??5.2v on hook leakage current 1 i lk v tr =?48v ? ? 7 a operating loop current i lp fcc / japan modes 13 ? 120 ma operating loop current i lp ctr21 mode 13 ? 60 ma dc ring current 1 dc flowing through ring detection circuitry ?? 7 a ring detect voltage 2 v rd rt = 0 11 ? 22 v rms ring detect voltage 2 v rd rt = 1 17 ? 33 v rms ring frequency f r 15 ? 68 hz ringer equivalence number 3 ren ? ? 0.2 notes: 1. r25 and r26 installed. 2. the ring signal is guaranteed to not be det ected below the minimum. the ring signal is guaranteed to be detected above the maximum. 3. rz = 0. see "4.12. ringer impedance" on page 18. tip ring + ? si3016 v tr 600 10 f i l
si3016 6 rev. 1.0 table 3. dc characteristics (t a = 0 to 70 c for k-grade and ?40 to 85 c for b-grade) parameter symbol test condition min typ max unit input leakage current i l ?10 ? 10 a power supply current, analog* i a ?0.3 ?ma *note: this current is required from the integr ated system-side interface to communicate with the si3 016 through the isolation interface. table 4. ac characteristics (t a = 0 to 70 c for k-grade and ?40 to 85 c for b-grade; see figure 6 on page 9) parameter symbol test condition min typ max unit sample rate fs fs = f pll2 /5120 7.2 ? 11.025 khz transmit frequency respon se low ?3 dbfs corner ? 0 ? hz receive frequency response low ?3 dbfs corner ? 5 ? hz transmit full scale level 1 v fs full = 0 (?1 dbm) ? 1 ? v peak full = 1 (+3.2 dbm) 2 ?1.58?v peak receive full scale level 1,3 v fs full = 0 (?1 dbm) ? 1 ? v peak full = 1 (+3.2 dbm) 3 ?1.58?v peak dynamic range 4,5,6 dr act=0, dct=10 (fcc) i l =100 ma ?82?db dynamic range 4,5,7 dr act=0, dct=01 (japan) i l =20 ma ?83?db dynamic range 4,5,6 dr act=1, dct=11(ctr21) i l =60 ma ?84?db transmit total harmonic distortion 6,8 thd act=0, dct=10 (fcc) i l =100 ma ??85?db transmit total harmonic distortion 7,8 thd act=0, dct=01 (japan) i l =20 ma ??76?db receive total harmonic distortion 7,8 thd act=0, dct=01 (japan) i l =20 ma ??74?db receive total harmonic distortion 6,8 thd act=1, dct=11 (ctr21) i l =60 ma ??82?db dynamic range (caller id mode) dr cid vin=1khz, ?13dbm ? 60 ? db notes: 1. measured at tip and ring with 600 termination at 1 khz, as shown in figure 1. 2. r2 should be changed to a 243 resistor when the fullscale bit (ful l) is set to 1 (register 18, bit 7). 3. receive full scale level will produce ?0.9 dbfs at sdo. 4. dr = 20 x log |vin| + 20 x log (rms signal/rms noise). 5. measurement is 300 to 3400 hz. applies to both transmit and receive paths. 6. vin = 1 khz, ?3 dbfs, fs = 10300 hz. 7. vin = 1 khz, ?6 dbfs, fs = 10300 hz. 8. thd = 20 x log (rms distortion/rms signal). 9. the aout pin is an optional pin locat ed on the integrated system-side module. v d refers to the digital power supply of the integrated syst em-side module.
si3016 rev. 1.0 7 caller id full scale level (0 db gain) v cid mode = 0 ? 0.8 ? v pp caller id full scale level (arx = 00) v cid mode = 1 ? 1.4 ? v pp gain accuracy 5,6 2-w to sdo, atx and arx = 000, 001, or 010 ?0.5 0 0.5 db gain accuracy 5,6 2-w to sdo, atx and arx = 011, 1xx ?1 0 1 db table 5. absolute maximum ratings parameter symbol value unit operating temperature range t a ?40 to 100 c storage temperature range t stg ?65 to 150 c note: permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specif ied in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. digital fir filter characteristics?transmit and receive (sample rate = 8khz, t a = 70 c for k-grade and ?40 to 85 c for b-grade) parameter symbol min typ max unit passband (0.1 db) f (0.1 db) 0?3.3khz passband (3 db) f (3 db) 0?3.6khz passband ripple peak-to-peak ?0.1 ? 0.1 db stopband ? 4.4 ? khz stopband attenuation ?74 ? ? db group delay t gd ? 12/fs ? sec note: typical fir filter characteristics for fs = 8000 hz are shown in figures 2, 3, 4, and 5. table 4. ac characteristics (continued) (t a = 0 to 70 c for k-grade and ?40 to 85 c for b-grade; see figure 6 on page 9) parameter symbol test condition min typ max unit notes: 1. measured at tip and ring with 600 termination at 1 khz, as shown in figure 1. 2. r2 should be changed to a 243 resistor when the fullscale bit (ful l) is set to 1 (register 18, bit 7). 3. receive full scale level will produce ?0.9 dbfs at sdo. 4. dr = 20 x log |vin| + 20 x log (rms signal/rms noise). 5. measurement is 300 to 3400 hz. applies to both transmit and receive paths. 6. vin = 1 khz, ?3 dbfs, fs = 10300 hz. 7. vin = 1 khz, ?6 dbfs, fs = 10300 hz. 8. thd = 20 x log (rms distortion/rms signal). 9. the aout pin is an optional pin locat ed on the integrated system-side module. v d refers to the digital power supply of the integrated syst em-side module.
si3016 8 rev. 1.0 figure 2. fir receive filter response figure 3. fir receive filter passband ripple figure 4. fir transmit filter response figure 5. fir transmit filter passband ripple for figures 2?5, all filter plots apply to a sample rate of fs = 8 khz. the filters scale with the sample rate as follows: f (0.1 db) = 0.4125 fs f (?3 db) = 0.45 fs where fs is the sample frequency. input frequency?hz attenuation?db input frequency ?hz attenuation?db attenuation?db input frequency?hz input frequency?hz attenuation?db
si3016 rev. 1.0 9 c6 + c14 r11 c2 r17 c1 tip z4 r25 c7 c31 q4 note 2: r12, r13 and c14 are only required if complex ac termination is used (act bit = 1). c19 r28 c9 fb1 c16 + c5 d4 bav99 u2 si3016 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 qe2 dct ignd c1b rng1 rng2 qb qe vreg vreg2 ref rext2 rext rx filt filt2 q3 r27 r10 c22 c13 ring c8 q2 r26 11 12 9 13 c1a gnd aout va no ground plane in daa section r16 r15 r9 rv2 r5 r18 note 3: see "billing tone detection" section for optional billing tone filter (germany, switzerland, south africa). fb2 host processor w/ silicon laboratories integrated daa system-side device aout q1 c30 c20 r12 d2 + c12 see note 1 r2 c25 note 1: please refer to appendix b for information regarding the installation of l1 and l2. r24 decoupling cap for va r7 r6 d1 r13 rv1 c32 c24 z1 note 4: see appendix a for applications requiring ul 1950 3rd edition compliance. d3 bav99 z5 c4 r19 r8 c18 l1 l2 c3 figure 6. si3016 typical application circuit
si3016 10 rev. 1.0 2. bill of materials table 7. si3016 global component values component value supplier(s) c1,c4 1 150 pf, 3 kv, x7r,20% novacap, venkel, johanson, murata, panasonic c2, c31, c32 not installed c3, c13 2 0.22 f, 16 v, x7r, 20% c5 0.1 f, 50 v, elec/tant, 20% c6,c16 0.1 f, 16 v, x7r, 20% c7,c8 560 pf, 250 v, x7r, 20% novacap, johanson, murata, panasonic c9 10 nf, 250 v, x7r, 20% c12 1.0 f, 16 v, tant, 20% panasonic c14 0.68 f, 16 v, x7r/elec/tant, 20% c18,c19 3.9 nf, 16 v, x7r, 20% c20 0.01 f, 16 v, x7r, 20% c22 1800 pf, 50 v, x7r, 20% c24,c25 1 1000 pf, 3 kv, x7r, 10% c30 3 not installed d1,d2 4 dual diode, 300 v, 225 ma central semiconductor d3,d4 bav99 dual diode, 70 v, 350 mw diodes inc., onsemiconductor, fairchild fb1,fb2 ferrite bead murata l1, l2 5 330 h, dcr < 3 , 120 ma, 10% taiyo-yuden, act, tran stek magnetics, cooper electronics q1,q3 a42, npn, 300 v onsemiconductor, fairchild q2 a92, pnp, 300 v onsemiconductor, fairchild q4 6 bcp56t1, npn, 80 v, 1/2 w onsemiconductor, fairchild rv1 sidactor, 275 v, 100 a teccor, st microelectronics, microsemi, ti rv2 7 not installed r2 8 402 , 1/16 w, 1% r5 100 k , 1/16 w, 1% r6 120 k , 1/16 w, 5% r7,r8,r15,r16,r17,r19 9 5.36 k , 1/4 w, 1% r9,r10 56 k , 1/10 w, 5% r11 9.31 k , 1/16 w, 1% r12 78.7 , 1/16 w, 1% r13 215 , 1/16 w, 1% r18 2.2 k , 1/10 w, 5% r24 150 , 1/16 w, 5% r25,r26 10 m , 1/16 w, 5% r27,r28 10 , 1/10 w, 5% u1 si3021 silicon labs u2 silicon labs system-side device silicon labs z1 zener diode, 43 v, 1/2 w vishay, motorola, rohm z4,z5 zener diode, 5.6 v, 1/2 w vishay, motorola, rohm notes: 1. y2 class capacitors are n eeded for the nordic requirements of en60950 and may also be used to achieve sur ge performance of 5 kv or better. 2. c13 is used to ensure compliance with on-hook pulse dialing and sp ark quenching requirements in countries, such as australia an d south africa. if this is not a concern, a 0.1 f cap may be used. 3. install only if needed for improved radiated emissions performance (10 pf, 16 v, npo, 10%). 4. several diode bridge configurations are acceptable (suppliers include general semi., diodes inc.). 5. see appendix b for additional requirements. 6. q4 may require copper on board to meet 1/2 w power requirement. (contact manufacturer for details.) 7. rv2 can be installed to improve performance from 2500 v to 3500 v for multiple longitudinal surges (270 v, mov). 8. if supporting +3.2 dbfs voice applications, r2 should be 243 and set the fullscale bit (reg 18[7]). 9. the r7, r8, r15, and r16, r17, and r19 resistors may each be replaced with a single resistor of 1.62 k , 3/4 w, 1%.
si3016 rev. 1.0 11 3. analog output figure 7 illustrates an optional application circuit to su pport the anal og output capability of the daa system-side module for call progress monitoring purposes. the arm bi ts in register 6 allow the receive path to be attenuated by 0, ?6, or ?12 db. the atm bits, which are also in re gister 6, allow the transmit path to be attenuated by ?20, ?26, or ?32 db. both the transmit and receive paths can also be independently muted. figure 7. optional connection to aout for a call progress speaker table 8. component values?optional connection to aout symbol value c1 2200 pf, 16 v, 20% c2, c3, c5 0.1 f, 16 v, 20% c4 100 f, 16 v, elec. 20% c6 820 pf, 16 v, 20% r1 10 k , 1/10 w, 5% r2 10 , 1/10 w, 5% r3 47 k , 1/10 w, 5% u1 lm386 aout c1 c2 c6 r1 r3 c4 c3 c5 r2 speaker + ? + 3 2 4 5 6 +5 v
si3016 12 rev. 1.0 4. functional description the si3016 is an integrated direct access arrangement (daa) that provides a programmable line interface to meet global telephone line interface requirements. the device implements silicon laboratories? proprietary capacitive isolation technology which offers the highest level of integration by replacing an analog front end (afe), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid with a 16-pin small outline integrated circuit (soic) package in conjunction with a system-side module that is integrated into another device. the si3016 chip can be fully programmed to meet international requirements and is compliant with fcc, ctr21, jate, and various other country-specific ptt specifications as shown in table 9. in addition, the si3016 has been designed to meet the most stringent global requirements for out-of-band energy, emissions, immunity, lightning surges, and safety. the si3016 is intended for single-channel applications. for multi-channel applications, up to eight si3044 daas can be daisy-chained together on one serial port. table 9. country specific register settings register 16 17 18 country ohs act dct[1:0] rz rt lim vol argentina 0010000 0 australia 1 11 01 00 0 0 austria 0 0 or 1 11 0 0 1 0 bahrain 0 0 10 0 0 0 0 belgium 0 0 or 1 11 0 0 1 0 brazil 1 00 01 00 0 0 bulgaria 0 1 11 0 0 1 0 canada 0 0 10 0 0 0 0 chile 0 0 10 0 0 0 0 china 1 00 01 00 0 0 colombia 0 0 10 0 0 0 0 croatia 01110010 ctr21 1,2 00 or 1 11 0 0 1 0 cyprus 0 1 11 0 0 1 0 czech republic 0 1 11 0 0 1 0 denmark 0 0 or 1 11 0 0 1 0 ecuador 0 0 10 0 0 0 0 egypt 1 00 01 00 0 0 el salvador 0 0 10 0 0 0 0 finland 0 0 or 1 11 0 0 1 0 france 0 0 or 1 11 0 0 1 0 germany 0 0 or 1 11 0 0 1 0 greece 0 0 or 1 11 0 0 1 0 guam 00 10 00 0 0 hong kong 0 0 10 0 0 0 0 notes: 1. see "4.9. dc termination considerations" on page 17 for more information. 2. ctr21 includes the following countries: austria, be lgium, denmark, finland, france, germany, greece, iceland, ireland, italy, luxembourg, netherlands, no rway, portugal, spain, swe den, switzerland, and the united kingdom. 3. supported for loop current 20 ma.
si3016 rev. 1.0 13 hungary 0 0 10 0 0 0 0 iceland 0 0 or 1 11 0 0 1 0 india 0010000 0 indonesia 0 0 10 0 0 0 0 ireland 0 0 or 1 11 0 0 1 0 israel 0 0 or 1 11 0 0 1 0 italy 0 0 or 1 11 0 0 1 0 japan 1 00 01 00 0 0 jordan 1 00 01 00 0 0 kazakhstan 1 00 01 00 0 0 kuwait 0 0 10 0 0 0 0 latvia 0 0 or 1 11 0 0 1 0 lebanon 0 0 or 1 11 0 0 1 0 luxembourg 0 0 or 1 11 0 0 1 0 macao 0010000 0 malaysia 1,3 00 01 00 0 0 malta 0 0 or 1 11 0 0 1 0 mexico 0 0 10 0 0 0 0 morocco 0 0 or 1 11 0 0 1 0 netherlands 0 0 or 1 11 0 0 1 0 new zealand 0 1 10 0 0 0 0 nigeria 0 0 or 1 11 0 0 1 0 norway 0 0 or 1 11 0 0 1 0 oman 1 00 01 00 0 0 pakistan 1 00 01 00 0 0 peru 00 10 00 0 0 philippines 1 00 01 00 0 0 poland 00 10 11 0 0 portugal 0 0 or 1 11 0 0 1 0 romania 0010000 0 russia 1 00 01 00 0 0 saudi arabia 0 0 10 0 0 0 0 singapore 0 0 10 0 0 0 0 slovakia 0 0 10 0 0 0 0 slovenia 0 0 10 1 1 0 0 south africa 1 0 10 1 0 0 0 south korea 0010000 0 table 9. country specific register settings register 16 17 18 country ohs act dct[1:0] rz rt lim vol notes: 1. see "4.9. dc termination considerations" on page 17 for more information. 2. ctr21 includes the following countries: austria, be lgium, denmark, finland, france, germany, greece, iceland, ireland, italy, luxembourg, netherlands, no rway, portugal, spain, swe den, switzerland, and the united kingdom. 3. supported for loop current 20 ma.
si3016 14 rev. 1.0 4.1. initialization when the integrated system-side module and the si3016 are initially powere d up, the daa registers will have default values that guarantee the line-side chip (si3016) is powered down with no possibility of loading the line (i.e., off-hook). an example initialization procedure is outlined below: 1. program the desired sample rate with the sample rate control register. 2. wait until the si3016 pll is locked. this time is between 100 s and 1 ms. 3. write a 00h into the daa control 2 register. this powers up the line-side chip (si3016) and enables the aout for call progress monitoring. 4. set the desired line interface parameters (i.e., dct[1:0], act, ohs, rt, lim[1:0], and vol) as defined by ?country specific register settings? shown in table 9, ?country specific register settings,? on page 12. after this procedure is complete, the si3016 is ready for ring detection and off-hook. 4.2. power supply when on-hook, the si3016 draws power across the isolation link from the system-side module. when off- hook, power is drawn from the 2-wire line. thus, no power supply connections are needed for the si3016. 4.3. isolation barrier the si3016 achieves an isol ation barrier through low- cost, high-voltage capacitors in conjunction with silicon laboratories? proprietary signal processing techniques. these techniques eliminate any signal degradation due to capacitor mismatches, common mode interference, or noise coupling. as shown in figure 6 on page 9, the c1, c4, c24, and c25 capacitors isolate the system side from the si3016 (line side). all transmit, receive, control, ring detect, and caller id data are communicated through this barrier. the isolated communications lin k is disabled by default. to enable it, the pdl bit must be cleared. no communication between the system-side module and the si3016 can occur until this bit is cleared. when the pdl bit is cleared, a check is performed to ensure that the line-side device is an si3016 device. if it is not, the system-side module will not function. 4.4. transmit/recei ve full scale level the si3016 supports programmable maximum transmit and receive levels. the full-scale tx/rx level is established by writing the fu ll bit in register 18. with full = 1, the full scale tx/rx level is increased to 3.2 dbm to support certain fcc voice applications that require higher tx/rx levels. when full = 1, r2 must be changed from 402 to 243 . the default full scale value is ?1 dbm (full = 0). note that this higher tx/ rx full-scale mode must be used in fcc/600 termination mode. spain 0 0 or 1 11 0 0 1 0 sweden 0 0 or 1 11 0 0 1 0 switzerland 0 0 or 1 11 0 0 1 0 syria 1 00 01 00 0 0 taiwan 1 00 01 00 0 0 thailand 1 00 01 00 0 0 uae 0010000 0 united kingdom 0 0 or 1 11 0 0 1 0 usa 0010000 0 yemen 0010000 0 table 9. country specific register settings register 16 17 18 country ohs act dct[1:0] rz rt lim vol notes: 1. see "4.9. dc termination considerations" on page 17 for more information. 2. ctr21 includes the following countries: austria, be lgium, denmark, finland, france, germany, greece, iceland, ireland, italy, luxembourg, netherlands, no rway, portugal, spain, swe den, switzerland, and the united kingdom. 3. supported for loop current 20 ma.
si3016 rev. 1.0 15 4.5. parallel handset detection the si3016 is capable of detecting a parallel handset going off-hook. when the si3016 is off-hook, the loop current can be monitored via the lvcs bits. a significant drop in loop current can signal a parallel handset going off-hook. if a parallel handset causes the lvcs bits to read all 0s, the drop-out detect (dod) bit may be checked to verify that a valid line still exists. when on-hook, the lvcs bits may also be read to determine the line voltage. significant drops in line voltage may also be used to detect a parallel handset. for the si3016 to operate in parallel with another handset, the parallel handset must have a sufficiently high dc termination to support two off-hook daas on the same line. the off bit in register 16 is designed to improve parallel handset operation by changing the dc impedance from 50 to 800 and reducing the dct pin voltage. 4.6. line voltage/ loop current sensing the si3016 has the ability to measure both line voltage and loop current. the five bit lvcs register reports line voltage measurements when on-hook, loop current measurements when off-hook, or on-hook line monitor data depending on the state of the mode, oh, and onhm bits. using the lvcs bits, the user can determine the following: ? when on-hook, detect if a line is connected. ? when on-hook, detect if a parallel phone is off-hook. ? when off-hook, detect if a parallel phone goes on or off-hook. ? detect if enough loop current is available to operate. ? detect if there is an overload condition which could damage the daa (see over load protection feature). 4.6.1. line voltage measurement the si3016 reports the line voltage with the lvcs bits in register 19. lvcs has a full scale of 87 v with an lsb of 2.75 v. the first code (0 1) is skewed such that a 0 indicates that the line voltage is < 3 v. the accuracy of the lvcs bits is 20%. the user can read these bits directly through the lvcs register when it is on-hook and the mode bit is set to 1. a typical transfer function is shown in figure 8. 4.6.2. loop current measurement when the si3016 is off-hook, the lvcs bits measure loop current in 3 ma/bit resolution. these bits enable the user to detect another phone going off-hook by monitoring the dc loop current. the line voltage current sense transfer function is shown in figure 9 and is detailed in table 10. figure 8. typical loop voltage lvcs transfer function 15 0 0 5 10 36 33 30 27 24 21 18 15 12 9 3639424548 100 lvcs bits loop voltage (v) 20 25 30 72 69 66 63 60 57 54 51 75 78 81 84 87
si3016 16 rev. 1.0 figure 9. typical loop current lvcs transfer function 4.7. off-hook the communication system generates an off-hook command by setting the oh bit. with the oh bit set, the system is in an off-hook state. the off-hook state is used to seize the line for incoming/ outgoing calls and can also be used for pulse dialing. when the daa is on-hook, negligible dc current flows through the hookswitch. when the daa is placed in the off-hook state, the hookswitch transistor pair, q1 and q2, turn on. this applies a termination impedance across tip and ring and causes dc loop current to flow. the termination impedance has both an ac and dc component. when executing an off-hook sequence, the si3016 requires 1548/fs seconds to complete the off-hook and provide phone-line data on the serial link. this includes the 12/fs filter group delay. if necessary, for the shortest delay, a higher fs may be established prior to executing the off-hook, such as an fs of 10.286 khz. the delay allows for line transients to settle prior to normal use. 4.8. dc termination the si3016 has four programmable dc termination modes that are selected with the dct[1:0] bits in register 16. fcc mode (dct[1:0] = 10 b), shown in figure 10, is the default dc termination mode and supports a transmit full scale level of ?1 dbm at tip and ring. this mode meets fcc requirements in addition to the requirements of many other countries. figure 10. fcc mode i/v characteristics ctr21 mode (dct[1:0] = 11 b), shown in figure 11, 15 0 0 5 10 36 33 30 27 24 21 18 15 12 9 3639424548 140 lvcs bits loop current (ma) 20 25 30 72 69 66 63 60 57 54 51 75 78 81 84 87 90 93 ctr21 overload table 10. loop current transfer function lvcs[4:0] condition 00000 insufficient line current for normal operation. use the dod bit to determine if a line is still connected. 00001 minimum line current for normal operation. 11111 loop current is excessive (overload). overload > 140 ma in all modes except ctr21. overload > 54 ma in ctr21 mode. 12 11 10 9 8 7 6 fcc dct mode .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 loop current (a) voltage across daa (v)
si3016 rev. 1.0 17 provides current limiting while maintaining a transmit full scale level of ?1 dbm at tip and ring. in this mode, the dc termination will curr ent limit before reaching 60 ma if the lim bit is set. figure 11. ctr21 mode i/v characteristics japan mode (dct[1:0] = 01 b), shown in figure 12, is a lower voltage mode and supports a transmit full scale level of ?2.71 dbm. higher transmit levels for dtmf dialing are also supported. see "4.13. dtmf dialing" on page 19. the low-voltage requirement is dictated by countries, such as japan and malaysia. figure 12. japan mode i/v characteristics low voltage mode (dct[1:0] = 00b), shown in figure 13, is the lowest line voltage mode supported on the si3016, with a transmit full scale level of ?5 dbm. higher transmit levels fo r dtmf dialing are also supported. see "4.13. dtmf dialing" on page 19. this low-voltage mode is offered for situations that require very low line voltage operatio n. it is important to note that this mode should only be used when necessary, as the dynamic range will be si gnificantly reduced, and thus the si3016 will not be abl e to transmit or receive large signals without clipping them. figure 13. low voltage mode i/v characteristics 4.9. dc termination considerations under certain line co nditions, it may be beneficial to use other dc termination modes no t intended for a particular world region. for instance, in countries that comply with the ctr21 standard, improved distortion characteristics can be seen for very low loop current lines by switching to fcc mode. thus, after going off-hook in ctr21 mode, the loop current monitor bits (lvcs[4:0]) may be used to measure the loop current, and if lvcs[4:0] < 6, it is recommended t hat fcc mode be used. additionally, for very low- voltage countries, such as japan and malaysia, the following procedure should be used to optimize distortion characteristics and maximize transmit levels: 1. when first going off-hook, use the low voltage mode with the vol bit set to 1. 2. measure the loop current using the lvcs[4:0] bits. 3. if lvcs[4:0] 2, maintain the current settings, and proceed with normal operation. 4. if lvcs[4:0] > 2 or < 6, switch to japan mode, leave the vol bit set, and proceed with normal operation. 5. if lvcs[4:0] 6, switch to fcc mode, set the vol bit to 0, and proceed with normal operation. note: a single decision of dc termination mode following off- hook is appropriate for most applications. however, during ptt testing, a false dc termination i/v curve may be generated if the dc i/v curve is determined fol- lowing a single off-hook event. finally, australia has se parate dc termination requirements for line seizure versus line hold. japan mode may be used to satisfy both requirements. however, if a higher transmit level for modem operation is desired, switch to fcc mode 500 ms after the initial 45 40 35 30 25 20 15 10 5 .015 .02 .025 .03 .035 .04 .045 .05 .055 .06 loop current (a) ctr21 dct mode voltageacrossdaa(v) 10.5 10 9.5 9 8.5 8 7.5 7 6.5 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 loop current (a) japan dct mode voltage across daa ( v ) 6 5.5 .11 10.5 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 loop current (a) low voltage mode voltage across daa (v) 5.0
si3016 18 rev. 1.0 off-hook. this will satisfy th e australian dc termination requirements. 4.10. ac termination the si3016 has two ac term ination impedances, which are selected with the act bit. act = 0 is a real, nominal 600 termination, which satisfies the impedance requirements of fcc part 68, jate, and other countries. this real impedance is set by circuitry internal to the si3016 as well as the resistor r2 connected to the rext pin. act = 1 is a complex imped ance, which satisfies the impedance requirements of australia, new zealand, south africa, ctr21, and some european net4 countries, such as the uk and germany. this complex impedance is set by circuitry internal to the si3016 as well as the complex network formed by r12, r13, and c14 connected to the rext2 pin. 4.11. ring detection the ring signal is capaciti vely coupled from tip and ring to the rng1 and rng2 pins. the si3016 supports either full- or half-wave ring detection. with full-wave ring detection, the designer can detect a polarity reversal as well as the ring signal. see "4.18. caller id" on page 20. the ring detection threshold is programmable with the rt bit. the ring detector output can be monitored in one of two ways. the first method uses the register bits, rdtp, rdtn, and rdt. the second method uses the sdo output internal to the integrated system-side module. the dsp must detect the frequen cy of the ring signal in order to distinguish a ring from pulse dialing by telephone equipment connected in parallel. a positive ringing signal is defined as a voltage greater than the ring threshold across rng1-rng2. rng1 and rng2 are pins 5 and 6 of the si3016. conversely, a negative ringing signal is defined as a voltage less than the negative ring threshold across rng1-rng2. the first ring detect method uses the ring detect bits, rdtp, rdtn, and rdt. rdtp and rdtn behavior is based on the rng1-rng2 voltage. whenever the signal on rng1-rng2 is above the positive ring threshold, the rdtp bit is set. whenever the signal on rng1-rng2 is below the negative ring threshold, the rdtn bit is set. when t he signal on rng1-rng2 is between these thresholds , neither bit is set. the rdt behavior is also based on the rng1-rng2 voltage. when the rfwe bit is a 0 or a 1, a positive ringing signal will set the rdt bit for a period of time. the rdt bit will not be set for a negative ringing signal. the rdt bit acts as a one shot. whenever a new ring signal is detected, the one shot is reset. if no new ring signals are detected prior to the one shot counter counting down to zero, the rdt bit will return to zero. the length of this count (in seconds) is 65536 divided by the sample rate. the rdt will also be reset to zero by an off-hook event. the second ring detect method uses the internal serial output of the integrated system-side module (sdo) to transmit ring data. if the link is active (pdl = 0) and the device is not off-hook or not in on-hook line monitor mode, the ring data will be sent by the system-side module to the host processor. the waveform on sdo depends on the state of the rfwe bit. when the rfwe bit is 0, sdo will be ?32768 (0x8000) while the rng1-rng2 vo ltage is between the thresholds. when a ring is detected, sdo will transition to +32767 while the ring signal is positive, then go back to ?32768 while the ring is near zero and negative. thus, a near square wave is presented on sdo that swings from ?32768 to +32767 in cadence with the ring signal. when the rfwe bit is 1, sdo will sit at approximately +1228 while the rng1-rng2 voltage is between the thresholds. when the ring goes positive, sdo will transition to +32767. when the ring signal goes near zero, sdo will remain near 1228. then, as the ring goes negative, the sdo will transition to ?32768. this will repeat in cadence with the ring signal. the best way to observe the ring signal on sdo is simply to observe the m sb of the data. the msb will toggle in cadence with the ring signal independent of the ring detector mode. this is adequate information for determining the ring freq uency. the msb of sdo will toggle at the same frequency as the ring signal. 4.12. ringer impedance the ring detector in many daas is ac-coupled to the line with a large, 1 f, 250 v decoupling capacitor. the ring detector on the si3016 is also capacitively coupled to the line, but it is des igned to use smaller, less expensive 1.8 nf capacitors. inherently, this network produces a high ringer impedance to the line of approximately 800 to 900 k . this value is acceptable for the majority of countries, including fcc and ctr21. several countries including poland, south africa, and slovenia, require a maximum ringer impedance that can be met with an internally-synthesized impedance by setting the rz bit in register 16.
si3016 rev. 1.0 19 4.13. dtmf dialing in ctr21 dc termination mode, the dial bit should be set during dtmf dialing if the lvcs[4:0] bits are less than 12. setting this bit in creases headroom for large signals. this bit should not be used during normal operation or if the lvcs[4:0] bits are greater than 11. in japan dc termination mode, the system-side module attenuates the transmit output by 1.7 db to meet headroom requirements. similarly, in low voltage termination mode, the syst em-side module attenuates the transmit output by 4 db. however, when dtmf dialing is desired in these modes, this attenuation must be removed. this is achieved by entering the fcc dc termination mode and setting either the fjm or the flvm bits. when in the fcc dc termination modes, these bits will enable the respective lower loop current termination modes without the associated transmit attenuation. increased di stortion may be observed, which is acceptable during dtmf dialing. after dtmf dialing is complete, the attenuation should be enabled by returning to either the japan dc termination mode (dct[1:0] = 01b) or the low voltage termination mode (dct[1:0] = 00b). the fjm and the flvm bits have no effect in any other termination mode other than the fcc dc termination mode. higher dtmf levels may also be achieved if the amplitude is increased and the peaks of the dtmf signal are clipped at digital full scale (as opposed to wrapping). clipping the signal will produce some distortion and intermodulation of the signal. generally, somewhat increased distortion (between 10?20%) is acceptable during dtmf signaling. several db higher dtmf levels can be achieved with this technique, compared with a digital full-scale peak signal. 4.14. pulse dialing pulse dialing is accomplished by going off- and on-hook to generate make and break pulses. the nominal rate is 10 pulses per second. some countries have very tight specifications for pulse fi delity, including make and break times, make resistance , and rise and fall times. in a traditional solid-state dc holding circuit, there are a number of issues in meeting these requirements. the si3016 dc holding circuit has active control of the on-hook and off-hook transients to maintain pulse dialing fidelity. spark quenching requirements in countries, such as italy, the netherlands, south africa, and australia deal with the on-hook transition during pulse dialing. these tests provide an inductive dc feed, resulting in a large voltage spike. this spike is caused by the line inductance and the sudden decrease in current through the loop when going on-hook. the traditional way of dealing with this problem is to put a parallel rc shunt across the hookswitch relay. the capacitor is large (~1 f, 250 v) and relatively expensive. in the si3016, the ohs bit can be used to slowly ramp down the loop current to pass these tests without requiring additional components. 4.15. billing tone detection ?billing tones? or ?metering pulses? generated by the central office can cause modem connection difficulties. the billing tone is typically either a 12 khz or 16 khz signal and is sometimes used in germany, switzerland, and south africa. depending on line conditions, the billing tone may be large en ough to caus e major errors related to the modem data. the si3016 has a feature that allows the device to provide feedback as to whether a billing tone has occurred and when it ends. billing tone detection is enab led by setting the bte bit. billing tones less than 1.1 v pk on the line will be filtered out by the low-pass digital filter on the si3016. the rov bit is set when a line signal is greater than 1.1 v pk , indicating a receive overload condition. the btd bit is set when a line signal (billin g tone) is la rge enough to excessively reduce the line-de rived power supply of the line-side device (si3016). when the btd bit is set, the dc termination is changed to an 800 dc impedance. this ensures minimum line voltage levels even in the presence of billing tones. the ovl bit should be polled following a billing tone detection. when the ovl bit returns to zero, indicating that the billing tone has pa ssed, the bte bit should be written to zero to return the dc termination to its original state. it will take approximate ly one second to return to normal dc operating conditions. the btd and rov bits are sticky, and they must be written to zero to be reset. after the bte, rov, and btd bits are all cleared, the bte bit can be set to re-en able billing tone detection. certain line events, such as an off-hook event on a parallel phone or a polarity reversal, may trigger the rov or the btd bits, after which the billing tone detector must be reset. the user should look for multiple events before qualifying whether billing tones are actually present. although the daa will remain off-hook during a billing tone event, the received data from the line will be corrupted when a large billing tone occurs. if the user wishes to receive data through a billing tone , an external lc filter must be added. a modem manufacturer can provide this filter to users in the form of a dongle that connects on the phone line bef ore the daa. this keeps the manufacturer from having to include a costly lc filter internal to the modem when it may only be necessary to support a few countries/customers.
si3016 20 rev. 1.0 alternatively, when a billing t one is detect ed, the system software may notify the user that a billing tone has occurred. this notification can be used to prompt the user to contact the tel ephone company and have the billing tones disabled or to pur chase an external lc filter. 4.16. billing tone filter (optional) in order to operat e without degradati on during billing tones in germany, switzerland, and south africa, an external lc notch filter is required. (the si3016 can remain off-hook during a b illing tone even t, but modem data will be lost in the pr esence of large billing tone signals.) the notch filter design requires two notches, one at 12 khz and one at 16 khz. because these components are fairly expensive and few countries supply billing tone su pport, this filter is typically placed in an external dongle or added as a population option for these countries. figure 14 shows an example billing tone filter. l1 must carry the entire loop current. the series resistance of the inductors is important to achieve a narrow and deep notch. this design has more than 25 db of attenuation at both 12 khz and 16 khz. figure 14. billing tone filter the billing tone filter affe cts the ac termination and return loss. the current complex ac termination will pass worldwide return loss specifications both with and without the billing tone filter by at least 3 db. the ac termination is optimized for frequency response and hybrid cancellation, while having greater than 4 db of margin with or without the dongle for south africa, australia, ctr21, german, and swiss country-specific specifications. 4.17. on-hook line monitor the si3016 allows the user to receive line activity when in an on-hook state. this is accomplished through a low-power adc located on-chip that digitizes the signal passed across the rng1/2 pins and then sends this signal digitally across the isolation link to the system- side module. this mode is typically used to detect caller id data (see the ?caller id? section). there are two low- power adcs on the si3016. one is enabled by setting the onhm bit in register 5. this adc draws approximately 450 a of current from the line when activated. a lower-power adc also exists on the si3016, which enables a reduced current draw from the line of approximately 7 a. this lower power adc is enabled by setting the mode bit (in conjunction with the onhm bit) to 1. (see the mode bit description in the ?control registers? secti on.) regardless of which adc is being used, the on-hook line monitor function must be disabled before the device is taken off-hook. thus, ensure that the onhm bit is cleared before setting the oh bit. the signal to the lower power adc can be attenuated to accommodate larger signals. this is accomplished through the use of the arx[2:0] bits. it is important to note that while these arx bits provide gain to the normal receive path of the daa, they also function as attenuation bits for the on-hook line monitor low-power adc. attenuation settings incl ude 0, 1, 2.2, 3.5, and 5 db. it is recommended that the new lower-power adc be used for on-hook line monitoring. 4.18. caller id the si3016 provides the de signer with the ability to pass caller id data from the phone line to a caller id decoder connected to the serial port. 4.18.1. type i caller id type i caller id sends the cid data while the phone is on-hook. table 11. component values?optional billing tone filters symbol value c1,c2 0.027 f, 50 v, 10% c3 0.01 f, 250 v, 10% l1 3.3 mh, >120 ma, <10 , 10% l2 10 mh, >40 ma, <10 , 10% l2 c3 ring tip from line to daa c1 c2 l1
si3016 rev. 1.0 21 in systems where the caller id data is passed on the phone line between the first and second rings, the following method should be ut ilized to capt ure the caller id data: 1. after identifying a ring signal using one of the methods described in "4.11. ring detection" on page 18, determine when the first ring has completed. 2. set the off/sql2 bit.this bit resets the ac coupling network on the ring input in preparation for the caller id data. this bit should not be cleared until after the caller id data has been received. 3. assert the mode bit and then the onhm bit. this enables the lower current caller id adc. 4. the low-power adc (which is powered from the system chip, allowing for approximately 7 a current draw from the line) then digitizes the caller id data passed across the rng 1/2 pins and presents the data to the dsp via the sdo signal internal to the integrated system-side module. 5. clear the onhm, mode, and off/sql2 bits after the caller id data has been received but prior to the start of the second ring. in systems where the caller id data is preceded by a line polarity (battery) reversal, the following method should be used to capture the caller id data: 1. enable full wave rectified ring detection with the rfwe bit. 2. monitor the rdtp and rdtn register bits to identify whether a polarity reversal or a ring signal has occurred. a polarity reversal will trip either the rdtp or rdtn ring detection bits, and thus the full-wave ring detector must be used to distinguish a polarity reversal from a ring. the lowest specified ring frequency is 15 hz; therefore, if a battery reversal occurs, the dsp should wait a minimum of 40 ms to verify that the event observed is a battery reversal and not a ring signal. this time is greater than half the period of the longest ring signal. if another edge is detected during this 40 ms pause, this event is characterized as a ring signal and not a battery reversal. 3. once the signal has been identified as a battery reversal, the ac coupling network on the ring input must be reset in preparation for the caller id data. set the off/slq2 bit. this bit should not be cleared until after the caller id data has been received. 4. assert the mode bit and then the onhm bit. this enables the lower current caller id adc. 5. the low-power adc (which is powered from the system chip, allowing for approximately 7 a current draw from the line) then digitizes the caller id data passed across the rng 1/2 pins and presents the data to the dsp via the sdo signal internal to the system-side module. 6. clear the onhm, mode, and off/slq2 bits after the caller id data has been received but prior to the start of the second ring. 4.18.2. type ii caller id type ii caller id sends the cid data while the daa is off-hook. this mode is often referred to as caller id/ call waiting (cid/cw). to receive the cid data while off- hook, the following procedure should be used (also see figure 15): 1. the caller alert signal (cas) tone is sent from the central office (co) and is digitized along with the line data. the host processor must detect the presence of this tone. 2. the daa must then check to see if there is another parallel device on the same line. this is accomplished by briefly going on-hook, measuring the line voltage, and then returning to an off-hook state. a. set the cald bit to 1. this disables the calibration that automati cally occurs when going off-hook. b. with the oh bit set to 1 and the onhm bit set to 0, set the mode bit to 1. this forces the daa to go on-hook and disables the off-hook counter that is normally enabled when going back off- hook. c. read the lvcs bits to determine the state of the line. d. if the lvcs bits read the typical on-hook line voltage, there are no parallel devices active on the line, and cid data reception can be continued. e. if the lvcs bits read well below the typical on- hook line voltage, then there are one or more devices present and active on the same line that are not compliant with type ii cid. cid data reception should not be continued. f. set the mode bit to 0 to return to an off-hook state. 3. immediately after returning to an off-hook state, the onhm bit must be set and left enabled for at least 30 ms. this allows the line voltage to settle before transmitting or receiving any data. after 30 ms, the onhm bit should be disabled to allow normal data transmission and reception.
si3016 22 rev. 1.0 4. if a non-compliant parallel device is present, a reply tone is not sent by the ho st tone generator, and the co does not proceed with sending the cid data. 5. if all devices on the line are type ii cid compliant, the host must mute its upstream data output to avoid the propagation of its reply tone and the subsequent cid data. after muting its upstream data output, the host processor must then send an acknowledgement (ack) tone back to the co to request the transmission of the cid data. 6. the co then responds with the cid data. after receiving this, the host processor unmutes the upstream data output and continues with normal operation. 7. the muting of the upstream data path by the host processor has the effect of muting the handset in a telephone application so the user cannot hear the acknowledgement tone and cid data being sent. 8. the cald bit can be set to 0 to reenable the automatic calibration when going off-hook. due to the nature of the low-power adc, the data presented on sdo could have up to a 10% dc offset. the caller id decoder must use either a high-pass or a band-pass filter to accurately retrieve the caller id data. figure 15. implementing type ii caller id on the si3016 4.19. overload protection the si3016 can detect if an overload condition capable of damaging the daa circuit is present. the daa may be damaged if excessive line voltage or loop current is sustained. the overload protection circuit utilizes the lvcs bits to determine an excessive line current or voltage per the lvcs bit transfer functions outlined in figures 8 and 9. when off-hook, if ope is set and lvcs = 11111, the dc termination is disabled (800 presented to the line), the hookswitch current is reduc ed, and the opd bit is set. note: if the ope bit is enabled before going off-hook, the overload protection circuit can be activated by the line transients produced by going off-hook. to avoid this, the ope bit should be 0 prior to going off-hook. this bit can then be set ~25 ms after going off-hook to enable the overload protection feature. 4.20. analog output the integrated system-side module that the si3016 is connected to supports an analog output (aout) for driving the call progress speaker found with most of today?s modems. aout is an analog signal that is comprised of a mix of the transmit and receive signals. notes: 1. the off-hook counter is used to prevent transmission or rece ption of data for 1548/fs to allow time for the line voltage to settle. if the cald bit is 0, an automatic calibration will also be performed during this time. 2. the caller alert signal (cas) tone is transmitt ed from the co, which signals an incoming call. 3. when the mode bit is set while the device is off-hook, the device is forced on-hook. this is done to read the line voltage in the lvcs bits to detect parallel handsets. in this mode, no data is transmitted on the sdo pin. 4. when the device returns off-hook after being forced on-hoo k using the mode bit, the no rmal off-hook counter is disabled. additionally, if the cald bit is set, the automatic calibration will not be performe d. the fast dct mode must be manually enabled for at least 30 ms in order to properly settle the line voltage. this is done by setting the onhm bit after disabling the mode bit. 5. after allowing the line voltage to settle in fast dct mode, normal off-hook mode should be entered by disabling the onhm bit. if cid data reception is desired, the appropriate signal should be sent to the co at this time. 30 ms on-hook off-hook counter (1548/fs) off-hook cas tone received force on-hook fast dct mode off-hook ack line oh bit onhm bit cald bit 1 234 5 mode bit
si3016 rev. 1.0 23 the receive portion of this mixed signal has a 0 db gain, while the transmit signal has a gain of ?20 db. the transmit and receive signals of the aout signal have independent controls found in register 6. the atm[1:0] bits control the tr ansmit portion, while the arm[1:0] bits control the re ceive portion. the bits only affect the aout signal and do not affect the modem data. figure 7 on page 11 illustrates a recommended application circuit. in the configuration shown, the lm386 provides a gain of 26 db. additional gain adjustments may be made by varying the voltage divider created by r1 and r3. 4.21. gain control the si3016 supports multiple receive gain and transmit attenuation settings. the receive path can support gains of 0, 3, 6, 9, and 12 db, as selected with the arx[2:0] bits. the receive path can also be muted with the rxm bit. the transmit path can support attenuations of 0, 3, 6, 9, and 12 db, as selected with the atx[2:0] bits. the transmit path can also be muted with the txm bit. the gain control bits, arxb and atxb, should be set to 0 at all times. 4.22. clocking the system-side module that the si3016 connects to is integrated onto a host processor and is thus clocked from the processor. the si3016 receives all clocking from this system-side modu le and does not need any other clock inputs. the sample rate for the si3016 is controlled by the sample rate control register. 4.23. power management the si3016 supports four basic power management operation modes. the modes are normal operation, reset operation, sleep mode, and full powerdown mode. the power management modes are controlled by the pdn and pdl bits in register 6. on powerup or following a re set, the daa is in reset operation. in this mode, the pdl bit is set while the pdn bit is cleared. the syst em-side module is fully operational except for the link. no communication between the system-side module and si3016 can occur during reset operation. note that any register bits associated with the si3016 are not valid in this mode. the most common mode of operation is the normal operation. in this mode, the pdl and pdn bits are cleared. the daa is fully operational, and the link is passing information between the system-side module and the si3016. the desired sample rate should be programmed prior to entering this mode. the si3016 supports a low-power sleep mode. this mode supports the popular wake-up-on-ring feature of many modems. to enable it, the pdn bit must be set and the pdl bit then cleared. when the si3016 is in sleep mode, the host processor clock signal may be stopped or remain active to the system-side module, but it must be active before waking up the daa. the system-side module is non-f unctional except for the link. to take the si3016 out of sleep mode, the system-side module should be reset. in summary, the powerdown/up sequence for sleep mode is as follows: 1. set the pdn bit and clear the pdl bit. 2. the system-side module clock may stay active or stop. 3. restore the system-sid e module clock before initiating the powerup sequence. 4. reset the system-side module (after system-side module clock is present). 5. program registers to desired settings. the si3016 also supports an additional power-down mode. when both the pdn and pdl bits are set, the chipset enters a complete power-down mode and draws negligible current (deep sleep mode). in this mode, the ring detect function does no t operate. normal operation may be restored using the same process for taking the daa out of sleep mode. 4.24. calibration the si3016 initiates an auto-calibration by default whenever the device goes of f-hook or experiences a loss in line power. calibration is used to remove any offsets in the on-chip a/d converter that could affect the a/d dynamic range. auto-calibra tion is typically initiated after the daa dc terminati on stabilizes and takes 512/fs seconds to complete. due to the large variation in line conditions and line card beha vior that can be presented to the daa, it may be beneficial to use manual calibration in lieu of auto-calibration. manual calibration should be executed as close to 512/ fs seconds as possible before valid transmit/receive data is expected. the following steps should be taken to implement manual calibration: 1. the cald (auto-calibration disable) bit must be set to 1. 2. the mcal (manual calibration) bit must be toggled to one and then zero to begin and complete the calibration. 3. the calibration will be co mpleted in 512/fs seconds.
si3016 24 rev. 1.0 4.25. in-circuit testing the si3016?s advanced design provides the designer with an increased abilit y to determ ine system functionality during production line tests, as well as support for end-user diagnostics. four loopback modes exist allowing increased coverage of system components. for three of the test modes, a line-side power source is needed. while a standard phone line can be used, the test circuit in figure 1 on page 5 is adequate. in addition, an off-hook sequence must be performed to connect the power source to the line-side chip. for the startup test mode, no line-side power is necessary and no off-hook sequence is required. the startup test mode is enabled by default. when the pdl bit is set (the default case), the line side is in a power- down mode and the system-side module is in a digital loop-back mode. in this mode, data received on sdi is passed through the internal filters and transmitted on sdo. this path will intro duce approximately 0.9 db of attenuation on the sdi signal received. the group delay of both transmit and rece ive filters will exist between sdi and sdo. clearing the pdl bit disables this mode, and the sdo data is switched to the receive data from the line-side. when the pdl bi t is cleared, the fdt bit becomes active, indicating successful communication between the line-side and dsp-side. this can be used to verify that the isolation link is operational. the remaining test modes require an off-hook sequence to operate. the following sequence defines the off-hook requirements: 1. powerup or reset. 2. program the desired sample rate. 3. enable the line side by clearing the pdl bit. 4. issue off-hook 5. delay 1548/fs sec to a llow calibration to occur. 6. set the desired test mode. the isolation link digital loopback mode allows the data pump to provide a digital input test pattern on the system-side module and receive that digital test pattern back on the system-side module. to enable this mode, set the dl bit. in this mo de, the isolation barrier is actually being tested. the digital stream is delivered across the isolation capacitor, c1, of figure 6 on page 9 to the line side device and returned across the same barrier. note that in this mode, the 0.9 db attenuation and filter group delays also exist. the analog loopback mode allows an external device to drive a signal on the telephone line into the si3016 line- side device and have it driven back out onto the line. this mode allows testing of external components connecting the rj-11 jack (tip and ring) to the si3016. to enable this mode, set the al bit. the final testing mode, internal analog loopback, allows the system to test the basic operation of the transmit and receive paths on the line-side chip and the external components in figure 6 on page 9. in this test mode, the data pump provides a digital test waveform on the system-side module. this data is passed across the isolation barrier, transmitted to and received from the line, passed back across the isolation barrier, and presented back to the data pump from the system-side module. to enable this mode, clear the hbe bit. when the hbe bit is cleared, this will cause a dc offset which affects the signal swing of the transmit signal. in this test mode, it is recommended that the transmit signal be 12 db lower than normal transmit levels. this lower level will eliminate clippi ng caused by the dc offset which results from disabling the hybrid. it is assumed in this test that the line ac impedance is nominally 600 . note: all test modes are mutually exclusive. if more than one test mode is enabled concurrently, the results are unpredictable. 4.26. exception handling the si3016 provides several mechanisms to determine if an error occurs during operation. through the secondary frames of the seri al link, the controlling dsp can read several status bits. the bit of highest importance is the frame detect bit fdt. this bit indicates that the system-side module and line-side (si3016) device are communicating. during normal operation, the fdt bit can be checked before reading any bits that indicate information about the line side. if fdt is not set, the following bits related to the line side are invalid: rdt, rdtn, rdtp, lcs[3:0], cbid, revb[3:0], lvcs[4:0], rov, btd, dod, opd, and ovl. following powerup and reset, the fdt bit is not set because the pdl bit defaults to 1. in this state, the link is not operating, and no information about the line side can be determined. the user must program the desired sample rate and clear the pdl bit to activate the link. while the system and line side are establishing communication, the system-side does not generate fsync signals. establishing communication will take less than 10 ms. the fdt bit can also indica te if the line side executes an off-hook request successfully. if the line side is not connected to a phone line (i.e., the user fails to connect a phone line to the modem), the fdt bit remains cleared. the controlling proc essor must allow sufficient time for the line side to execute the off-hook request. the maximum time for fdt to be valid following an off- hook request is 10 ms. if the fdt bit is high, the
si3016 rev. 1.0 25 lvcs[4:0] bits indicate the amount of loop current flowing. if the fdt fails to be set following an off-hook request, the pdl bit in register 6 must be set high for at least 1 ms to reset the line side. another useful bit is the communication link error (cle) bit. the cle bit indicates a timeout error for the isolation link. this conditio n indicates a severe error in programming or possibly a defective line-side chip. 4.27. revision identification the si3016 provides the sys tem designer the ability to determine the revision of the system-side module and/ or the si3016. the reva[3:0] bits identify the revision of the system-side module. the revb[3:0] and cbid bits identify the revision of the si3016. table 12 lists revision values for both chips. table 12. revision values revision system-side module si3016 c1010 ? d?1100 e?1101 f?1110
si3016 26 rev. 1.0 5. control registers note: any register not listed here is re served and must not be written. table 13. register summary register name bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 1 control 1 sr dl 2 control 2 al hbe rxe 3:4 reserved 5 daa control 1 rdtn rdtp onhm rdt oh 6 daa control 2 atm[1] arm[1] pdl pdn atm[0] arm[0] 7:8 reserved 9 sample rate control src[2:0] 10 reserved 11 chip a revision reva[3:0] 12 line side status cle fdt lcs[3:0] 13 chip b revision cbid revb[3:0] arxb atxb 14 line side validation chk cip safe 15 tx/rx gain control txm atx[2:0] rxm arx[2:0] 16 international control 1 off/ sql2 ohs act dct[1:0] rz rt 17 international control 2 mcal cald lim ope bte rov btd 18 international control 3 full dial fjm vol flvm mode rfwe sqlh 19 international control 4 lvcs[4:0] ovl dod opd
si3016 rev. 1.0 27 reset settings = 0000_0000 reset settings = 0000_0011 register 1. control 1 bit d7d6d5d4d3d2d1d0 name sr dl type r/w r/w bit name function 7sr software reset. 0 = enables chip for normal operation. 1 = sets all registers to their reset value. note: bit will automatically clear after being set. 6:2 reserved read returns zero. 1dl isolation digital loopback. 0 = digital loopback across isolation barrier disabled. 1 = enables digital loopback mode across isolation barrier. the line side must be enabled prior to setting this mode. 0 reserved read returns zero. register 2. control 2 bit d7d6d5d4d3d2d1d0 name al hbe rxe type r/w r/w r/w bit name function 7:4 reserved read returns zero. 3al analog loopback. 0 = analog loopback mode disabled. 1 = enables external analog loopback mode. 2 reserved read returns zero. 1hbe hybrid enable. 0 = disconnects hybrid in transmit path. 1 = connects hybrid in transmit path. 0rxe receive enable. 0 = receive path disabled. 1 = enables receive path.
si3016 28 rev. 1.0 reset settings = 0000_0000 reset settings = 0000_0000 register 3. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. register 4. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero.
si3016 rev. 1.0 29 reset settings = 0000_0000 register 5. daa control 1 bit d7d6d5d4d3d2d1d0 name rdtn rdtp onhm rdt oh type rr r/wr r/w bit name function 7 reserved read returns zero. 6 rdtn ring detect signal negative. 0 = no negative ring signal is occurring. 1 = a negative ring signal is occurring. 5rdtp ring detect signal positive. 0 = no positive ring signal is occurring. 1 = a positive ring signal is occurring. 4 reserved read returns zero. 3onhm on-hook line monitor. 0 = normal on-hook mode. 1 = enables low-power monitoring mode allowing the dsp to re ceive line activity without going off-hook. this mode is used for caller-id detection. when mode bit = 1 (register 18, bit 2), the device consumes ~7 a from the phone line when in on-hook line monitor mode. when mode = 0, the device consumes ~450 a from the phone line when in on-hook line monitor mode. note: this bit should be cleared before setting the oh bit. 2 rdt ring detect. 0 = reset either 4.5?9 seconds after last positiv e ring is detected or when the system exe- cutes an off-hook. 1 = indicates a ring is occurring. 1 reserved read returns zero. 0oh off-hook. 0 = line-side device on-hook. 1 = causes the line-side chip to go off-hook. th is bit operates independently of the ohe bit and is a logic or with the off-hook pin when enabled. when the mode bit (register 12, bit 2) is set to 1, the device will go on-hook without enabling the off-h ook counter, thus allowing the device to go immediately (i.e., no timeout required on the counter) back off-hook when the mode bit is cleared. this is usef ul in supporting type ii caller id. note: the onhm bit should be cleared before setting this bit.
si3016 30 rev. 1.0 reset settings = 0111_0000 register 6. daa control 2 bit d7d6d5d4d3d2d1d0 name atm[1] arm[1] pdl pdn atm[0] arm[0] type r/w r/w r/w r/w r/w r/w bit name function 7 reserved read returns zero. 6,1 atm[1:0] aout transmit pa th level control. 00 = ?26 db transmit path attenuation for call progress aout pin only. 01 = ?20 db transmit path attenuation for call progress aout pin only. 10 = mutes transmit path for call progress aout pin only. 11 = ?32 db transmit path attenuation for call progress aout pin only. 5,0 arm[1:0] aout receive path level control. 00 = ?6 db receive path attenuation for call progress aout pin only. 01 = 0 db receive path attenuation for call progress aout pin only. 10 = mutes receive path for call progress aout pin only. 11 = ?12 db receive path attenuation for call progress aout pin only. 4pdl powerdown line-side chip. 0 = normal operation. program the clock generator before clearing this bit. 1 = places the si3016 in lower power mode. 3pdn powerdown. 0 = normal operation. 1 = powers down the system-side module. an internal reset to the system-side module is required to restore normal operation. 2 reserved read returns zero. register 7. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero.
si3016 rev. 1.0 31 reset settings = 0000_0000 register 8. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. register 9. sample rate control bit d7d6d5d4d3d2d1d0 name src[2:0] type r/w bit name function 7:3 reserved read returns zero. 2:0 src[2:0] sample rate control. this 3-bit value controls the sampling rate of the daa. 000 = 7200 hz. 001 = 8000 hz. 010 = 8229 hz. 011=8400hz. 100 = 9000 hz. 101 = 9600 hz. 110 = 10286 hz. 111 = reserved. register 10. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero.
si3016 32 rev. 1.0 reset settings = n/a reset settings = n/a register 11. chip a revision bit d7d6d5d4d3d2d1d0 name reva[3:0] type r bit name function 7:4 reserved read returns zero. 3:0 reva[3:0] chip a revision. four-bit value indicating the revision of the integrated system-side module. register 12. line side status bit d7d6d5d4d3d2d1d0 name cle fdt lcs[3:0] type r/w r r bit name function 7cle communications (isolation link) error. 0 = communication link between the integrated system-side module and si3016 is operating correctly. 1 = indicates a communication pr oblem between the integrated system-side module and the si3016. when it goes high, it remains high until a logic 0 is written to it. 6fdt frame detect. 0 = indicates link has not established frame lock. 1 = indicates link frame lock has been established. 5:4 reserved read returns zero. 3:0 lcs[3:0] loop current sense. four-bit value returning the loop current. it is decoded from th e lvcs bits. see lvcs bits for line voltage and current monitoring. when off-hook, these bits are decoded as follows from lvcs[4:0]: lcs[3:0] = lvcs[4:1] except when lvcs[4:0] = 11110, lcs[3:0] = 1110 or when lvcs[4:0] = 00001, lcs[3:0] = 0001. when on-hook, lcs[3:0] = lvcs[4:1].
si3016 rev. 1.0 33 reset settings = n/a register 13. chip b revision bit d7d6d5d4d3d2d1d0 name cbid revb[3:0] arxb atxb type rrr/wr/w bit name function 7 reserved read returns zero. 6cbid chip b id. 0 = indicates the line side is domestic only. 1 = indicates the line side has international support. 5:2 revb[3:0] chip b revision. four-bit value indicating the revision of the si3016 (line-side) chip. 1arxb receive gain. 0 = 0 db gain is applied. 1 = a 6 db gain is applied to the receive path. note: this bit should not be used. the si3016 has the additional receive gain settings arx[2:0]. arxb should be set to 0 and the arx bits should be used. 0atxb transmit attenuation. 0 = 0 db gain is applied. 1 = a 3 db attenuation is applied to the transmit path. note: this bit should not be used. the si3016 has the additional transmit gain settings atx[2:0]. atxb should be set to 0 and the atx bits should be used.
si3016 34 rev. 1.0 reset settings = 0000_0100 register 14. line side validation bit d7d6d5d4d3d2d1d0 name chk cip safe type rrr bit name function 7:3 reserved read returns zero. 2chk line-side chip verification performed. when the line-side device is first enabled, an auto matic safety check is performed internally to ensure that it is the correct device. 0 = a check has been performed on the line-side chip to ensure that it is the proper device. 1 = a check has not yet been performed on the line-side device to ensure that it is the proper device. 1cip line-side chip verification in progress 0 = the line-side device check is not in progress. 1 = the line-side device check is currently in progress. 0 safe line-side chip verification result. this bit is only valid after a line side verification check has been performed. thus, the chk and cip bits should be clear when this bit is read. 0 = a correct line-side device was detected. chip operation is normal. 1 = an incorrect line-side device was detected . the integrated system-side module will not function properly. re gister accesses can still be performe d, but data transfer will not occur.
si3016 rev. 1.0 35 reset settings = 0000_0000 register 15. tx /rx gain control bit d7d6d5d4d3d2d1d0 name txm atx[2:0] rxm arx[2:0] type r/w r/w r/w r/w bit name function 7txm transmit mute. 0 = transmit signal is not muted. 1 = mutes the transmit signal. 6:4 atx[2:0] analog transmit attenuation. 000 = 0 db attenuation. 001 = 3 db attenuation. 010 = 6 db attenuation. 011 = 9 db attenuation. 1xx = 12 db attenuation. note: the atxb bit must be 0 if these bits are used. 3rxm receive mute. 0 = receive signal is not muted. 1 = mutes the receive signal. 2:0 arx[2:0] analog receive gain/on-hook line monitor receive attenuation. this register functions as both a gain setting for the regular daa receive path and an attenua- tion setting for the new low-power on-hook line monitor adc receive path. receive gain on-hook line monitor attenuation 000 = 0 db gain. 000 = 0 db attenuation. 001 = 3 db gain. 001 = 1 db attenuation. 010 = 6 db gain. 010 = 2.2 db attenuation. 011 = 9 db gain. 011 = 3.5 db attenuation. 1xx = 12 db gain. 1xx = 5 db attenuation. note: the arxb bit must be 0 if these bits are used.
si3016 36 rev. 1.0 reset settings = 0000_1000 register 16. inte rnational control 1 bit d7d6d5d4d3d2d1d0 name off/sql2 ohs act dct[1:0] rz rt type r/w r/w r/w r/w r/w r/w bit name function 7off/sql2 dc termination off (daa is off-hook). when the daa is off-hook, this bit functions as the dc termination off bit. when the daa is on-hook, this bit functions as the enh anced ring detect network squelch bit. 0 = normal operation. 1 = dc termination disabled and the device presents an 800 dc impedance to the line which is used to enhance operation with a parallel phone. the dct pin voltage is also reduced for improved low line voltage performance. enhanced ring detect network squelch (daa is on-hook). to properly receive caller id data, this bit must be set following a polarity reversal or ring sig- nal detection and must be left enabled during t he reception of caller id data. it should be dis- abled before the start of the next ring signal. it is used to recover the offset on the rng1/2 pins after a polarity reversal or ring signal. 0 = normal operation. 1 = enhanced squelch function is enabled. 6ohs on-hook speed. 0 = the si3016 will execute a fast on-hook. (off-hook counter = 1024/fs seconds.) 1 = the si3016 will execute a slow, contro lled on-hook. (off- hook counter = 4096/fs seconds.) 5act ac termination select. 0 = selects the real impedance. 1 = selects the complex impedance. 4 reserved read returns zero. 3:2 dct[1:0] dc termination select. 00 = low voltage mode. (transmit level = ?5 dbm). 01 = japan mode. lower voltage mode. (transmit level = ?3 dbm). 10 = fcc mode. standard voltage mode. (transmit level = ?1 dbm). 11 = ctr21 mode. current limiting mode. (transmit level = ?1 dbm). 1rz ringer impedance. 0 = maximum (high) ringer impedance. 1 = synthesized ringer impedance. c15, r14, z2, and z3 must not be installed when setting this bit. see "4.12. ringer impedance" on page 18. 0rt ringer threshold select. used to satisfy country requirements on ring de tection. signals below the lower level will not generate a ring detection; signals above t he upper level are guaranteed to generate a ring detection. 0 = 11 to 22 v rms 1 = 17 to 33 v rms
si3016 rev. 1.0 37 reset settings = 0000_0000 register 17. inte rnational control 2 bit d7d6d5d4d3d2d1d0 name mcal cald lim ope bte rov btd type r/w r/w r/w r/w r/w r/w r/w bit name function 7 reserved must be zero. 6mcal manual calibration. 0 = no calibration. 1 = initiate calibration. 5cald auto-calibration disable. 0 = enable auto-calibration. 1 = disable auto-calibration. 4lim current limit this bit only affects chip operation when the ctr21 dc termination mode is selected. 0 = no current limiti ng in ctr21 mode. 1 = enables current limiting in ctr21 mode. the dc terminati on will current limit before 60 ma. 3ope overload protect enable. 0 = disable overload protection. 1 = enable overload protection. the overload protection feat ure prevents damage to the daa when going off-hook with excessive line current or voltage. when off-hook, if ope is set and lvcs = 11111, the dc ter- mination is disabled (800 presented to the line), the hookswitch current is reduced, and the opd bit is set. the ope bit should be written ~25 ms after going off-hook; it should be written to 0 to reset. 2bte billing tone protect enable. 0 = disabled. 1 = enabled. when set, the si3016 will automatically respond to a collapse of the line-derived power supply during a billing tone event. when off-hook, if bte = 1 and btd goes high , the dc termination is changed to present 800 to the line, and the dct pin stops tracking the receive input pin. during normal operation, the dct pin tracks the receive input. 1rov receive overload. this bit is set when the receive input has an excessive input level (i.e., receive pin goes below ground). this bit is cleared by writing a zero to this location. 0 = normal receive input level. 1 = excessive receive input level. 0btd billing tone detected. this bit will be set if a billing tone is detected. this bit is cleared by writing a zero to this loca- tion. 0 = no billing tone detected. 1 = billing tone detected.
si3016 38 rev. 1.0 reset settings = 0000_0000 register 18. inte rnational control 3 bit d7d6d5d4d3d2d1d0 name full dial fjm vol flvm mode rfwe sqlh type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7full full scale. 0=default. 1 = transmit/receive full scale = +3.2 dbm. this bit changes the full scale of the adc and dac from ?1 dbm min to +3.2 dbm min. when this bit is set, r2 must be changed from 402 to 243 . this mode can be useful for certain voice applications and should only be used in the fcc/600 ac termination mode. 6dial dtmf dialing mode. this bit should be set during dtmf dialing in ctr21 mode if lcs[3:0] < 6 or lvcs[4:0] < 12 decimal. 0 = normal operation. 1 = increase headroom for dtmf dialing. 5fjm force japan dc termination mode. 0=normal gain 1 = when the dct[1:0] bits are set to 10b (fcc m ode), setting this bit will force the japan dc ter- mination mode while allo wing for a transmit level of ?1 dbm. see "4.13. dtmf dialing" on page 19. 4vol line voltage adjust. when set, this bit will adjust the tip-ring line voltage. lowering this voltage will improve margin in low-voltage countries. raising this voltage may improve large signal distortion performance. 0 = normal operation. 1 = lower dct voltage. description dct off vol vdct delta ctr21/fcc 1x 0 0 4.00 ctr21/fcc+vol 1013.510.49v japan 01 0 0 3.15 japan+vol 01 0 1 2.87 0.28 v lvmode 00 0 0 2.65 lvmode+vol 00 0 1 2.47 0.18 v ctr21/fcc+off 1x 1 0 2.33 ctr21/fcc+vol+off 1x 1 1 2.21 0.12 v japan+off 01 1 0 2.10 japan+vol+off 01 1 1 2.01 0.09 v lvmode+off 00 1 0 1.94 lvmode+vol+off 00 1 1 1.87 0.07 v
si3016 rev. 1.0 39 3flvm force low voltage dc termination mode. 0 = normal gain. 1 = when the dct[1:0] bits are set to 10b (fcc mode), setting this bit will force the low voltage dc termination mode while allowing for a transmit level of ?1 dbm. see "4.13. dtmf dialing" on page 19. 2mode mode control. this bit is used to enable the on-hook line monitor adc and the line voltage monitor. mode oh onhm line function sdo lvcs[4:0] 0 0 0 on-hook ring data 0 0 0 1 on-hook line data using 11111 if a line the higher voltage current line exists, or monitor 00000 if no line voltage exists 0 1 0 off-hook line data loop current 0 1 1 off-hook/fast dct mode line data loop current 1 0 0 on-hook ring data line voltage 1 0 1 on-hook line data using line voltage the low current line monitor 1 1 0 force on-hook no data is line voltage transmitted on sdo in this mode 1 1 1 force on-hook line data using line voltage the low current line monitor notes: 1. if rz = 1, lvcs[4:0] = either 11111 or 00000 during a ring ev ent. all ones are shown if a line voltage exists; all zeroes are shown if no line voltage exists. 2. force on-hook mode puts the si3016 into an on-hook state wi thout restarting the off-hook counter. this is used to support type ii caller id. 3. the mode bit is in a different register than the oh an d onhm bits. the user should write the registers in a sequence so as not to pass through an undesired state. 4. fast dct mode puts the si3016 into an off-hook state that is intended to quickly settle the line voltage just after going off-hook. while in this mode, data transmission is no t recommended. this is used to support type ii caller id. 5. the onhm bit should be cleared before setting the oh bit. if both bits need to be set, the oh bit should be set first, and then the onhm bit should be set in a separate register access. 1rfwe ring detector full wave rectifier enable. when set, the ring detection circ uitry provides full-wave rectification. this will affect the rgdt pin as well as the data stream presented on sdo during ring detection. 0 = half wave. 1 = full wave. 0sqlh ring detect network squelch. this bit must be set, then cleared after at least 1 ms, following a polarity reversal or ring signal detection. it is used to quickly recover the offset on the rng1/2 pins after a polarity reversal or ring signal. if the sql2 bit is enabled during cid data reception, this bit should not be used. 0 = normal operation. 1 = squelch function is enabled. bit name function
si3016 40 rev. 1.0 reset settings = 0000_0000 register 19. inte rnational control 4 bit d7d6d5d4d3d2d1d0 name lvcs [4:0] ovl dod opd type rrrr bit name function 7:3 lvcs[4:0] line voltage/current sense. represents either the line voltage, loop current, or on-hook line monitor depending on the state of the mode, oh, and onhm bits. on-hook voltage monitor (2.75 v/bit). 00000 = no line connected. 00001 = minimum line voltage (v min =3v 0.5v). 11111 = maximum line voltage (87 v 20%). the line voltage monitor full scale may be modified by changing r5 as follows: v max =v min + 4.2 (10m + r5 + 1.6 k)/[(r5 +1.6 k)*5] off-hook loop current monitor (3 ma/bit). 00000 = loop current is less than required for normal operation. 00001 = minimum normal loop current. 11110 = maximum normal loop current. 11111 = loop current is excessive (overload). overload > 140 ma in all modes except ctr21. overload > 54 ma in ctr21 mode. 2ovl overload detected. this bit has the same function as rov in regist er 17 but will clear itself after the overload has been removed. see "4.15. billin g tone detection" on page 19. th is bit is only masked by the off-hook counter and is not affected by the bte bit. 0 = normal receive input level. 1 = excessive receive input level. 1dod recal/dropout detect. when the line-side device is off-hook, it is powered from the line itse lf. if this line-derived power supply collapses, such as when the line is disconnected, this bit is set to 1. sixteen frames (16/fs) after the line-derived power supply returns, this bit is set to 0. when on-hook, this bit is set to 0. 0 = normal operation. 1 = line supply dropout detected when on-hook. 0opd overload protect detected. 0 = inactive. 1 = overload protection active. note: see description of overload protect operation (ope bit).
si3016 rev. 1.0 41
si3016 42 rev. 1.0 a ppendix a?ul1950 3 rd e dition although designs using the si3016 comply with ul1950, 3rd edition, and pass all overcurrent and overvoltage tests, there are still several issues to consider. figure 16 shows two designs that can pass the ul1950 overvoltage tests, as well as electromagnetic emissions. the top schematic of figure 16 shows the configuration in which the ferrite beads (fb1, fb2) are on the unprotected side of the sidactor (rv1). for this configuration, the current rating of the ferrite beads needs to be 6 a. however, the higher current ferrite beads are less effective in reducing electromagnetic emissions. the bottom schematic of figure 16 shows the configuration in which the ferrite beads (fb1, fb2) are on the protected side of the sidactor (rv1). for this design, the ferrite beads can be rated at 200 ma. in a cost-optimized design, it is important to remember that compliance to ul1950 does not always require overvoltage tests. it is best to plan ahead and know which overvoltage tests will apply to your system. system-level elements in th e construction, such as fire enclosure and spacing requirements, need to be considered during the design stages. consult with your professional testing agency during the design of the product to determine which tests apply to your system. figure 16. circuits that pass all ul1950 overvoltage tests fb1 fb2 tip ring 1.25 a rv1 c25 c24 75 @ 100 mhz, 6 a fb1 fb2 tip ring 1.25 a rv1 600 @ 100 mhz, 200 ma 75 @ 100 mhz, 6 a 600 @ 100 mhz, 200 ma c24 c25
si3016 rev. 1.0 43 a ppendix b?cispr22 c ompliance various countries are expected to adopt the iec cispr22 standard over the next few years. for example, the european union (eu) has adopted a standard entitled en55022, which is based on the cispr22 standard. adherence to this standard will be necessary to displa y the ce mark on designs intended for sale in the eu. the typical schematic and global bill of materials (bom) (see figure 6 and table 7) contained in this data sheet are designed to be compliant to the cispr22 standard. if smaller inductors are desired, a notch filter may be used and compliance to cispr22 still achieved. as shown in figure 17, a seri es capacitor-resistor in parallel with l1 and l2 forms the simple notch filter. table 14 shows corresponding values used for c24, c25, c38, c39, l1, l2, r31, and r32. figure 17. notch filter for cispr22 compliance the direct current resistance (dcr) of the listed inductors is an important co nsideration. if the dcr of the inductors used is less than 3 each, then country ptt specifications which require 300 or less of dc resistance at tip and ring with 20 ma of loop current can be satisfied with the japan dc termination mode. if the dcr of the inductors is at or slightly above 3 , the low-voltage termination mode may need to be used to satisfy the 300 dc resistance requirement at 20 ma of loop current. in all cases, "4.9. dc termination considerations" on page 17 should be followed. if compliance to the cispr22 standard and certain other country ptt requirements are not desired, then l1 and l2 may be removed. if these inductors are removed, c24 and c25 should be increased to 2200 pf, and c9 should be changed to 22 nf, 250 v. with these changes, ptt compliance in the following countries will not be achieved: india (i/fax -03/03 standard), taiwan (id0001 standard), chile (decree no. 220 1981 standard), and argentina (cnc-st2-44.01 standard). for questions concerning compliance to cispr22 or other relevant standards, co ntact a silicon laboratories technical representative. table 14. notch filter component values c24/c25 c38/c39 l1/l2 r31/r32 1000pf 33pf, 50 v 150 h, dcr <3 , i >120ma 680 , 1/10 w c38 c24 l1 r31 fb1 tip to daa c39 c25 l2 r32 fb2 ring
si3016 44 rev. 1.0 6. pin descriptions: si3016 table 15. si3016 pin descriptions pin # pin name description 1qe2 transistor emitter 2. connects to the emitter of q4. 2 dct dc termination. provides dc termination to the telephone network. 3ignd isolated ground. connects to ground on the line-side interface. also connects to capacitor c2. 4c1b isolation capacitor 1b. connects to one side of isolation capacito r c1. used to communicate with the system- side module. 5rng1 ring 1. connects through a capacitor to the tip lead of the telephone line. provides the ring and caller id signals to the si3016. 6rng2 ring 2. connects through a capacitor to the ring le ad of the telephone line. provides the ring and caller id signals to the si3016. 7qb transistor base. connects to the base of transistor q3. used to go on/off-hook. 8qe transistor emitter. connects to the emitter of transistor q3. used to go on/off-hook. 9vreg voltage regulator. connects to an external capacitor to provide bypassing for an internal power supply. 10 vreg2 voltage regulator 2. connects to an external capacitor to provide bypassing for an internal power supply. 11 ref reference. connects to an external resistor to provide a high-accuracy reference current. 12 rext2 external resistor 2. sets the complex ac termination impedance. 13 rext external resistor. sets the real ac termination impedance. 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 qe2 dct ignd c1b rng1 rng2 qb qe filt2 filt rx rext rext2 ref vreg2 vreg
si3016 rev. 1.0 45 14 rx receive input. serves as the receive side input from the telephone network. 15 filt filter. provides filtering for the dc termination circuits. 16 filt2 filter 2. provides filtering for the bias circuits. table 15. si3016 pin descriptions (continued) pin # pin name description
si3016 46 rev. 1.0 7. ordering guide part number package pb-free temp range si3016-ks 16-pin soic no 0 to 70 c SI3016-F-FS 16-pin soic yes 0 to 70 c si3016-bs 16-pin soic no ?40 to 85 c
si3016 rev. 1.0 47 8. package outline: soic figure 18 illustrates the package details for the si3016. table 16 lists the valu es for the dimensions shown in the illustration. figure 18. 16-pin small outline integrated circuit (soic) package table 16. package diagram dimensions symbol millimeters min max a 1.35 1.75 a1 .10 .25 a2 1.30 1.50 b.33.51 c.19.25 d 9.80 10.01 e 3.80 4.00 e 1.27 bsc ? h 5.80 6.20 h.25.50 l .40 1.27 l1 1.07bsc ? ?0.10 0o 8o e h a1 b c h l e see detail f detail f a 16 9 8 1 ga uge pl a ne 0.010 d a2 seating plane l1
si3016 48 rev. 1.0 d ocument c hange l ist revision 0.2 to revision 0.3 ? pages 9-10: updated schematic and bom. ? page 16: updated figure 13. ? page 44: added appendix b revision 0.3 to revision 0.41 ? table 9 updated. ? ?appendix b?cispr22 compliance? updated. ? the ?ringer impedance network? figure and the ?component values?optional ringer impedance network? table were deleted from the ?ringer impedance?section as well as a paragraph discussing czech republic designs. ? the ?dongle applications circuit? figure was deleted. revision 0.41 to revision 0.42 ? page 1: updated features list. ? table 2, page 5: revised note 3. ? page 12: added single-channel information to functional description. revision 0.42 to revision 0.44 ? table 3 on page 6 updated. ? page 26: removed sb from register 1, bit 0. ? register 1, bit 0: removed sb and description from register. ? register 5, bits 6,1 and 5,0: revised transmit path attenuation transmit and receive controls. revision 0.44 to revision 1.0 ? updated "7. ordering guide" on page 46. ? updated "4.27. revision identification" on page 25.
si3016 rev. 1.0 49 n otes :
si3016 50 rev. 1.0 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: sidaainfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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