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octal, 12-/14-/16-bit spi voltage output densedac with 5 ppm/c on-chip reference ad5628/ad5648/ad5668 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2011 analog devices, inc. all rights reserved. features low power, small footprint, pin-compatible octal dacs ad5668: 16 bits ad5648: 14 bits ad5628: 12 bits 14-lead/16-lead tssop and 16-lead lfcsp on-chip 1.25 v/2.5 v, 5 ppm/c reference power down to 400 na @ 5 v, 200 na @ 3 v 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to zero scale or midscale 3 power-down functions hardware ldac and ldac override function clr function to programmable code rail-to-rail operation applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagram interface logic input register din ldac gnd v out h v dd ldac 1 v refin / v refout sync sclk ad5628/ad5648/ad5668 clr 1 1 ru-16 package only 1.25v/2.5v ref v out a v out b v out c v out d v out e v out f v out g dac register string dac a buffer input register dac register string dac b buffer input register dac register string dac c buffer input register dac register string dac d buffer input register dac register string dac e buffer input register dac register string dac f buffer input register dac register string dac g buffer input register dac register string dac h buffer power-down logic power-on reset 05302-001 figure 1. general description the ad5628/ad5648/ad5668 devices are low power, octal, 12-/14-/16-bit, buffered voltage-output dacs. all devices operate from a single 2.7 v to 5.5 v supply and are guaranteed monotonic by design. the ad5668 and ad5628 are available in both a 4 mm 4 mm lfcsp and a 16-lead tssop, while the ad5648 is available in both a 14-lead and 16-lead tssop. the ad5628/ad5648/ad5668 have an on-chip reference with an internal gain of 2. the ad5628-1/ad5648-1/ad5668-1 have a 1.25 v 5 ppm/c reference, giving a full-scale output range of 2.5 v; the ad5628-2/ad5648-2/ad5668-2 and ad5668-3 have a 2.5 v 5 ppm/c reference, giving a full-scale output range of 5 v. the on-board reference is off at power-up, allowing the use of an external reference. the internal reference is enabled via a software write. the part incorporates a power-on reset circuit that ensures that the dac output powers up to 0 v (ad5628-1/ad5648-1/ad5668-1, ad5628-2/ad5648-2/ad5668-2) or midscale (ad5668-3) and remains powered up at this level until a valid write takes place. the part contains a power-down feature that reduces the current consumption of the device to 400 na at 5 v and provides software- selectable output loads while in power-down mode for any or all dac channels. the outputs of all dacs can be updated simul- taneously using the ldac function, with the added functionality of user-selectable dac channels to simultaneously update. there is also an asynchronous clr that updates all dacs to a user- programmable codezero scale, midscale, or full scale. the ad5628/ad5648/ad5668 utilize a versatile 3-wire serial interface that operates at clock rates of up to 50 mhz and is compatible with standard spi?, qspi?, microwire?, and dsp interface standards. the on-chip precision output amplifier enables rail-to-rail output swing. product highlights 1. octal, 12-/14-/16-bit dac. 2. on-chip 1.25 v/2.5 v, 5 ppm/c reference. 3. available in 14-lead/16-lead tssop and 16-lead lfcsp. 4. power-on reset to 0 v or midscale. 5. power-down capability. when powered down, the dac typically consumes 200 na at 3 v and 400 na at 5 v.
ad5628/ad5648/ad5668 rev. e | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? ac characteristics........................................................................ 6 ? timing characteristics ................................................................ 7 ? absolute maximum ratings............................................................ 8 ? esd caution.................................................................................. 8 ? pin configurations and function descriptions ........................... 9 ? typical performance characteristics ........................................... 10 ? terminology .................................................................................... 18 ? theory of operation ...................................................................... 20 ? d/a section................................................................................. 20 ? resistor string............................................................................. 20 ? internal reference ...................................................................... 20 ? output amplifier........................................................................ 21 ? serial interface ............................................................................ 21 ? input shift register .................................................................... 22 ? sync interrupt .......................................................................... 22 ? internal reference register....................................................... 23 ? power-on reset.......................................................................... 23 ? power-down modes .................................................................. 23 ? clear code register ................................................................... 23 ? ldac function .......................................................................... 25 ? power supply bypassing and grounding................................ 25 ? outline dimensions ....................................................................... 26 ? ordering guide .......................................................................... 28 ? revision history 1/11rev. d to rev. e changes to ad5628 relative accuracy, zero-code error, offset error, and reference tc parameters, table 1............................... 3 changes to ad5628 relative accuracy, zero-code error, offset error, and reference tc parameters, table 2............................... 5 changes to output voltage settling time, table 3 ...................... 6 added figure 53; renumbered sequentially .............................. 17 change to output amplifier section........................................... 21 changes to ordering guide .......................................................... 28 9/10rev. c to rev. d change to title.................................................................................. 1 added 16-lead lfcsp throughout ................................universal changes to table 1............................................................................ 3 changes to table 2............................................................................ 5 changes to table 3............................................................................ 6 changes to table 4............................................................................ 7 deleted snpb from table 5.............................................................. 8 added figure 5; renumbered sequentially .................................. 9 changes to table 6............................................................................ 9 replaced typical performance characteristics section ............ 10 changes to power-on reset section............................................ 23 updated outline dimensions ....................................................... 26 changes to ordering guide .......................................................... 28 1/10rev. b to rev. c changes to figure 3........................................................................ 10 changes to ordering guide .......................................................... 28 2/09rev. a to rev. b changes to reference current parameter, table 1........................3 changes to i dd (normal mode) parameter, table 1......................4 changes to reference current parameter, table 2........................5 changes to i dd (normal mode) parameter, table 2......................6 11/05rev. 0 to rev. a change to specifications ..................................................................3 10/05revision 0: initial version
ad5628/ad5648/ad5668 rev. e | page 3 of 28 specifications v dd = 4.5 v to 5.5 v, r l = 2 k to gnd, c l = 200 pf to gnd, v refin = v dd . all specifications t min to t max , unless otherwise noted. table 1. a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments static performance 2 ad5628 resolution 12 12 bits relative accuracy 0.5 4 0.5 1 lsb see figure 8 differential nonlinearity 0.25 0.25 lsb guaranteed monotonic by design (see figure 11 ) ad5648 resolution 14 14 bits relative accuracy 2 8 2 4 lsb see figure 7 differential nonlinearity 0.5 0.5 lsb guaranteed monotonic by design (see figure 10 ) ad5668 resolution 16 16 bits relative accuracy 8 32 8 16 lsb see figure 6 differential nonlinearity 1 1 lsb guaranteed monotonic by design (see figure 9 ) zero-code error 6 19 6 19 mv all 0s loaded to dac register (see figure 25 ) zero-code error drift 2 2 v/c full-scale error ?0.2 ?1 ?0.2 ?1 % fsr all 1s loaded to dac register (see figure 26 ) gain error 1 1 % fsr gain temperature coefficient 2.5 2.5 ppm of fsr/c offset error 6 19 6 19 mv dc power supply rejection ratio C80 C80 db v dd 10% dc crosstalk (external reference) 10 10 v due to full-scale output change, r l = 2 k to gnd or v dd 5 5 v/ma due to load current change 10 10 v due to powering down (per channel) dc crosstalk (internal reference) 25 25 v due to full-scale output change, r l = 2 k to gnd or v dd 10 10 v/ma due to load current change output characteristics 3 output voltage range 0 v dd 0 v dd v capacitive load stability 2 2 nf r l = 10 10 nf r l = 2 k dc output impedance 0.5 0.5 short-circuit current 30 30 ma v dd = 5 v power-up time 4 4 s coming out of power-down mode, v dd = 5 v reference inputs reference current 40 55 40 55 a v ref = v dd = 5.5 v (per dac channel) reference input range 0 v dd 0 v dd v reference input impedance 14.6 14.6 k reference output output voltage ad56x8-2, ad56x8-3 2.495 2.505 2.495 2.505 v at ambient reference tc 3 5 10 5 10 ppm/c tssop 15 5 10 ppm/c lfcsp reference output impedance 7.5 7.5 k
ad5628/ad5648/ad5668 rev. e | page 4 of 28 a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments logic inputs 3 input current 3 3 a all digital inputs input low voltage, v inl 0.8 0.8 v v dd = 5 v input high voltage, v inh 2 2 v v dd = 5 v pin capacitance 3 3 pf power requirements v dd 4.5 5.5 4.5 5.5 v all digital inputs at 0 or v dd , dac active, excludes load current i dd (normal mode) 4 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 1.0 1.5 1.0 1.5 ma internal reference off v dd = 4.5 v to 5.5 v 1.8 2.25 1.7 2.25 ma internal reference on i dd (all power-down modes) 5 v dd = 4.5 v to 5.5 v 0.4 1 0.4 1 a v ih = v dd and v il = gnd 1 temperature range is ?40c to +105c, typi cal at 25c. 2 linearity calculated using a reduced code range of ad5628 (code 32 to code 4064), ad5648 (code 128 to code 16,256), and ad5668 (code 512 to 65,024). output unloaded. 3 guaranteed by design and characterization; not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all eight dacs powered down.
ad5628/ad5648/ad5668 rev. e | page 5 of 28 v dd = 2.7 v to 3.6 v, r l = 2 k to gnd, c l = 200 pf to gnd, v refin = v dd . all specifications t min to t max , unless otherwise noted. table 2. a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments static performance 2 ad5628 resolution 12 12 bits relative accuracy 0.5 4 0.5 1 lsb see figure 8 differential nonlinearity 0.25 0.25 lsb guaranteed monotonic by design (see figure 11 ) ad5648 resolution 14 14 bits relative accuracy 2 8 2 4 lsb see figure 7 differential nonlinearity 0.5 0.5 lsb guaranteed monotonic by design (see figure 10 ) ad5668 resolution 16 16 bits relative accuracy 8 32 8 16 lsb see figure 6 differential nonlinearity 1 1 lsb guaranteed monotonic by design (see figure 9 ) zero-code error 6 19 6 19 mv all 0s loaded to dac register (see figure 25 ) zero-code error drift 2 2 v/c full-scale error ?0.2 ?1 ?0.2 ?1 % fsr all 1s loaded to dac register (see figure 26 ) gain error 1 1 % fsr gain temperature coefficient 2.5 2.5 ppm of fsr/c offset error 6 19 6 19 mv dc power supply rejection ratio 3 C80 C80 db v dd 10% dc crosstalk 3 (external reference) 10 10 v due to full-scale output change, r l = 2 k to gnd or v dd 5 5 v/ma due to load current change 10 10 v due to powering down (per channel) dc crosstalk 3 (internal reference) 25 25 v due to full-scale output change, r l = 2 k to gnd or v dd 10 10 v/ma due to load current change output characteristics 3 output voltage range 0 v dd 0 v dd v capacitive load stability 2 2 nf r l = 10 10 nf r l = 2 k dc output impedance 0.5 0.5 short-circuit current 30 30 ma v dd = 3 v power-up time 4 4 s coming out of power-down mode, v dd = 3 v reference inputs reference current 40 55 40 55 a v ref = v dd = 5.5 v (per dac channel) reference input range 0 v dd 0 v dd reference input impedance 14.6 14.6 k reference output output voltage ad5628/ad5648/ad5668-1 1.247 1.253 1.247 1.253 v at ambient reference tc 3 5 15 5 15 ppm/c tssop 15 5 15 ppm/c lfcsp reference output impedance 7.5 7.5 k
ad5628/ad5648/ad5668 rev. e | page 6 of 28 a grade 1 b grade 1 parameter min typ max min typ max unit conditions/comments logic inputs 3 input current 3 3 a all digital inputs input low voltage, v inl 0.8 0.8 v v dd = 3 v input high voltage, v inh 2 2 v v dd = 3 v pin capacitance 3 3 pf power requirements v dd 2.7 3.6 2.7 3.6 v all digital inputs at 0 or v dd , dac active, excludes load current i dd (normal mode) 4 v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 1.0 1.5 1.0 1.5 ma internal reference off v dd = 2.7 v to 3.6 v 1.8 2.25 1.7 2.25 ma internal reference on i dd (all power-down modes) 5 v dd = 2.7 v to 3.6 v 0.2 1 0.2 1 a v ih = v dd and v il = gnd 1 temperature range is ?40c to +105c, typi cal at 25c. 2 linearity calculated using a reduced code range of ad5628 (code 32 to code 4064), ad 5648 (code 128 to code 16256), and ad5668 (code 512 to 65024). output unloaded. 3 guaranteed by design and characterization; not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all eight dacs powered down. ac characteristics v dd = 2.7 v to 5.5 v, r l = 2 k to gnd, c l = 200 pf to gnd, v refin = v dd . all specifications t min to t max , unless otherwise noted. table 3. parameter 1 , 2 min typ max unit conditions/comments 3 output voltage settling time 2.5 7 s ? to ? scale settling to 2 lsb (16-bit resolution) slew rate 1.2 v/s digital-to-analog glitch impulse 4 nv-s 1 lsb(16-bit resolution) change around major carry (see figure 41 ) 19 nv-s from code 0xea00 to code 0xe9ff (16-bit resolution) digital feedthrough 0.1 nv-s digital crosstalk 0.2 nv-s analog crosstalk 0.4 nv-s dac-to-dac crosstalk 0.8 nv-s multiplying bandwidth 320 khz v ref = 2 v 0.2 v p-p total harmonic distortion ?80 db v ref = 2 v 0.1 v p-p, frequency = 10 khz output noise spectral density 120 nv/hz dac code = 0x8400(16-bit resolution), 1 khz 100 nv/hz dac code = 0x8400(16-bit resolution), 10 khz output noise 12 v p-p 0.1 hz to 10 hz, dac code = 0x0000 1 guaranteed by design and characterization; not production tested. 2 see the terminology section. 3 temperature range is ?40c to +105c, typi cal at 25c.
ad5628/ad5648/ad5668 rev. e | page 7 of 28 timing characteristics all input signals are specified with tr = tf = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 2 . v dd = 2.7 v to 5.5 v. all specifications t min to t max , unless otherwise noted. table 4. limit at t min , t max parameter v dd = 2.7 v to 5.5 v unit conditions/comments t 1 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 13 ns min sync to sclk falling edge set-up time t 5 4 ns min data set-up time t 6 4 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 15 ns min minimum sync high time t 9 13 ns min sync rising edge to sclk fall ignore t 10 0 ns min sclk falling edge to sync fall ignore t 11 10 ns min ldac pulse width low t 12 15 ns min sclk falling edge to ldac rising edge t 13 5 ns min clr pulse width low t 14 0 ns min sclk falling edge to ldac falling edge t 15 300 ns typ clr pulse activation time 1 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v. guaranteed by design and characterization; not production tested. 05302-002 t 4 t 3 sclk sync din t 1 t 2 t 5 t 6 t 7 t 8 db31 t 9 t 10 t 11 t 12 ldac 1 ldac 2 t 14 1 asynchronous ldac update mode. 2 synchronous ldac update mode. clr t 13 t 15 v out db0 figure 2. serial write operation
ad5628/ad5648/ad5668 rev. e | page 8 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v v out to gnd ?0.3 v to v dd + 0.3 v v refin /v refout to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max ) 150c tssop package power dissipation (t j max ? t a )/ ja ja thermal impedance 150.4c/w reflow soldering peak temperature pb free 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5628/ad5648/ad5668 rev. e | page 9 of 28 pin configurations and function descriptions 05302-003 1 2 3 4 5 6 7 ad5628/ ad5648/ v dd v out a v out c v refin /v refout v out g v out e 14 13 12 11 10 9 8 din gnd v out b v out h v out f v out d sclk top view (not to scale) sync figure 3. 14-lead tssop (ru-14) 05302-004 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sync v dd v out a v out g v out e v out c ldac din gnd v out b v out h v refin /v refout clr v out f v out d sclk ad5628/ ad5648/ ad5668 top view (not to scale) figure 4. 16-lead tssop (ru-16) 05302-005 12 11 10 1 3 4 gnd v out b v out d 9 v out f v dd v out c 2 v out a v out e 6 v refin /v refout 5 v out g 7 clr 8 v out h 16 sync 15 ldac 14 sclk 13 d in top view (not to scale) notes 1. exposed pad must be tied to gnd. ad5628/ad5668 figure 5. 16-lead lfcsp(cp-16-17) table 6. pin function descriptions pin no. 14-lead tssop 16-lead tssop 16-lead lfcsp mnemonic description n/a 1 15 ldac pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows all dac outputs to simultaneously update. alternatively, this pin can be tied permanently low. 1 2 16 sync active low control input. this is the fram e synchronization signal for the input data. when sync goes low, it powers on the sclk an d din buffers and enables the input shift register. data is transferred in on the falling edges of the next 32 clocks. if sync is taken high before the 32 nd falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 2 3 1 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 3 4 2 v out a analog output voltage from dac a. the outp ut amplifier has rail-to-rail operation. 11 13 11 v out b analog output voltage from dac b. the outp ut amplifier has rail-to-rail operation. 4 5 3 v out c analog output voltage from dac c. the outp ut amplifier has rail-to-rail operation. 10 12 10 v out d analog output voltage from dac d. the outp ut amplifier has rail-to-rail operation. 7 8 6 v refin / v refout the ad5628/ad5648/ad5668 have a common pin for reference input and reference output. when using the internal reference, th is is the reference output pin. when using an external reference, this is the reference input pin. the default for this pin is as a reference input. n/a 9 7 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the input register and the dac register are updated with the data contained in the clr code registerzero, midscale, or full scale. default setting cl ears the output to 0 v. 5 6 4 v out e analog output voltage from dac e. the outp ut amplifier has rail-to-rail operation. 9 11 9 v out f analog output voltage from dac f. the o utput amplifier has rail-to-rail operation. 6 7 5 v out g analog output voltage from dac g. the outp ut amplifier has rail-to-rail operation. 8 10 8 v out h analog output voltage from dac h. the outp ut amplifier has rail-to-rail operation. 12 14 12 gnd ground reference point for all circuitry on the part. 13 15 13 din serial data input. this device has a 32-bit shif t register. data is clocked into the register on the falling edge of the serial clock input. 14 16 14 sclk serial clock input. data is cl ocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates of up to 50 mhz. epad epad it is recommended that the expos ed paddle be soldered to the ground plane.
ad5628/ad5648/ad5668 rev. e | page 10 of 28 typical performance characteristics 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 inl (lsb) v dd = 5v ext ref = 5v t a = 25c 05302-106 codes 0 10k 20k 30k 40k 50k 60k 65535 figure 6. inl ad5668external reference 05302-107 4 2 0 ?2 3 1 ?1 ?3 ?4 inl (lsb) v dd = 5v ext ref = 5v t a = 25c 0 5k 10k 15k 16384 codes figure 7. inl ad5648external reference 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 500 1000 1500 2000 2500 3000 3500 4095 inl (lsb) codes v dd = 5v ext ref = 5v t a = 25c 05302-108 figure 8. inl ad5628external reference 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 dnl (lsb) v dd = 5v ext ref = 5v t a = 25c 05302-109 codes 0 10k 20k 30k 40k 50k 60k 65535 figure 9. dnl ad5668external reference 05302-110 codes inl (lsb) v dd = 5v ext ref = 5v t a = 25c 0 5k 10k 15k 16384 0.5 0.3 0.2 0.1 0.4 0 ?0.2 ?0.1 ?0.3 ?0.5 ?0.4 figure 10. dnl ad5648external reference 05302-111 0 500 1000 1500 2000 2500 3000 3500 4095 dnl (lsb) codes ?0.05 ?0.10 ?0.15 ?0.20 0 0.05 0.10 0.15 0.20 v dd = 5v ext ref = 5v t a = 25c figure 11. dnl ad5628external reference
ad5628/ad5648/ad5668 rev. e | page 11 of 28 10 5 ?10 ?5 0 0 10k 20k 30k 40k 50k 60k 65535 inl (lsb) codes v dd = 5v int ref = 2.5v t a = 25c 05302-112 figure 12. inl ad5668-2/ad5668-3 codes inl (lsb) 4 ?4 ?3 ?2 ?1 0 1 2 3 v dd = 5v ext ref = 5v t a = 25c 0 5k 10k 15k 16383 05302-113 figure 13. inl ad5648-2 1.0 0.5 0 ?0.5 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4095 inl (lsb) codes v dd = 5v int ref = 2.5v t a = 25c 05302-114 figure 14. inl ad5628-2 1.0 0.5 ?1.0 ?0.5 0 0 10k 20k 30k 40k 50k 60k 65535 dnl (lsb) codes v dd = 5v int ref = 2.5v t a = 25c 05302-115 figure 15. dnl ad5668-2/ad5668-3 05302-116 codes dnl (lsb) v dd = 5v ext ref = 2.5v t a = 25c 0 5k 10k 15k 16383 0.5 0.3 0.2 0.1 0.4 0 ?0.2 ?0.1 ?0.3 ?0.5 ?0.4 figure 16. dnl ad5648-2 ?0.05 ?0.10 ?0.15 ?0.20 0 0.05 0.10 0.15 0.20 0 500 1000 1500 2000 2500 3000 3500 4095 dnl (lsb) codes v dd = 5v int ref = 2.5v t a = 25c 05302-117 figure 17. dnl ad5628-2
ad5628/ad5648/ad5668 rev. e | page 12 of 28 10 ?10 ?6 ?8 ?4 ?2 0 2 4 8 6 0 10k 20k 30k 40k 50k 60k 65535 inl (lsb) codes v dd = 3v int ref = 1.25v t a = 25c 05302-118 figure 18. inl ad5668-1 codes inl (lsb) 4 ?4 ?3 ?2 ?1 0 1 2 3 v dd = 3v ext ref = 1.25v t a = 25c 0 5k 10k 15k 16383 05302-119 figure 19. inl ad5648-1 0 500 1000 1500 2000 2500 3000 3500 4095 inl (lsb) codes v dd = 3v int ref = 1.25v t a = 25c 05302-120 1.0 0.5 0 ?0.5 ?1.0 figure 20. inl ad5628-1 0 10k 20k 30k 40k 50k 60k 65535 dnl (lsb) codes v dd = 3v int ref = 1.25v t a = 25c 05302-121 1.0 0.5 ?1.0 ?0.5 0 figure 21. dnl ad5668-1 05302-122 codes dnl (lsb) v dd = 3v ext ref = 1.25v t a = 25c 0 5k 10k 15k 16383 0.5 0.3 0.2 0.1 0.4 0 ?0.2 ?0.1 ?0.3 ?0.5 ?0.4 figure 22. dnl ad5648-1 0 500 1000 1500 2000 2500 3000 3500 4095 dnl (lsb) codes 05302-123 ?0.05 ?0.10 ?0.15 ?0.20 0 0.05 0.10 0.15 0.20 v dd = 3v int ref = 1.25v t a = 25c figure 23. dnl ad5628-1
ad5628/ad5648/ad5668 rev. e | page 13 of 28 0 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 ?40 125 11095 8065503520 5 ?10?25 error (% fsr) temperature (c) full-scale error gain error v dd = 5v 05302-124 figure 24. gain error and full-scale error vs. temperature 6 0 1 2 3 4 5 ?40 125 11095 8065503520 5 ?10?25 error (mv) temperature (c) zero-scale error offset error v dd = 5v 05302-125 figure 25. zero-scale error and offset error vs. temperature ? 0.16 ?0.26 ?0.25 ?0.24 ?0.23 ?0.22 ?0.21 ?0.20 ?0.19 ?0.18 ?0.17 2.7 5.5 5.1 4.7 4.3 3.9 3.5 3.1 error (% fsr) v dd (v) full-scale error gain error t a = 25c 05302-126 figure 26. gain error and full-scale error vs. supply voltage 1.95 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 2.7 5.5 5.1 4.7 4.3 3.9 3.5 3.1 error (mv) v dd (v) zero-scale error offset error t a = 25c 05302-127 figure 27. zero-scale error and offset error vs. supply voltage 05302-128 i dd with external reference (ma) number of hits 0.85 0.90 0.95 1.00 1.05 21 18 15 12 9 6 3 0 figure 28. i dd histogram with external reference 05302-129 i dd with internal reference (ma) number of hits 1.65 1.70 1.75 1.80 1.85 1.190 18 16 14 12 10 8 6 4 2 0 figure 29. i dd histogram with internal reference
ad5628/ad5648/ad5668 rev. e | page 14 of 28 0.4 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 error voltage (v) source/sink current (ma) v dd = 5v, int ref = 2.5v v dd = 3v, int ref = 1.25v 05302-130 figure 30. headroom at rails vs. source and sink 6 5 4 3 2 1 0 ?1 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 v out (v) current (ma) zero scale full scale midscale 1/4 scale 3/4 scale v dd = 5v int ref = 2.5v t a = 25c 05302-131 figure 31. ad5668-2/ad5668-3 source and sink capability 4.0 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 v out (v) current (ma) zero scale full scale midscale 1/4 scale 3/4 scale v dd = 3v int ref = 1.25v 05302-132 figure 32. ad5668-1 source and sink capability 1.8 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0 10k 20k 30k 40k 50k 60k i dd (ma) digital codes (decimal) t a = 25c 05302-133 v dd = 5v v dd = 3v figure 33. supply current vs. code 2.0 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 i dd (ma) temperature (c) 05302-134 v dd = 3.6v v dd = 5.5v figure 34. supply current vs. temperature 1.48 1.34 1.36 1.38 1.40 1.42 1.44 1.46 2.7 5.5 5.1 4.7 4.3 3.9 3.5 3.1 i dd (ma) v dd (v) t a = 25c 05302-135 figure 35. supply current vs. supply voltage
ad5628/ad5648/ad5668 rev. e | page 15 of 28 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 i dd (ma) v logic (v) t a = 25c 05302-136 v dd =5v v dd =3v figure 36. supply current vs. logic input voltage 6 5 4 3 2 1 0 ?2 8 6 4 2 0 v out (v) time (s) v dd = 5v ext ref = 5v t a = 25c 05302-137 figure 37. full-scale settling time, 5 v 5.5 4.5 3.5 2.5 1.5 0.5 5.0 4.0 3.0 2.0 1.0 0 ?0.5 ?0.0010 0.0010 0.0006 0.0002 ?0.0002 ?0.0006 voltage (v) time (s) v out a v dd v dd = 5v ext ref = 5v t a = 25c 05302-138 figure 38. power-on reset to 0 v 5.5 4.5 3.5 2.5 1.5 0.5 5.0 4.0 3.0 2.0 1.0 0 ?0.5 ?0.0010 0.0010 0.0006 0.0002 ?0.0002 ?0.0006 voltage (v) time (s) v out a v dd v dd = 5v ext ref = 5v t a = 25c 05302-139 figure 39. power-on reset to midscale 5.5 4.5 3.5 2.5 1.5 0.5 5.0 4.0 3.0 2.0 1.0 0 ?0.5 ?10 10 5 0 ?5 voltage (v) time (s) v out a 24 th clk rising edge v dd = 5v ext ref = 5v t a = 25c 05302-140 figure 40. exiting power-down to midscale ch3 10.0mv b w ch4 5.0v m400ns a ch4 1.50v t 17.0% 3 4 t 05302-141 v dd = 5v ext ref = 5v t a = 25c v out a 24 th clk rising edge figure 41. digital-to-analog glitch impulse (negative)
ad5628/ad5648/ad5668 rev. e | page 16 of 28 0.0010 ?0.0015 ?0.0010 ?0.0005 0 0.0005 09 87654321 glitch amplitude (v) time (s) 05302-142 v dd = 5v ext ref = 5v t a = 25c figure 42. analog crosstalk 0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0010 0.0015 0.0005 08 7654321 glitch amplitude (v) time (s) 05302-143 v dd = 5v ext ref = 5v t a = 25c figure 43. dac-to-dac crosstalk 0.06 ?0.08 ?0.06 ?0.04 ?0.02 0.02 0.04 0 01 89 7654321 output voltage (v) time (s) 0 ext ref = 5v 05302-144 figure 44. 0.1 hz to 10 hz output noise plot, external reference 0.20 ?0.20 ?0.15 ?0.10 ?0.05 0 0.10 0.15 0.05 01 89 7654321 output noise (v) time (s) 0 ext ref = 2.5v 05302-145 figure 45. 0.1 hz to 10 hz output noise plot, external reference 0.20 ?0.20 ?0.15 ?0.10 ?0.05 0 0.10 0.15 0.05 01 89 7654321 output noise (v) time (s) 0 int ref = 1.25v 05302-146 figure 46. 0.1 hz to 10 hz output noise plot, internal reference 800 0 100 200 300 400 600 700 500 100 1m 100k 10k 1k output noise (nv/ hz) frequency (hz) v ref = 1.25v v ref = 2.5v 05302-147 figure 47. noise spectral density, internal reference
ad5628/ad5648/ad5668 rev. e | page 17 of 28 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10,000 8000 6000 4000 2000 thd (db) frequency (hz) 05302-148 v dd = 5.5v ext ref = 5v t a = 25c v ref = 2v 0.1v p-p frequency = 10khz figure 48. total harmonic distortion 9 0 1 2 3 4 6 7 8 5 01 0 987654321 settling time (s) capacitive load (nf) v dd = external reference = 5v v dd = external reference = 3v t a = 25c 05302-149 figure 49. settling time vs. capacitive load 5.5 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?10 10 5 0 ?5 voltage (v) time (s) v out a clr pulse ext ref = 5v 05302-150 figure 50. hardware clr 10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100m 10m 1m 100k 1k0 1k 100 v out (dbm) frequency (hz) ch a ch b ch c ch d ch e ch f ch g ch h ?3db 05302-151 v dd = 5.5v ext ref = 5v t a = 25c v ref = 2v 0.2v p-p figure 51. multiplying bandwidth 1.2510 1.2490 1.2492 1.2494 1.2496 1.2498 1.2500 1.2502 1.2504 1.2506 1.2508 ?40 25 105 reference (ppm/c) temperature (c) 05302-152 v dd = 5.5v figure 52. 1.25 v reference temperature coefficient vs. temperature 05302-154 2.503 2.495 2.496 2.497 2.498 2.499 2.500 2.501 2.502 105 25 ?40 reference (ppm/c) temperature (c) figure 53. 2.5 v reference temperature coefficient vs. temperature
ad5628/ad5648/ad5668 rev. e | page 18 of 28 terminology relative accuracy for the dac, relative accuracy, or integral nonlinearity (inl), is a measure of the maximum deviation in lsbs from a straight line passing through the endpoints of the dac transfer function. figure 6 to figure 8 , figure 12 to figure 14 , and figure 18 to figure 20 show plots of typical inl vs. code. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed mono- tonic by design. figure 9 to figure 11 , figure 15 to figure 17 , and figure 21 to figure 23 show plots of typical dnl vs. code. offset error offset error is a measure of the difference between the actual v out and the ideal v out , expressed in millivolts in the linear region of the transfer function. offset error is measured on the ad5668 with code 512 loaded into the dac register. it can be negative or positive and is expressed in millivolts. zero-code error zero-code error is a measure of the output error when zero code (0x0000) is loaded into the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5628/ad5648/ad5668, because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in millivolts. figure 27 shows a plot of typical zero- code error vs. temperature. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percentage of the full-scale range. zero-code error drift zero-code error drift is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. full-scale error full-scale error is a measure of the output error when full-scale code (0xffff) is loaded into the dac register. ideally, the output should be v dd C 1 lsb. full-scale error is expressed as a percentage of the full-scale range. figure 24 shows a plot of typical full-scale error vs. temperature. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 41 . dc power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in decibels. v ref is held at 2 v, and v dd is varied 10%. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac (or soft power-down and power-up) while monitoring another dac kept at midscale. it is expressed in microvolts. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in microvolts per milliamp. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (that is, ldac is high). it is expressed in decibels. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device, but is measured when the dac is not being written to ( sync held high). it is specified in nv-s and measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s. analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping ldac high, and then pulsing ldac low and monitoring the output of the dac whose digital code has not changed. the area of the glitch is expressed in nv-s.
ad5628/ad5648/ad5668 rev. e | page 19 of 28 dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s or vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in decibels.
ad5628/ad5648/ad5668 rev. e | page 20 of 28 theory of operation d/a section the ad5628/ad5648/ad5668 dacs are fabricated on a cmos process. the architecture consists of a string of dacs followed by an output buffer amplifier. each part includes an internal 1.25 v/2.5 v, 5 ppm/c reference with an internal gain of 2. figure 54 shows a block diagram of the dac architecture. 05302-153 dac register v refin resistor string ref gnd v dd output amplifier (gain = 2) v out figure 54. dac architecture because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n refin out d vv 2 the ideal output voltage when using the internal reference is given by ? ? ? ? ? ? = n refout out d v v 2 2 where: d = decimal equivalent of the binary code that is loaded to the dac register. 0 to 4095 for ad5628 (12 bits). 0 to 16,383 for ad5648 (14 bits). 0 to 65,535 for ad5668 (16 bits). n = the dac resolution. resistor string the resistor string section is shown in figure 55 . it is simply a string of resistors, each of value r. the code loaded into the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. 05302-053 to output amplifier r r r r r figure 55. resistor string internal reference the ad5628/ad5648/ad5668 have an on-chip reference with an internal gain of 2. the ad5628/ad5648/ad5668-1 have a 1.25 v, 5 ppm/c reference, giving a full-scale output of 2.5 v; the ad5628/ad5648/ad5668-2, -3 have a 2.5 v, 5 ppm/c reference, giving a full-scale output of 5 v. the on-board reference is off at power-up, allowing the use of an external reference. the internal reference is enabled via a write to the control register (see table 7 ). the internal reference associated with each part is available at the v refout pin. a buffer is required if the reference output is used to drive external loads. when using the internal reference, it is recommended that a 100 nf capacitor be placed between the reference output and gnd for reference stability. individual channel power-down is not supported while using the internal reference.
ad5628/ad5648/ad5668 rev. e | page 21 of 28 output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . the amplifier is capable of driving a load of 2 k in parallel with 200 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 31 and figure 32 . the slew rate is 1.5 v/s with a ? to ? scale settling time of 7 s. serial interface the ad5628/ad5648/ad5668 have a 3-wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards as well as most dsps. see for a timing diagram of a typical write sequence. figure 2 the write sequence begins by bringing the sync line low. data from the din line is clocked into the 32-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 50 mhz, making the ad5628/ad5648/ad5668 compatible with high speed dsps. on the 32 nd falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in dac register contents and/or a change in the mode of operation. at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. sync should be idled low between write sequences for even lower power operation of the part. as is mentioned previously, however, sync must be brought high again just before the next write sequence. table 7. command definitions command c3 c2 c1 c0 description 0 0 0 0 write to input register n 0 0 0 1 update dac register n 0 0 1 0 write to input register n, update all (software ldac ) 0 0 1 1 write to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 load clear code register 0 1 1 0 load ldac register 0 1 1 1 reset (power-on reset) 1 0 0 0 set up internal ref register 1 0 0 1 reserved C C C C reserved 1 1 1 1 reserved table 8. address commands address (n) a3 a2 a1 a0 selected dac channel 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 0 1 0 0 dac e 0 1 0 1 dac f 0 1 1 0 dac g 0 1 1 1 dac h 1 1 1 1 all dacs
ad5628/ad5648/ad5668 rev. e | page 22 of 28 input shift register the input shift register is 32 bits wide. the first four bits are dont cares. the next four bits are the command bits, c3 to c0 (see table 7 ), followed by the 4-bit dac address, a3 to a0 (see table 8 ) and finally the 16-/14-/12-bit data-word. the data- word comprises the 16-/14-/12-bit input code followed by four, six, or eight dont care bits for the ad5668, ad5648, and ad5628, respectively (see figure 56 through figure 58 ). these data bits are transferred to the dac register on the 32 nd falling edge of sclk. sync interrupt in a normal write sequence, the sync line is kept low for 32 falling edges of sclk, and the dac is updated on the 32 nd falling edge and rising edge of sync . however, if sync is brought high before the 32 nd falling edge, this acts as an interrupt to the write sequence. the shift register is reset, and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see ). figure 59 05302-054 address bits command bits c3 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x xxx db31 (msb) db0 (lsb) data bits figure 56. ad5668 input register contents 05302-055 address bits command bits c3 c2 c1 c0 a3 a2 a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x xxx db31 (msb) db0 (lsb) data bits figure 57. ad5648 input register contents 05302-056 address bits command bits c3 c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x x xxx db31 (msb) db0 (lsb) data bits figure 58. ad5628 input register contents 05302-057 sclk din db31 db0 invalid write sequence: sync high before 32nd falling edge valid write sequence, output updates on the 32nd falling edge db31 db0 sync figure 59. sync interrupt facility
ad5628/ad5648/ad5668 rev. e | page 23 of 28 internal reference register the on-board reference is off at power-up by default. this allows the use of an external reference if the application requires it. the on-board reference can be turned on or off by a user-program- mable internal ref register by setting bit db0 high or low (see table 9 ). command 1000 is reserved for setting the internal ref register (see table 7 ). table 11 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device. power-on reset the ad5628/ad5648/ad5668 family contains a power-on reset circuit that controls the output voltage during power-up. the ad5628/ad5648/ad5668-1, -2 dac output powers up to 0 v, and the ad5668-3 dac output powers up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. there is also a software executable reset function that resets the dac to the power-on reset code. command 0111 is reserved for this reset function (see table 7 ). any events on ldac or clr during power-on reset are ignored. power-down modes the ad5628/ad5648/ad5668 contain four separate modes of operation. command 0100 is reserved for the power-down function (see table 7 ). these modes are software-programmable by setting two bits, bit db9 and bit db8, in the control register. table 11 shows how the state of the bits corresponds to the mode of operation of the device. any or all dacs (dac h to dac a) can be powered down to the selected mode by setting the corresponding eight bits (db7 to db0) to 1. see table 12 for the contents of the input shift register during power-down/power- up operation. when using the internal reference, only all channel power-down to the selected modes is supported. when both bits are set to 0, the part works normally with its normal power consumption of 1.3 ma at 5 v. however, for the three power-down modes, the supply current falls to 0.4 a at 5 v (0.2 a at 3 v). not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode. there are three different options. the output is connected internally to gnd through either a 1 k or a 100 k resistor, or it is left open-circuited (three-state). the output stage is illustrated in figure 60 . the bias generator of the selected dac(s), output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. the internal reference is powered down only when all channels are powered down. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 4 s for v dd = 5 v and for v dd = 3 v. see figure 40 for a plot. any combination of dacs can be powered up by setting pd1 and pd0 to 0 (normal operation). the output powers up to the value in the input register ( ldac low) or to the value in the dac register before powering down ( ldac high). clear code register the ad5628/ad5648/ad5668 have a hardware clr pin that is an asynchronous clear input. the clr input is falling edge sensitive. bringing the clr line low clears the contents of the input register and the dac registers to the data contained in the user-configurable clr register and sets the analog outputs accordingly. this function can be used in system calibration to load zero scale, midscale, or full scal e to all channels together. these clear code values are user-programmable by setting two bits, bit db1 and bit db0, in the clr control register (see ). the default setting clears the outputs to 0 v. command 0101 is reserved for loading the clear code register (see ). table 13 table 7 the part exits clear code mode on the 32 nd falling edge of the next write to the part. if clr is activated during a write sequence, the write is aborted. the clr pulse activation timethe falling edge of clr to when the output starts to changeis typically 280 ns. however, if outside the dac linear region, it typically takes 520 ns after executing clr for the output to start changing (see ). figure 50 see table 14 for contents of the input shift register during the loading clear code register operation.
ad5628/ad5648/ad5668 rev. e | page 24 of 28 table 9. internal reference register internal ref register (db0) action 0 reference off (default) 1 reference on table 10. 32-bit input shift register contents for reference set-up command msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db1 db0 x 1 0 0 0 x x x x x 1/0 dont cares command bits (c3 to c0) addre ss bits (a3 to a0)dont cares dont cares internal ref register table 11. power-down modes of operation db9 db8 operating mode 0 0 normal operation power-down modes 0 1 1 k to gnd 1 0 100 k to gnd 1 1 three-state table 12. 32-bit input shift register contents for power-down/power-up function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 x 0 1 0 0 x x x x x pd1 pd0 dac h dac g dac f dac e dac d dac c dac b dac a dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares dont cares power- down mode power-down/power-up channel selectionset bit to 1 to select resistor network v out resistor string dac 05302-058 power-down circuitry amplifier figure 60. output stage during power-down table 13. clear code register clear code register db1 db0 cr1 cr0 clears to code 0 0 0x0000 0 1 0x8000 1 0 0xffff 1 1 no operation table 14. 32-bit input shift register contents for clear code function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db2 db1 db0 x 0 1 0 1 x x x x x cr1 cr0 dont cares command bits (c3 to c0) address bits (a3 to a0)dont cares dont cares clear code register
ad5628/ad5648/ad5668 rev. e | page 25 of 28 ldac function the outputs of all dacs can be updated simultaneously using the hardware ldac pin. synchronous ldac : after new data is read, the dac registers are updated on the falling edge of the 32 nd sclk pulse. ldac can be permanently low or pulsed as in . figure 2 asynchronous ldac : the outputs are not updated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the contents of the input register. alternatively, the outputs of all dacs can be updated simulta- neously using the software ldac function by writing to input register n and updating all dac registers. command 0011 is reserved for this software ldac function. an ldac register gives the user extra flexibility and control over the hardware ldac pin. this register allows the user to select which combination of channels to simultaneously update when the hardware ldac pin is executed. setting the ldac bit register to 0 for a dac channel means that this channels update is controlled by the ldac pin. if this bit is set to 1, this channel updates synchronously; that is, the dac register is updated after new data is read, regardless of the state of the ldac pin. it effectively sees the ldac pin as being tied low. (see for the table 15 ldac register mode of operation.) this flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. writing to the dac using command 0110 loads the 8-bit ldac register (db7 to db0). the default for each channel is 0, that is, the ldac pin works normally. setting the bits to 1 means the dac channel is updated regardless of the state of the ldac pin. see for the contents of the input shift register during the load tabl e 16 ldac register mode of operation. power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5628/ad5648/ ad5668 should have separate analog and digital sections. if the ad5628/ad5648/ad5668 are in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5628/ad5648/ad5668. the power supply to the ad5628/ad5648/ad5668 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should physically be as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and low effective series inductance (esi), such as is typical of common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board. table 15. ldac register load dac register ldac bits (db7 to db0) ldac pin ldac operation 0 1/0 determined by ldac pin. 1 xdont care dac channels update, overriding the ldac pin. dac channels see ldac as 0. table 16. 32-bit input shift register contents for ldac register function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db8 db7 db6 db5 db4 db3 db2 db1 db0 x 0 1 1 0 x x x x x dac h dac g dac f dac e dac d dac c dac b dac a dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares dont cares setting ldac bit to 1 overrides ldac pin
ad5628/ad5648/ad5668 rev. e | page 26 of 28 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 61. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 62. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters
ad5628/ad5648/ad5668 rev. e | page 27 of 28 2.70 2.60 sq 2.50 compliant to jedec standards mo-220-wggc. 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.45 0.40 0.35 s eating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-16-2010-c figure 63. 16-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-16-17) dimensions shown in millimeters
ad5628/ad5648/ad5668 rev. e | page 28 of 28 ordering guide model 1 temperature range package description package option power-on reset to code accuracy internal reference AD5628BRUZ-1 ?40c to +105c 14-lead tssop ru-14 zero 1 lsb inl 1.25 v AD5628BRUZ-1reel7 ?40c to +105c 14-lead tssop ru-14 zero 1 lsb inl 1.25 v ad5628bruz-2 ?40c to +105c 16-lead tssop ru-16 zero 1 lsb inl 2.5 v ad5628bruz-2reel7 ?40c to +105c 16-lead tssop ru-16 zero 1 lsb inl 2.5 v ad5628aruz-2 ?40c to +105c 16-lead tssop ru-16 zero 2 lsb inl 2.5 v ad5628aruz-2reel7 ?40c to +105c 16-lead tssop ru-16 zero 2 lsb inl 2.5 v ad5628acpz-1-rl7 ?40c to +105c 16-lead lfcsp_wq cp-16-17 zero 2 lsb inl 1.25 v ad5628acpz-2-rl7 ?40c to +105c 16-lead lfcsp_wq cp-16-17 zero 2 lsb inl 2.5 v ad5628bcpz-2-rl7 ?40c to +105c 16-lead lfcsp_wq cp-16-17 zero 1 lsb inl 2.5 v ad5648bruz-1 ?40c to +105c 14-lead tssop ru-14 zero 4 lsb inl 1.25 v ad5648bruz-1reel7 ?40c to +105c 14-lead tssop ru-14 zero 4 lsb inl 1.25 v ad5648bruz-2 ?40c to +105c 16-lead tssop ru-16 zero 4 lsb inl 2.5 v ad5648bruz-2reel7 ?40c to +105c 16-lead tssop ru-16 zero 4 lsb inl 2.5 v ad5648aruz-2 ?40c to +105c 16-lead tssop ru-16 zero 8 lsb inl 2.5 v ad5648aruz-2reel7 ?40c to +105c 16-lead tssop ru-16 zero 8 lsb inl 2.5 v ad5668bruz-1 ?40c to +105c 16-lead t ssop ru-16 zero 16 lsb inl 1.25 v ad5668bruz-1reel7 ?40c to +105c 16-lead tssop ru-16 zero 16 lsb inl 1.25 v ad5668bruz-2 ?40c to +105c 16-lead t ssop ru-16 zero 16 lsb inl 2.5 v ad5668bruz-2reel7 ?40c to +105c 16-lead tssop ru-16 zero 16 lsb inl 2.5 v ad5668bruz-3 ?40c to +105c 16-lead tsso p ru-16 midscale 16 lsb inl 2.5 v ad5668bruz-3reel7 ?40c to +105c 16-lead t ssop ru-16 midscale 16 lsb inl 2.5 v ad5668aruz-2 ?40c to +105c 16-lead tssop ru-16 zero 32 lsb inl 2.5 v ad5668aruz-2reel7 ?40c to +105c 16-lead tssop ru-16 zero 32 lsb inl 2.5 v ad5668aruz-3 ?40c to +105c 16-lead tsso p ru-16 midscale 32 lsb inl 2.5 v ad5668aruz-3reel7 ?40c to +105c 16-lead t ssop ru-16 midscale 32 lsb inl 2.5 v ad5668bcpz-1-rl7 ?40c to +105c 16-lead lfcsp_wq cp-16-17 zero 16 lsb inl 1.25 v ad5668bcpz-1500rl7 ?40c to +105c 16-lead lfcsp_wq cp-16-17 zero 16 lsb inl 1.25 v ad5668bcpz-2-rl7 ?40c to +105c 16-lead lfcsp_wq cp-16-17 zero 16 lsb inl 2.5 v ad5668bcpz-2500rl7 ?40c to +105c 16-lead lfcsp_wq cp-16-17 zero 16 lsb inl 2.5 v ad5668acpz-2-rl7 ?40c to +105c 16-lead lfcsp_wq cp-16-17 zero 32 lsb inl 2.5 v ad5668acpz-3-rl7 ?40c to +105c 16-lead lfcs p_wq cp-16-17 midscale 32 lsb inl 2.5 v eval-ad5668ebcz lfcsp evaluation board eval-ad5668ebrz tssop evaluation board 1 z = rohs compliant part. ?2005C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05302-0-1/11(e)

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