peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2003 page 1 of 7 product description figure 1. functional schematic diagram rfcommon rf1 rf2 ctrl figure 2. package type 8-lead msop table 1. electrical specifications -55 c to +125 c, v dd = 3 v (z s = z l = 50 ? ) parameter conditions minimum typical maximum units operation frequency 1 dc 3000 mhz insertion loss 2000 mhz 0.7 0.95 db isolation ? rfcommon to rf1/rf2 2000 mhz 25 28 db isolation ? rf1 to rf2 2000 mhz 24 27 db return loss 2000 mhz 18 25 db ?on? switching time ctrl to 0.1 db final value, 2 ghz 200 ns ?off? switching time ctrl to 25 db isolation, 2 ghz 90 ns video feedthrough 2 15 mv pp input 1 db compression 2000 mhz 25 27 dbm input ip3 2000 mhz, 14dbm 40 42 dbm notes: 1. device linearity will begin to degrade below 10 mhz. 2. the dc transient at the output of any port of the switch when the control voltage is switched from low to high or high to lo w in a 50 ? test set-up, measured with 1ns risetime pulses and 500 mhz bandwidth. spdt mosfet rf switch features ? single +3.0-volt power supply ? low insertion loss: 0.70 db up to 2.0 ghz ? high isolation of 39 db at 1.0 ghz, 28 db at 2.0 ghz, typical ? typical 1 db compression of +27 dbm ? single-pin cmos logic control ? packaged in 8-lead msop the pe84244 mosfet rf switch is designed to cover a broad range of applications from dc to 3.0 ghz. this switch integrates on-board cmos control logic with a low voltage cmos compatible control input. using a +3-volt nominal power supply voltage, a 1 db compression point of +27 dbm can be achieved. the pe84244 also exhibits excellent isolation of 28 db at 2.0 ghz and is offered in a small 8-lead msop package. the pe4244 mosfet rf switch is manufactured in peregrine?s patented ultra thin silicon (utsi ? ) cmos process, offering the performance of gaas with the economy and integration of conventional cmos. preliminary specification pe84244 military operating temperature range
pe84244 preliminary specification copyright ? peregrine semiconductor corp. 2003 file no. 70/0129~00a | utsi ? cmos rfic solutions page 2 of 7 figure 3. pin configuration table 2. pin descriptions pin no. pin name description 1 v dd nominal 3 v supply connection. a bypass capacitor (100 pf) to the ground plane should be plac ed as close as possible to the pin 2 ctrl cmos logic level: high = rfcommon to rf1 signal path low = rfcommon to rf2 signal path 3 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 4 rf common common rf port for switch (note 1) 5 rf2 rf2 port (note 1) 6 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 7 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 8 rf1 rf1 port (note 1) note 1: all rf pins must be dc blocked with an external series capacitor or held at 0v dc . table 3. absolute maximum ratings symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v t st storage temperature range -65 150 c t op operating temperature range -55 125 c p in input power (50 ? ) 30 dbm v esd esd voltage (human body model) 1500 v table 4. dc electrical specifications parameter min typ max units v dd power supply voltage 2.7 3.0 3.3 v i dd power supply current v dd = 3v, v cntl = 3v 250 500 na control voltage high 0.7xv dd v control voltage low 0.3xv dd v table 5. control logic truth table control voltage signal path ctrl = cmos high rfcommon to rf1 ctrl = cmos low rfcommon to rf2 electrostatic discharge (esd) precautions when handling this utsi device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, utsi cmos devices are immune to latch-up. pe84244 1 2 3 4 8 7 6 5 ctrl rfcommon gnd rf1 gnd v dd gnd rf2
pe84244 preliminary specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2003 page 3 of 7 typical performance data -55 c to +125 c (unless otherwise noted) figure 4. insertion loss ? rfc to rf1 figure 5. input 1 db compression point & iip3 figure 6. insertion loss ? rfc to rf2 figure 7. isolation ? rfc to rf1 -1.5 -1.2 -0.9 -0.6 -0.3 0.0 0 500 1000 1500 2000 2500 3000 fr eq uency ( m hz) frequency (mhz) insertion loss (db) -55c 25c 125c 20 30 40 50 60 0 500 1000 1500 2000 2500 3000 fr eq uency (m hz) power (dbm) frequency (mhz) -55c 1db compression iip3 25c 125c -1.5 -1.2 -0.9 -0.6 -0.3 0.0 0 500 1000 1500 2000 2500 3000 fr eq uency ( m hz) insertion loss (db) frequency (mhz) -55c 25c 125c -100 -80 -60 -40 -20 0 0 500 1000 1500 2000 2500 3000 freq uency ( m hz) isolation (db) frequency (mhz) -55c 25c 125c
pe84244 preliminary specification copyright ? peregrine semiconductor corp. 2003 file no. 70/0129~00a | utsi ? cmos rfic solutions page 4 of 7 -100 -80 -60 -40 -20 0 0 500 1000 1500 2000 2500 3000 fr eq uency (m hz) isolation (db) frequency (mhz) typical performance data -55 c to +125 c (unless otherwise noted) figure 8. isolation ? rfc to rf2 figure 9. isolation ? rf1 to rf2, rf2 to rf1 figure 10. return loss ? rfc to rf1, rf2 figure 11. return loss ? rf1, rf2 -100 -80 -60 -40 -20 0 0 500 1000 1500 2000 2500 3000 freq uency (m hz) isolation (db) frequency (mhz) -55c 25c 125c rf1 rf2 -40 -30 -20 -10 0 0 500 1000 1500 2000 2500 3000 fr eq uency (m hz) return loss (db) frequency (mhz) rf1 rf2 -35 -30 -25 -20 -15 -10 -5 0 0 500 1000 1500 2000 2500 3000 fr eq uency (m hz) rf1 rf2 return loss (db)
pe84244 preliminary specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2003 page 5 of 7 vdd cntl gnd rfc rf1 gnd gnd rf2 100 pf optional 100 pf optional j2-7 j2-3 j1 j3 j4 j6 j8 evaluation kit information evaluation kit the spdt switch evaluation kit board was designed to ease customer evaluation of the pe84244 spdt switch. the rf common port is connected through a 50 ? transmission line to the top left sma connector, j1. port 1 and port 2 are connected through 50 ? transmission lines to the top two sma connectors on the right side of the board, j3 and j4. a through transmission line connects sma connectors j6 and j8. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed of a two metal layer fr4 material with a total thickness of 0.031?. the bottom layer provides ground for the rf transmission lines. the transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.030?, trace gaps of 0.007?, dielectric thickness of 0.028?, metal thickness of 0.0014? and r of 4.4. j2 provides a means for controlling dc and digital inputs to the device. starting from the lower left pin, the second pin to the right (j2-3) is connected to the device cntl input. the fourth pin to the right (j2-7) is connected to the device v dd input. a decoupling capacitor (100 pf) is provided on both cntl and v dd traces. it is the responsibility of the customer to determine proper supply decoupling for their design application. removing these components from the evaluation board has not been shown to degrade rf performance. figure 12. evaluation board layouts figure 13. evaluation board schematic
pe84244 preliminary specification copyright ? peregrine semiconductor corp. 2003 file no. 70/0129~00a | utsi ? cmos rfic solutions page 6 of 7 front view 2.950.10 0.08 a b c 0.33 +0.07 -0.08 0.10 a 0.100.05 3.000.10 0.860.08 1.10 max - c - - a - 1 0.65bsc 0.510.13 2.450.10 0.510.13 2x 8 3.000.10 .25 a b c 234 - b - .525bsc top view 5 6 7 4.900.15 3.000.10 side view 2.950.10 figure 14. package drawing 8-lead msop table 6. ordering information order code part marking description package shipping method 84244-01 84244 pe84244-08msop-50a 8-lead msop 50 units / tube 84244-02 84244 pe84244-08msop-2000c 8-lead msop 2000 units / t&r 84244-00 pe84244-ek pe84244-08msop-ek evaluation kit 1 / box
pe84244 preliminary specification peregrine semiconductor corp. ? | http://www.peregrine-semi.com copyright ? peregrine semiconductor corp. 2003 page 7 of 7 sales offices united states peregrine semiconductor corp. 6175 nancy ridge drive san diego, ca 92121 tel 1-858-455-0660 fax 1-858-455-0770 japan peregrine semiconductor k.k. 5a-5, 5f imperial tower 1-1-1 uchisaiwaicho, chiyoda-ku tokyo 100-0011 japan tel: 03-3507-5755 fax: 03-3507-5601 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f- 92380 garches tel 33-1-47-41-91-73 fax 33-1-47-41-91-73 australia peregrine semiconductor australia 8 herb elliot ave. homebush, nsw 2140 australia tel: 011-61-2-9763-4111 fax: 011-61-2-9746-1501 for a list of representatives in your area, please refer to our web site at: http://www.peregrine-semi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target s pecifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final dat a. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a pcn (product change notice). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. peregrine products are protected under one or more of the following u.s. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. other patents are pending. peregrine, the peregrine logotype, pe regrine semiconductor corp., and utsi are registered trademarks of pere grine semiconductor corporation. copyright ? 2003 peregrine semic onductor corp. all rights reserved.
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