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general description the ds4026 is a temperature-compensated crystal oscillator (tcxo) that provides ?ppm frequency stabili- ty over the -40? to +85? industrial temperature range. the ds4026 is also available in stratum 3 versions (see the ordering information?tratum 3 table). each device is factory calibrated over temperature to achieve the ?ppm frequency stability. standard frequencies for the device include 10, 12.8, 19.44, 20, 38.88, 40, and 51.84mhz. contact the factory for custom frequencies. the ds4026 provides excellent phase-noise characteris- tics. the output is a push-pull cmos square wave with symmetrical rise and fall times. in addition, the ds4026 is designed to provide a maximum frequency deviation of less than ?.6ppm over 20 years. the device also provides an i 2 c interface to allow pushing and pulling of the output frequency by a minimum of ?ppm (?ppm for 10mhz) with typical 1ppb resolution. the ds4026 implements a temperature-to-voltage con- version with a nonlinear relationship. the output from the temperature-to-voltage converter is used to drive the voltage-controlled crystal oscillator to compensate for frequency change. the device implements an on-chip temperature sensor lookup table, and a digital-to-analog converter (dac) to adjust the frequency. an i 2 c interface used to commu- nicate with the ds4026 performs temperature readings and frequency push-pull. applications reference clock generation wireless telecom/datacom/satcom test and measurement features ? ?ppm frequency accuracy over -40? to +85? ? standard frequencies: 10, 12.8, 19.44, 20, 38.88, 40, 51.84mhz ? stratum 3 frequencies: 10, 12.8, 19.2, 20mhz ? maximum ?.6ppm deviation over 20 years ? minimum ?ppm (?ppm for 10mhz) digital frequency tuning through i 2 c interface ? surface-mount 16-pin so package ? pb free/rohs compliant ds4026 10mhz to 51.84mhz tcxo 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 gnda v ccd fout gndd scl sda gnd n.c. n.c. top view v ref v cc n.c. v osc gndosc n.c. n.c. ds4026 + pin configuration rev 2; 4/08 ________________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead-free package. *the top mark will include a ??for a lead-free/rohs-compliant device. ordering information continued at end of data sheet. ordering information part temp range output (f c ) (mhz, cmos) pin-package top mark* ds4026s+acc 0c to +70c 10.00 16 so ds4026-acc ds4026s+acn -40c to +85c 10.00 16 so ds4026-acn ds4026s+bcc 0c to +70c 12.80 16 so ds4026-bcc ds4026s+bcn -40c to +85c 12.80 16 so ds4026-bcn ds4026s+ecc 0 c to +70 c 16.80 16 so ds4026-ecc ds4026s+ecn -40 c to +85 c 16.80 16 so ds4026-ecn ds4026s+fcc 0 c to +70 c 16.384 16 so ds4026-fcc ds4026s+fcn -40 c to +85 c 16.384 16 so ds4026-fcn
ds4026 10mhz to 51.84mhz tcxo 2 _______________________________________________________________________________________ absolute maximum ratings recommended dc operating conditions (t a = -40? to +85?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc , v ccd , and v osc relative to ground..............................................-0.3v to +3.8v voltage range on sda, scl, and fout relative to ground...................................-0.3v to (v cc + 0.3v) operating temperature range (noncondensing) ....-40? to +85? storage temperature range ...............................-40? to +85? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units power-supply voltage v cc 3.135 3.3 3.465 v oscillator power supply v osc 3.135 3.3 3.465 v driver power supply v ccd 3.135 3.3 3.465 v dc electrical characteristics (v cc = 3.135v to 3.465v, t a = -40? to +85?, unless otherwise noted.) (notes 1, 2, 3) parameter symbol conditions min typ max units v cc active-supply current i cc (note 4) 1.5 2.5 ma fout cmos output on, cl = 10pf, frequency < 25mhz 3 4 v osc oscillator active-supply current i osc fout cmos output on, cl = 10pf, frequency 25mhz 5 9 ma fout cmos output on, cl = 10pf, frequency < 25mhz 2 3 v ccd driver active-supply current i ccd fout cmos output on, cl = 10pf, frequency 25mhz 3 5 ma scl input leakage i li -1 +1 a sda leakage i lo output off -1 +1 a scl, sda high input voltage v ih 0.7 x v cc v cc + 0.3 v scl, sda low input voltage v il -0.3 +0.3 x v cc v sda logic 0 output i ol v cc = 3.0v, v ol = 0.4v 3 ma fout high output voltage v oh v ccd = 3v, i oh = -2ma 2.4 v fout low output voltage v ol v ccd = 3v, i ol = 2.0ma 0.4 v fout rise/fall time t r /t f (0.1 x v ccd ) - (0.9 x v ccd ) 2 ns fout duty cycle t d 0.5 x v ccd (note 5) 45 55 %
ds4026 10mhz to 51.84mhz tcxo _______________________________________________________________________________________ 3 ac electrical characteristics?cxo (v cc = 3.135v to 3.465v, t a = -40? to +85?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units frequency stability vs. temperature f/f c cl = 10pf to ground f c C 1ppm f c f c + 1ppm ppm frequency stability vs. voltage f voltage /f c cl = 10pf to ground, +25c -2 +2 ppm/v first year -1 +1 aging years 2C20 f aging /f c (note 5) -2 +2 ppm except 10mhz 8 15 frequency pull range 10mhz f/f c ftuneh = 3fh and ftunel = ffh; ftuneh = 40h and ftunel = 00h at +25c 5 10 ppm frequency pull resolution f res /f c 1 ppb ac electrical characteristics?tratum 3 (v cc = +3.135v to +3.465v, t a = -40? to +85?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units stratum 3 frequency stability frequency stability vs. temperature f temp /f c -40c to +85c (note 6) -0.28 +0.28 ppm initial tolerance and reflow f initial /f c t a = +25c, 3c and v dd = 3.3v -0.8 +0.8 ppm frequency stability vs. voltage f voltage /f c v cc = 3.3v 5%, c l = 10pf to ground, +25c (note 7) -0.33 +0.33 ppm frequency stability vs. aging/20 years f aging /f c f c = nominal (note 8) -3.0 +3.0 ppm frequency stability vs. load change f load /f c load = 10pf 5%, +25c (note 5) -0.1 +0.1 ppm free-run accuracy operating temperature, load, supply, and initial tolerance, aging (20 years) (notes 5, 8) -4.6 +4.6 ppm holdover stability (24 hours) f 24hours /f c 24-hour elapsed time (notes 5, 9) -0.32 +0.32 ppm phase noise phase noise (dbc/hz) (typical, +25c, 3.3v) offset (mhz) 10hz 100hz 1khz 10khz 100khz 1mhz 12.80 -88.41 -130.16 -147.84 -150.84 -151.71 -151.87 19.44 -82.63 -125.12 -145.03 -146.87 -151.69 -151.52 20.00 -83.71 -120.76 -145.44 -150.96 -151.18 -151.45 38.88 -79.01 -120.06 -141.75 -150.59 -152.50 -153.06 40.00 -80.80 -115.44 -141.17 -151.59 -152.37 -153.00 51.84 -74.09 -120.39 -142.33 -151.14 -153.21 -153.94 10.0 -92.52 -134.83 -147.22 -150.84 -151.25 -150.84 16.384 -87.44 -128.53 -147.67 -150.78 -152.72 -151.75 16.8 -89.6 -126.20 -146.88 -151.90 -152.28 -151.93 carrier frequency 24.0 -83.98 -119.45 -143.08 -150.33 -150.34 -150.67
ac electrical characteristics? 2 c serial interface (v cc = 3.135v to 3.465v, t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units standard mode 0 100 scl clock frequency f scl fast mode 100 400 khz standard mode 4.7 bus free time between stop and start conditions t buf fast mode 1.3 s standard mode 4.0 hold time (repeated) start condition (note 10) t hd:sta fast mode 0.6 s standard mode 4.7 low period of scl clock t low fast mode 1.3 s standard mode 4.0 high period of scl clock t high fast mode 0.6 s standard mode 0 0.9 data hold time (notes 11, 12) t hd:dat fast mode 0 0.9 s standard mode 250 data setup time (note 13) t su:dat fast mode 100 ns standard mode 4.7 start setup time t su:sta fast mode 0.6 s standard mode 20 + 0.1c b 1000 rise time of both sda and scl signals (note 14) t r fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 300 fall time of both sda and scl signals (note 14) t f fast mode 20 + 0.1c b 300 ns standard mode 4.7 setup time for stop condition t su:sto fast mode 0.6 s pin capacitance sda, scl (note 5) c i/o 10 pf ds4026 10mhz to 51.84mhz tcxo 4 _______________________________________________________________________________________ temperature sensor electrical characteristics (v cc = 3.135v to 3.465v, t a = -40? to +85?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units temperature sensor accuracy t -3 +3 c temperature sensor conversion time t convt 11 ms temperature sensor resolution n2 12 bits
ds4026 note 1: typical values are at +25?, nominal supply voltages, unless otherwise indicated. note 2: voltages referenced to ground. note 3: limits at -40? are guaranteed by design and not production tested. note 4: specified with i 2 c bus inactive. note 5: guaranteed by design and not production tested. note 6: frequency stability vs. temperature is defined as ( f max - f min )/2. note 7: maximum power-supply variations to meet the specification are 5%. note 8: crystal vendor specification. note 9: holdover is defined as (f max - f min )/2 as measured within a 24-hour period. warmup time = 1 hour. note 10: after this period, the first clock pulse is generated. note 11: a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 12: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 13: a fast-mode device can be used in a standard-mode system, but the requirement that t su:dat 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does not stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 14: c b ?otal capacitance of one bus line in pf. ac electrical characteristics? 2 c serial interface (continued) (v cc = 3.135v to 3.465v, t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units capacitive load for each bus line (note 14) c b 400 pf pulse width of spikes that must be suppressed by the input filter t sp fast mode 30 ns 10mhz to 51.84mhz tcxo _______________________________________________________________________________________ 5 data transfer on i 2 c serial bus sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start
ds4026 10mhz to 51.84mhz tcxo 6 _______________________________________________________________________________________ typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) active-supply current vs. power-supply current ds4026 toc01 v cc (v) current (ma) 3.5 3.4 3.3 3.2 3.1 0.3 0.2 0.1 0.6 0.5 0.4 0.8 0.7 0.9 1.1 1.0 1.4 1.3 1.2 1.6 1.5 0 3.0 3.6 12.8 51.84 active-supply current vs. oscillator power supply ds4026 toc02 v osc (v) current (ma) 3.5 3.4 3.3 3.2 3.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 3.0 3.6 51.84 12.8 active-supply current vs. driver power supply ds4026 toc03 v ccd (v) current (ma) 3.5 3.4 3.3 3.2 3.1 8.0 6.0 4.0 2.0 10.0 -0.1 3.0 3.6 51.84 12.8 frequency vs. ftune ds4026 toc04 vc (v) offset (ppm) 000h 4000h -25 -20 -15 -10 -5 0 5 10 15 20 -30 3fffh 12.8 51.84 frequency vs. temperature ds4026 toc05 temperature ( c) deviation (ppm) 60 40 20 0 -20 -10 -13 -8 -3 -5 3 15 13 10 8 5 18 0 20 -15 -40 80 dcomp = 1 dcomp = 0 phase noise (typ) ds4026 toc06 offset (hz) phase noise (dbc/hz) -5.0 -30.0 -55.0 -80.0 -105.0 -130.0 -155.0 -180.0 10 100 1000 10,000 100,000 1,000,000 51.84mhz 12.8mhz 19.44mhz 38.88mhz
ds4026 10mhz to 51.84mhz tcxo _______________________________________________________________________________________ 7 gnda 0.1 f 0.1 f 0.1 f 20 v ref 100 f 20% ceramic 3.3v 3.3v 3.3v 5% v cc v osc gndosc n.c. n.c. n.c. v ccd fout gndd scl sda gnd n.c. n.c. ds4026 pin description pin name function 1 gnda ground for dac 2 v ref voltage reference output. this pin must be decoupled with a 100f ceramic capacitor to ground. 3 v cc power supply for digital control and temperature sensor. this pin must be decoupled with a 100nf capacitor to ground. 4 v osc power supply for oscillator circuit. this pin must be decoupled with a 0.1f capacitor to gr ound. 5 gndosc ground for osc illator circuit 6C10 n.c. no connection. must be connected to ground. 11 gnd ground for digital control, temperature sensor, and controller substrate 12 sda serial data input/output. sda is the data input/output for the i 2 c interface. this open-drain pin requires an external pullup resistor. 13 scl serial clock input. scl is the clock input for the i 2 c interface and is used to synchronize data movement on the serial interface. 14 gndd ground for osc illator output driver 15 fout frequency output, cmos push-pull 16 v ccd power supply for oscillator output driver. this pin must be decoupled with a 0.1f capacitor to ground. a 20 resistor must be placed in series between the power supply and v ccd . figure 1. typical operating circuit
ds4026 10mhz to 51.84mhz tcxo 8 _______________________________________________________________________________________ temp sensor v cc v cc gnd v osc gndosc gndd v ref v ccd fout gnda scl sda i 2 c interface controller dac cmos buffer a/d gnd eeprom array gnd gnd v cc v cc ds4026 figure 2. functional diagram detailed description the ds4026 is a tcxo capable of operating at 3.3v ?%, and it allows digital tuning of the fundamental fre- quency. the device is calibrated in the factory to achieve an accuracy of ?ppm over the industrial tem- perature range, and its minimum pullability is ?ppm with a typical resolution of 1ppb (typ) per lsb. the ds4026 contains the following blocks: oscillator block with variable capacitor for compen- sation output driver block temperature sensor controller to read the temperature, control lookup table, and adjust the dac input dac output to adjust the capacitive load ? 2 c interface to communicate with the chip the oscillator block consists of an amplifier and variable capacitor in a pierce crystal oscillator with a crystal res- onator of fundamental mode. the oscillator amplifier is a single transistor amplifier and its transconductance is temperature compensated. the variable capacitor is adjusted by the dac to provide temperature compensa- tion. with the ftuneh and ftunel registers, a minimum pullability of ?ppm (?ppm for 10mhz) is achieved with a typical resolution of 1ppb (typ) per lsb.
ds4026 10mhz to 51.84mhz tcxo _______________________________________________________________________________________ 9 the output driver is a cmos square-wave output with symmetrical rise and fall time. the temperature sensor provides a 12-bit temperature reading with a resolution of 0.0625?. the sensor is in continuous conversion mode. if dcomp is set, conver- sions continue but temperature updates are inhibited. the controller coordinates the conversion of tempera- ture into digital codes. when the temperature reading is different from the previous one or the frequency tuning register is changed, the controller looks up the two cor- responding capacitance trim codes from the lookup table at a 0.5? increment. the trim codes are interpo- lated to 0.0625? resolution. the result is added with the tuning value from the fre- quency tuning register and loaded into the dac regis- ters to adjust voltage output. the monotonic dac provides an analog voltage based on temperature compensation to drive the variable capacitor. the ds4026 operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification code fol- lowed by data. subsequent registers can be accessed sequentially until a stop condition is executed. address map disable compensation update (dcomp) dcomp is bit 7 of the frequency tuning register (see the frequency tuning register (00h?1h), por = 00h table). when set to logic 1, this bit? temperature-com- pensation function is disabled. this disabling prevents the variable capacitor in the oscillator block from changing. however, the temperature register still per- forms temperature conversions. the temperature trim code from the last temperature conversion before dcomp is enabled is used for temperature compensa- tion. the ftune registers are still functional when dcomp is disabled. the frequency tuning registers adjust the base frequen- cy. the frequency tuning value is represented in two? complement data. bit 6 of ftuneh is the sign, bit 5 is the msb, and bit 0 of ftunel is the lsb (see table 1). when the tuning register low (01h) is programmed with a value, the next temperature update cycle sums the programmed value with the factory compensated value. this allows the user to digitally control the base frequency using the i 2 c protocol. these frequency tuning register bits allow the tuning of the base frequency. each bit typically represents about 1ppb (typ). for ftuneh = 3fh and ftunel = ffh, the device pushes the base frequency by approx- imately +15ppm. frequency tuning register (00h?1h), por = 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h dcomp sign data data data data data data por 0 0 0 0 0 0 0 0 01h data data data data data data data data por 0 0 0 0 0 0 0 0 temperature register (02h?3h) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02h sign data data data data data data data por 0 0 0 0 0 0 0 0 03h data data data data 0 0 0 0 por 0 0 0 0 0 0 0 0
ds4026 10mhz to 51.84mhz tcxo 10 ______________________________________________________________________________________ read mode in the temperature register (see the temperature register (02h?3h) table), temperature is represented as a 12-bit code and is accessible at location 02h and 03h. the upper 8 bits are at location 02h and the lower 4 bits are in the upper nibble of the byte at location 03h. upon power reset, the registers are set to a +25? default temperature and the controller starts a tempera- ture conversion. the temperature register stores new temperature readings. the current temperature is loaded into the (user) tem- perature registers when a valid i 2 c slave address and write is received and when a word address is received. consequently, if the two temperature registers are read in individual i 2 c transactions, it is possible for a tem- perature conversion to occur between reads, and the results can be inaccurate. to prevent this from occur- ring, the registers should be read using a single, multi- byte read operation (figure 5). i 2 c reads do not affect the internal temperature registers. i 2 c serial data bus the ds4026 supports a bidirectional i 2 c bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter and a device receiv- ing data is defined as a receiver. the device that con- trols the message is called a master. the devices that are controlled by the master are slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and gener- ates the start and stop conditions. the ds4026 operates as a slave on the i 2 c bus. connections to the bus are made through the open-drain i/o lines sda and scl. within the bus specifications, a standard mode (100khz maximum clock rate) and a fast mode (400khz maximum clock rate) are defined. the ds4026 works in both modes. the following bus protocol has been defined (figure 3): data transfer can be initiated only when the bus is not busy. table 1. register map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function 00 dcomp sign ftuneh frequency tuning high 01 ftunel frequency tuning low 02 sign tregh temperature msb 03 tregl temperature lsb stop condition or repeated start condition repeated if more bytes are transfered ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 3. i 2 c data transfer overview
ds4026 10mhz to 51.84mhz tcxo ______________________________________________________________________________________ 11 during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low, while the clock line is high, defines a start condition. stop data transfer: a change in the state of the data line from low to high, while the clock line is high, defines a stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and the stop conditions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge (ack) after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figures 4 and 5 detail how data transfer is accom- plished on the i 2 c bus. depending upon the state of the r/ w bit, two types of data transfer are possible: data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge (ack) bit after each received byte. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is trans- mitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge (nack) is returned. the master device generates all the serial clock pulses and the start and stop conditions. a trans- fer is ended with a stop condition or with a repeat- ed start condition. because a repeated start condition is also the beginning of the next serial transfer, the bus is not released. a xxxxxxxx a 1000001 s 0 xxxxxxxx a xxxxxxxx a xxxxxxxx a p s = start a = acknowledge p = stop r/w = read/write or direction bit address = 82h data transferred (x + 1 bytes + acknowledge) figure 4. slave receiver mode (write mode) a xxxxxxxx a 1000001 s 1 xxxxxxxx a xxxxxxxx a xxxxxxxx a p s = start a = acknowledge p = stop a = not acknowledge r/w = read/write or direction bit address = 83h data transferred (x + 1 bytes + acknowledge) note: last data byte is followed by a not acknowledge (a) signal figure 5. slave transmitter mode (read mode)
ds4026 10mhz to 51.84mhz tcxo 12 ______________________________________________________________________________________ the ds4026 can operate in the following two modes: slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. the slave address byte is the first byte received after the mas- ter generates a start condition. the slave address byte contains the 7-bit ds4026 address, which is 1000001, followed by the direction bit (r/ w ), which is 0 for a write. after receiving and decoding the slave address byte, the ds4026 outputs an acknowledge on sda. after the ds4026 acknowledges the slave address and write bit, the master transmits a word address to the ds4026. this sets the register pointer on the ds4026, with the ds4026 acknowledging the transfer. the master can then transmit zero or more bytes of data, with the ds4026 acknowledging each byte received. the register pointer increments after each data byte is transferred. the master generates a stop condition to terminate the data write. slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indi- cates that the transfer direction is reversed. serial data is transmitted on sda by the ds4026 while the serial clock is input on scl. start and stop condi- tions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. the slave address byte is the first byte received after the master generates a start condi- tion. the slave address byte contains the 7-bit ds4026 address, which is 1000001, followed by the direction bit (r/ w ), which is 1 for a read. after receiv- ing and decoding the slave address byte, the ds4026 outputs an acknowledge on sda. the ds4026 then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not written to before the initia- tion of a read mode, the first address that is read is the last one stored in the register pointer. the ds4026 must receive a not acknowledge to end a read.
ds4026 10mhz to 51.84mhz tcxo ______________________________________________________________________________________ 13 ordering information (continued) part temp range output (f c ) (mhz, cmos) pin-package top mark* ds4026s+hcc 0c to +70c 19.44 16 so ds4026-hcc ds4026s+hcn -40c to +85c 19.44 16 so ds4026-hcn ds4026s+jcc 0c to +70c 20.00 16 so ds4026-jcc ds4026s+jcn -40c to +85c 20.00 16 so ds4026-jcn ds4026s+mcc 0c to +70c 38.88 16 so ds4026-mcc ds4026s+mcn -40c to +85c 38.88 16 so ds4026-mcn ds4026s+pcc 0c to +70c 40.00 16 so ds4026-pcc ds4026s+pcn -40c to +85c 40.00 16 so ds4026-pcn ds4026s+qcc 0c to +70c 51.84 16 so ds4026-qcc ds4026s+qcn -40c to +85c 51.84 16 so ds4026-qcn ds4026s+rcc 0 c to +70 c 24.00 16 so ds4026-rcc ds4026s+rcn -40 c to +85 c 24.00 16 so ds4026-rcn ordering information?tratum 3 part temp range output (f c ) (mhz, cmos) pin-package top mark* ds4026s3+acn -40 c to +85 c 10.00 16 so ds4026s3-acn ds4026s3+bcn -40 c to +85 c 12.80 16 so ds4026s3-bcn ds4026s3+gcn -40 c to +85 c 19.20 16 so ds4026s3-gcn ds4026s3+jcn -40 c to +85 c 20.00 16 so ds4026s3-jcn + denotes a lead-free package. *the top mark will include a ??for a lead-free/rohs-compliant device. package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . chip information transistor count: 77, 712 substrate connected to ground process: cmos + denotes a lead-free package. *the top mark will include a ??for a lead-free/rohs-compliant device. package type package code document no. 16 so (300 mils) 56-g4009-001
ds4026 10mhz to 51.84mhz tcxo maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/07 initial release. 1 9/07 changed device from 12.8mhz to 51.84mhz to 10mhz to 51.84mhz; added 5ppm (min, typ) digital frequency tuning for the 10mhz option; added new ordering information and phase noise data; changed capacitor value designators from 10nf to 0.1f; changed push-pull value from 15ppm (typ) to 8ppm (min). 1C12 2 4/08 changed maximum frequency deviation from over 10 years to over 20 years; added stratum 3 electrical characteristics table; added ordering information for stratum 3 parts. 1, 5, 13

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