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for a more integrated solution use xicor system management products rev 1.2 11/28/00 characteristics subject to change without notice. 1 of 13 www.xicor.com recommend system management alternative: x4163 8k x24c08 1024 x 8 bit serial eeprom features 2.7v to 5.5v power supply low power cmos active read current less than 1 ma active write current less than 3 ma internally organized 1024 x 8 2-wire serial interface bidirectional data transfer protocol schmitt trigger input noise suppression 400khz across v cc range sixteen byte page write mode minimizes total write time per byte self-timed write cycle typical write cycle time of 5 ms high reliability endurance: 1,000,000 cycles data retention: 100 years 8-pin soic package description the x24c08 is a cmos 8,192 bit serial eeprom, internally organized 1024 x 8. the x24c08 features a serial interface and software protocol allowing opera- tion on a simple two wire bus. the x24c08 is fabricated with xicors advanced cmos textured poly floating gate technology. the x24c08 utilizes xicors proprietary direct write cell providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. block diagram start stop logic control logic slave address register +comparator h.v. generation timing & control word address counter xdec ydec d out ack eeprom 64 x 128 data register start cycle (8) v cc r/w pin (4) v ss (5) sda (6) scl (3) a 2 (2) a 1 (1) a 0 d out load inc ck (7) test 8
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 2 of 13 rev 1.2 11/28/00 www.xicor.com pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open col- lector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the pull- up resistor selection graph at the end of this data sheet. address (a 0 , a 1 ) a 0 and a 1 are unused by the x24c08; however, they must be tied to v ss to insure proper device operation. address (a 2 ) the a 2 input is used to set the appropriate bit of the seven bit slave address. this input can be used static or actively driven. if used statically, it must be tied to v ss or v cc as appropriate. if actively driven, it must be driven to v ss or to v cc . pin configuration pin names device operation the x24c08 supports a bidirectional bus oriented pro- tocol. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers, and pro- vide the clock for both transmit and receive operations. therefore, the x24c08 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the x24c08 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condition is also used by the x24c08 to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. v cc test scl a 0 a 1 a 2 v ss x24c08 soic sda 1 2 3 4 8 7 6 5 symbol description a 0 ? 2 address inputs sda serial data scl serial clock test hold at v ss v ss ground v cc supply voltage nc no connect
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 3 of 13 rev 1.2 11/28/00 www.xicor.com figure 1. data validity figure 2. definition of start and stop scl sda data stable data change scl sda start bit stop bit acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the x24c08 will respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the x24c08 will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode the x24c08 will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the x24c08 will continue to transmit data. if an acknowledge is not detected, the x24c08 will terminate further data trans- missions. the master must then issue a stop condition to return the x24c08 to the standby power mode and place the device into a known state. figure 3. acknowledge response from receiver scl from master data output from transmitter data output from receiver start acknowledge 189
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 4 of 13 rev 1.2 11/28/00 www.xicor.com device addressing following a start condition the master must output the address of the slave it is accessing. the most signi? cant four bits of the slave address are the device type identi?r (see figure 4). for the x24c08 this is ?ed as 1010[b]. figure 4. slave address the next bit addresses a particular device. a system could have up to two x24c08 devices on the bus (see figure 10). the two addresses are de?ed by the state of the a2 input. the next two bits of the slave address ?ld are an extension of the arrays address and are concatenated with the eight bits of address in the word address ?ld, providing direct access to the whole 1024 x 8 array. the last bit of the slave address de?es the operation to be performed. when set to one a read operation is selected; when set to zero a write operation is selected. following the start condition, the x24c08 monitors the sda bus comparing the slave address being transmit- ted with its slave address (device type and state of a2 input.) upon a correct compare the x24c08 outputs an acknowledge on the sda line. depending on the state of the r/w bit, the x24c08 will execute a read or write operation. write operations byte write for a write operation, the x24c08 requires a second address ?ld. this address ?ld is the word address, comprised of eight bits, providing access to any one of 1024 words in the array. upon receipt of the word address the x24c08 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the x24c08 begins the internal write cycle to the non- volatile memory. while the internal write cycle is in progress the x24c08 inputs are disabled, and the device will not respond to any requests from the mas- ter. refer to figure 5 for the address, acknowledge and data transfer sequence. a2 a1 a0 r/w device type identifier device address 0 1 0 1 high order word address figure 5. byte write bus activity: master sda line bus activity: x24c08 s t a slave address s s t p a a a word address data o p r t c k c k c k page write the x24c08 is capable of a sixteen byte page write operation. it is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the ?st data word is transferred, the master can transmit up to ?teen more words. after the receipt of each word, the x24c08 will respond with an acknowledge. after the receipt of each word, the four low order address bits are internally incremented by one. the high order six bits of the word address remain con- stant. if the master should transmit more than sixteen words prior to generating the stop condition, the address counter will ?oll over and the previously writ- ten data will be overwritten. as with the byte write oper- ation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowledge and data transfer sequence.
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 5 of 13 rev 1.2 11/28/00 www.xicor.com acknowledge polling the disabling of the inputs can be used to take advan- tage of the typical 5 ms write cycle time. once the stop condition is issued to indicate the end of the hosts write operation, the x24c08 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition, followed by the slave address for a write operation. if the x24c08 is still busy with the write operation no ack will be returned. if the x24c08 has completed the write oper- ation an ack will be returned and the host can then proceed with the next read or write operation. refer to flow 1. flow 1. ack polling sequence write operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed issue stop no yes yes proceed issue stop no figure 6. page write bus activity: master sda line bus activity: s t a slave address s s t p a a a a a word address data n data n+1 data n+15 r t o p c k c k c k c k c k x24c08 note: in this example n = xxxx 000 (b); x = 1 or 0
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 6 of 13 rev 1.2 11/28/00 www.xicor.com read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read and sequential read. it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle, or hold sda high during the ninth clock cycle and then issue a stop condition. current address read internally the x24c08 contains an address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the x24c08 issues an acknowledge and transmits the eight bit word. the read operation is terminated by the master by not responding with an acknowledge and by issuing a stop condition. refer to figure 7 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must ?st perform a ?ummy write opera- tion. the master issues the start condition, and the slave address followed by the word address it is to read. after the word address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to one. this will be fol- lowed by an acknowledge from the x24c08 and then by the eight bit word. the read operation is terminated by the master by not responding with an acknowledge and by issuing a stop condition. refer to figure 8 for the address, acknowledge and data transfer sequence. figure 7. current address read figure 8. random read bus activity: master sda line bus activity: x24c08 s t a slave address s s t p a data r t o p c k bus activity: master sda line bus activity: x24c08 s t a slave address s s t p a a a word address n slave address data n s t a s r t r t o p c k c k c k sequential read sequential reads can be initiated as either a current address read or random access read. the ?st word is transmitted as with the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the x24c08 continues to output data for each acknowledge received. the read operation is terminated by the master by not responding with an acknowledge and by issuing a stop condition.
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 7 of 13 rev 1.2 11/28/00 www.xicor.com the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space (address 1023) the counter ?olls over to address 0 and the x24c08 continues to output data for each acknowledge received. refer to figure 9 for the address, acknowledge and data transfer sequence. figure 9. sequential read figure 10. typical system configuration address a a data n+x s t p data n a data n+1 a data n+2 c k c k c k c k o p bus activity: sda line bus activity: x24c08 slave master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl v cc pull-up resistors
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 8 of 13 rev 1.2 11/28/00 www.xicor.com absolute maximum ratings temperature under bias ....................?5? to +135? storage temperature .........................?5? to +150? voltage on any pin with respect to v ss ..................................... ?.0v to +7v d.c. output current .............................................. 5 ma lead temperature (soldering, 10 seconds).........300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this speci?a- tion) is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0? 70? industrial ?0? +85? supply voltage limits x24c08-2.7 2.7v to 5.5v d.c. operating characteristics (over recommended operating conditions, unless otherwise specified.) capacitance t a = 25?, f = 1.0mhz, v cc = 5v notes: (1) must perform a stop command prior to measurement. (2) v il min and v ih max. are for reference only and are not 100% tested. (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits unit test conditions min. max. l cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100 khz, sda = open, all other inputs = gnd or v cc ?0.3v l cc2 v cc supply current (write) 3 i sb1 (1) v cc standby current 150 ? scl = sda = v cc ?0.3v, all other inputs = gnd or v cc , v cc = 5.5v i sb2 (1) v cc standby current 50 ? scl = sda = v cc ?0.3v, all other inputs = gnd or v cc , v cc = 3v i li input leakage current 10 ? v in = gnd to v cc i lo output leakage current 10 ? v out = gnd to v cc v ll (2) input low voltage ?.0 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3 ma symbol test max. unit conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 9 of 13 rev 1.2 11/28/00 www.xicor.com a.c. conditions of test equivalent a.c. load circuit input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns i/o timing levels v cc x 0.5 1533 ? output 100pf 5.0v a.c. characteristics limits (over recommended operating conditions, unless otherwise specified.) read & write cycle limits power-up timing symbol parameter min. max. unit t scl scl clock frequency 0 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 ? t buf time the bus must be free before a new transmission can start 4.7 ? t hd:sta start condition hold time 4.0 ? t low clock low period 4.7 ? t high clock high period 4.0 ? t su:sta start condition setup time 4.7 ? t hd:dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 ? t dh data out hold time 300 ns symbol parameter max. unit t pur (4) power-up to read operation 1 ms t puw (4) power-up to write operation 5 ms
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 10 of 13 rev 1.2 11/28/00 www.xicor.com bus timing note: (4) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. write cycle limits notes: (5) typical values are for t a = 25? and nominal supply voltage (5v). (6) t wr is the minimum cycle time from the system perspective when polling techniques are not used. it is the maximum time the device requires to perform the internal write operation. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/pro- gram cycle. during the write cycle, the x24c08 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. write cycle timing symbol parameter min. typ. (5) max. unit t wr (6) write cycle time 5 10 ms t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high sda 8 th bit word n ack t wr stop condition start condition x24c08 address scl
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 11 of 13 rev 1.2 11/28/00 www.xicor.com guidelines for calculating typical values of bus pull-up resistors symbol table 120 100 80 40 60 20 20 40 60 80 100 120 bus capacitance (pf) min. resistance max. resistance r max = c bus t r max. r min = i ol min. v cc max. = 1.8k ? 0 0 resistance (k ? ) waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 12 of 13 rev 1.2 11/28/00 www.xicor.com packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0?- 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint
for a more integrated solution use xicor system management products x24c08 characteristics subject to change without notice. 13 of 13 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending rev 1.2 11/28/00 www.xicor.com ordering information park mark convention device v cc limits 2.7 = 2.7v to 5.5v temperature range blank = commercial = 0? to +70? i = industrial = ?0? to +85? package s8 = 8-lead soic x24c08 p -v t x24c08 x x s8 = 8-lead soic f = 2.7v to 5.5v, 0? to +70? g = 2.7v to 5.5v, ?0? to +85?

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