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rev . 2 1 description the 73s 8014bn is a single smart card (icc) interface circuit designed to provide full electrical compliance with iso 7816 - 3, emv ? 4.2, and nds specifications . it is derived from the 73s8024rn industry - standard electrical interface , but adds support for 1.8v smart card applications. the 73s 8014bn has been optimized to match set - t op b ox/a/v c onditional a ccess applications. the o ptimization adds functionality while creating a device with a smaller pin count . for nds applications requiring an on - chip adjustable por, see the maxim 73s8024rn series of interface ics. the 73s 8014bn interfaces with the host processor through the same bus (digital i/os) as the 73s8024rn and most other 8024 type devices . as a result, the 73s 8014bn is a very attractive cost - reduction path from traditional 8024 ics. interfacing with the system controller is done through a control bus, composed of digital inputs to control the 73s 8014bn , and one interrupt output to inform the system controller of the ca rd presence , device readiness and faults. the card clock can be generated by an on - chip oscillator using an external crystal or by connection to an externally supplied clock signal. in addition, the clock divider provides divisor values of divide by 1, 2, 4 , and 8 that are controlled through a single pin . the 73s 8014bn incorporates an iso 7816 - 3 activation/deactivation sequencer that controls the card signals. level - shifters drive the card signals with the selected card voltage ( 1.8v, 3v , or 5v), coming fro m an internal l ow d rop o ut (ldo) voltage regulator. this ldo regulator is powered by a dedicated power - supply input , v pc . digital circuitry is powered separately by a digital power supply , v dd . with its embedded ldo regulator, the 73s 8014bn is a cost - effect ive solution for any application where a 5v (typically - 5% +10%) power supply is available. emergency card deactivation is initiated upon card extraction or upon any fault detected by the protection circuitry. the fault can be a card overcurrent, v cc under voltage , or power - supply fault (v dd ). the card overcurrent circuitry is a true current - detection function, as opposed to v cc voltage drop detection, as usually implemented in non - maxim 8024 interface ics. the 73s 8014bn contains a power - down mode wi th typical power consumption of 1 a on each of the v dd and v pc supplies. the power - down mode is controlled through existing control pins without the need for a dedicated control pin. applications ? set - top box conditional access and pay - per - view ? general - p urpose s mart c ard r eaders advanta ges ? nds c ompliant ? same a dvantages as the maxim 73s80xxr f amily: ? card v cc g enerated by an ldo r egulator ? very l ow p ower d issipation ( s aves u p to 1/2w) ? fewer e xternal c omponents a re r equired ? better n oise p erformance ? true c ard o vercurrent d etection ? fi rmware c ompatibility with 8024 ics ? small - f ormat 20 - pin so p ackage c apable of f ully s upport ing nds a pplications ? power - d own m ode features ? card interface ? complies with iso 7816 - 3, emv 4. 2 , and nds ? s upports 3v/5v c ards u p to 65ma and 1.8v c ards u p to 40ma ? iso 7816 - 3 activation/deactivation s equencer ? automated d eactivation u pon h ardware f ault (i.e. , u pon d rop on v dd p ower s upply or c ard o vercurrent) ? overcurrent d etection 1 45 ma max ? card clk c lock f requency u p to 20mhz ? system controller interface ? three digital i nputs c ontrol the c ard a ctivation/ d eactivation, c ard re set , p ower - d own , and c ard v oltage ? one digital i nput c ontrol s the c ard c lock f requency ? one digital o utput, i nterrupt to the s ystem c ontroller, r eports to the h ost the c ard p resence , d evice r eadiness , and f aults ? crystal o scillator or h ost c lock, u p to 27mhz ? regulator power supply ? 4.75v to 5.5v (emv 4. 2 ) ? 4.85v to 5.5v (nds) ? digital interfacing: 2.7v to 3.6 v ? 6kv esd p rotection on the c ard i nterface ? 20- p in so package ? rohs - c ompliant (6/6) /l ead (pb) - f ree p ackage 19 - 5669; rev 2 ; 1 2 /1 1 emv is a registered trademark of emvco l lc . 73S8014BN smart card interface ds_8014bn_057
73S8014BN data sheet ds_8014bn_057 2 rev. 2 functional diagram smart card signal control and level shifters ldo regulator sc sequencer voltage and current references clock generation controller and fault logic reset buffer clock buffer r-c osc. vdd fault vcc fault clock 1.5mhz v dd v pc v cc rst clk pres c4 c4uc cmdvcc rstin 5v# v gnd off bias currents vref vcc circuits vdd ckt vdd circuits vdd circuits vcc control c8uc i/ouc i/o c8 xtal osc xtalin/ clkin xtalout ckdiv power down figure 1 : 73s 8014bn block diagram
ds_8014bn_057 73S8014BN data sheet rev. 2 3 table of contents 1 pinout .............................................................................................................................................................. 5 2 electrical specifications ................................................................................................................................. 8 2.1 absolute maximum ratings ...................................................................................................................... 8 2.2 recommended operating conditions ....................................................................................................... 8 2.3 smart card interface requirements ......................................................................................................... 9 2.4 digital signals characteristics ................................................................................................................ 11 2.5 dc characteristics ................................................................................................................................. 12 2.6 voltage fault - detection circuits ............................................................................................................. 12 3 applications information .............................................................................................................................. 13 3.1 example 73S8014BN schematics .......................................................................................................... 13 3.2 system controller interface .................................................................................................................... 15 3.3 power - down mode ................................................................................................................................. 15 3.4 power supply and voltage supervision .................................................................................................. 16 3.5 card power supply ................................................................................................................................ 16 3.6 on - chip oscillator and card clock ......................................................................................................... 17 3.7 activation sequence ............................................................................................................................... 18 3.8 deactivation sequence ........................................................................................................................... 19 3.9 fault detection and off ......................................................................................................................... 20 3.10 i/o, c4, and c8 circuitry and timing ...................................................................................................... 20 4 equivalent circuits ....................................................................................................................................... 22 5 mechanical drawing ..................................................................................................................................... 27 6 ordering information .................................................................................................................................... 28 7 contact information ..................................................................................................................................... 28 revision history .................................................................................................................................................. 29
73S8014BN data sheet ds_8014bn_057 4 rev. 2 figures figure 1: 73S8014BN block diagram .................................................................................................................... 2 figure 2: 73S8014BN 20 - so pinout ...................................................................................................................... 5 figure 3: 73S8014BN typical application schematic ........................................................................................ 14 figure 4: power - down mode and pres debounce ............................................................................................. 16 figure 5: clkdiv usage ..................................................................................................................................... 17 figure 6: activation sequence rstin low when cmdvcc goes low ............................................................. 18 figure 7: acti vation sequence rstin high when cmdvcc goes low ............................................................ 19 figure 8: deactivation sequence ......................................................................................................................... 19 figure 9: timing diagram management of the inter rupt line off ...................................................................... 20 figure 10: i/o and i/ouc state diagram .............................................................................................................. 21 figure 11: timing diagram i/o to i/ouc delays ................................................................................................ 21 figure 12: open - drain type off ...................................................................................................................... 22 figure 13: power input/output circuit v dd , v pc , v cc .......................................................................................... 22 figure 14: smart card clk driver circuit ............................................................................................................ 23 figure 15: smart card rst driver circuit ............................................................................................................ 23 figure 16: smart card i/o, c4, and c8 interface circuit ....................................................................................... 24 figure 17: smart card i/ouc interface circuit ..................................................................................................... 24 figure 18: general input circuit ........................................................................................................................... 25 figure 19: oscillator circuit .................................................................................................................................. 25 figure 20: clkdiv .............................................................................................................................................. 26 figure 21: mechanical drawing 20 - pin so package ............................................................................................ 27 tables table 1: 73S8014BN 20 - pin so pin definitions ..................................................................................................... 6 table 2: absolute maximum device ratings .......................................................................................................... 8 table 3: recommended operating conditions ....................................................................................................... 8 table 4: dc smart card interface requirements ................................................................................................... 9 tabl e 5: digital signals characteristics ................................................................................................................ 11 table 6: dc characteristics ................................................................................................................................. 12 table 7: voltage and current fault - detection circuits .......................................................................................... 12 table 8: v cc voltage logic table ......................................................................................................................... 15 table 9: order numbers and packaging marks .................................................................................................... 28
ds_8014bn_057 73S8014BN data sheet rev. 2 5 1 pinout the 73s 8014bn is offered in a 20- pin so package. 1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 19 20 clkdiv c4uc 5v/# v v pc pres i/o i/ouc xtalin/clkin xtalout off v dd rstin cmdvcc v cc rst clk c8 c4 gnd 73S8014BN c8uc figure 2 : 73s 8014bn 20- so pinout
73S8014BN data sheet ds_8014bn_057 6 rev. 2 table 1 provides the 73s 8014bn pin names, pin numbers, type, equivalent circuits , a nd descriptions. table 1 : 73s 8014bn 20- pin so pin definitions name pin type equivalent circuit figure # description card interface i/o 13 io figure 16 card i/o: data s ignal to/fr om c ard. includes an 11 k? pullup resistor to v cc. c4 12 io figure 16 card c4: data s ignal to/from c ard. includes an 11 k ? pullup resistor to v cc. c8 14 io figure 16 card c8: data s ignal to/from c ard. includes an 11 k ? pullup resistor to v cc. rst 15 o figure 15 card r eset . p rovides reset (rst) signal to card. clk 17 o figure 14 card c lock: p rovide s clock signal (clk) to card. the rate of this clock is determined by the external crystal frequency or frequency of the external clock signal applied on xtalin and clkdiv selections. pres 19 i figure 18 card presence s witch . a ctive high indicates the card is present. includes a high - impedance pulldown current source. the pres input includes a 5ms debounce for card insertion . v cc 18 pso figure 13 card pow er s upply . l ogically controlled by sequencer, output of ldo regulator. requires an external filter capacitor to the card gnd. gnd 16 gnd card and d igital g round host processor interface cmdvcc 8 i figure 18 command v cc (n egative a ssertion) . logic - low on this pin causes the ldo regulator to ramp the v cc supply to the card and initiate s a card activation sequence, only when a card is present. 5v/ 3 v 9 i figure 18 5 v/3 v /1.8 v c ard s election. logic - high selects 5v for v cc and card interface. logic - low selects 3 v operation. logic going from high to low within 400ns of cmdvcc falling select s 1.8v. when the device is to be used with a single card voltage (3v o r 5v only), this pin should be connecte d to either gnd or v dd . however, it includes a high - impedance pullup resistor to default this pin high (selection of 5v card) when not connected. do not change the level of this pin when cmdvcc is low. clkdiv 6 i figure 20 sets the d ivide r atio from the xtal o scillator (or e xternal c lock i nput) to c a rd c lock. this is a multilevel input that uses a ratio of the v dd voltage to select the clock divider as shown: clkdiv clock rate gnd xtalin/4 v dd /3 xtalin v dd x 2/3 xtalin/8 v dd xtalin/2 note: this input has no internal pullup or pulldown so it must not be left unconnected . off 20 o figure 12 active - low interrupt s i gnal to the p rocessor. active - l ow m ultifunction indicating fault conditions, device readiness , and card presence. open - drain output configuration. it includes an internal 20k ? pullup to v dd.
ds_8014bn_057 73S8014BN data sheet rev. 2 7 name pin type equivalent circuit figure # description rstin 1 i figure 18 reset input . within a card session, this signal is the reset command to the card. outside a card session, this signal is used to place the device in power - down. c8uc 2 io figure 17 system c ontroller d ata c8 to/from the c ard. includes an 11 k? pull up resistor to v dd. i/ouc 3 io figure 17 system controller data i/o to/fr om the card. includes an 11k ? pullup resistor to v dd. c4uc 5 io figure 17 system c ontroller d ata c4 to/from the c ard. includes an 11 k? pull up resistor to v dd. miscellaneous inputs and outputs xtalin/ cl kin 10 i figure 19 crystal oscillator input. this pin can either be connected to crystal or driven as a source for the card clock. xtalout 11 o figure 19 crystal oscillator output. connected to crystal. this pin can be left open if xtalin is being used as external clock input. power supply and ground v dd 7 pso figure 13 system interface supply voltage an d supply voltage for internal circuitry v pc 4 pso figure 13 ldo regulator power supply source
73S8014BN data sheet ds_8014bn_057 8 rev. 2 2 electrical specifications this section provides the following: ? absolute maximum ratings ? recommende d operatin g conditions ? smart card interface requirements ? digita l signals characteristics ? dc characteristics ? voltage fault - detection circuits 2.1 absolute maximum ratings table 2 lists the maximum operating conditions for the 73s 8014bn . permane nt device damage can occur if absolute maximum ratings are exceeded. exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. the smart card interface pins are protected against short circuits to v cc , grou nd, and each other. table 2 : absolute maximum device ratings parameter rating supply voltage range, v dd - 0.5v to 4 .0v dc supply voltage range, v pc - 0.5v to 6.0v dc input voltage for digital inputs - 0.3v to (v dd + 0.5v ) dc stora ge temperature range -60 c to + 150 c pin voltage range (except c ard i nterface) - 0.3v to (v dd + 0.5v ) dc pin voltage range (c ard i nterface) - 0.3v to (v cc + 0.5v ) dc esd tolerance ( card i nterface p ins )* 6kv esd tolerance ( other p ins ) 2kv *esd testing on smart card pins is human body model (hbm) condition, three pulses, each polarity referenced to ground. note: smart card pins are protected against shorts between any combinations of smart card pins. 2.2 recommended operating conditions function operation should be restricted to the recommended operating conditions specified in table 3 . table 3 : recommended operating conditions parameter rating supply voltage range, v dd 2.7 v to 3.6 v dc supply voltage range, v pc 4.75 v to 5.5v dc ambient operating temperature range -40 c to +85 c input voltage for digital inputs 0 to (v dd + 0.3v )
ds_8014bn_057 73S8014BN data sheet rev. 2 9 2.3 smart card interface requirements table 4 lists the 73s 8014bn s mart c ard interface requireme nts. table 4 : dc smart card interface requirements parameter symbol condition s min typ max units card power supply (v cc ) regulator (general conditions: 4.75v < v pc < 5.5v, 2.7v < v dd < 5.5v; - 40 c < t a < +85 c, unless otherwise n oted.) (nds conditions: 4.85v < v pc < 5.5v, unless otherwise noted.) card supply voltage including ripple a nd noise v cc inactive mode - 0.1 + 0.1 v inactive mode, i cc = 1ma - 0.1 + 0.4 active mode; i cc < 65ma; 5v 4.65 5.25 active mode; i cc < 65m a; 5v, nds condition 4.75 5.25 active mode; i cc < 65ma; 3v 2.85 3.15 active mode; single pulse of 100ma for 2 s; 5v, fixed load = 25ma (note 1) 4.6 5.25 active mode; i cc < 40ma; 1.8v 1.68 1.92 active mode; single pulse of 100ma for 2 s; 3v, fixed load = 25ma (note 1) 2.76 3.15 active mode; current pulses of 40nas with peak |i cc | < 200ma, t < 400ns; 5v (note 1) 4.6 5.25 active mode; current pulses of 40nas with peak |i cc | <200ma, t < 400ns; 5v, nds condition (note 1) 4.65 5 .25 active mode; current pulses of 40nas with peak |i cc | <200ma, t < 400ns; 3v (note 1) 2.7 3.15 active mode; current pulses of 20nas with peak |i cc | <100ma, t < 400ns; 1.8v (note 1) 1.62 1.92 v cc ripple v ccrip f ripple = 20 khz C 200mhz (note 1) 350 mv card supply output current i cc max static load current, v cc > 4.6 v or 2.7 v as selected 65 ma static load current, v cc >1.65 40 i cc fault current i ccf v cc = 3v or 5v 70 145 ma v cc = 1.8v 50 110 ma v cc slew rate, rise v sr c f = 1.0 f on v cc 0.06 0.150 0.30 v/ s v cc slew rate, fall v sf c f = 1.0 f on v cc 0.075 0.150 0.60 v/ s external filter cap (v cc to gnd) c fnds nds applications, c f should be ceramic with low esr (< 100m ? ) (note 1) 0.5 1.0 1.5 f
73S8014BN data sheet ds_8014bn_057 10 rev. 2 parameter symbol condition s min typ max units interface requirements data sign als: i/o, c4, c8 hos t interfaces: i/ouc, c4uc, c8uc ( i shortl , i shorth , and v inact requirements do not pertain to i/ouc, c4uc, and c8uc. ) output level high (i/ouc, c4uc, c8uc) v oh i oh = - 40 a 0.9 x v dd v dd + 0.1 v i oh = 0 ma 0.75 x v dd v dd + 0.1 out put level high (i/o, c4, c8) i oh = - 40 a (v cc = 3 v /5v), - 20 a (v cc = 1.8v) 0.9 x v cc v cc + 0.1 i ol = 1ma 0.75 v cc v cc +0.1 output level low (i/ouc, c4uc, c8uc) v ol i ol = 1ma 0.15 x v dd v output level low (i/o, c4, c8) 0.15 x v cc input leve l high (i/ouc, c4uc, c8uc) v ih 0.6 x v dd v dd + 0.30 v input level hig h (i/o, c4, c8) 0.6 x v cc v cc + 0.30 input level low (i/ouc, c4uc, c8uc) v il - 0.15 0.20 x v dd v input level low (i/o, c4, c8) i ol = 0 ma - 0.15 0.20 x v cc output voltage w hen outside of session v inact i ol = 1ma 0.1 v v ih = v cc 0.3 input leakage i leak v il = 0 v 10 a input current low i il for output low, shorted to v cc through 33 ? 0.65 ma sh ort - circuit output current i shortl for output high, shorted to ground through 33 ? 15 ma short - circuit output current i shorth c l = 80pf, 10% to 90% 15 ma output rise time, fall times t r , t f 100 ns input rise, fall times t ir , t if out put stable for > 400ns (note 1) 1 s internal pull u p resistor r pu 8 11 15 k? maximum data rate fd max edge from master to slave, measured at 50% 1 mhz delay, i/o to i/ouc, i/ouc to i/o, c4 to c4uc, c4uc to c4, c8 to c8uc, c8uc to c8 (respectively f alling edge to falling edge and rising edge to rising edge) t fdio 60 100 200 ns t rdio 15 input capacitance c in (note 1) 10 pf
ds_8014bn_057 73S8014BN data sheet rev. 2 11 parameter symbol condition s min typ max units reset and clock for card interface: rst, clk output level high v oh i oh = - 200 a 0.9 x v cc v cc v output level low v ol i ol =200 a 0 0.15 x v cc v output voltage when outside o f session v inact i ol = 0 ma 0.1 v i ol = 1ma 0.3 output current limit, rst i rst_lim 30 ma output current limit, clk i clk_lim 70 ma output rise time, fall time t r , t f c l = 35pf for clk, 10% to 90% 8 ns c l = 200pf for rst, 10% to 90% 100 duty cycle f or clk c l =35pf, f clk 20mhz 45 55 % note 1: g uaranteed by design ; not production tested . 2.4 digital signals characteristics table 5 lists the 73s 8014bn digital signals characteristics. table 5 : digital signals characteristics parameter symbol conditions min typ max units input low voltage v il - 0.3 + 0.8 v input high voltage v ih 1.8 v dd + 0.3 v output low voltage v ol i ol = 2ma 0.45 v output high voltage v oh i oh = - 1ma v dd - 0.45 v pull up r esistor, off r out 13.5 20 26.5 k? input leakage current |i il1 | v gnd < v in < v dd - 5 + 5 a input l evel, clkdiv v incd1 level range 1 - 0.3 + 0.400 v v incd2 level range 2 0.26 x v dd 0.40 x v dd v incd3 level range 3 0.6 x v dd 0.80 x v dd v incd4 level range 4 v dd - 0.400 v dd + 0.3 input low voltage , xtalin v ilx tal - 0.3 0.3 x v dd v input high voltage , xtalin v ihx tal 0.7 x v dd v dd + 0.3 v input current , xtalin i ilxtal v gnd < v in < v dd - 30 + 30 a max f req uency osc illator or external c lock f max 27 mhz external input duty - cy cle limit in t r/ t f < 10% f in , 45% < clk < 55% (note 1) 48 52 % note 1: g uaranteed by design ; not production tested .
73S8014BN data sheet ds_8014bn_057 12 rev. 2 2.5 dc characteristics table 6 lists the 73s 8014bn dc characteristics. table 6 : dc chara cteristics parameter symbol conditions min typ max units v dd supply current i dd v dd = 2.7 v to 3.6v 2.0 4 ma v dd supply current i pd power - d own 1 5 a v pc supply current i pc v cc on, i cc = 0 ma , clk = 2.0mhz, ext ernal load < 10pf, i/o, c4, c8 = high 1 2 ma v pc s upply c urrent i pcpd cmdvcc = 1 1 2 a 2.6 voltage fault - detection circuits table 7 lists the 73s 8014bn voltage and current fault - detection circuits . table 7 : voltage and current fault - detection ci rcuits parameter symbol conditions min typ max units v dd f ault v ddf v dd falling 2.15 2.4 v i cc f ault c urrent i ccf v cc = 3v or 5v 70 145 ma v cc = 1.8v 50 110 v cc f ault (v cc voltage s upervisor t hreshold) v ccf v cc = 5v 4.6 v v cc = 3v 2.7 v cc = 1.8v (note 1) 1.65 note 1: guaranteed by design; not production tested.
ds_8014bn_057 73S8014BN data sheet rev. 2 13 3 applications information this section provides general usage information for the design and implementation of the 73s 8014bn . 3.1 example 73s 8014bn schematics figure 3 shows a typical application schematic for the implementation of the 73s 8014bn . note that minor changes can occur to the reference material from time to time and the reader is encouraged to contact maxim for the latest information.
73S8014BN data sheet ds_8014bn_057 14 rev. 2 c1 nds, emv & iso7816= 1.0uf low esr (<100mohms) c1 should be placed near the sc connector contact clkdiv2_from_uc clk track should be routed far from rst, i/o, c4 and c8. notes: 1) vdd = 2.7v to 3.6v dc.* 2) vpc = 4.75v(iso)/4.85v(nds) to 5.5v dc* 3) required if external clock from up is used. 4) required if crystal is used. y1, c2 and c3 must be removed if external clock is used. see note 2 73S8014BN 1 2 3 4 5 6 7 12 8 9 10 11 13 14 15 16 17 18 19 20 clkdiv c8 vpc pres i/o clk rst vcc c4 rstin vdd gnd xtalout xtalin c8uc smart card connector 1 2 3 4 5 6 7 8 9 10 vcc rst clk c4 gnd vpp i/o c8 sw-1 sw-2 c4 100nf c5 10uf vpc off_interrupt_to_uc c8uc_to/from_uc rstin_from_uc cmdvcc_from_uc see note 4 y1 crystal c2 22pf c3 22pf external_clock_from uc see note 3 - or - vdd r4 1k card detection switch is normally open 47k r2 * do not begin a nds card session until vpc > 4.85v and vdd > vth (vdd fault threshold) off 5v3v cmdvcc c4uc i/ouc i/ouc_to/ from_uc c4uc_to/from_uc 5v/#v_select_from_uc see note 1 c6 100nf vdd see note 5 5) since the internal pres pull down is weak, it is recommended that an external pull down is included 6) pull down resistor r5 must be installed when using vcc = 1.8v, optional otherwise r5 20k see note 6 figure 3 : 73s 8014bn typical application schematic
ds_8 014bn_057 73S8014BN data sheet rev. 2 15 3.2 system controller interface three digital inputs allow direct control of the card interface by the host. the 73s 8014bn is cont rolled as follows: ? pin cmdvcc : when asserted low, starts an activation sequence . when deasserted high, starts deactivation sequence. ? pin rstin: c ontrols the card rst signal (when enabled by the sequencer) w hile the card is activated and the power - down mode when the card is not activated . ? pin 5v/ 3 v : defines the card v dd voltage according to table 8 . table 8 : v cc voltage logic table control pins v cc voltage (v) notes cmdvcc 5v/ 3 v 1 x 0 off 1 5 5v/ 3 v mu st be stable for at least 1 s before assertion of cmdvcc and held high until de assertion of cmdvcc. 0 3 5v/ 3 v must be stable for at least 1 s before assertion of cmdvcc and held low until de assertion of cmdvcc. 1.8 must be asserted low within 400ns of each other to generate 1.8v and held low until assertion of cmdvcc . the off digital output reports status back to the host . see the fault detection and off section for details on the operation of the off output . note: 5v/ 3 v should not change during a card session. doing so does not change the voltage on v cc during that session, but if it is changed, the 5v / 3 v must be taken high outside the current card session and before beginning the next card session. otherwise, the next card session may not power up to the selected v cc voltage. 3.3 power - d own m ode the 73s 8014bn includes a power - down mode to greatly reduce the power consumption on the v dd and v pc supplies when the smart card interface is de activated. the power - down mode shut s down the crystal oscillat or and other internal circuits to save power. when the power - down mode is released, the oscillator is restarted. it require s some t ime to start up and stabilize. during this time, the off output goes low (if a card is inserted) and is held low until the os cillator stabilize s , and then the off output goes high to indicate that the device is ready to activate the card. the power - down mode is initiated when rstin, cmdvcc , and 5 v / 3 v are all logic - high for more than 2ms. the power - down mode is released immediat ely by bringing rstin low. this action force s the off output low for a pproximately 5 ms to 7 ms to allow the oscillator to start up and stabilize. this action inform s the host that the 73s 8014bn is busy and should not be activated while the off output is low . this e nsures a proper activation sequence after coming out of power - down. the card - detection logic on the pres input remains active in power - down mode. the card status is reported on off . note: t he cmdvcc and 5v/ 3 v inputs have no effect when exiting po wer - down. bringing rstin low is th e only way to exit power - down. figure 4 shows the power - down mode control t iming with pres debounce. see s ection 3.9 for a full description of the pres debounce behavior.
73S8014BN data sheet ds_8014bn_057 16 rev. 2 cmdvcc 5v/#v rstin pres pwr_down off this is a sequence of pres events during the time when the host is requesting power down by setting cmdvcc = 5v/#v = rstin = high. in such a sequence, the circuit has to sense pres and de-assert power down and time (de-bounce) the pres signal, or assert the power down as appropriate. 5 - 7ms when power down is de-asserted (rstin=low), offb will go low indicating circuit is not ready, and then go high after 5ms (if pres is high) 2ms 5ms 5ms figure 4 : power - down mode and pres d ebounce 3.4 power supply and voltage supervision the 73s 8014bn smart card interface ic incorporate s a low dropout (ldo ) voltage regulator fo r v cc . the voltage output is controlled by the digital input 5v/ 3 v of the 73s 8014bn . this regulator can provide 1.8v, 3v , or 5v card voltage from the power supply applied on the v pc pin. the voltage regulator can provide a current of at least 65ma on v cc f or both 3v and 5v or 40ma for 1.8v that complies with emv 4.0 and nds specifications. an overcurrent supervisor trigger s a fault if the current on v cc exceeds the threshold at the given v cc voltage. digital circuitry is powered by the power supply applied on the v dd pin. v dd is sourced by 2.7 to 3.6v so the system controller must operate with this supply level . a card deactivation sequence is forced upon fault of any voltage or overcurrent supervisor. one supervisor monitors the v c c output voltage at the selected v cc voltage level. the maximum v cc voltage - fault threshold does not exceed the minimum v cc voltage spec according to iso 7816. see v ccf specification for the v cc voltage thresholds. another voltage supervisor constantly monitors the v dd voltage. this fixed threshold supervisor is used to initialize the iso 7816 - 3 sequencer at power - on and to deactivate the card at power - off or upon fault. the voltage threshold of the v dd voltage supervisor is internally set to 2.26v ty pical ( v ddf ). if an adjustable v dd threshold (>2.26v) is required on the device , then the 73s8024rn should be considered or an external circuit configured for the desired v dd threshold should be added to the circuit to control either the cmdvcc or pres input for an immediate v cc deactivation. note: since the v dd and the v pc power supplies are separate, special care must be taken to e nsure that the v pc voltage is greater than 4.85v before beginning a ctivating the card. in addition, v dd must be grea ter than the threshold for v dd fault before card activation. when turning off power to the v dd and the v pc power supplies, the card should be d eactivated before shutdown or the v pc power supply must remain higher than 4.85v when the v dd fault is detected a nd the emergency deactivation sequence is completed. 3.5 card power supply the 73s 8014bn smart card interface ic incorporates a n ldo voltage regulator for v cc . the voltage output is controlled by the digital inputs 5v/ 3 v and cmdvcc of the 73s 8014bn . this reg ulator can provide 1.8v, 3v , or 5v card voltage from the power supply applied on the v pc pin. the voltage regulator can provide a current of at least 65ma on v cc for both 3v and 5v and 40ma for 1.8v that complies with emv 4. 2 and nds specifications. note: when using v cc = 1.8v , a minimum load is required on v cc to e nsure proper output regulator stability. a 20 k ? resistor is required between v cc and gnd to meet this minimum load requirement. if v cc = 1.8v is never used in a given application, the resistor is not required.
ds_8 014bn_057 73S8014BN data sheet rev. 2 17 3.6 on - chip oscillator and card clock the 73s 8014bn device ha s an on - chip oscillator that can generate the smart card clock using an external crystal (connected between xtalin and xtalout) to set the oscillator frequency. when the clock signal is available from another source it can be connected to xtalin, and xtalo ut should be left unconnected. for th is device t he card clock frequency can be chosen among four different division rates, defined by multiple - state input clkdiv, as per the followin g table: clkdiv clk max xtalin/clkin (mhz) gnd 1/4 xtalin 27 v dd /3 xtalin 20 v dd x 2/3 1/8 xtalin 27 v dd 1/2 xtalin 27 note: the clock - divider ratio must be configured prior to activation and must not change during the card session. note: special c are should be taken when configuring the clkdiv input when using the power - down mode. the clkdiv input does not contain an internal pullup or pulldown so it must not be allowed to be left unconnected . in addition, the clkdiv input should be set in such a m anner as to set the voltage level to gnd or v dd to keep the current consumption to an absolute minimum. there are numerous simple methods available to control clkdiv as shown in figure 5. clkdiv pin host i/o pin 1. selecting between divide by 2 (i/o high) or divide by 4 (i/o low) clkdiv pin host i/o pin 2. selecting between divide by 2 (io high) or divide by 8 (io low) vdd clkdiv pin host i/o pin 1 host i/o pin 2 3. selecting any of the four divide ratios r 2r 2r r figure 5 : cl kdiv u sage
73S8014BN data sheet ds_8014bn_057 18 rev. 2 3.7 activation sequence the 73s 8014bn smart card interface ic ha s an internal 1ms delay on the application of v dd where v dd > v ddf . no activation is allowed during this 1ms period. the cmdvcc (edge triggered) signal must then be set low to activate the card. t o initiate activation , the card must be present and there can be no v dd fault. the following steps show the activation sequence and the timing of the card control signals when the system controller sets cmdvcc low while the rstin is low: ? cmdvc c is set low at t 0 . ? v cc rise s to the selected level and then the internal v cc control circuit checks the presence of v cc at the end of t 1 . in normal operation, the voltage v cc to the card becomes valid before t 1 . if v cc is not valid at t 1 , off goes low to report a fault to the system controller, and v cc to the card is shut off. ? turn i/o to reception mode at t 2 . ? clk is applied to the card at t 3 . ? rst is a copy of rstin after t 3 . cmdvcc vcc i / o clk rstin t 1 t 2 t 3 rst t 0 t 1 = 0. 2 ms (timing by 1.5mhz internal oscillato r) t 2 = 1.5 s, i/o goes to reception state t 3 = > 0.5 s, clk starts, rst to become the copy of rstin figure 6 : activation sequence rstin low when cmdvcc goes low the startup of the clk output can be delayed in the activation sequence by setting the rstin input high before beginning activation by bringing cmdvcc low. the clk output is delayed until rstin is taken low. special care must be taken when performing this type of activation. the power - down mode is initiated by setting the rstin and 5v/ 3 v inputs high while cmdvcc is high (outside a card session). if this state is held for more than 2ms, the power mode is initiated . as a result, to use this activation mode, the cmdvcc falling edge must occur within 1ms of the rstin input being set high. the following steps show the activation sequence and the timing of the card control signals when the system controller pulls the cmdvcc low while the rstin is high: ? cmdvcc is set low at t 0 . ? v cc rise s to the selected level and then the int ernal v cc control circuit checks the presence of v cc at the end of t 1 . in normal operation, the voltage v cc to the card becomes valid before t 1 . if v cc is not valid at t 1 , off goes low to report a fault to the system controller, and v cc to the card is shut off. ? at the fall of rstin (under host control) at t 2 , clk is applied to the card . ? rst is a copy of rstin after t 2 .
ds_8 014bn_057 73S8014BN data sheet rev. 2 19 cmdvcc vcc i/o clk rstin t 1 t 2 t 0 rst t 1 = 0. 2 ms (timing by 1.5mhz internal oscillator, i/o goes to reception state) t 2 = rstin goes low and cl k becomes active t 3 = > 0.5 s, clk active, rst to become the copy of rstin figure 7 : activation sequence rstin high when cmdvcc goes low 3.8 deactivation sequence deactivation is initiated either by the system controller by setting the cmdvcc high or automatically in the event of hardware faults. hardware faults are overcurrent, v dd fault, v cc fault, and card extraction during the session. the following steps show the deactivation sequence and the timing of the card control signal s when the system controller sets the cmdvcc high or off goes low due to a fault or card removal: ? rst goes low at the end of t 1 . ? clk is set low at the end of t 2 . ? i/o goes low at the end of t 3 . out of reception mode. ? v cc is shut down at the end of time t 4 . after a delay t 5 (discharge of the v cc capacitor), v cc is low. rst clk i/o vcc t 1 t 2 t 3 t 4 t 5 cmdvcc -- or -- off t 1 = > 0.5 s, timing by 1.5mhz internal o scillator t 2 = > 7.5 s t 3 = > 0.5 s t 4 = > 0.5 s t 5 = depends on v cc filter capacitor for nds ap plication, c f =1 f makes t 1 + t 2 + t 3 + t 4 + t 5 < 100 s figure 8 : deactivation sequence
73S8014BN data sheet ds_8014bn_057 20 rev. 2 3.9 fault detection and off there are two different cases that the system controller can monitor the off signal: to query regarding the card p resence and device readiness outside card sessions, or for fault detection during card sessions. the off interrupt output operates as follows: as long as the card is not activated ( cmdvcc is always high ), off informs the host about the card presence or dev ice readiness. when no card is inserted, the off output is low. when a card is inserted, the off output is set high after a 5ms debounce period . upon card removal, there is no debounce on the pres input as the emergency deactivation must occur as soon as p ossible to prevent any potential card errors or data corruption. the off output go es low immediately upon detection of a logic - low on the pres input, but the off output does not bounce and remain s low for at least 5ms . in addition, when a card is present a nd the power - down mode is released, the off output is taken low for about 5ms to indicate that the device is not ready. this time allows the crystal oscillator to start up and stabilize. when cmdvcc is asserted low ( card activation sequence requested from the host), low level on off means a fault has been detected (e.g. , card removal during card session, voltage fault, or overcurrent fault) that automatically initiates a deactivation sequence . figure 9 shows the timing diagram for the signals cmdvcc , pres, and off while the card is activated and deactivated: pres off cmdvcc vcc outside card session within card session off is low by card extracted off is low by any fault within card session figure 9 : timing diagram management of the interrupt line off 3.10 i/o , c4 , and c8 circuitry and tim ing the i/o, c4, and c8 are smart card data signals that operate identically , and i/ouc, c4uc, and c8uc are the corresponding microcontroller interface signals . the i/o and i/ouc data signal s are described henceforth. the state of the i/o and i/ouc pins ar e low after power - on reset and goes high when the activation sequencer turns on the i/o reception state. see the activation sequence section for details on when the i/o reception is enabled. the state of i/ouc is high after power - on reset. when the card is activated and the i/o reception state is turned on, the first i/o line on which a falling edge is detected becomes the input i/o line and the other becomes the output i/o line. when the input i /o line rising edge is detected , both i/o lines return to their neutral state. note: in certain situations and conditions, the i/o logic can get confused if the host and the card attempt to drive the i/ouc and the i/o signal low at the same time. it shoul d be noted that this is an illegal condition as all card communication is initiated by the host with a command/response protocol. the next host command should not be sent until a valid response has been completely received from the card. however, if this c ondition should occur, the 73S8014BN could set both i / ouc and i/o as outputs where they are both driven low at the same time. when either side drives their respective signal high, this mode should be released. h owever, if there is a series resistance betwe en the host and the 73S8014BN, there may not be enough drive to release this mode. if the series resistance is greater than a pproximately 100? , this can cause this mode to become locked for the duration of the card session. i f the host detects this conditi on (i / ouc held low for more than 1 byte time), the card session must be terminated and restarted.
ds_8 014bn_057 73S8014BN data sheet rev. 2 21 figure 10 shows the state diagram of how the i/o and i/ouc lines are managed to become input or output. t he delay between the i/o signals is shown in figure 11. neutral state i/ouc in i/o reception i/oicc in no yes no no no yes no yes i/o & not i/ouc i/ouc & not i/o i/ouc i/o yes yes figure 10 : i/o and i/ouc state diagram i/o i/ouc t i/o_hl t i/o_lh t i/ouc_hl t i/ouc_lh delay from i/o to i /ouc: t i/o_hl = 100ns t i/o_lh = 25ns delay from i/ouc to i/o: t i/ouc_hl = 100ns t i/ouc_lh = 25ns figure 11: timing diagram i/o to i/ouc delays
73S8014BN data sheet ds_8014bn_057 22 rev. 2 4 equivalent circuits this section provides illustrations of circuits equivalent t o those described in the pinout section. pin vdd strong nfet data from circuit output disable 20k esd figure 12 : open- drain t ype off pin esd to internal circuits figure 13 : power input/output circuit v dd , v pc , v cc
ds_8 014bn_057 73S8014BN data sheet rev. 2 23 figure 14 : smart card clk driver circuit figure 15 : sma rt card rst driver circuit clk pin vcc very strong pfet very strong nfet from circuit esd esd rst pin vcc strong pfet strong nfet from circuit esd esd
73S8014BN data sheet ds_8014bn_057 24 rev. 2 figure 16 : smart card i/o , c4, and c8 interface circuit 400ns delay i/ouc pin vdd strong pfet strong nfet rl=11k from circuit cmos to circuit esd esd figure 17 : smart card i/ouc interface circuit 400ns delay i/o, c4, and c8 pin vcc strong pfet strong nfet rl=11k from circuit cmos to circuit esd esd
ds_8 014bn_057 73S8014BN data sheet rev. 2 25 figure 18 : general input circuit pin pin vdd xtalin/ clkin xtalout enableb enable esd esd esd esd very weak fets strong nfet strong nfet strong pfet strong pfet figure 19 : oscillator circuit pin vdd ttl to circuit pull-up disable very weak pfet esd very weak nfet pull-down enable esd note: 5v / 3 v has the pullup enabled. pres has the pulldown enabled. cmdvcc and rstin have pullup and pulldown disabled.
73S8014BN data sheet ds_8014bn_057 26 rev. 2 clkdiv pin vdd vin>vmid esd + - + - + - vmid vlow vhigh vin>vlow vin>vhigh esd figure 20: clkdiv
ds_8 014bn_057 73S8014BN data sheet rev. 2 27 5 mechanical drawing 0.505(12.83) 0.406(10.31) 0.296(7.52) + .003(.07) - .004(.10) .005(.127) + .004(.10) - .006(.15) base plane seating plane 0.505(12.83) 0.009 (.22) 0.092 (2.34) .002(.05) 0.016(.41) 0.050(1.27) typ + .003(.07) - .002(.06) .005(.127) + .0025(.07) - .004(.093) 0.01(.25) + .0025(.007) - .0009(.002) detail a .032 (.81) detail a 0- 8 .008(.20) figure 21: mechanical drawing 20 - pin so package inches (mm)
73S8014BN data sheet ds_8014bn_057 28 rev. 2 6 ordering information table 9 lists the order numbers and packaging marks used to identify 73s 8014bn products. table 9 : order numbers and packaging marks part pin - package top mark 73S8014BN - il/f 20 so 73s 8014bn 73S8014BN - ilr/f 20 so 73s 8014bn f = lead(pb) - free/rohs - compliant package. r = tape and reel. 7 contact information for more information about maxim products or to check the availability of the 7 3s8014bn , contact technical support at www.maxim - ic.com /support .
ds_8 014bn_057 73S8014BN data sheet rev. 2 29 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no cir cuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 20 1 1 maxim integrated products maxim is a registered trademark of maxim integrated products. revision history revision number revision date description pages changed 1.0 12/10 initial release 2 1 2 /11 deleted certification pending from the nds logo. added designed to provide full electrical compliance with iso 7816- 3, emv? 4.2 , and nds specifications to the first sentence. added for nds applications requiring an on - chip adjustable por, see the maxim 73s8024rn series of interface ics. to the first paragraph. 1 provided additional description to section 3.4. 16

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