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| preliminary w78e516 8-bit microcontroller publication release date: sep. 1998 - 1 - revision a0 general description the w78e516 is an 8-bit microcontroller which has an in-system programmable mtp-rom for on-chip firmware updating. the instruction set of the w78e516 is fully compatible with the standard 8052. the w78e516 contains a 64k bytes of main mtp-rom and a 4k bytes of auxiliary mtp-rom which allows the contents of the 64kb main mtp-rom to be updated by the loader program located in the 4kb mtp-rom; a 512 bytes of ram; four 8-bit bi-directional and bit-addressable i/o ports; an additional 4-bit port p4; three 16-bit timer/counters; a serial port. these peripherals are supported by a six sources two-level interrupt capability. to facilitate programming and verification, the mtp-rom inside the w78e516 allows the program memory to be programmed and read electronically. once the code is confirmed, the user can protect the code for security. the w78e516 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. the idle mode turns off the processor clock but allows for continued peripheral operation. the power-down mode stops the crystal oscillator for minimum power consumption. the external clock can be stopped at any time and in any state without affecting the processor. features fully static design 8-bit cmos microcontroller up to 40mhz. 64k bytes of in-system programmable mtp-rom for application program (aprom). 4k bytes of auxiliary mtp-rom for loader program (ldrom). 512 bytes of on-chip ram. (including 256 bytes of aux-ram, software selectable) 64k bytes program memory address space and 64k bytes data memory address space. four 8-bit bi-directional ports. one 4-bit general purpose i/o port. three 16-bit timer/counters one full duplex serial port six-sources, two-level interrupt capability built-in power management code protection package -dip 40 :w78e516-24/40 -plcc 44 :w78e516p-24/40 -pqfp 44: w78e516f-24/40 -tqfp 44: w78e516m-24/40
preliminary w78e516 - 2 - pin configurations : vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 p0.0, ad0 p0.1, ad1 p0.2, ad2 p0.3, ad3 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.5, a13 p2.6, a14 p2.7, a15 p2.0, a8 p2.1, a9 p2.2, a10 p2.3, a11 p2.4, a12 t2, p1.0 40-pin dip (w78e516) p1.2 p1.3 p1.4 p1.5 p1.6 rxd, p3.0 txd, p3.1 p1.7 rst int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 wr, p3.6 rd, p3.7 xtal1 xtal2 vss t2ex, p1.1 44-pin plcc (w78e516p) 44-pin qfp/tqfp (w78e516f/w78e516m) 40 2 1 44 43 42 41 6543 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 p4.1 p 4 . 0 int2, p4.3 / i n t 3 , p 4 . 2 34 40 39 38 37 36 35 44 43 42 41 33 32 31 30 29 28 27 26 25 24 23 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 22 21 20 19 18 17 16 15 14 13 12 11 4 3 2 1 8 7 6 5 10 9 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 p 4 . 0 / i n t 3 , p 4 . 2 p4.1 int2, p4.3 preliminary w78e516 publication release date: sep. 1998 - 3 - revision a0 pin description symbol type descriptions ea i external access enable: this pin forces the processor to execute the external rom. the rom address and data will not be present on the bus if the ea pin is high and the program counter is within the 48 kb area. otherwise they will be present on the bus. psen o h program store enable: psen enables the external rom data in the port 0 address/data bus. when internal rom access is performed, no psen strobe signal outputs originate from this pin. ale o h address latch enable: ale is used to enable the address latch that separates the address from the data on port 0. ale runs at 1/6th of the oscillator frequency. an ale pulse is omitted during external data memory accesses. rst i l reset: a high on this pin for two machine cycles while the oscillator is running resets the device. xtal1 i crystal 1: this is the crystal oscillator input. this pin may be driven by an external clock. xtal2 o crystal 2: this is the crystal oscillator output. it is the inversion of xtal1. v ss i ground: ground potential. v dd i power supply: supply voltage for operation. p0.0 - p0.7 i/o d port 0: function is the same as that of the standard 8052. p1.0 - p1.7 i/o h port 1: function is the same as that of the standard 8052. p2.0 - p2.7 i/o h port 2: port 2 is a bi-directional i/o port with internal pull-ups. p3.0 - p3.7 i/o h port 3: function is the same as that of the standard 8052. p4.0 - p4.3 i/o h port 4: a bi-directional i/o port with alternate function. see details below. * note : type i: input, o: output, i/o: bi-directional, h: pull-high, l: pull-low, d: open drain port 4 port 4, sfr p4 at address d8h, p4.0~p4.3 is a bi-directional i/o port which is same as port 1. p4.2 and p4.3 also serve as external interrupt int3 and int2 if enabled. preliminary w78e516 - 4 - block diagram p3.0 p3.7 p1.0 p1.7 alu port 0 latch port 1 latch timer 1 timer 0 timer 2 port 1 uart xtal1 psen ale vss vcc rst xtal2 oscillator interrupt psw instruction decoder & sequencer reset block bus & clock controller sfr ram address power control 512 bytes ram & sfr stack pointer b addr. reg. incrementor pc dptr temp reg. t2 t1 acc port 3 latch port 4 latch port 3 port 2 latch p4.0 p4.3 port 4 port 0 port 2 p2.0 p2.7 p0.0 p0.7 64kb mtp-rom 4kb mtp-rom int2 / int3 functional description the w78e516 architecture consists of a core controller surrounded by various registers, four general purpose i/o ports, one special purpose programmable 4-bits i/o port, 512 bytes of ram, three timer/counters, a serial port ,and an internal 74373 latch and 74244 buffer which can be switched to port2. the processor supports 111 different opcodes and references both a 64k program address space and a 64 k data storage space. ram the internal data ram in w78e516 is 512x 8 bytes. it is divided into two banks: 256 bytes of ram and 256 bytes of aux-ram . these rams are addressed by different ways. ram 0h ~127h can be addressed directly and indirectly as the same as in 8051. address pointers are r0 and r1 of the selected register bank. ram 128h~255h can only be addressed indirectly as the same as in 8051. address pointers are r0,r1 of the selected registers bank. preliminary w78e516 publication release date: sep. 1998 - 5 - revision a0 aux-ram 0h~255h is addressed indirectly as the same way to access external data memory with the movx instruction. address pointer are r0 and r1 of the selected register bank and dptr register. an access to external data memory locations higher than 255 will be performed with the movx instruction in the same way as in the 8051. the aux-ram is disable after power-on reset. setting the bit 4 in chpcon register will enable the access to aux-ram. when aux-ram is enabled the instructions of "movx @ri" will always access to the on-chip aux-ram. on-chip mtp-rom the w78e516 includes one 64k bytes of main mtp-rom for application program (aprom) and one 4k bytes of mtp-rom for loader program (ldrom) when operating the in-system programming feature. in normal operation, the microcontroller will excute the code from the 64k bytes of main mtp- rom. by setting program registers, user can force microcontroller to switch to the the programming mode which microcontroller will excute the code (loader program) from the 4k bytes of auxiliary mtp- rom, and this loader program is going to update the contents of the 64k bytes of main mtp-rom. after reset, the microcontroller executes the new application program in the main mtp-rom. this in- system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. in some applications, the in-system programmimg feature make it possible that the end-user is able to easily update the system firmware by themselve without opening the chassis. timers 0, 1, and 2 timers 0, 1, and 2 each consist of two 8-bit data registers. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for timer 2. the tcon and tmod registers provide control functions for timers 0, 1. the t2con register provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture registers for timer 2. the operations of timer 0 and timer 1 are the same as in the w78c51. timer 2 is a 16-bit timer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit c/t2 in t2con. timer 2 has three operating modes: capture, auto-reload, and baud rate generator. the clock speed at capture or auto-reload mode is the same as that of timers 0 and 1. int2 / int3 two additional external interrupts, int2 and int3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80c52. the functions/status of these interrupts are determined/shown by the bits in the xicon (external interrupt control) register. the xicon register is bit-addressable but is not a standard register in the standard 80c52. its address is at 0c0h. to set/clear bits in the xicon register, one can use the "setb (/clr) bit" instruction. for example, "setb 0c2h" sets the ex2 bit of xicon. ***xicon - external interrupt control (c0h) px3 ex3 ie3 it3 px2 ex2 ie2 it2 px3: external interrupt 3 priority high if set ex3: external interrupt 3 enable if set ie3: if it3 = 1, ie3 is set/cleared automatically by hardware when interrupt is detected/serviced it3: external interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software px2: external interrupt 2 priority high if set ex2: external interrupt 2 enable if set ie2: if it2 = 1, ie2 is set/cleared automatically by hardware when interrupt is detected/serviced preliminary w78e516 - 6 - it2: external interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software eight-source interrupt informations: interrupt source vector address polling sequence within priority level enable required settings interrupt type edge/level external interrupt 0 03h 0 (highest) ie.0 tcon.0 timer/counter 0 0bh 1 ie.1 - external interrupt 1 13h 2 ie.2 tcon.2 timer/counter 1 1bh 3 ie.3 - serial port 23h 4 ie.4 - timer/counter 2 2bh 5 ie.5 - external interrupt 2 33h 6 xicon.2 xicon.0 external interrupt 3 3bh 7 (lowest) xicon.6 xicon.3 clock the w78e516 is designed to be used with either a crystal oscillator or an external clock. internally, the clock is divided by two before it is used by default. this makes the w78e516 relatively insensitive to duty cycle variations in the clock. crystal oscillator the w78e516 incorporates a built-in crystal oscillator. to make the oscillator work, a crystal must be connected across pins xtal1 and xtal2. in addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from xtal1 to xtal2 to provide a dc bias when the crystal frequency is above 24 mhz. external clock an external clock should be connected to pin xtal1. pin xtal2 should be left unconnected. the xtal1 input is a cmos-type input, as required by the crystal oscillator. as a result, the external clock signal should have an input one level of greater than 3.5 volts. power management idle mode the idle mode is entered by setting the idl bit in the pcon register. in the idle mode, the internal clock to the processor is stopped. the peripherals and the interrupt logic continue to be clocked. the processor will exit idle mode when either an interrupt or a reset occurs. power-down mode when the pd bit of the pcon register is set, the processor enters the power-down mode. in this mode all of the clocks, including the oscillator are stopped. the only way to exit power-down mode is by a reset. reset the external reset signal is sampled at s5p2. to take effect, it must be held high for at least two machine cycles while the oscillator is running. an internal trigger circuit in the reset line is used to preliminary w78e516 publication release date: sep. 1998 - 7 - revision a0 deglitch the reset line when the w78e516 is used with an external rc network. the reset logic also has a special glitch removal circuit that ignores glitches on the reset line. during reset, the ports are initialized to ffh, the stack pointer to 07h, pcon (with the exception of bit 4) to 00h, and all of the other sfr registers except sbuf to 00h. sbuf is not reset. w78e516 special function registers (sfrs) and reset values f8 ff f0 +b 00000000 chpenr 00000000 f7 e8 ef e0 +acc 00000000 e7 d8 +p4 xxxx1111 df d0 +psw 00000000 d7 c8 +t2con 00000000 rcap2l 00000000 rcap2h 00000000 tl2 00000000 th2 00000000 cf c0 xcion 00000000 c7 b8 +ip 00000000 bf b0 +p3 00000000 b7 a8 +ie 00000000 af a0 +p2 11111111 a7 98 +scon 00000000 sbuf xxxxxxxx 9f 90 +p1 11111111 97 88 +tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 8f 80 +p0 11111111 sp 00000111 dpl 00000000 dph 00000000 pcon 00110000 87 note: 1.the sfrs marked with a plus sign(+) are both byte- and bit-addressable. 2. the text of sfr with bold type characters are extension function registers. in-system programming mode enable register (chpenr) (f6h) the chpcon is read only by default .you must write #87, #59h sequentially to this special register chpenr to enable the chpcon write attribute, and write other value to disable chpcon write attribute. this register protects from writing to the chpcon register carelessly. sfrah,sfral: the objective address of on-chip mtp-rom in programming mode. sfrfah contains the high-order byte of address, sfrfal contains the low-order byte of address. sfrfd : the programming data for on-chip flash memory in programming mode. sfrcn : the control byte of on-chip flash memory programming mode. sfrcn (c7) preliminary w78e516 - 8 - bit name function 7 - reserve. 6 wfwin on-chip mtp-rom bank select for in-system programming. =0 : 64k bytes mtp-rom bank is selected as destination for re-programming. =1 : 4k bytes mtp-rom bank is selected as destination for re-programming. 5 oen mtp-rom output enable. 4 cen mtp-rom chip enable. 3,2,1,0 ctrl[3:0] the flash control signals mode ctrl<3:0> wfwin oen cen sfrah,sfral sfrfd erase 64kb aprom 0010 0 1 0 x x program 64kb aprom 0001 0 1 0 address in data in read 64kb aprom 0000 0 0 0 address in data out in-system programming control register (chpcon) chpcon (bfh) bit name function 7 swreset ( f04kmode) when this bit is set to 1, and both fbootsl and fprogen are set to 1. it will enforce microcontroller reset to initial condition just like power on reset. this action will re-boot the microcontroller and start to normal operation. to read this bit can determine that the f04kboot mode is running. 6 - reserve. 5 - reserve. 4 enauxram =1: enable on-chip aux-ram. =0: disable the on-chip aux-ram 3 0 must set to 0. 2 0 must set to 0. 1 fbootsl the loader program location select. 0: the loader program locates at the 64kb flash memory bank. 1: the loader program locates at the 4kb flash memory bank. 0 fprogen mtp-rom programming enable 1:enable. the microcontroller switches to the programming flash mode after entering the idle mode and waken up from interrupt. the microcontroller will execute the loader program while in on-chip programming mode. 0:disable. the on-chip flash memory is read-only. in-system programmability is disabled. f04kboot mode (boot from 4k bytes of ldrom ) the w78e516 boots from aprom program (64k bytes) by default at power on reset. on some occasions, user can force the w78e516 to boot from the ldrom program (4k bytes) at a power on reset via following settings. f04kboot mode preliminary w78e516 publication release date: sep. 1998 - 9 - revision a0 p4.3 p2.7 p2.6 mode x l l fo4kboot l x x fo4kboot note1: the possible situation that you need to enter f04kboot mode is when the aprom program can not run normally and w78e516 can not jump to ldrom to execute on chip programming function. then you can use this f04kboot mode to force the w78e516 jump to ldrom and run the in-system programming procedure. when you design your system, you can connect the pins p2.6,p2.7 to switches or jumpers. when the aprom program is fail to execute the normal application program user can force the w78e516 to enter the f04kboot mode and resume the in-system programming procedure for recovering the aprom code. note2: in application system design, user must take care the p2, p3, ale, /ea and /psen pin value at reset to avoid w78e516 entering the programming mode or f04kboot mode in normal operation. p2.7 p2.6 rst 300ms hi-z the reset timing for entering f04kboot mode 10ms hi-z preliminary w78e516 - 10 - start the algorithm of in-system programming enter in-system programming mode ? (conditions depend on user's application) setting control registers mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h setting timer (about 1.5us) and enable timer interrupt start timer and enter idle mode. ( cpu will be wakened from idle mode by timer interrupt, then enter in-system programming mode) execute the normal application program no yes end cpu will be wakened by interrupt and re-boot from 4kb ldrom to execute the loader program. go part 1:64kb aprom procedure of entering in-system programming mode preliminary w78e516 publication release date: sep. 1998 - 11 - revision a0 part 2: 4kb ldrom procedure of updating the 48kb aprom go timer interrupt service routine: stop timer & disable interrupt is f04kboot mode? (chpcon.7=1 or chpcon.0=0) reset the chpcon register: mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h no yes setting timer and enable timer interrupt for wake-up . (15ms for erasing operation) setting erase operation mode: mov sfrcn,#22h (erase 48kb aprom) start timer and enter idle mode. (erasing...) end of erase operation. cpu will be wakened by timer interrupt. pgm pgm setting timer and enable timer interrupt for wake-up . (150us for program operation) end of programming ? get the parameters of new code (address and data bytes) through i/o ports, uart or other interfaces. is currently in the f04kboot mode ? setting control registers for programming: mov sfrah,#address_h mov sfral,#address_l mov sfrfd,#data mov sfrcn,#21h software reset cpu and re- boot from the48kb aprom. mov chpenr,#87h mov chpenr,#59h mov chpcon,#83h end executing new code from address 00h in the 48kb aprom. hardware reset to re- boot from new 48kb aprom. (s/w reset is invalid in f04kboot mode) yes no yes no note: setting the chpcon from 00h to 03h will clear the program counter (pc). security preliminary w78e516 - 12 - during the on-chip mtp-rom programming mode, the mtp-rom can be programmed and verified repeatedly. until the code inside the mtp-rom is confirmed ok, the code can be protected. the protection of mtp-rom and those operations on it are described below. the w78e516 has several special setting registers, including the security register and company/device id registers, which can not be accessed in programming mode. those bits of the security registers can not be changed once they have been programmed from high to low. they can only be reset through erase-all operation. the contents of the company id and device id registers have been set in factory. the security register is located at the 0fffh on the 4kb ldrom. lock bits these bits are used to protect the customer's program code in the w78e516. it may be set after the programmer finishes the programming and verifies sequence. once these bits are set to logic 0, both the mtp-rom data and special setting registers can not be accessed again. movc inhibit these bits are used to restrict the accessible region of the movc instruction. it can prevent the movc instruction in external program memory from reading the internal program code. when these bits are set to logic 0, a movc instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. a movc instruction in internal program memory space will always be able to access the rom data in both internal and external memory. if these bits are logic 1, there are no restrictions on the movc instruction. encryption this bit is used to enable/disable the encryption logic for code protection. once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. only whole chip erase will reset this bit. b0 b1 b0 : lock bit, logic 0 : active b1 : movc inhibit, logic 0 : the movc instruction in external memory cannot access the code in internal memory. logic 1 : no restriction. default 1 for each bit. special setting registers company id (#dah) d7 d6 d5 d4 d3 d2 d1 d0 11011010 device id (#62h) 111 00 00 security bits 0 4kb ldrom program memory reserved security register 0ffffh 0000h 0fffh reserved b2 b1 : encryption logic 0 : the encryption logic enable logic 1 : the encryption logic disable preliminary w78e516 publication release date: sep. 1998 - 13 - revision a0 absolute maximum ratings item symbol parameter min. max. unit 1 v dd - v ss dc power supply -0.3 +6.0 v 2v in input voltage v ss -0.3 v dd +0.3 v 3t a operating temperature 0 70 c 4t st storage temperature -55 +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. d.c. electrical characteristics (v dd -v ss = 5v 10%, t a = 25 c, fosc = 20mhz, unless otherwise specified.) symbol parameter specification test conditions min max unit v dd operating voltage 4.5 5.5 v rst=1, p0 = v dd i dd operating current - 20 ma no load v dd =5.5v i idle idle current - 6 ma idle mode v dd =5.5v i pwdn power down current - 50 m a power-down mode v dd =5.5v i in1 input current p1, p2, p3, p4 -50 +10 m a v dd =5.5v v in =0v or v dd i in2 input current rst -10 +300 m a v dd =5.5v 0 preliminary w78e516 publication release date: sep. 1998 - 15 - revision a0 program fetch cycle parameter symbol min. typ. max. unit notes address valid to ale low t aas 1 t cp - d --ns 4 address hold from ale low t aah 1 t cp - d - - ns 1, 4 ale low to psen low t apl 1 t cp - d --ns 4 psen low to data valid t pda --2 t cp ns 2 data hold after psen high t pdh 0 -1 t cp ns 3 data float after psen high t pdz 0 -1 t cp ns ale pulse width t alw 2 t cp - d 2 t cp - ns 4 psen pulse width t psw 3 t cp - d 3 t cp -ns 4 notes: 1. p0.0 - p0.7, p2.0 - p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t cp . 3. data have been latched internally prior to psen going high. 4. " d " (due to buffer driving delay and wire loading) is 20 ns. data read cycle parameter symbol min. typ. max. unit notes ale low to rd low t dar 3 t cp - d - 3 t cp+ d ns 1, 2 rd low to data valid t dda --4 t cp ns 1 data hold from rd high t ddh 0-2 t cp ns data float from rd high t ddz 0-2 t cp ns rd pulse width t drd 6 t cp - d 6 t cp -ns2 notes: 1. data memory access time is 8 t cp . 2. " d " (due to buffer driving delay and wire loading) is 20 ns. data write cycle item symbol min. typ. max. unit ale low to wr low t daw 3 t cp - d - 3 t cp + d ns data valid to wr low t dad 1 t cp - d --ns data hold from wr high t dwd 1 t cp - d --ns wr pulse width t dwr 6 t cp - d 6 t cp -ns note: " d " (due to buffer driving delay and wire loading) is 20 ns. port access cycle preliminary w78e516 - 16 - parameter symbol min. typ. max. unit port input setup to ale low t pds 1 t cp -- ns port input hold from ale low t pdh 0--ns port output to ale t pda 1 t cp -- ns note: ports are read during s5p2, and output data becomes available at the end of s6p2. the timing data are referenced to ale, since it provides a convenient reference. timing waveforms program fetch cycle data read cycle data write cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 xtal1 ale psen data a8-a15 port 2 port 0 a0-a7 rd t ddh, t ddz t dda t drd t dar preliminary w78e516 publication release date: sep. 1998 - 17 - revision a0 s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd port access cycle typical application circuit xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds preliminary w78e516 - 18 - expanded external program memory and crystal ad0 a0 a0 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 27512 ad0 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 ad0 ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 16 psen 29 ale 30 txd 11 rxd 10 w78e516 10 u 8.2 k v crystal c1 c2 r ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd a1 a2 a3 a4 a5 a6 a7 a1 a2 a3 a4 a5 a6 a7 a8 a9 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a10 a11 a12 a13 a14 a15 gnd a9 a10 a11 a12 a13 a14 a15 dd figure a crystal c1 c2 r 6 mhz 47p 47p - 16 mhz 30p 30p - 24 mhz 15p 10p - 32 mhz 10p 10p 6.8k 40 mhz 5p 5p 4.7k above table shows the reference values for crystal applications. note1: c1, c2, r components refer to figure a note2: crystal layout must get close to xtal1 and xtal2 pins on user's application board. expanded external data memory and oscillator preliminary w78e516 publication release date: sep. 1998 - 19 - revision a0 10 u 8.2 k v oscillator ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 p0.0 39 p0.1 38 p0.2 37 p0.3 36 p0.4 35 p0.5 34 p0.6 33 p0.7 32 p2.0 21 p2.1 22 p2.2 23 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 rd 17 wr 16 psen 29 ale 30 txd 11 rxd 10 w78e516 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a0 a1 a2 a3 a4 a5 a6 a7 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 a0 a1 a2 a3 a4 a5 a6 a7 10 9 8 7 6 5 4 3 a0 a1 a2 a3 a4 a5 a6 a7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a12 a13 a14 25 24 21 23 26 1 20 2 a8 a9 a10 a11 a12 a13 a14 ce gnd a8 a9 a10 a11 a12 a13 a14 gnd 22 27 oe wr 20256 dd figure b preliminary w78e516 - 20 - package dimensions 40-pin dip seating plane 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 a b c d e a l s a a 1 2 e b 1 1 e e 1 a 2.055 2.070 52.20 52.58 015 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2 44-pin plcc 44 40 39 29 28 18 17 7 61 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e notes: on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.508 3.683 0.66 0.406 0.203 16.46 14.99 17.27 2.296 3.81 0.711 0.457 0.254 16.59 15.49 17.53 2.54 1.27 4.699 3.937 0.813 0.559 0.356 16.71 16.00 17.78 2.794 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680 q preliminary w78e516 publication release date: sep. 1998 - 21 - revision a0 44-pin pqfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.254 0.101 0.010 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.006 0.152 --- 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.025 0.063 0.003 0 7 0.394 0.031 0.398 0.037 9.9 0.80 0.65 1.6 10.00 0.8 10.1 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.2 12.95 10.1 10.00 9.9 7 0 0.08 0.031 0.01 0.02 0.25 0.5 --- --- --- --- --- q 2 q 0.025 0.036 0.635 0.952 0.530 0.520 0.510 13.45 13.2 12.95 0.051 0.075 1.295 1.905 44-pin tqfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.200 0.090 0.008 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm --- --- 0.047 0.002 0.037 0.0039 0.039 0.013 0.041 0.015 0.95 0.22 0.05 1.00 0.32 1.05 0.38 0.390 0.018 0.039 0.003 0 7 0.394 0.024 0.398 0.030 9.9 0.80 0.45 1.00 10.00 0.60 10.1 0.75 0.398 0.394 0.390 0.476 0.472 0.468 12.10 12.00 11.90 10.1 10.00 9.9 7 0 0.08 0.031 0.004 0.006 0.10 0.15 --- --- --- --- 1.20 a b c d e h d h e l y a a l 1 1 2 e q 2 q 0.025 0.036 0.635 0.952 0.476 0.472 0.468 12.10 12.00 11.90 --- --- --- --- preliminary w78e516 - 22 - application note: in-system programming software examples this application note illustrates the in-system programmability of the winbond w78e516 mtp-rom microcontroller. in this example, microcontroller will boot from 64kb aprom bank and waiting for a key to enter in-system programming mode for re-programming the contents of 64kb aprom. while entering in-system programming mode, microcontroller excutes the loader program in 4kb ldrom bank. the loader program erases the 64kb aprom then reads the new code data from external sram buffer (or through other interfaces) to update the 64kb aprom. example 1: ;******************************************************************************************************************* ;* example of 64k aprom program: program will scan the p1.0. if p1.0 = 0, enters in-system ;* programming mode for updating thecontents of aprom code else excutes the current rom code. ;* xtal = 40 mhz ;******************************************************************************************************************* .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 0h ljmp 100h ;jump to main program ;************************************************************************ ;* timer0 service vector org=000bh ;************************************************************************ org 00bh clr tr0 ;tr0=0,stop timer0 mov tl0,r6 mov th0,r7 reti ;************************************************************************ ;* 64k aprom main program ;************************************************************************ org 100h main_64k: mov a,p1 ;scan p1.0 anl a,#01h cjne a,#01h,program_64k ;if p1.0=0, enter in-system programming mode jmp normal_mode program_64k: mov chpenr,#87h ;chpenr=87h, chpcon register wrte enable mov chpenr,#59h ;chpenr=59h, chpcon register write enable mov chpcon,#03h ;chpcon=03h, enter in-system programming mode mov tcon,#00h ;tr=0 timer0 stop mov ip,#00h ;ip=00h preliminary w78e516 publication release date: sep. 1998 - 23 - revision a0 mov ie,#82h ;timer0 interrupt enable for wake-up from idle mode mov r6,#feh ;tl0=feh mov r7,#ffh ;th0=ffh mov tl0,r6 mov th0,r7 mov tmod,#01h ;tmod=01h,set timer0 a 16-bit timer mov tcon,#10h ;tcon=10h,tr0=1,go mov pcon,#01h ;enter idle mode for launching the in-system ;programmability ;******************************************************************************** ;* normal mode 64kb aprom program: depending user's application ;******************************************************************************** normal_mode: . ;user's application program . . . . example 2: ;***************************************************************************************************************************** ;* example of 4kb ldrom program: this lorder program will erase the 64kb aprom first, then reads the new ;* code from external sram and program them into 64kb aprom bank. xtal = 40 mhz ;***************************************************************************************************************************** .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 000h ljmp 100h ;jump to main program ;************************************************************************ ;* 1. timer0 service vector org=0bh ;************************************************************************ org 000bh clr tr0 ;tr0=0,stop timer0 mov tl0,r6 mov th0,r7 reti ;************************************************************************ ;* 4kb ldrom main program preliminary w78e516 - 24 - ;************************************************************************ org 100h main_4k: mov chpenr,#87h ;chpenr=87h, chpcon write enable. mov chpenr,#59h ;chpenr=59h, chpcon write enable. mov 7fh,#01h ;set f04kboot mode flag. mov a,chpcon anl a,#01h cjne a,#00h,update_64k ;check chpcon bit 0 mov 7fh,#00h ; flag=0, not in the f04kboot mode. mov chpcon,#01h ;chpcon=01h, enable in-system programming. mov chpenr,#00h ;disable chpcon write attribute mov tcon,#00h ;tcon=00h ,tr=0 timer0 stop mov tmod,#01h ;tmod=01h ,set timer0 a 16bit timer mov ip,#00h ;ip=00h mov ie,#82h ;ie=82h,timer0 interrupt enabled mov r6,#feh mov r7,#ffh mov tl0,r6 mov th0,r7 mov tcon,#10h ;tcon=10h,tr0=1,go mov pcon,#01h ;enter idle mode update_64k: mov chpenr,#00h ;disable chpcon write-attribute mov tcon,#00h ;tcon=00h ,tr=0 tim0 stop mov ip,#00h ;ip=00h mov ie,#82h ;ie=82h,timer0 interrupt enabled mov tmod,#01h ;tmod=01h ,mode1 mov r6,#3ch ;set wake-up time for erase operation, about 15ms. depending ;on user's system clock rate. mov r7,#b0h mov tl0,r6 mov th0,r7 erase_p_4k: mov sfrcn,#22h ;sfrcn(c7h)=22h erase 64k mov tcon,#10h ;tcon=10h,tr0=1,go mov pcon,#01h ;enter idle mode( for erase operation) ;********************************************************************* ;* blank check ;********************************************************************* mov sfrcn,#0h ;read 64kb aprom mode mov sfrah,#0h ;start address = 0h mov sfral,#0h mov r6,#fbh ;set timer for read operation, about 1.5us. mov r7,#ffh mov tl0,r6 preliminary w78e516 publication release date: sep. 1998 - 25 - revision a0 mov th0,r7 blank_check_loop: setb tr0 ;enable timer 0 mov pcon,#01h ;enter idle mode mov a,sfrfd ;read one byte cjne a,#ffh,blank_check_error inc sfral ;next address mov a,sfral jnz blank_check_loop inc sfrah mov a,sfrah cjne a,#0h,blank_check_loop ;end address=ffffh jmp program_64krom blank_check_error: mov p1,#f0h mov p3,#f0h jmp $ ;******************************************************************************* ;* re-programming 64kb aprom bank ;******************************************************************************* program_64krom: mov dptr,#0h ;the address of new rom code mov r2,#00h ;target low byte address mov r1,#00h ;target high byte address mov dptr,#0h ;external sram buffer address mov sfrah,r1 ;sfrah, target high address mov sfrcn,#21h ;sfrcn(c7h)=21 (program 64k) mov r6,#0ch ;set timer for programming, about 150us. mov r7,#feh mov tl0,r6 mov th0,r7 prog_d_64k: mov sfral,r2 ;sfral(c4h)= low byte address movx a,@dptr ;read data from external sram buffer mov sfrfd,a ;sfrfd(c6h)=data in mov tcon,#10h ;tcon=10h,tr0=1,go mov pcon,#01h ;enter idle mode( prorgamming) inc dptr inc r2 cjne r2,#0h,prog_d_64k inc r1 mov sfrah,r1 cjne r1,#0h,prog_d_64k ;***************************************************************************** ; * verify 64kb aprom bank ;***************************************************************************** mov r4,#03h ;error counter mov r6,#fbh ;set timer for read verify, about 1.5us. mov r7,#ffh preliminary w78e516 - 26 - mov tl0,r6 mov th0,r7 mov dptr,#0h ;the start address of sample code mov r2,#0h ;target low byte address mov r1,#0h ;target high byte address mov sfrah,r1 ;sfrah, target high address mov sfrcn,#00h ;sfrcn=00 (read rom code) read_verify_64k: mov sfral,r2 ;sfral(c4h)= low address mov tcon,#10h ;tcon=10h,tr0=1,go mov pcon,#01h inc r2 movx a,@dptr inc dptr cjne a,sfrfd,error_64k cjne r2,#0h,read_verify_64k inc r1 mov sfrah,r1 cjne r1,#0h,read_verify_64k ;****************************************************************************** ;* programming completly, software reset cpu ;****************************************************************************** mov chpenr,#87h ;chpenr=87h mov chpenr,#59h ;chpenr=59h mov chpcon,#83h ;chpcon=83h, software reset. error_64k: djnz r4,update_64k ;if error occurs, repeat 3 times. . ;in-system programming fail, user's process to deal with it. . . . preliminary w78e516 publication release date: sep. 1998 - 27 - revision a0 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27516023 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice. |
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