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products and specifications discussed herein ar e subject to change by micron without notice. 1gb (x64, sr) 240-pin ddr2 sdram udimm features pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 1 ?2003 micron technology, inc. all rights reserved. ddr2 sdram udimm mt8htf12864az ? 1gb for component data sheets, re fer to micron's web site: www.micron.com features ? 240-pin, unbuffered dual in-line memory module (udimm) ? fast data transfer rates: pc2-8500, pc2-6400, pc2-5300, pc2-4200, or pc2-3200 ? 1gb (128 meg x 64) ?v dd = v ddq = +1.8v ?v ddspd = +1.7v to +3.6v ? jedec-standard 1.8v i/ o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ?4 n -bit prefetch architecture ? single rank ? multiple internal device banks for concurrent operation ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency - 1 t ck ? programmable burst lengths (bl) 4 or 8 ? adjustable data-output drive strength ? 64ms, 8192-cycle refresh ? on-die termination (odt) ? serial presence-det ect (spd) with eeprom ? gold edge contacts ? halogen-free figure 1: 240-pin udimm (mo-237 r/c d) notes: 1. contact micron for industrial temperature module offerings. 2. not recommended for new designs. options marking ? operating temperature 2 ? commercial (0c t a +70c) none ? industrial (?40c t a +85c) i ?package ? 240-pin dimm (halogen-free) z ? frequency/cas latency ? 1.875ns @ cl = 7 (ddr2-1066) 2 -1ga ? 2.5ns @ cl = 5 (ddr2-800) -80e ? 2.5ns @ cl = 6 (ddr2-800) -800 ? 3.0ns @ cl = 5 (ddr2-667) -667 pcb height: 30.0mm (1.18in) table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 7 cl = 6 cl = 5 cl = 4 cl = 3 -1ga pc2-8500 1066 800 667 ? ? 13.125 13.125 54 -80e pc2-6400 ? ? 800 533 ? 12.5 12.5 55 -800 pc2-6400 ? 800 667 533 ? 15 15 55 -667 pc2-5300 ? ? 667 533 400 15 15 55 -53e pc2-4200 ? ? ? 533 400 15 15 55 -40e pc2-3200 ? ? ? 400 400 15 15 55
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 2 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm features notes: 1. data sheets for the base device s can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown) that desi gnates component and pcb revisions. consult factory for current revision codes. example: mt8htf12864az-800h1 . table 2: addressing parameter 1gb refresh count 8k row address 16k (a[13:0]) device bank address 8 (ba[2:0]) device page size per bank 1kb device configuration 1gb (128 meg x 8) column address 1k (a[9:0]) module rank address 1 (s0#) table 3: part numbers and timing parameters ? 1gb modules base device: mt47h128m8, 1 1gb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt8htf12864az-1ga__ 1gb 128 meg x 64 8.5 gb/s 1.875ns/1066 mt/s 7-7-7 mt8htf12864az-80e__ 1gb 128 meg x 64 6.2 gb/s 2.5ns/ 800 mt/s 5-5-5 mt8htf12864az-800__ 1gb 128 meg x 64 6.2 gb/s 2.5ns/ 800 mt/s 6-6-6 mt8htf12864az-667__ 1gb 128 meg x 64 5.3 gb/s 3.0ns/ 667 mt/s 5-5-5
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 3 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm pin assignments and descriptions pin assignments and descriptions table 4: pin assignments 240-pin udimm front 240-pin udimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 31 dq19 61 a4 91 v ss 121 v ss 151 v ss 181 v ddq 211 dm5 2v ss 32 v ss 62 v ddq 92 dqs5# 122 dq4 152 dq28 182 a3 212 nc 3 dq0 33 dq24 63 a2 93 dqs5 123 dq5 153 dq29 183 a1 213 v ss 4 dq1 34 dq25 64 v dd 94 v ss 124 v ss 154 v ss 184 v dd 214 dq46 5v ss 35 v ss 65 v ss 95 dq42 125 dm0 155 dm3 185 ck0 215 dq47 6dqs0#36dqs3#66 v ss 96 dq43 126 nc 156 nc 186 ck0# 216 v ss 7 dqs037dqs367 v dd 97 v ss 127 v ss 157 v ss 187 v dd 217 dq52 8v ss 38 v ss 68 nc 98 dq48 128 dq6 158 dq30 188 a0 218 dq53 9 dq2 39 dq26 69 v dd 99 dq49 129 dq7 159 dq31 189 v dd 219 v ss 10 dq3 40 dq27 70 a10 100 v ss 130 v ss 160 v ss 190 ba1 220 ck2 11 v ss 41 v ss 71 ba0 101 sa2 131 dq12 161 nc 191 v ddq 221 ck2# 12 dq8 42 nc 72 v ddq 102 nc 132 dq13 162 nc 192 ras# 222 v ss 13 dq9 43 nc 73 we# 103 v ss 133 v ss 163 v ss 193 s0# 223 dm6 14 v ss 44 v ss 74 cas# 104 dqs6# 134 dm1 164 nc 194 v ddq 224 nc 15 dqs1# 45 nc 75 v ddq 105 dqs6 135 nc 165 nc 195 odt0 225 v ss 16 dqs1 46 nc 76 nc 106 v ss 136 v ss 166 v ss 196 a13 226 dq54 17 v ss 47 v ss 77 nc 107 dq50 137 ck1 167 nc 197 v dd 227 dq55 18 nc 48 nc 78 v ddq 108 dq51 138 ck1# 168 nc 198 v ss 228 v ss 19 nc 49 nc 79 v ss 109 v ss 139 v ss 169 v ss 199 dq36 229 dq60 20 v ss 50 v ss 80 dq32 110 dq56 140 dq14 170 v ddq 200 dq37 230 dq61 21 dq10 51 v ddq 81 dq33 111 dq57 141 dq15 171 nc 201 v ss 231 v ss 22 dq11 52 cke0 82 v ss 112 v ss 142 v ss 172 v dd 202 dm4 232 dm7 23 v ss 53 v dd 83 dqs4# 113 dqs7# 143 dq20 173 nc 203 nc 233 nc 24 dq16 54 ba2 84 dqs4 114 dqs7 144 dq21 174 nc 204 v ss 234 v ss 25 dq17 55 nc 85 v ss 115 v ss 145 v ss 175 v ddq 205 dq38 235 dq62 26 v ss 56 v ddq 86 dq34 116 dq58 146 dm2 176 a12 206 dq39 236 dq63 27 dqs2# 57 a11 87 dq35 117 dq59 147 nc 177 a9 207 v ss 237 v ss 28 dqs2 58 a7 88 v ss 118 v ss 148 v ss 178 v dd 208 dq44 238 v ddspd 29 v ss 59 v dd 89 dq40 119 sda 149 dq22 179 a8 209 dq45 239 sa0 30 dq18 60 a5 90 dq41 120 scl 150 dq23 180 a6 210 v ss 240 sa1
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 4 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm pin assignments and descriptions table 5: pin descriptions symbol type description a[13:0] input (sstl_18) address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write co mmands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba[2:0]) or all devi ce banks (a10 high). the addr ess inputs also provide the op- code during a load mode command. ba[2:0] input (sstl_18) bank address inputs: ba[2:0] define the device bank to which an active, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr, emr1, emr2, and emr3), is loaded during the load mode command. ck[2:0] ck#[2:0] input (sstl_18) clock: ck and ck# are differential clock inputs. all control, command, and address input signals are sampled on the crossing of the positi ve edge of ck and the negative edge of ck#. cke0 input (sstl_18) clock enable: cke enables (registered high) and disabl es (registered low) internal circuitry and clocks on the ddr2 sdram. dm[7:0] input (sstl_18) input data mask: dm is an input mask si gnal for write data. input data is masked when dm is sampled high, along with that input data, during a write access. dm is sampled on both edges of dqs. although the dm pins are input-only, dm loading is designed to match that of the dq and dqs pins. odt0 input (sstl_18) on-die termination: odt enables (registered high) an d disables (registered low) termination resistance internal to the ddr2 sdram. when enabled in no rmal operation, odt is only applied to the following pins: dq, dqs, dqs#, and dm. the odt input will be ignored if disabled vi a the load mode command. ras#, cas#, we# input (sstl_18) command inputs: ras#, cas#, and we# (along with s#) define the command being entered. s0# input (sstl_18) chip select: s# enables (registered low) and disables (registered high) the command decoder. sa[2:0] input serial address inputs: these pins are used to configur e the spd eeprom address range on the i 2 c bus. scl input serial clock for spd eeprom: scl is used to synchronize communication to and from the spd eeprom. dq[63:0] i/o (sstl_18) data input/output: bidirectional data bus. dqs[7:0] dqs#[7:0] i/o (sstl_18) data strobe: output with read data. edge-aligned wi th read data. input with write data. center-aligned with write data. dqs# is only used when differential data strobe mode is enabled via the load mode command. sda i/o serial data: sda is a bidirectional pin used to transfer addresses and data into and out of the spd eeprom on the module on the i 2 c bus. v dd /v ddq supply power supply: 1.8v 0.1v. the component v dd and v ddq are connected to the module v dd . v ddspd supply spd eeprom power supply: +1.7v to +3.6v. v ref supply reference voltage: v dd /2. v ss supply ground. nc ? no connect: these pins are not co nnected on the module.
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 5 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm functional block diagrams functional block diagrams figure 2: functional block diagram, type 1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u1 dm cs# dqs dqs# dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 u5 dm cs# dqs dqs# dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 u2 dm cs# dqs dqs# dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u3 dm cs# dqs dqs# dq dq dq dq dq dq dq dq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dm cs# dqs dqs# dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u6 dm cs# dqs dqs# dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u7 dm cs# dqs dqs# dq dq dq dq dq dq dq dq dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u8 dm cs# dqs dqs# dqs0# dqs0 dm0 s0# dqs1# dqs1 dm1 dqs2# dqs2 dm2 dqs3# dqs3 dm3 dqs4# dqs4 dm4 dqs5# dqs5 dm5 dqs6# dqs6 dm6 dqs7# dqs7 dm7 u4, u5 ck0 ck0# u1?u3 ck1 ck1# u6?u8 ck2 ck2# a0 spd eeprom a1 a2 sa0 sa1 sa2 sda scl wp u9 or u10 ba[2:0] a[13:0] ras# cas# we# cke0 odt0 ba[2:0]: ddr2 sdram a[13:0]: ddr2 sdram ras#: ddr2 sdram cas#: ddr2 sdram we#: ddr2 sdram cke0: ddr2 sdram odt0: ddr2 sdram v ref v ss ddr2 sdram ddr2 sdram ddr2 sdram v ddspd spd eeprom v dd /v ddq v ss v ss v ss v ss
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 6 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm general description general description the mt8htf12864az ddr2 sdram modules ar e high-speed, cmos dynamic random access 1gb memory modules organized in a x64 configuration. these modules use 1gb ddr2 sdram devices with eight internal banks. ddr2 sdram modules use double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 4 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module effectively consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and four corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o pins. a bidirectional data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram device during reads and by the memory controller during writes. dqs is edge- aligned with data for reads and center-aligned with data for writes. ddr2 sdram modules operate fr om a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. clock, control, command, and address signals are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. serial presence-detec t eeprom operation ddr2 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are progra mmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa[2:0], which provide eight sa[1:0] unique dimm/eeprom addresses. write protect (wp) is connected to v ss , permanently disabling hardware write protection.
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 7 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm electrical specifications electrical specifications stresses greater than those listed in table 6 may cause permanent damage to the dram devices on the module. this is a stress rating only, and functional operation of the mod- ule at these or any other conditions outside those indicated in each device?s data sheet is not implied. exposure to abso lute maximum rating conditio ns for extended periods may adversely affect reliability. notes: 1. the refresh rate is requ ired to double when 85c < t c 95c. 2. for further information, refer to technical note tn-00-08: ? thermal applications ,? avail- able on micron?s web site. table 6: absolute maximum ratings symbol parameter min max units v dd /v ddq v dd /v ddq supply voltage relative to v ss ?0.5 +2.3 v v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v i i input leakage curren t; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) address inputs ras#, cas#, we#, s#, cke, odt, ba ?40 +40 a ck0, ck0# (pcb type 1) ?10 +10 ck1, ck1#, ck2, ck2# (pcb type 1) ?15 +15 ck1, ck1#, ck2, ck2# (pcb type 2) ?20 +20 dm ?5 +5 i oz output leakage current; 0v v out v ddq ; dqs and odt are disabled dq, dqs, dqs# ?5 +5 a i vref v ref leakage current; v ref = valid v ref level ?16 +16 a t c 1 ddr2 sdram componen t case operating temperature 2 commercial 0+85c industrial ?40 +95 c
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 8 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm electrical specifications dram operating conditions recommended ac operating conditions are given in the ddr2 component data sheets. component specifications are available on micron?s web site. module speed grades cor- relate with component speed grades, as shown table 7. design considerations simulations micron memory modules are designed to op timize signal integr ity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good sign al integrity starts at the system level. micron encourages designers to simulate the signal characteristics of the system?s mem- ory bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram , not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. table 7: module and component speed grades module speed grade component speed grade -1ga -187e -80e -25e -800 -25 -667 -3 -53e -37e -40e -5e
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 9 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm electrical specifications i dd specifications ta bl e 8 : dd r2 i dd specifications and conditions ? 1gb values are shown for the mt47h128m8 ddr2 sdram only and are computed from values specified in the 1gb (128 meg x 8) component data sheet parameter/condition symbol -1ga -80e/ -800 -667 units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch ing; data bus inpu ts are switching i dd0 920 720 680 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high be tween valid commands; address bus inputs are switching; da ta pattern is same as i dd4w i dd1 1040 880 800 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable ; data bus inputs are floating i dd2p 56 56 56 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q 480 400 320 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and addr ess bus inputs are switching; data bus inputs are switching i dd2n 480 400 320 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd3pf 400 320 240 ma slow pdn exit mr[12] = 1 i dd3ps 80 80 80 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd3n 560 480 440 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high betw een valid commands; address bus inputs are switching; data bus inputs are switching i dd4w 1680 1280 1080 ma operating burst read current: all device banks open; continuous burst reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch ing; data bus inpu ts are switching i dd4r 1680 1280 1080 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inpu ts are switching i dd5 2120 1880 1720 ma self refresh current (standard): ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floati ng; data bus inputs are floating i dd6 56 56 56 ma self refresh current (low power): ck and ck# at 0v; cke 0.2v; other control and address bus inputs are fl oating; data bus inputs are floating i dd6l 24 24 24 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd )-1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid command s; address bus inputs are stable during deselects; data bus inputs are switching i dd7 3400 2680 2240 ma
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 10 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm serial presence-detect serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or ri sing edge of sda. 2. this parameter is sampled. 3. for a restart condition or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/progra m cycle. during the write cycle, the eeprom bus in terface circuit is disabled, sda remains high due to the pull-up resistance, and the eeprom do es not respond to its slave address. serial presence-detect data for the latest serial presence-detec t data, refer to micron?s spd page: www.micron.com/spd table 9: serial presence-detec t eeprom dc operating conditions parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il ?0.6 v ddspd 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li 0.10 3.0 a output leakage current: v out = gnd to v dd i lo 0.05 3.0 a standby current i sb 1.6 4.0 a power supply curren t, read: scl clock frequency = 100 khz i ccr 0.4 1.0 ma power supply current, write: scl clock frequency = 100 khz i ccw 2.0 3.0 ma table 10: serial presence-detec t eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t dh 200 ? ns sda and scl fall time t f ? 300 ns 2 data-in hold time t hd:dat 0 ? s start condition hold time t hd:sta 0.6 ? s clock high period t high 0.6 ? s noise suppression time con stant at scl, sda inputs t i?50ns clock low period t low 1.3 ? s sda and scl rise time t r?0.3s2 scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s write cycle time t wrc ? 10 ms 4
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 11 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm module dimensions module dimensions figure 3: 240-pin ddr2 udimm notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference on ly. refer to the jedec mo document for com- plete design dimensions. 30.5 (1.2) 29.85 (1.175) pin 1 17.78 (0.7) typ 98) d (2x) 1) typ 5.0 (0.197) typ 123.0 (4.84) typ 1.0 (0.039) typ 0.80 (0.031) typ 79) r (4x) 0.76 (0.03) r pin 120 133.50 (5.256) 133.20 (5.244) 55.0 (2.165) typ 63.0 (2.48) typ 10.0 (0.394) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) max u1 u2 u3 u4 u10 u6 u7 u8 u9 no components this side of module (0.087) typ (0.039) typ 197) typ 70.66 (2.782) typ
pdf: 09005aef83b94f21/source: 09005aef83b94f31 micron technology, inc., reserves the right to change products or specifications without notice. htf8c128x64az.fm - rev. a 8/09 en 12 ?2003 micron technology, inc. all rights reserved. 1gb (x64, sr) 240-pin ddr2 sdram udimm revision history revision history rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/09 ? new data sheet (pcb 0796)

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