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this document is a general product descript ion and is subject to change without notic e. hynix semiconductor does not assume any responsibility for use of circuits descr ibed. no patent licenses are implied. rev. 1.5 / apr. 2006 1 hy5rs123235fp 512m (16mx32) gddr3 sdram hy5rs123235fp
rev. 1.5 / apr. 2006 2 hy5rs123235fp revision history revision no. history draft date remark 0.1 defined target spec. mar. 2004 0.2 page 11) add cas latency 11 page 14) write latency definitions page15) di, wr_a, al definitions page47) table18 typo corrected page48) table19 renewered page50) note 46 added july.2004 cl wl di/wr_a/al speed bin several parameters trpre 0.3 page4) ballout configurations correct appendix c) bst function description aug.2004 a3/a8/a9/a10 0.4 - non-consectutive read to write timing clarifications - read to precharge timing clarifications sep.24,2004 page28 page41 page23 0.5 - modified the pin descriptions and added command description for bst - added the lp mode feature for emrs nov.8,2004 page4,6,21 page15,16 0.6 -added the lead free package part number and package dimen- sion page jan.31,2005 page3,56 1.0 - clarified the odt control and data terminator disable command and its duration timing - modify the data termination disable mode note of emrs - modified the pin description of vdda/ vssa(k1,12/j1,12) - changed the tpdix, from 4tck to 6tck - changed the txsrd, from 300tck to 1000tck - added the tcjc definition - idd spec update - dc spec update apr.30,2005 page 15,20 page 9 page 4,7 page 47 page 48 page 48 page 46 ta b l e 1 2 1.1 vdd/vddq change, 500mhz speed bin insert, idd value tuning & typo corrected jun. 2005 1.2 vdd/vddq change at 600mhz speed bin to 1.8v from 2.0v nov. 2005 1.3 900mhz speed bin insert feb. 2006 1.4 vdd/vddq change for 800mhz speed bin & idd value change mar. 2006 1.5 changed async parameter at 700/800/900mhz speed bin (tras/trc/trfc/trcdw/trp/tdal) apr. 2006 rev. 1.5 / apr. 2006 3 hy5rs123235fp description the hynix hy5rs123235 is a high-speed cmos, dynami c random-access memory containing 536,870,912 bits. the hynix hy5rs123235 is internally configured as a eight-bank dram. the hynix hy5rs123235 uses a double data rate architecture to achieve high-speed opreration. the double date rate architectu re is essentially a 4n-prefetch architecture, wi th an interface designed to transfer two data words per clock cycle at the i/o pin s. a single read or write access for the hynix hy5rs123235 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. read and write accesses to the hyni x hy5rs123235 is burst oriented; accesses start at a selected loca tions and continue for a programmed number of locations in a pr o- grammed sequence. accesses begin with the re gistration of an active command, which is then followed by a read of write com- mand. the address bits regi stered coincident with the active command are us ed to select the bank and row to be accessed (ba0,ba1, ba2 select the bank; a0-a11 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operatio n, the hynix hy5rs123235 must be ini- tialized. features note) hy5rs123235f p -xx is the lead free package part number ordering information part no. power supply clock frequency max data rate interface package hy5rs123235fp-11 vdd=2.2v, vddq=2.2v 900mhz 1800mbps/pin pod_18 12mmx14mm 136ball fbga hy5rs123235fp-12 800mhz 1600mbps/pin hy5rs123235fp-14 vdd=2.0v, vddq=2.0v 700mhz 1400mbps/pin hy5rs123235fp-16 vdd=1.8v, vddq=1.8v 600mhz 1200mbps/pin HY5RS123235FP-2 500mhz 1000mbps/pin ? 2.2v +/-0.1v vdd/vddq power supply supports 900 / 800mhz ? 2.0v vdd/ vddq wide range min/max power supply supports 700mhz ? 1.8v vdd/ vddq wide range min/max power supply supports 500 / 600mhz ? single ended read strobe (rdqs) per byte ? single ended write strobe (wdqs) per byte ? internal, pipelined double-data-rate (ddr) architecture; two data accesses per clock cycle ? calibrated output driver ? differential clock inputs (ck and ck#) ? commands entered on each positive ck edge ? rdqs edge-aligned with data for read; with wdqs center-aligned with data for write ? eight internal banks for concurrent operation ? data mask (dm) for masking write data ? 4n prefetch ? programmable burst lengths: 4, 8 ? 32ms, 8k-cycle auto refresh ? auto precharge option ? auto refresh and self refresh modes ? 1.8v pseudo open drain i/o ? concurrent auto precharge support ? tras lockout support, active termination support ? programmable write latency(1, 2, 3, 4, 5, 6) ? boundary scan feature for connectivity test(refer to jedec std., not in this version of specifications) rev. 1.5 / apr. 2006 4 hy5rs123235fp ballout configuration 1 2 3 4 5678 9 10 11 12 a vddq vdd vss zq mf vss vdd vddq b vssq dq0 dq1 vssq vssq dq9 dq8 vssq cvddq dq2 dq3 vddq vddq dq11 dq10 vddq d vssq wdqs0 rdqs0 vssq vssq rdqs1 w dqs1 vssq evddq dq4 dm0 vddq vddq dm1 dq12 vddq fvdd dq6 dq5 cas# cs# dq13 dq14 vdd g vss vssq dq7 ba0 ba1 dq15 vssq vss h vref a1 ras# cke we# ba2 a5 vref j vss nc rfu vddq vddq ck# ck vss k vdd a10 a2 a0 a4 a6 a8/ap vdd l vss vssq dq25 a11 a7 dq17 vssq vss mvdd dq24 dq27 a3 a9 dq19 dq16 vdd nvddq dq26 dm3 vddq vddq dm2 dq18 vddq p vssq wdqs3 rdqs3 vssq vssq rdqs2 w dqs2 vssq rvddq dq28 dq29 vddq vddq dq21 dq20 vddq t vssq dq30 dq31 vssq vssq dq23 dq22 vssq u vddq vdd vss sen res vss vdd vddq 16m x 32 configuration 2m x 32 x 8 banks refresh count 8 k bank address ba0 - ba2 row address a0~a11 column address a0~a7, a9 ap flag a8 rev. 1.5 / apr. 2006 5 hy5rs123235fp functional block diagram 8banks x 2mbit x 32 i/o double data rate synchronous dram bank0 row address latch & decoder bank5 bank6 bank8 bank0 memory array (4096x512x128) sense amplifiers bank5 bank6 bank7 column decoder bank control logic column address counter latch dll drvrs mux ccl0, ccl1 ck/ ck# data 32 32 32 32 32 read latch 128 4 4 rcvrs 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 16 128 mask data ck/ck# 128 write fifo & drivers ck out ck in input registers i/o gating dm mask logic bank0 row address latch & decoder bank1 bank2 bank3 bank0 memory array (4096x512x128) sense amplifiers bank1 bank2 bank3 128 row address mux refresh counter 12 12 7 2 col0, col1 40% 66,536 512 (x128) control logic command decode mode registers address register 3 3 12 15 9 15 cke ck ck# cs# ras# cas# we# a0~a11 ba0- ba2 4 ck/ck# dq0~dq32 wck(0~3) dm(0~3) bank4 bank4 rev. 1.5 / apr. 2006 6 hy5rs123235fp ballout descriptions fbga ballout symbol type description j10, j11 ck, ck# input clock: ck and ck# are differential clock inputs. all address and con- trol input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. h4 cke input clock enable: cke high activates and cke low deactivates the inter- nal clock, input buffers and output drivers. taking cke low provides precharge power-down and self refresh operations(all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry and exit, and for self refresh entry. cke is asynchronous for se lf refresh exit and for disabling the outputs. cke must be maintained high throughout read and write accesses. input buffers (excluding ck, ck# and cke) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. f9 cs# input chip select: cs# enables (register ed low)and disables (registered high) the command decoder. all co mmands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. h3, f4, h9 ras#, cas#, we# input command inputs: ras#, cas# and we#(along with cs#) define the command being entered. e(3, 10), n(3, 10) dm0-dm3 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sample d high along with that input data during a write access. dm is sampled on rising and falling edges of wdqs. g(4, 9), h10 ba0 - ba2 input bank address inputs: ba0 and ba2 define to which bank an active, read, write or precharge command is being applied. h(2, 11), k(2-4, 9-11), l(4, 9), m(4, 9) a0-a11 input address inputs: provide the row a ddress for active commands, and the column address and auto pr echarge bit(a8) for read/write commands, to select one location out of the memory array in the respective bank. a8 sampled during a precharge command deter- mines whether the precharge applies to one bank (a8 low, bank selected by ba0 - ba2 ) or all banks (a8 high). the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode register) is loaded during the load mode register com- mand. b(2, 3), c(2, 3), e2, f(2, 3), g3,b(10, 11), c(10, 11), e11, f(11, 19), g10, l10, m(10, 11), n11, r(10, 11), t(10,11), l3, m(2, 3), n2,r(2, 3), t(2, 3) dq0-31 i/o data input/output: d(3, 10), p(3, 10) rdqs0-3 output read data strobe: output with read data. rdqs is edge-aligned with read data. d(2, 11), p(2, 11) wdqs0-3 input write data strobe: input with write data. wdqs is center aligned to the input data. u4 sen input scan enable pin. logic high would enable scan mode. should be tied to gnd when not in use. this pin is a cmos input. j(2, 3) nc/rfu no connect rev. 1.5 / apr. 2006 7 hy5rs123235fp ballout descriptions -c ontinue mirror function the gddr3 sdram provides a mirror function(mf) ball to change the physical location of the control lines and all address lines, assisting in routing devices back to back. the mf ball will affect ras#, cas#, we#, cs# and cke on balls h3, f4, h9, f9 and h4 respectively and a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, ba0, ba1 and ba2 on balls k4, h2, k3, m4, k9, h11, k10, l9, k11, m9, k2, l4, g4, g9 and h10 respectively and only detects a dc input. the mf ball should be tied directly to vss of vdd dependin g on the control line orientation desired. when mf ball is tied low the ball orientation is as follows. ras#-h3, cas#-f4, we#-h9, cs#-f9, cke-h4, a0-k4, a1-h2, a2-k3, a3- m4, a4-k9, a5-h11, a6-k10, a7-l9, a8-k11, a9-m9, a10-k2, a11-l4 , ba0-g4, ba1-g9 and ba2-h10. the high condition on the mf ball will change the location of the control balls as follows; cs#-f4, cas#-f9, ras#-h10, we#-h4, cke-h9, a0-k9, a1-h11, a2-k10 , a3-m9, a4-k4, a5-h2, a6-k3, a7-l4, a8-k2, a9-m4, a10-k11, a11-l9, ba0-g9, ba1-g4 and ba2-h3. this mirror fuction does not work under boundary scan test condition. mirror function signal mapping fbga ball out symbol type description a(1, 12), c(1, 4, 9, 12), j(4, 9), n(1, 4, 9, 12), r(1, 4, 9, 12), u(1, 12) vddq supply dq power supply: +1.8v. isolated on the die for improved noise immunity. b(1, 4, 9, 12), d(1, 4, 9, 12), g(2, 11), l(2, 11), p(1, 4, 9, 12), t(1, 4, 9, 12) vssq supply dq ground: isolated on the die for improved noise immu- nity. a(2, 11), f(1, 12), m(1, 12), u(2, 11) k(1, 12) vdd supply power supply: +1.8v. a(3, 10), g(1, 12), l(1, 12), u(3, 10) j(1, 12) vss supply ground h(1, 12) vref supply reference voltage. a9 mf reference mirror function for clamshell mounting of drams a4 zq reference external reference pin for autocalibration. it should be connected to rq(=240 ) u9 res reference reset pin. the res pin is a vdd cmos input. pin mf logic state high low ras# h10 h3 cas# f9 f4 we# h4 h9 cs# f4 f9 cke h9 h4 a0 k9 k4 a1 h11 h2 a2 k10 k3 a3 m9 m4 a4 k4 k9 a5 h2 h11 a6 k3 k10 a7 l4 l9 a8 k2 k11 a9 m4 m9 a10 k11 k2 a11 l9 l4 ba0 g9 g4 ba1 g4 g9 ba2 h3 h10 rev. 1.5 / apr. 2006 8 hy5rs123235fp gddr3 initialization and power up gddr3 sdrams must be powered up and initialized in a predefined manner. oper ational procedures other than those specified may result in undefined operation. power must be first applied to vdd and vddq simultaneously or vdd first and vddq later, and then to vref. vref can be applied any time after vddq. once power has been applied and the clocks are stabl e the gddr3 device requires 200us before the res pin transitions to high. upon power-up and after the clock is stable, the on-die ter- mination value for the address and control pins will be set, based on the state of cke when the res pin transitions from low to high. on the rising edge of res, the cke pin is latched to de termine the on die termination value for the address and control l ines. if cke is sampled at a logic low then the on die termination will be set to 1/2 of zq and, if cke is sampled logic high then th e on die termination will be set to the same value as zq. cke must meet tats and tath on the rising of res to set the on die termina tion for address and control lines. once tath is met, set cke to high. an additional 200us is required for the address and command o n die terminations to calibrate and update. res must be maintained at a logic low-level value and cs# must be maintained high, during the first stage of power-up to ensure that the dq outputs will be in a high-z state( un-terminated ). after the res pin transitions from low to high, wait until a 200us delay is satisfied. issue deselect on the command bus during this time. issue a precharge all command. ne xt a load mode register command must be issued for the extended mode regis- ter (ba1 low and ba0 high) to activate th e dll and set operating parameters, followed by the load mode register command (ba0/ba1 both low) to reset the dll and to program the rest of the operating parameters. 20k clock cycles are required between the dll reset and any read command to allo w the dll to lock. a precharge all command should then be applied, placing the device in the all banks idle state. once in the idle state, two auto ref resh cycles must be issued. following these requirements, the gddr3 sdram is ready for normal operation. w $ 7 6 9 ' ' 9 ' ' 4 9 5 ( ) & |