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8mb, sync lw, r-l, hstl, rev 1.3 1 / 24 june 23, 2000 cxk77s36l80agb / cxk77s18l80agb sony 4/42/43/44 8mb late write hstl high speed synchronous srams (256k x 36 or 512k x 18 organization) preliminary description features ? 4 speed bins cycle time / access time -4 (-4a) (-4b) 4.0ns / 3.9ns (3.8ns) (3.7ns) -42 (-42a) (-42b) 4.2ns / 4.2ns (4.1ns) (4.0ns) -43 (-43a) (-43b) 4.3ns / 4.5ns (4.4ns) (4.3ns) -44 4.4ns / 4.7ns ? single 3.3v power supply (v dd ): 3.3v 5% ? register - latch (r-l) read operations ? late write (lw), fully coherent, self-timed write operations ? byte write capability ? one cycle deselect ? differential input clocks (k/k ) ? asynchronous output enable (g ) ? dedicated output supply voltage (v ddq ): 1.9v typical ? extended hstl-compatible i/o interface with dedicated input reference voltage (v ref ): 0.85v typical ? programmable impedance output drivers ? sleep (power down) mode via dedicated mode pin (zz) ? jtag boundary scan (subset of ieee standard 1149.1) ? 119 pin (7x17), 1.27mm pitch, 14mm x 22mm ball grid array (bga) package the cxk77s36l80agb (organized as 262,144 words by 36 bits) and the cxk77s18l80agb (organized as 524,288 words by 18 bits) are high speed cmos synchronous static rams with common i/o pins. these synchronous srams integrate input registers, high speed ram, output latches, and a one-deep write buffer onto a single monolithic ic. register - latch (r-l) read operations and late write (lw) write operations are supported, providing a high-performance user interface. all address and control input signals except g (output enable) and zz (sleep mode) are registered on the rising edge of k (input clock). during read operations, output data is driven valid from the falling edge of k, one half clock cycle after the address is regis tered. during write operations, input data is registered on the rising edge of k, one full clock cycle after the address is registered . write operations are internally self-timed, eliminating the need for complex off-chip write pulse generation. the output drivers are series terminated, and the output impedance is programmable through an external impedance matching resistor rq. by connecting rq between zq and v ss , the output impedance of all dq pins can be precisely controlled. sleep (power down) mode control is provided through the asynchronous zz input. 250 mhz operation is obtained from a single 3.3v power supply. jtag boundary scan interface is provided using a subset of ieee standard 1149.1 protocol.
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 2 / 24 june 23, 2000 256k x 36 pin assignment (top view) notes: 1. pad locations 2t and 6t are true no-connects. however, they are defined as sa address inputs in x18 lw srams. 2. pad location 2b is a true no-connect. however, it is defined as an sa address input in 16mb lw srams. 3. pad location 6u must be left unconnected. it is used by sony for internal test purposes. 4. pad location 3r is defined as an m1 mode pin in lw srams. however, it must be tied high in this device. 5. pad location 5r is defined as an m2 mode pin in lw srams. however, it must be tied low in this device. 1234567 av ddq sa sa nc sa sa v ddq bncnc (2) sa nc sa sa nc cncsasav dd sa sa nc d dqc dqc v ss zq v ss dqb dqb e dqc dqc v ss ss v ss dqb dqb fv ddq dqc v ss g v ss dqb v ddq g dqc dqc sbw cncsbw b dqb dqb h dqc dqc v ss nc v ss dqb dqb jv ddq v dd v ref v dd v ref v dd v ddq k dqd dqd v ss kv ss dqa dqa l dqd dqd sbw dk sbw a dqa dqa mv ddq dqd v ss sw v ss dqa v ddq n dqd dqd v ss sa v ss dqa dqa p dqd dqd v ss sa v ss dqa dqa rncsam1 (4) v dd m2 (5) sa nc tncnc (1) sa sa sa nc (1) zz uv ddq tms tdi tck tdo rsvd (3) v ddq
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 3 / 24 june 23, 2000 512k x 18 pin assignment (top view) notes: 1a. pad location 4t is a true no-connect. however, it is defined as an sa address input in x36 lw srams. 1b. pad locations 2d, 7d, 1e, 6e, 2f, 1g, 6g, 2h, 7h, 1k, 6k, 2l, 7l, 6m, 2n, 7n, 1p, and 6p are true no-connects. however, they are defined as dq data inputs / outputs in x36 lw srams. 2. pad location 2b is a true no-connect. however, it is defined as an sa address input in 16mb lw srams. 3. pad location 6u must be left unconnected. it is used by sony for internal test purposes. 4. pad location 3r is defined as an m1 mode pin in lw srams. however, it must be tied high in this device. 5. pad location 5r is defined as an m2 mode pin in lw srams. however, it must be tied low in this device. 1234567 av ddq sa sa nc sa sa v ddq bncnc (2) sa nc sa sa nc cncsasav dd sa sa nc d dqb nc (1b) v ss zq v ss dqa nc (1b) enc (1b) dqb v ss ss v ss nc (1b) dqa fv ddq nc (1b) v ss g v ss dq6a v ddq gnc (1b) dqb sbw bnc v ss nc (1b) dqa h dqb nc (1b) v ss nc v ss dqa nc (1b) jv ddq v dd v ref v dd v ref v dd v ddq knc (1b) dqb v ss kv ss nc (1b) dqa l dqb nc (1b) v ss k sbw a dqa nc (1b) mv ddq dqb v ss sw v ss nc (1b) v ddq n dqb nc (1b) v ss sa v ss dqa nc (1b) pnc (1b) dqb v ss sa v ss nc (1b) dqa rncsam1 (4) v dd m2 (5) sa nc tncsasanc (1a) sa sa zz uv ddq tms tdi tck tdo rsvd (3) v ddq
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 4 / 24 june 23, 2000 pin description symbol type description sa input synchronous address inputs - registered on the rising edge of k. dqa, dqb dqc, dqd i/o synchronous data inputs / outputs - registered on the rising edge of k during write operations. driven from the falling edge of k during read operations. dqa - indicates data byte a dqb - indicates data byte b dqc - indicates data byte c dqd - indicates data byte d k, k input differential input clocks ss input synchronous select input - registered on the rising edge of k. ss = 0 specifies a write operation when sw = 0 specifies a read operation when sw = 1 ss = 1 specifies a deselect operation sw input synchronous global write enable input - registered on the rising edge of k. sw = 0 specifies a write operation when ss = 0 sw = 1 specifies a read operation when ss = 0 sbw a, sbw b, sbw c, sbw d input synchronous byte write enable inputs - registered on the rising edge of k. sbw a = 0 specifies write data byte a when ss = 0 and sw = 0 sbw b = 0 specifies write data byte b when ss = 0 and sw = 0 sbw c = 0 specifies write data byte c when ss = 0 and sw = 0 sbw d = 0 specifies write data byte d when ss = 0 and sw = 0 g input asynchronous output enable input - de-asserted (high) forces the data output drivers to hi-z. zz input asynchronous sleep mode input - asserted (high) forces the sram into low-power mode. m1, m2 input read operation protocol select - these mode pins must be tied high and low respectively to select register - latch read operations. zq input output impedance control resistor input v dd 3.3v core power supply - core supply voltage. v ddq output power supply - output buffer supply voltage. v ref input reference voltage - input buffer threshold voltage. v ss ground tck input jtag clock tms input jtag mode select tdi input jtag data in tdo output jtag data out rsvd reserved - this pin is used for sony test purposes only. it must be left unconnected. nc no connect - these pins are true no-connects, i.e. there is no internal chip connection to these pins. they can be left unconnected or tied directly to v dd , v ddq , or v ss .
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 5 / 24 june 23, 2000 address write pulse 256k x 36 dout din 2:1 mux output latch reg. 2:1 mux reg. write store reg. read comp. reg. reg. reg. self time write logic output clock sa ss sw sbw k/k g dq ^ ^ ^ ^ block diagram kint kint kint kint kint or 512k x 18 input clock
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 6 / 24 june 23, 2000 ? truth table ? sleep (power down) mode sleep (power down) mode is provided through the asynchronous input signal zz. when zz is asserted (high), the output drivers will go to a hi-z state, and the sram will begin to draw standby current. con- tents of the memory array will be preserved. an enable time (t zze ) must be met before the sram is guaranteed to be in sleep mode, and a recovery time (t zzr ) must be met before the sram can resume normal operation. ? programmable impedance output drivers these devices have programmable impedance output drivers. the output impedance is controlled by an external resistor, rq, connected between the srams zq pin and v ss , and is equal to one-fifth the value of this resistor, nominally. see the dc electrical characteristics section for further information. the output impedance is updated whenever the output drivers are in a hi-z state. consequently, imped- ance updates will occur during write and deselect operations, and when g is deasserted (high) (see note 1 below). at power up, 8192 clock cycles followed by an impedance update via one of the three methods described above are required to ensure that the output impedance has reached the desired value. after power up, periodic impedance updates via one of the three methods described above are also required to ensure that the output impedance remains within specified tolerances. note 1: in order to allow the sram sufficient time to update the output impedance when g is deasserted (high), g must meet setup and hold times with respect to k clock. see the ac electrical characteristics sections for further information. ? power-up sequence for reliability purposes, sony recommends that power supplies power up in the following sequence: v ss , v dd , v ddq , v ref , and inputs. v ddq should never exceed v dd . if this power supply sequence can- not be met, a large bypass diode may be required between v dd and v ddq . please contact sony memory application department for further information. zz ss (t n ) sw (t n ) sbw x (t n ) g operation dq (t n ) dq (t n+1 ) hxxxxsleep (power down) mode hi - zhi - z lhxxxdeselect hi - zx l l h x h read hi - z hi - z l l h x l read q(t n )x llllxwrite all bytes hi - zd(t n ) l l l x x write bytes with sbw x = l hi - z d(t n ) l l l h x abort write hi - z x
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 7 / 24 june 23, 2000 ? absolute maximum ratings (1) (1) stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ? bga package thermal characteristics ? i/o capacitance (t a = 25 o c, f = 1 mhz) note: these parameters are sampled and are not 100% tested. item symbol rating unit supply voltage v dd -0.5 to +3.9 v output supply voltage v ddq -0.5 to +3.6 v input voltage v in -0.5 to v ddq +0.5 (3.2v max) v output voltage v out -0.5 to v ddq +0.5 (3.2v max) v operating temperature t a 0 to 85 c junction temperature t j 0 to 110 c storage temperature t stg -55 to 150 c item symbol rating unit junction to case temperature q jc 1.0 c/w item symbol test conditions min max unit input capacitance address c addr v in = 0v --- 3.0 pf control c ctrl v in = 0v --- 3.5 pf clock c clk v in = 0v --- 3.5 pf output capacitance c out v out = 0v --- 4.5 pf
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 8 / 24 june 23, 2000 ? dc recommended operating conditions ( v ss = 0v , t a = 0 to 85 o c) (1) the peak-to-peak ac component superimposed on v ref may not exceed 5% of the dc component. (2) v ih (max) ac = v ddq + 1.0v for pulse width less than one-quarter of the cycle time (t cyc /4). (3) v il (min) ac = -1.0v for pulse width less than one-quarter of the cycle time (t cyc /4). (4) these devices support two different input clocking schemes: a. differential - in this scheme, both clock inputs (k and k ) are driven differentially. v kin , v dif , and v cm must all be considered when using this scheme. b. single ended - in this scheme, one of the two clock inputs (either k or k ) is driven to the same voltage levels as the other inputs, i.e. from v ss to v ddq nominally, while the other clock input (either k or k) is tied to an external reference voltage (v x ). v kin , v dif , and v x must all be considered when using this scheme. item symbol min typ max unit supply voltage v dd 3.13 3.3 3.47 v output supply voltage v ddq 1.8 1.9 2.0 v input reference voltage (1) v ref 0.7 0.85 1.0 v input high voltage (2) v ih v ref + 0.1 --- v ddq + 0.3 v input low voltage (3) v il -0.3 --- v ref - 0.1 v clock input signal voltage (4) v kin -0.3 --- v ddq + 0.3 v clock input differential voltage v dif 0.2 --- v ddq + 0.6 v clock input common mode voltage v cm 0.7 --- 1.1 v clock input cross point voltage v x 0.7 --- 1.0 v
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 9 / 24 june 23, 2000 ? dc electrical characteristics (v dd = 3.3v 5%, v ss = 0v, t a = 0 to 85 o c) 1. for maximum output drive, the zq pin can be tied directly to v ss . 2. for minimum output drive, the zq pin can be left unconnected or tied to v ddq . item symbol test conditions min typ max unit input leakage current i li v in = v ss to v ddq -1 --- 1 ua output leakage current i lo v out = v ss to v ddq g = v ih -10 --- 10 ua average power supply operating current - x36 i dd-4 i dd-42 i dd-43 i dd-44 i out = 0 ma ss = v il , zz = v il --- --- --- --- 660 640 630 620 770 750 740 730 ma average power supply operating current - x18 i dd-4 i dd-42 i dd-43 i dd-44 i out = 0 ma ss = v il , zz = v il --- --- --- --- 630 610 600 590 740 720 710 700 ma average power supply operating current (3 mhz operation) i dd3 i out = 0 ma ss = v il , zz = v il t cyc = 3 mhz --- 170 300 ma power supply standby current i sb i out = 0 ma zz = v ih --- 50 100 ma output high voltage v oh i oh = -8.0 ma rq = 125 w v ddq -0.4 --- --- v output low voltage v ol i ol = 8.0 ma rq = 125 w --- --- 0.4 v output driver impedance r out 1,2 v oh , v ol = v ddq /2 rq < 100 w 17 (20*0.85) 20 23 (20*1.15) w v oh , v ol = v ddq /2 100 w rq 150 w (rq/5)* 0.85 rq/5 (rq/5)* 1.15 w v oh , v ol = v ddq /2 rq > 150 w 25 (30*0.85) 30 35 (30*1.15) w
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 10 / 24 june 23, 2000 ? ac electrical characteristics all parameters are specified over the range t a = 0 to 85 o c. all parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise noted. 1. these parameters are measured from v ref 200mv to the clock mid-point (-4 bin only). 2. these parameters apply only when deasserting g (high) in order to induce output impedance updates. 3. these parameters are sampled and are not 100% tested. 4. these parameters are measured at 50mv from steady state voltage. parameter symbol -4 -42 -43 -44 units notes min max min max min max min max k cycle time t khkh 4.0 --- 4.2 --- 4.3 --- 4.4 --- ns k clock high pulse width t khkl 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns k clock low pulse width t klkh 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns address setup time t avkh 0.3 --- 0.5 --- 0.5 --- 0.5 --- ns 1 address hold time t khax 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns write enables setup time t wvkh 0.3 --- 0.5 --- 0.5 --- 0.5 --- ns 1 write enables hold time t khwx 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns synchronous select setup time t svkh 0.3 --- 0.5 --- 0.5 --- 0.5 --- ns 1 synchronous select hold time t khsx 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns output enable setup time t gvkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns 2,3 output enable hold time t khgx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns 2,3 data input setup time t dvkh 0.3 --- 0.5 --- 0.5 --- 0.5 --- ns 1 data input hold time t khdx 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns k clock high to output valid (a sub-bin) (b sub-bin) t khqv --- 3.9 3.8 3.7 --- 4.2 4.1 4.0 --- 4.5 4.4 4.3 --- 4.7 ns k clock low to output valid t klqv --- 1.8 --- 2.0 --- 2.1 --- 2.2 ns k clock low to output hold t klqx 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns 3 k clock low to output low-z t klqx1 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns 3,4 k clock high to output high-z t khqz 1.2 2.2 1.2 2.3 1.2 2.4 1.2 2.5 ns 3,4 output enable low to output valid t glqv --- 2.2 --- 2.3 --- 2.4 --- 2.5 ns output enable low to output low-z t glqx 0.3 --- 0.3 --- 0.3 --- 0.3 --- ns 3,4 output enable high to output high-z t ghqz --- 2.2 --- 2.3 --- 2.4 --- 2.5 ns 3,4 sleep mode enable time t zze --- 100 --- 100 --- 100 --- 100 ns 3 sleep mode recovery time t zzr 100 --- 100 --- 100 --- 100 ns 3
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 11 / 24 june 23, 2000 ? ac electrical characteristics (guaranteed by design) 1. this parameter is applicable when t khqv 3.8ns. 2. this parameter is measured at the gate of the output driver of the sram. 3. please refer to the previous page (p. 10) of this document for information concerning to what specification this parameter is tested. parameter symbol -4 units notes min max k clock high to output high-z t khqz t khqv - 2.4 2.0 ns 1,2,3
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 12 / 24 june 23, 2000 ? ac test conditions (v dd = 3.3v 5%, v ddq = 1.9v 0.1v, t a = 0 to 85 c) item symbol conditions units notes input reference voltage v ref 0.85 v address / control input high level v caih 1.45 v address / control input low level v cail 0.35 v data input high level v dih 1.25 v data input low level v dil 0.55 v input rise & fall time 0.5 v/ns input reference level 0.85 v clock input high voltage v kih 1.45 v v dif = 0.7v clock input low voltage v kil 0.75 v v dif = 0.7v clock input common mode voltage v cm 1.10 v clock input rise & fall time 0.5 v/ns clock input reference level k/k cross v output reference level 0.95 v output load conditions fig.1 rq = 250 w dq 0.95 v fig. 1: ac test output load 50 w 50 w 5 pf 16.7 w 0.95 v 50 w 50 w 5 pf 16.7 w 16.7 w
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 13 / 24 june 23, 2000 register - latch mode timing diagram of write operations g ss sw /sbw x k n n+1 n+2 k sa dn dn+1 dq t khdx t dvkh dn-1 n+3 dn+2 t svkh t khsx t klqx1 t ghqz t glqv t glqx t klqv qn+1 t khqz sw k k timing diagram of read and deselect operations n qn n+1 sa g dq t wvkh t avkh t khwx t khax t khkh t khkl t klkh ss n+3 qn-1 t klqx t klqv t khqv
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 14 / 24 june 23, 2000 sa ss g = v il timing diagram of read-write-read operations k k n n+2 n+4 n+5 sw /sbw x read n write n+1 read n+2 deselect t khqz dq qn qn+2 dn+1 qn+4 read n+4 n+1 t khqz register - latch mode
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 15 / 24 june 23, 2000 ? test mode description these devices provide a jtag test access port (tap) and boundary scan interface using a limited set of ieee std. 1149.1 functions. this test mode is intended to provide a mechanism for testing the interconnect between master (processor, con- troller, etc.), srams, other components, and the printed circuit board. in conformance with a subset of ieee std. 1149.1, these devices contain a tap controller and four tap registers. the tap registers consist of one instruction register and three data registers (id, bypass, and boundary scan registers). the tap consists of the following four signals: tck: test clock induces (clocks) tap controller state transitions. tms: test mode select inputs commands to the tap controller. sampled on the rising edge of tck. tdi: test data in inputs data serially to the tap registers. sampled on the rising edge of tck. tdo: test data out outputs data serially from the tap registers. driven from the falling edge of tck. disabling the tap when jtag is not used, tck should be tied low to prevent clocking the sram. tms and tdi should either be tied low or tied high through a pull-up resistor, but they cannot be left unconnected. tdo should be left unconnected. note: operation of the tap does not interfere with normal sram operation except during the sample-z instruction, which forces the srams data output drivers (dqs) to a high-z state. consequently, when jtag is not used the tap can be operated or disabled any number of ways without adversely affecting the functionality of the device. jtag dc recommended operating conditions (t a = 0 to 85 c ) jtag ac test conditions (v dd = 3.3v 5%, t a = 0 to 85 c ) parameter symbol test conditions min max unit jtag input high voltage (tck) v tkih --- 1.7 2.8 v jtag input low voltage (tck) v tkil --- -0.3 0.7 v jtag input high voltage (tms, tdi) v tih --- v ref + 0.4 2.8 v jtag input low voltage (tms, tdi) v til --- -0.3 v ref - 0.4 v jtag output high voltage (tdo) v toh i toh = -2.0 ma 2.6 --- v jtag output low voltage (tdo) v tol i tol = 2.0 ma --- 0.2 v jtag input leakage current i tli v tin = 0v to 2.5v -1 1 ua parameter symbol conditions units notes jtag input high level v tih 2.5 v jtag input low level v til 0.0 v jtag input rise & fall time 0.5 v/ns jtag input reference level 1.25 v jtag output reference level 1.25 v jtag output load condition see fig.1 (page 12)
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 16 / 24 june 23, 2000 jtag ac electrical characteristics jtag timing diagram parameter symbol min max unit tck cycle time t thth 100 ns tck high pulse width t thtl 40 ns tck low pulse width t tlth 40 ns tms setup time t mvth 10 ns tms hold time t thmx 10 ns tdi setup time t dvth 10 ns tdi hold time t thdx 10 ns tck low to tdo valid t tlqv 20 ns tck low to tdo hold t tlqx 0ns figure 2 t thtl t tlth t thth t thmx t mvth t thdx t dvth t tlqv t tlqx tck tms tdi tdi tdo
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 17 / 24 june 23, 2000 tap registers tap registers are serial shift registers that capture serial input data (from tdi) on the rising edge of tck, and drive serial output data (to tdo) on the subsequent falling edge of tck. they are divided into two groups: instruction registers, of which there is one- the instruction register, and data registers, of which there are three - the id register, the bypass reg- ister, and the boundary scan register. individual tap registers are selected (inserted between tdi and tdo) when the appropriate sequence of commands is given to the tap controller. instruction register (3 bits) the instruction register stores the instructions that are executed by the tap controller when the tap controller is in the run-test / idle state, or in any of the various data register states. it is loaded with the idcode instruction at power- up, or when the tap controller is in the test-logic reset state or the capture-ir state. it is inserted between tdi and tdo when the tap controller is in the shift-ir state, at which time it can be loaded with a new instruction. however, newly loaded instructions are not executed by the tap controller until the tap controller has reached the update-ir state. the instruction register is 3 bits wide, and is encoded as follows: bit 0 is the lsb of the instruction register, and bit 2 is the msb. when the instruction register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. id register (32 bits) the id register is loaded with a predetermined device- and manufacturer-specific identification code when the idcode instruction has been loaded into the instruction register and the tap controller is in the capture-dr state. it is inserted between tdi and tdo when the idcode instruction has been loaded into the instruction register and the tap controller is in the shift-dr state. the id register is 32 bits wide, and is encoded as follows: bit 0 is the lsb of the id register, and bit 31 is the msb. when the id register is selected, the lsb serially shifts data out through tdo. however, unlike the instruction register and the other data registers, tdi does not serially shift data into the msb. the id register is a read-only register. code (2:0) instruction description 000 bypass inserts the bypass register between tdi and tdo. 001 idcode inserts the id register between tdi and tdo. 010 sample-z captures the srams i/o ring contents in the boundary scan register. inserts the boundary scan register between tdi and tdo. forces the srams outputs (dqs) to high-z. 011 bypass inserts the bypass register between tdi and tdo. 100 sample captures the srams i/o ring contents in the boundary scan register. inserts the boundary scan register between tdi and tdo. 101 private do not use. reserved for manufacturer use only. 110 bypass inserts the bypass register between tdi and tdo. 111 bypass inserts the bypass register between tdi and tdo. device revision number (31:28) part number (27:12) sony id (11:1) start bit (0) 256k x 36 xxxx 0000 0000 0100 0001 0000 1110 001 1 512k x 18 xxxx 0000 0000 0100 0010 0000 1110 001 1
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 18 / 24 june 23, 2000 bypass register (1 bit) the bypass register is one bit wide, and provides the minimum length serial path between tdi and tdo. it is loaded with a logic 0 when the bypass instruction has been loaded in the the instruction register and the tap controller is in the capture-dr state. it is inserted between tdi and tdo when the bypass instruction has been loaded into the instruction register and the tap controller is in the shift-dr state. boundary scan register (70 bits for x36, 51 bits for x18) the boundary scan register is equal in length to the number of active signal connections to the sram (excluding the tap pins) plus a number of place holder locations reserved for density and/or functional upgrades. the boundary scan register is loaded with the contents of the srams i/o ring when the sample or sample-z instruction has been loaded into the instruction register and the tap controller is in the capture-dr state. it is inserted between tdi and tdo when the sam- ple or sample-z instruction has been loaded into the instruction register and the tap controller is in the shift-dr state. the boundary scan register contains the following bits: for deterministic results, all signals composing the srams i/o ring must meet setup and hold times with respect to tck (same as tdi and tms) when sampled. k/k are connected to a differential input receiver that generates a single-ended input clock signal to the device. therefore, in order to capture specific values for these signals in the boundary scan register, these signals must be at opposite logic levels when sampled. place holders are required for some nc pins to allow for future density and/or functional upgrades. they are connected to v ss internally, regardless of pin connection externally. the boundary scan order assignment tables that follow depict the order in which the bits from the table above are arranged in the boundary scan register. in each notation, bit 1 is the lsb bit of the register. when the boundary scan register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. 256k x 36 512k x 18 dq 36 dq 18 sa 18 sa 19 k, k 2k, k 2 ss , sw , sbw x6ss , sw , sbw x4 g , zz 2 g , zz 2 m1, m2 2 m1, m2 2 zq 1 zq 1 place holder 3 place holder 3
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 19 / 24 june 23, 2000 boundary scan order assignments (by exit sequence) 256k x 36 bit signal pad bit signal pad 1m2 5r 36sa 3b 2 sa 4p 37 **nc** 2b 3sa 4t 38sa 3a 4sa6r 39sa3c 5sa 5t 40sa 2c 6zz 7t 41sa 2a 7 dqa 6p 42 dqc 2d 8 dqa 7p 43 dqc 1d 9 dqa 6n 44 dqc 2e 10 dqa 7n 45 dqc 1e 11 dqa 6m 46 dqc 2f 12 dqa 6l 47 dqc 2g 13 dqa 7l 48 dqc 1g 14 dqa 6k 49 dqc 2h 15 dqa 7k 50 dqc 1h 16 sbw a5l 51sbw c3g 17 k 4l 52 zq 4d 18 k 4k 53 ss 4e 19 g 4f 54 **nc** 4g 20 sbw b 5g 55 **nc** 4h 21 dqb 7h 56 sw 4m 22 dqb 6h 57 sbw d3l 22 dqb 7g 58 dqd 1k 24 dqb 6g 59 dqd 2k 25 dqb 6f 60 dqd 1l 26 dqb 7e 61 dqd 2l 27 dqb 6e 62 dqd 2m 28 dqb 7d 63 dqd 1n 29 dqb 6d 64 dqd 2n 30 sa 6a 65 dqd 1p 31 sa 6c 66 dqd 2p 32 sa 5c 67 sa 3t 33 sa 5a 68 sa 2r 34 sa 6b 69 sa 4n 35 sa 5b 70 m1 3r 512k x 18 bit signal pad bit signal pad 1m2 5r 36sbw b3g 2sa 6t 37zq 4d 3sa 4p 38ss 4e 4 sa 6r 39 **nc** 4g 5 sa 5t 40 **nc** 4h 6zz 7t 41sw 4m 7 dqa 7p 42 dqb 2k 8 dqa 6n 43 dqb 1l 9 dqa 6l 44 dqb 2m 10 dqa 7k 45 dqb 1n 11 sbw a 5l 46 dqb 2p 12 k 4l 47 sa 3t 13 k 4k 48 sa 2r 14 g 4f 49 sa 4n 15 dqa 6h 50 sa 2t 16 dqa 7g 51 m1 3r 17 dqa 6f 52 18 dqa 7e 53 19 dqa 6d 54 20 sa 6a 55 21 sa 6c 56 22 sa 5c 57 22 sa 5a 58 24 sa 6b 59 25 sa 5b 60 26 sa 3b 61 27 **nc** 2b 62 28 sa 3a 63 29 sa 3c 64 30 sa 2c 65 31 sa 2a 66 32 dqb 1d 67 33 dqb 2e 68 34 dqb 2g 69 35 dqb 1h 70 note: nc pins at pad location 2b, 4g, and 4h are connected to v ss internally, regardless of pin connection externally.
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 20 / 24 june 23, 2000 tap instructions idcode the idcode instruction causes a predetermined device- and manufacturer-specific identification code to be loaded into the id register when the tap controller is in the capture-dr state, and causes the id register to be inserted between tdi and tdo when the tap controller is in the shift-dr state. idcode is the default instruction loaded into the instruction register at power-up, and when the tap controller is in the test-logic reset state. bypass the bypass instruction causes a logic 0 to be loaded into the bypass register when the tap controller is in the capture- dr state, and causes the bypass register to be inserted between tdi and tdo when the tap controller is in the shift- dr state. sample the sample instruction causes the logic levels of the signals composing the srams i/o ring (see the boundary scan reg- ister description for the complete list of signals) to be loaded into the boundary scan register when the tap controller is in the capture-dr state, and causes the boundary scan register to be inserted between tdi and tdo when the tap con- troller is in the shift-dr state. the sample instruction does not affect the state of the srams data output drivers (dqs). they behave exactly as they do during normal sram operation. specifically, the dqs remain in either a high-z (input) state or low-z (output) state dur- ing this instruction, depending on when the instruction is executed, as follows: sample executed after and state of g then state of dqs power-up x high-z (inputs) sleep mode x high-z (inputs) read l low-z (outputs - drive most recent read data) h high-z (inputs) write x high-z (inputs) deselect x high-z (inputs) sample-z like the sample instruction, the sample-z instruction causes the logic levels of the signals composing the srams i/o ring (see the boundary scan register description for the complete list of signals) to be loaded into the boundary scan reg- ister when the tap controller is in the capture-dr state, and causes the boundary scan register to be inserted between tdi and tdo when the tap controller is in the shift-dr state. however, unlike the sample instruction, the sample-z instruction does affect the state of the srams data output driv- ers (dqs). specifically, the dqs are forced to a high-z (input) state, allowing an external source to drive these signals as inputs during this instruction. tap controller the tap controller is a 16-state state machine that controls access to the various tap registers and executes the operations associated with each tap instruction (see figure 3). state transitions are controlled by tms and occur on the rising edge of tck. the tap controller enters the test-logic reset state in one of two ways: 1. at power up. 2. when a logic 1 is applied to tms for at least 5 consecutive rising edges of tck. the tdi input receiver is sampled only when the tap controller is in either the shift-ir state or the shift-dr state. the tdo output driver is active only when the tap controller is in either the shift-ir state or the shift-dr state.
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 21 / 24 june 23, 2000 tap controller state diagram figure 3 test-logic reset run-test / idle select dr-scan select ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 22 / 24 june 23, 2000 ordering information . part number v dd i/o type size speed (cycle / access time) cxk77s36l80agb-4 cxk77s36l80agb-4a cxk77s36l80agb-4b 3.3v hstl 256k x 36 4.0ns / 3.9ns 4.0ns / 3.8ns 4.0ns / 3.7ns cxk77s36l80agb-42 cxk77s36l80agb-42a cxk77s36l80agb-42b 3.3v hstl 256k x 36 4.2ns / 4.2ns 4.2ns / 4.1ns 4.2ns / 4.0ns cxk77s36l80agb-43 cxk77s36l80agb-43a cxk77s36l80agb-43b 3.3v htsl 256k x 36 4.3ns / 4.5ns 4.3ns / 4.4ns 4.3ns / 4.3ns cxk77s36l80agb-44 3.3v hstl 256k x 36 4.4ns / 4.7ns cxk77s18l80agb-4 CXK77S18L80AGB-4A cxk77s18l80agb-4b 3.3v hstl 512k x 18 4.0ns / 3.9ns 4.0ns / 3.8ns 4.0ns / 3.7ns cxk77s18l80agb-42 cxk77s18l80agb-42a cxk77s18l80agb-42b 3.3v hstl 512k x 18 4.2ns / 4.2ns 4.2ns / 4.1ns 4.2ns / 4.0ns cxk77s18l80agb-43 cxk77s18l80agb-43a cxk77s18l80agb-43b 3.3v htsl 512k x 18 4.3ns / 4.5ns 4.3ns / 4.4ns 4.3ns / 4.3ns cxk77s18l80agb-44 3.3v hstl 512k x 18 4.4ns / 4.7ns sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illu s- trating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circui ts.
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 23 / 24 june 23, 2000 13.0 a x4 b 2.5 max 0.6 0.1 s 7.62 1.27 119 - f 0.75 0.15 s ab (7x17) 119 pin bga package dimensions s 14.0 s a 0.15 12 345 67 a b c d e f g h j k l m n p r t u f 0.15 m 0.15 0.20 preliminary preliminary 4- c 0.7 4- c 1.0 19.0 22.0 0.15 s b 0.35 s 20.32 sony code eiaj code jedec code package material borad treatment lead material package mass solder package structure bga-119p-021 bga119-p-1422 epoxy resin copper-clad laminate 1.3g
sony ? cxk77s36l80agb / cxk77s18l80agb preliminary 8mb, sync lw, r-l, hstl, rev 1.3 24 / 24 june 23, 2000 revision history rev. # rev. date description of modification rev 0.0 09/03/99 initial version rev 0.1 09/29/99 1. modified ac timing characteristics (p. 11). -4 t dvkh 0.5ns to 0.4ns 2. added guaranteed by design ac timing characteristics (p. 12). -4 t khqz (min) at gate of output driver, when t khqv 3.8ns t khqv - 2.4ns t khqz (max) at gate of output driver, when t khqv 3.8ns 2.0ns rev 1.0 10/29/99 1. modified dc recommended operating conditions (p. 8). v ih (max) ac (note 2) v ddq + 1.5v to v ddq + 1.0v v il (min) ac (note 3) -1.5v to -1.0v v ih (max) ac and v il (min) ac duration (max) 1ns to (t cyc / 4) removed output impedance control resistor (rq) specifications. 2. modified dc electrical characteristics (p. 9). updated max and typ average power supply operating currents (i dd ). updated max and typ average power supply operating current at 3 mhz (i dd3 ). updated max and typ power supply standby current (i sb ). updated output driver impedance - specified pull-up and pull-down min, typ, and max r out output impedance per various rq impedance control resistor values. 3. modified jtag dc recommended operating conditions (p. 17). v tih (max) 2.6v to 2.8v rev 1.1 11/10/99 1. modified ac timing characteristics (p. 11). added note 4 regarding address, write enables, synchronous select, and data input setup times in the -4 bin that states these parameters are measured from v ref 200mv to the clock mid-point (-4 bin only). -4 t avkh , t wvkh , t svkh , t dvkh 0.4ns to 0.3ns rev 1.2 04/11/00 1. modified dc electrical characteristics (p. 9). i dd3 (max) 200ma to 300ma i sb (max) 75ma to 100ma 2. modified ac electrical characteristics (p. 11). indicated that t gvkh and t khgx are sampled and not 100% tested. 3. modified jtag dc recommended operating conditions (p. 17). v toh (min) 1.9v to 2.6v rev 1.3 06/23/00 1. added bga package thermal characteristics (p. 7). junction to case temperature ( q jc ) 1.0 c/w 2. modified dc recommended operating conditions (p. 8). v ddq (min) 1.4v to 1.8v v ref , v x (max) 1.1v to 1.0v v ref , v cm , v x (min) 0.55v to 0.7v 3. modified dc electrical characteristics (p. 9). updated output driver impedance - a. combined separate pull-up / pull-down specs into one common spec for both. b. changed max end of rq operating range from 225 w for pull-up and 175 w for pull- down to 150 w for the common spec. 4. removed 1.5v hstl ac test condition. 5. added note to disabling the tap section that states that tap operation does not interfere with normal sram operation except during the sample-z instruction (p. 15). 6. modified jtag ac test conditions (p. 15). corrected v dd test condition 2.5v 5% to 3.3v 5%

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