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lc 2 mos microprocessor-compatible 14-bit dac ad7538 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features all grades 14-bit monotonic over the full temperature range low cost, 14-bit upgrade for 12-bit systems 14-bit parallel load with double buffered inputs small 24-pin, 0.30 dip and soic low output leakage (<20 na) over the full temperature range applications microprocessor-based control systems digital audio precision servo control control and measurement in high temperature environments functional block diagram 2 23 1 3 4 20 21 22 24 5 619 14-bit dac dac register input register 14 ad7538 db13 to db0 dgnd v dd v ss wr cs ldac agnd i out v ref r fb 01139-001 figure 1. general description the ad7538 is a 14-bit monolithic cmos digital-to-analog converter (dac) that uses laser trimmed thin-film resistors to achieve excellent linearity. the dac is loaded by a single 14-bit wide word using standard chip select and memory write logic. double buffering, which is optional using ldac , allows simultaneous updates in a system containing multiple ad7538s. a novel low leakage configuration (u.s. patent no. 4,590,456) enables the ad7538 to exhibit excellent output leakage current characteristics over the specified temperature range. the ad7538 is manufactured using the linear-compatible cmos (lc 2 mos) process. it is speed compatible with most microprocessors and accepts ttl or cmos logic level inputs. product highlights 1. guaranteed monotonicity. the ad7538 is guaranteed monotonic to 14-bits over the full temperature range for all grades. 2. low cost. the ad7538, with its 14-bit dynamic range, affords a low cost solution for 12-bit system upgrades. 3. small package size. the ad7538 is packaged in a small 24-pin, 0.3" dip and a 24-pin soic. 4. low output leakage. by tying v ss (pin 24) to a negative voltage, it is possible to achieve a low output leakage current at high temperatures. 5. wide power supply tolerance. the device operates on a +12 v to +15 v v dd , with a 5% tolerance on this nominal figure. all specifications are guaranteed over this range.
ad7538 rev. b | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac performance characteristics ................................................ 4 timing characteristics ................................................................ 4 timing diagram ........................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 terminology ...................................................................................... 8 dac section ...................................................................................... 9 circuit information ........................................................................ 10 equivalent circuit analysis ...................................................... 10 digital section ............................................................................ 10 unipolar binary operation (2-quadrant multiplication) .... 10 bipolar operation (4-quadrant multiplication) .................... 11 low leakage configuration ...................................................... 11 programmable gain amplifier ................................................. 12 application hints ........................................................................... 13 output offset .............................................................................. 13 general ground management .................................................. 13 microprocessor interfacing ....................................................... 13 ad7538-to-8086 interface ........................................................ 13 ad7538-to-mc68000 interface ............................................... 13 digital feedthrough ................................................................... 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 16 revision history 1/09rev. a to rev. b updated format .................................................................. universal changes to table 1 ............................................................................ 3 updated outline dimensions ....................................................... 15 changes to ordering guide .......................................................... 15 5/87rev. 0 to rev. a
ad7538 rev. b | page 3 of 16 specifications v dd = 11.4 v to 15.75 v 1 , v ref = 10 v; v pin3 = v pin4 = 0 v, v ss = ?300 mv; all specifications t min to t max , unless otherwise noted. table 1. parameter 2 a, j versions b, k versions s version t version unit test conditions/comments accuracy resolution 14 14 14 14 bits relative accuracy 2 1 2 1 lsb max all grades guaranteed monotonic differential nonlinearity 1 1 1 1 lsb max over temperature full-scale error measured using internal r fb dac +25c 4 4 4 4 lsb max registers loaded with all 1s t min to t max 8 5 10 6 lsb max gain temperature coefficient 3 ; gain/temperature 2 2 2 2 ppm/c typ output leakage current i out (pin 3) 25c 5 5 5 5 na max all digital inputs 0 v t min to t max 10 10 20 20 na max v ss = C300 mv t min to t max 25 25 150 150 na max v ss = 0 v reference input input resistance (pin 1) 3.5 3.5 3.5 3.5 k min typical input resistance = 6 k 10 10 10 10 k max digital inputs v ih (input high voltage) 2.4 2.4 2.4 2.4 v min v il (input low voltage) 0.8 0.8 0.8 0.8 v max i in (input current) 25c 1 1 1 1 a max v in = 0 v or v dd t min to t max 10 10 10 10 a max c in (input capacitance) 3 7 7 7 7 pf max power supply v dd range 11.4/15.75 11.4/15.75 11.4/15.75 11.4/15.75 v min/v max specification guaranteed over this range v ss range ?200/?500 ?200/ ?500 ?200/?500 ?200/?500 mv min/ mv max specification guaranteed over this range i dd 4 4 4 4 ma max all digital inputs are v il or v ih 500 500 500 500 a max all digital inputs are 0 v or v dd 1 specifications are guaranteed for a v dd of 11.4 v to 15.75 v. at v dd = 5 v, the device is fully functional with degraded specifications. 2 temperature range as follows: j, k versions: 0c to +70c a, b versions: ?25c to +85c s, t versions: ?55c to +125c 3 sample tested to ensure compliance.
ad7538 rev. b | page 4 of 16 ac performance characteristics these characteristics are included for design guidance only and are not subject to test. v dd = 11.4 v to 15.75 v, v ref = 10 v, v pin3 = v pin4 = 0 v, v ss = 0 v or ?300 mv, output amplifier is ad711 except where noted. table 2. parameter t a = 25c t a = t min , t max unit test conditions/comments output current settling time 1.5 s max to 0.003% of full-scale range i out load= 100 , c ext = 13 pf dac register alternately loaded with all 1s and all 0s; typical value of settling time is 0.8 s digital-to-analog glitch impulse 20 nv-sec typ measured with v ref = 0 v. i out load = 100 , c ext = 13 pf; dac register alternately loaded with all 1s and all 0s multiplying feedthrough error 3 5 mv p-p typ v ref = 10 v, 10 khz sine wave dac register loaded with all 0s power supply rejection gain/v dd 0.01 0.02 % per % max v dd = 5% output capacitance c out (pin 3) 260 260 pf max dac register loaded with all 1s c out (pin 3) 130 130 pf max dac register loaded with all 0s output noise voltage density (10 hz to 100 khz) 15 nvhz typ measured between r fb and i out timing characteristics v dd = 11.4 v to 15.75 v, v ref = 10 v, v pin3 = v pin4 = 0 v, v ss = 0 v or ?300 mv. all specifications t min to t max unless otherwise noted. see figure 2 for a timing diagram. table 3. parameter 1 limit at t a = +25c limit at t a = 0c to +70c t a = ?25c to +85c limit at t a = ?55c to +125c unit test conditions/comments t 1 0 0 0 ns min cs to wr setup time t 2 0 0 0 ns min cs to wr hold time t 3 170 200 240 ns min ldac pulse width t 4 170 200 240 ns min write pulse width t 5 140 160 180 ns min data setup time t 6 20 20 30 ns min data hold time 1 temperature range as follows: j, k versions: 0c to +70c a, b versions: ?25c to +85c s, t versions: ?55c to +125c
ad7538 rev. b | page 5 of 16 timing diagram cs ldac wr data 5v 0v 5v 0v 5v 0v 5v 0v notes 1. all input signal rise and fall times measures from 10% to 90% of 5v, t r = t f = 20ns. 2. timing measurement reference level is . 3. if ldac is activated prior to the rising edge of wr, then it must stay low for t 3 or longer after wr goes high. v ih + v il 2 t 1 t 6 t 5 t 2 t 3 t 4 01139-002 figure 2. timing diagram
ad7538 rev. b | page 6 of 16 absolute maximum ratings t a = +25c unless, otherwise stated. table 4. parameter rating v dd (pin 23) to dgnd ?0.3 v, +17 v v ss (pin 24) to agnd ?15 v, +0.3 v v ref (pin 1) to agnd 25 v v rfb (pin 2) to agnd 25 v digital input voltage (pins 6 to 22) to dgnd ?0.3 v, v dd +0.3 v v pin3 to dgnd ?0.3 v, v dd +0.3 v agnd to dgnd ?0.3 v, v dd +0.3 v power dissipation (any package) to 75c 1000 mw derates above 75c 10 mw/c operating temperature range commercial (j, k versions) 0c to +70c industrial (a, b versions) ?25c to +85c extended (s, t versions) ?55c to +125c storage temperature ?65c to +150c lead temperature (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7538 rev. b | page 7 of 16 pin configuration and fu nction descriptions v ref 1 r fb 2 i out 3 agnd 4 v ss 24 v dd 23 wr 22 cs 21 dgnd 5 (msb) db13 6 db12 7 ldac 20 db0 (lsb) 19 db1 18 db11 8 db2 17 db10 9 db3 16 db9 10 db4 15 db8 11 db5 14 db7 12 db6 13 ad7538 top view (not to scale) 0 1139-003 figure 3. pin configuration table 5. pin function description pin no. mnemonic description 1 v ref voltage reference. 2 r fb feedback resistor. used to close the loop around an external op amp. 3 i out current output terminal. 4 agnd analog ground 5 dgnd digital ground. 6 to 19 db13 to db0 data inputs. bit db13 (msb) to bit db0 (lsb). 20 ldac chip select input. active low. 21 cs asynchronous load dac input. active low. 22 wr write input. active low. cs ldac wr operation 0 1 0 load input register. 1 0 x 1 load dac register from input register. 0 0 0 input and dac registers are transparent. 1 1 x 1 no operation. x x 1 1 1 no operation. 23 v dd +12 v to +15 v supply input. 24 v ss bias pin for high temperature low leakage configuration. to implement low leakage system, the pin should be at a negative voltage. see figure 6 and figure 8 for recommended circuitry. 1 x = dont care.
ad7538 rev. b | page 8 of 16 terminology relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero error and full-scale error and is normally expressed in least significant bits or as a percentage of full- scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum over the operating temperature range ensures monotonicity. gain error gain error is a measure of the output error between an ideal dac and the actual device output. it is measured with all 1s in the dac after the offset error has been adjusted out and is expressed in least significant bits. gain error is adjustable to zero with an external potentiometer. digital-to-analog glitch impulse the amount of charge injected from the digital inputs to the analog output when the inputs change state is called digital-to- analog glitch impulse. this is normally specified as the area of the glitch in either pa-secs or nv-secs depending upon whether the glitch is measured as a current or voltage. it is measured with v ref = agnd. output capacitance this is the capacitance from i out to agnd. output leakage current output leakage current is current which appears at i out with the dac register loaded to all 0s. multiplying feedthrough error this is the ac error due to capacitive feedthrough from the v ref terminal to i out with the dac register loaded to all zeros.
ad7538 rev. b | page 9 of 16 dac section figure 4 shows a simplified circuit diagram for the ad7538 dac section. the three msbs of the 14-bit data word are decoded to drive the seven switches (a to g). the 11 lsbs of the data word consist of an r-2r ladder operated in a current steering configuration. the r-2r ladder current is ? of the total reference input current. ? current flows in the parallel ladder structure. switch a to switch g steer equally weighted currents between i out and agnd. because the input resistance at v ref is constant, it may be driven by a voltage source or a current source of positive or negative polarity. 2r 2r 2r 2r 2r 2r 2r 2r 2r 2r 2r rr r r/4 g f e d c b a s10 s9 s0 v ref r fb i out agnd 01139-004 figure 4. simplified circuit diagram for the ad7538 dac section
ad7538 rev. b | page 10 of 16 circuit information equivalent circuit analysis figure 5 shows an equivalent circuit for the analog section of the ad7538 dac. the current source i leakage is composed of surface and junction leakages. the r o resistor denotes the equivalent output resistance of the dac, which varies with input code. c out is the capacitance due to the current steering switches and varies from about 90 pf to 180 pf (typical values) depending upon the digital input. g(v ref , n) is the thevenin equivalent voltage generator due to the reference input voltage, v ref , and the transfer function of the dac ladder, n. i leakage c out i out agnd r fb r o r/4 g (v ref , n) 01139-005 figure 5. ad7538 equivalent analog output circuit digital section the digital inputs are designed to be both ttl and 5 v cmos compatible. all logic inputs are static protected mos gates with typical input currents of less than 1 na. to minimize power supply currents, it is recommended that the digital input voltages be driven as close as possible to 0 v and 5 v logic levels. unipolar binary op eration (2-quadrant multiplication) figure 6 shows the circuit diagram for unipolar binary operation. with an ac input, the circuit performs 2-quadrant multiplication. the code table for figure 6 is given in table 6. capacitor c1 provides phase compensation and helps prevent overshoot and ringing when high-speed op amps are used. 619 5 24 23 1 20 21 22 2 3 4 db13 to db0 dgnd v dd v ref v in r fb i out v dd v o ?15v agnd v ss ldac cs wr ldac cs wr ad7538 a1 r3 1k? r2 10? r1 20 ? r4 47k? input data digital gnd c2 4.7f c1 33pf analog gnd ad711 01139-006 + figure 6. unipolar binary operation table 6. unipolar binary code table binary number in dac register analog output, v out msb lsb 11 1111 1111 1111 ? v in (16,383/16,384) 10 0000 0000 0000 ? v in (8192/16,384) = ?? v in 00 0000 0000 0001 ? v in (1/16,384) 00 0000 0000 0000 0 v for zero offset adjustment, the dac register is loaded with all 0s and amplifier offset (v os ) adjusted so that v out is 0 v. adjusting v out to 0 v is not necessary in many applications, but it is recommended that v os be no greater than (25 10 ?6 ) (v ref ) to maintain specified dac accuracy (see the application hints section). full-scale trimming is accomplished by loading the dac register with all 1s and adjusting r1 so that v outa = ?v in (16,383/16,384). for high temperature operation, resistors and potentiometers should have a low temperature coefficient. in many applications, because of the excellent gain tc and gain error specifications of the ad7538, gain error trimming is not necessary. in fixed reference applications, full scale can also be adjusted by omitting r1 and r2 and trimming the reference voltage magnitude.
ad7538 rev. b | page 11 of 16 bipolar operation (4-quadrant multiplication) the recommended circuit diagram for bipolar operation is shown in figure 8 . offset binary coding is used. the code table for figure 8 is given in table 7 . with the dac loaded to 10 0000 0000 0000, adjust r1 for v o = 0 v. alternatively, one can omit r1 and r2 and adjust the ratio of r5 and r6 for v o = 0 v. full-scale trimming can be accom- plished by adjusting the amplitude of v in or by varying the value of r7. the values given for r1, r2 are the minimum necessary to calibrate the system for resistors r5, r6, r7 ratio matched to 0.1%. system linearity error is independent of resistor ratio matching and is affected by dac linearity error only. when operating over a wide temperature range, it is important that the resistors be of the same type so that their temperature coefficients match. low leakage configuration for cmos multiplying dac, as the device is operated at higher temperatures, the output leakage current increases. for a 14-bit resolution system, this can be a significant source of error. the ad7538 features a leakage reduction configuration (u.s. patent no. 4,590,456) to keep the leakage current low over an extended temperature range. one may operate the device with or without this configuration. if v ss (pin 24) is tied to agnd then the dac exhibits normal output leakage currents at high temperatures. to use the low leakage facility, v ss should be tied to a voltage of approximately ?0.3 v as in figure 6 and figure 8 . a simple resistor divider (r3, r4) produces approximately ?300 mv from ?15 v. the c2 capacitor in parallel with r3 is an integral part of the low leakage configuration and must be 4.7 f or greater. figure 7 is a plot of leakage current vs. temperature for both conditions. it clearly shows the improvement gained by using the low leakage configuration. table 7. bipolar code table fo r the offset binary circuit of figure 8 binary number in dac register analog output v out msb lsb 11 1111 1111 1111 + v in (8191/8192) 10 0000 0000 0001 + v in (1/8192) 10 0000 0000 0000 0 v 01 1111 1111 1111 ?v in (1/8192) 00 0000 0000 0000 ? v in (8191/8192) 30 40 50 60 70 80 90 100 110 120 temperature (c) leakage current (na) 60 50 40 30 20 10 0 v dd = 15v v ref = 10v v ss = 0v v ss = ?0.3v 01139-008 figure 7. graph of typical leakage current vs. temperature for ad7538 619 5 24 23 1 20 21 22 2 3 4 db13 to db0 dgnd v dd v ref r fb i out v dd ?15v agnd v ss ldac cs wr ldac cs wr ad7538 a1 r3 1k ? r2 22? r5 10k ? r7 20k ? r6 20k ? r8 5k ? , 10% r1 50 ? r4 47k ? input data digital gnd c2 4.7f c1 33pf analog gnd ad711 a2 ad711 01139-007 v in v o + figure 8. bipolar operation
ad7538 rev. b | page 12 of 16 programmable gain amplifier the circuit shown in figure 9 provides a programmable gain amplifier (pga). in it the dac behaves as a programmable resistance and thus allows the circuit gain to be digitally controlled. ad7538 n i out v dd v dd v ss v out v in v ref gnd digital input a a r fb notes 1. resistor r fb is actually included on the dice. 01139-009 figure 9. programmable gain amplifier (pga) the transfer function of figure 9 is: fb eq in out r r v v gain ?== (1) r eq is the equivalent transfer impedance of the dac from the v ref pin to the i out pin and can be expressed as n r r in n eq 2 = (2) where: n is the resolution of the dac. n is the dac input code in decimal. r in is the constant input impedance of the dac (r in = r lad ). substituting this expression into equation 1 and assuming zero gain error for the dac (r in = r fb ), the transfer function simplifies to nv v n in out 2 ?= (3) the ratio n/2 n is commonly represented by the term, d, and, as such, is the fractional representation of the digital input word. dnv v n in out 12 ? = ? ?= (4) equation 4 indicates that the gain of the circuit can be varied from 16,384 down to unity (actually 16,384/16,383) in 16,383 steps. the all 0s code is never applied. this avoids an open-loop condition thereby saturating the amplifier. with the all 0s code excluded there remains (2 n C 1) possible input codes allowing a choice of (2 n C 1) output levels. in decibels the dynamic range is ( ) db8412log20 log20 10 10 =? = n in out v v
ad7538 rev. b | page 13 of 16 application hints output offset cmos dacs in circuits such as figure 6 and figure 8 exhibit a code dependent output resistance, which in turn can cause a code dependent error voltage at the output of the amplifier. the maximum amplitude of this error, which adds to the dac nonlinearity, depends on v os , where v os is the amplifier input offset voltage. to maintain specified accuracy with v ref at 10 v, it is recommended that v os be no greater than 0.25 mv, or (25 10 ?6 ) (v ref ), over the temperature range of operation. the ad711 is a suitable op amp. the op amp has a wide bandwidth and high slew rate and is recommended for ac and other applications requiring fast settling. general ground management because the ad7538 is specified for high accuracy, it is impor- tant to use a proper grounding technique. ac or transient voltages between agnd and dgnd can cause noise injection into the analog output. the simplest method of ensuring that voltages at agnd and dgnd are equal is to tie agnd and dgnd together at the ad7538. in more complex systems where the agnd and dgnd intertie on the backplane, it is recommended that two diodes be connected in inverse parallel between the ad7538 agnd and dgnd pins (1n914 or equivalent). microprocessor interfacing the ad7538 is designed for easy interfacing to 16-bit micro- processors and can be treated as a memory mapped peripheral. this reduces the amount of external logic needed for interfacing to a minimal. ad7538-to-8086 interface figure 10 shows the 8086 processor interface to a single device. in this setup, the double buffering feature (using ldac ) of the dac is not used. the 14-bit word is written to the dac in one move instruction and the analog output responds immediately. address bus data bus ad0 to ad15 wr ale ad13 ad0 cs ldac wr db0 to db13 8096 ad7538 1 1 linear circuitry omitted for clarity. 01139-010 16-bit latch address decode figure 10. ad7538-to-8086 interface circuit in a multiple dac system, the double buffering of the ad7538 allows the user to simultaneously update all dacs. in figure 11 , a 14-bit word is loaded to the input registers of each of the dacs in sequence. then, with one instruction to the appropriate address, cs4 (that is, ldac ) is brought low, updating all the dacs simultaneously. address bus data bus ad0 to ad15 wr ale cs ldac wr db0 to db13 8096 ad7538 1 1 linear circuitry omitted for clarity. 01139-011 16-bit latch address decode cs4 cs3 cs2 cs1 cs ldac wr db0 to db13 ad7538 1 cs ldac wr db0 to db13 ad7538 1 figure 11. ad7538-to-8086 interface: multiple dac system ad7538-to-mc68000 interface figure 12 shows the mc68000 processor interface to a single device. in this setup, the double buffering feature of the dac is not used and the appropriate data is written into the dac in one move instruction. address bus data bus address decode d0 to d15 a1 to a23 r/w dtack as cs ldac wr db0 to db13 mc68000 ad7538 1 1 linear circuitry omitted for clarity. 01139-012 figure 12. ad7538-to-mc68000 interface
ad7538 rev. b | page 14 of 16 digital feedthrough the digital inputs to the ad7538 are directly connected to the microprocessor bus in the preceding interface configurations. these inputs are constantly changing even when the device is not selected. the high frequency logic activity on the bus can feed through the dac package capacitance to show up as noise on the analog output. to minimize this digital feedthrough isolate the dac from the noise source. figure 13 shows an interface circuit, which uses this technique. all data inputs are latched from the bus by the cs signal. one may also use other means, such as peripheral interface devices, to reduce the digital feedthrough. d0 to d15 wr a0 to a15 cs ldac wr db0 to db13 micro- processor system ad7538 1 1 linear circuitry omitted for clarity. 01139-013 address decode 16-bit latch en figure 13. ad7538 interface circuit using latches to minimize digital feedthrough
ad7538 rev. b | page 15 of 16 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001 071006-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 24 1 12 13 0.100 (2.54) bsc 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 14. 24-lead plastic dual in-line package [pdip] narrow body (n-24-1) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 24 11 2 13 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 1.280 (32.51) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) pin 1 100808-a figure 15. 24-lead ceramic dual in-lin e package [cerdip] (q-24-1) dimensions shown in inches and (millimeters)
ad7538 rev. b | page 16 of 16 compliant to jedec standards ms-013-ad controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 15.60 (0.6142) 15.20 (0.5984) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 24 13 12 1 1.27 (0.0500) bsc 060706-a figure 16. 24-lead standard small outline package [soic_w] wide body (rw-24) dimensions shown in millimeters and (inches) ordering guide model temperature range relative accuracy fu ll-scale error package description package option ad7538jn 0c to +70c 2 lsb 8 lsb 24-lead pdip n-24-1 ad7538jnz 1 0c to +70c 2 lsb 8 lsb 24-lead pdip n-24-1 ad7538kn 0c to +70c 1 lsb 5 lsb 24-lead pdip n-24-1 ad7538knz 1 0c to +70c 1 lsb 5 lsb 24-lead pdip n-24-1 ad7538jr 0c to +70c 2 lsb 8 lsb 24-lead soic_w rw-24 AD7538JR-REEL 0c to +70c 2 lsb 8 lsb 24-lead soic_w rw-24 ad7538jrz 1 0c to +70c 2 lsb 8 lsb 24-lead soic_w rw-24 ad7538jrz-reel 1 0c to +70c 2 lsb 8 lsb 24-lead soic_w rw-24 ad7538kr 0c to +70c 1 lsb 5 lsb 24-lead soic_w rw-24 ad7538kr-reel 0c to +70c 1 lsb 5 lsb 24-lead soic_w rw-24 ad7538krz 1 0c to +70c 1 lsb 5 lsb 24-lead soic_w rw-24 ad7538krz-reel 1 0c to +70c 1 lsb 5 lsb 24-lead soic_w rw-24 ad7538aq ?25c to +85c 2 lsb 8 lsb 24-lead cerdip q-24-1 ad7538bq ?25c to +85c 1 lsb 5 lsb 24-lead cerdip q-24-1 ad7538sq ?55c to +125c 2 lsb 10 lsb 24-lead cerdip q-24-1 ad7538tq ?55c to +125c 1 lsb 6 lsb 24-lead cerdip q-24-1 1 z = rohs compliant part. ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d01139-0-1/09(b)

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