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ltc3414 1 3414fb point-of-load regulation notebook computers portable instruments distributed power systems high efficiency: up to 95% 4a output current low quiescent current: 64 a low r ds(on) internal switch: 67m programmable frequency: 300khz to 4mhz 2.25v to 5.5v input voltage range 2% output voltage accuracy 0.8v reference allows low output voltage selectable forced continuous/burst mode ? operation with adjustable burst clamp synchronizable switching frequency low dropout operation: 100% duty cycle power good output voltage monitor overtemperature protected available in 20-lead exposed tssop package 4a, 4mhz, monolithic synchronous step-down regulator the ltc ? 3414 is a high efficiency monolithic synchro- nous, step-down dc/dc converter utilizing a constant frequency, current mode architecture. it operates from an input voltage range of 2.25v to 5.5v and provides a regulated output voltage from 0.8v to 5v while delivering up to 4a of output current. the internal synchronous power switch with 67m on-resistance increases effi- ciency and eliminates the need for an external schottky diode. switching frequency is set by an external resistor or can be synchronized to an external clock. 100% duty cycle provides low dropout operation extending battery life in portable systems. opti-loop ? compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the ltc3414 can be configured for either burst mode operation or forced continuous operation. forced continu- ous operation reduces noise and rf interference while burst mode operation provides high efficiency by reduc- ing gate charge losses at light loads. in burst mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the requirements of the application. 3414 f01a sync/mode v fb pgood sw pgnd sgnd rt run/ss i th sv in pv in ltc3414 294k 22 f c out * 0.47 h v out 2.5v at 4a v in 2.7v to 5.5v 1000pf 2.2m 470pf r ith * 75k 110k 392k *burst mode operation: c out = 470 f sanyo poscap 4tpb470m, r ith = 20k forced continuous: c out = (2) 100 f tdkc4532x5roj107m, r ith = 12.1k ltc3414 efficiency curve figure 1. 2.5v/4a step-down regulator load current (a) efficiency (%) 100 95 90 85 80 75 70 65 60 55 50 0.001 0.1 1.0 10 3414 f01b 0.01 burst mode operation forced continuous features descriptio u applicatio s u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. burst mode and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174
ltc3414 2 3414fb input supply voltage ................................... e0.3v to 6v i th , run/ss, v fb , sync/mode voltages .................................. e0.3 to v in sw voltages ................................. e0.3v to (v in + 0.3v) peak sw sink and source current ......................... 9.5a operating temperature range (note 2) e, i grades .............................................. e 40 c to 85 c mp grade ............................................. e 55 c to 125 c junction temperature (notes 5, 6) ....................... 125 c storage temperature range ................. e 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number exposed pad (pin 21), must be soldered to pcb t jmax = 125 c, v ja = 38c/w, v jc = 10c/w ltc3414efe ltc3414ife ltc3414mpfe absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3414e is guaranteed to meet performance specifications from 0 c to 85 c. specifications over the e40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3414i is guaranteed over the full e40 c to 85 c operating temperature range. the ltc3414mp is guaranteed over the full e55 c to 125 c operating tempaerature range. note 3: the ltc3414 is tested in a feedback loop that adjusts v fb to the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 3.3v unless otherwise specified. symbol parameter conditions min typ max units v in input voltage range 2.25 5.5 v i fb feedback pin input current (note 3) 0.2 r a v fb regulated feedback voltage e, i grade (note 3) 0.784 0.800 0.816 v mp grade 0.780 0.800 0.816 v ) v fb reference voltage line regulation v in = 2.7v to 5.5v (note 3) 0.04 0.2 %v v loadreg output voltage load regulation measured in servo loop, v ith = 0.36v 0.02 0.2 % mesured in servo loop, v ith = 0.84v e0.02 e0.2 % ) v pgood power good range 7.5 9% r pgood power good resistance 120 200 < i q input dc bias current (note 4) active current v fb = 0.75v, v ith = 1.2v 250 330 r a sleep v fb = 1v, v ith = 0v, v sync/mode = 0v 64 100 r a shutdown v run = 0v 0.02 1 r a f osc switching frequency r osc = 294k 0.88 1.00 1.12 mhz switching frequency range 0.3 4 mhz f sync sync capture range 0.3 4 mhz r pfet r ds(on) of p-channel fet i sw = 300ma 67 100 m < r nfet r ds(on) of n-channel fet i sw = e300ma 50 100 m < i limit peak current limit 6 8 a v uvlo undervoltage lockout threshold 1.75 2.00 2.25 v i lsw sw leakage current v run = 0v, v in = 5.5v 0.1 1.0 r a v run run threshold 0.5 0.65 0.8 v 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 pgnd rt sync/mode run/ss sgnd nc pv in sw sw pgnd pgnd v fb i th pgood sv in nc pv in sw sw pgnd fe package 20-lead plastic tssop 21 achieve a specified error amplifier output voltage (i th ). note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient temperature t a and power dissipation p d as follows: t j =t a + (p d )(38 c/w) note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliabability. order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
ltc3414 3 3414fb typical perfor a ce characteristics uw v ref vs temperature, v in = 3.3v switch on-resistance vs input voltage switch on-resistance vs temperature, v in = 3.3v temperature ( c) C40 0.795 v ref (v) 0.796 0.798 0.799 0.800 0 40 60 140 3414 g01 0.797 C20 20 80 100 120 input voltage (v) 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 on-resistance (m ) 90 80 70 60 50 40 30 20 10 0 3414 g02 pfet nfet t a = 25 c temperature ( c) C40 on-resistance (m ) 120 100 80 60 40 20 0 C25 3414 g03 C10 520 35 50 65 80 95 110 125 pfet nfet input voltage (v) 2.25 switch leakage current (na) 20 18 16 14 12 10 8 6 4 2 0 3.25 4.25 4.75 3414 g04 2.75 3.75 5.25 input voltage (v) 2.25 3.25 4.25 4.75 2.75 3.75 5.25 pfet nfet r osc (k) 25 frequency (khz) 7000 6000 5000 4000 3000 2000 1000 0 3414 g05 225 925 825 725 625 525 125 325 425 1040 1020 1000 980 960 940 920 900 3414 g06 frequency (khz) temperature ( c) C40 60 1090 1070 1050 1030 1010 990 970 950 930 910 3414 g07 C20 120 02040 80 100 input voltage (v) 2.25 350 300 250 200 150 100 50 0 3.75 4.75 3414 g08 2.75 3.25 4.25 5.25 quiescent current ( a) burst clamp voltage (v) 0 minimum peak inductor current (a) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.2 0.4 0.5 3414 g09 0.1 0.3 0.6 0.7 0.8 frequency (khz) active sleep v in = 3.3v t a = 25 c v in = 3.3v t a = 25 c v in = 3.3v r osc = 294k r osc = 294k t a = 25 c t a = 25 c t a = 25 c frequency vs temperature dc supply current vs input voltage minimum peak inductor current vs burst clamp voltage switch leakage vs input voltage frequency vs r osc frequency vs input voltage
ltc3414 4 3414fb load current (a) efficiency (%) 100 95 90 85 80 75 70 65 60 55 50 0.001 0.1 1 10 3414 g10 0.01 load current (a) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.001 0.1 1 10 0.01 3414 g11 input voltage (v) 2.5 efficiency (%) 3.0 3.5 4.0 4.5 3414 g13 5.0 98 96 94 92 90 88 86 84 82 80 78 5.5 load current (a) v out /v out (%) 3414 g15 0 C0.05 C0.10 C0.15 C0.20 C0.25 C0.30 0 1.0 2.0 2.5 0.5 1.5 3.0 3.5 4.0 frequency (khz) efficiency (%) 3414 g14 100 95 90 85 80 75 70 300 1300 2300 2800 800 1800 3300 3800 3414 g16 3414 g17 v in = 3.3v v in = 5v v in = 3.3v v in = 5v i out = 1a i out = 4a l = 0.47 h l = 0.2 h l = 1 h v in = 3.3v, v out = 2.5v load = 250ma output voltage 20mv/div inductor current 500ma/div v in = 3.3v, v out = 2.5v load step = 0a to 4a output voltage 100mv/div inductor current 2a/div load current (a) efficiency (%) 100 95 90 85 80 75 70 65 60 55 50 0.001 0.1 1 10 3414 g12 0.01 burst mode operation forced continuous 10 s/div 20 s/div v in = 3.3v v out = 2.5v v out = 2.5v t a = 25 c v out = 2.5v t a = 25 c v in = 3.3v v out = 2.5v t a = 25 c v in = 3.3v v out = 2.5v t a = 25 c t a = 25 c t a = 25 c typical perfor a ce characteristics uw efficiency vs load current, burst mode operation efficiency vs input voltage efficiency vs frequency efficiency vs load current, forced continuous load regulation burst mode operation load step transient forced continuous efficiency vs load current
ltc3414 5 3414fb pgnd (pins 1, 10, 11, 20): power ground. connect this pin closely to the (C) terminal of c in and c out . rt (pin 2): oscillator resistor input. connecting a resistor to ground from this pin sets the switching frequency. sync/mode (pin 3): mode select and external clock synchronization input. to select forced continuous, tie to sv in . connecting this pin to a voltage between 0v and 1v selects burst mode operation with the burst clamp set to the pin voltage. run/ss (pin 4): run control and soft-start input. forcing this pin below 0.5v shuts down the ltc3414. in shutdown all functions are disabled. less than 1 a of supply current is consumed. a capacitor to ground from this pin sets the ramp time to full output current. sgnd (pin 5): signal ground. all small signal components and compensation components should connect to this ground, which in turn connects to pgnd at one point. nc (pin 6): open. no internal connection. pv in (pins 7, 14): power input supply. decouple this pin to pgnd with a capacitor. sw (pins 8, 9, 12, 13): switch node connection to inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. nc (pin 15): open. no internal connection. sv in (pin 16): signal input supply. decouple this pin to sgnd with a capacitor. pgood (pin 17): power good output. open drain logic output that is pulled to ground when the output voltage is not within 7.5% of regulation point. i th (pin 18): error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is from 0.2v to 1.4v with 0.4v corresponding to the zero-sense voltage (zero current). v fb (pin 19): feedback pin. receives the feedback voltage from a resistive divider connected across the output. exposed pad (pin 21): should be connected to sgnd and soldered to the pcb. uu u pi fu ctio s start-up transient typical perfor a ce characteristics uw 3414 g19 v in = 3.3v, v out = 2.5v load = 4a output voltage inductor current 2a/div v run 1ms/div load step transient burst mode operation 3414 g18 v in = 3.3v, v out = 2.5v load step = 250ma to 4a output voltage 100mv/div inductor current 2a/div 20 s/div
ltc3414 6 3414fb main control loop the ltc3414 is a monolithic, constant-frequency, cur- rent-mode step-down dc/dc converter. during normal operation, the internal top power switch (p-channel mos- fet) is turned on at the beginning of each clock cycle. current in the inductor increases until the current com- parator trips and turns off the top power mosfet. the peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the i th pin. the error amplifier adjusts the voltage on the i th pin by comparing the feedback signal from a resistor divider on the v fb pin with an internal 0.8v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier raises the i th voltage until the average inductor current matches the new load current. when the top power mosfet shuts off, the synchronous power switch (n-channel mosfet) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. the bottom current limit is set at C5a for forced continuous mode and 0a for burst mode operation. the operating frequency is externally set by an external resistor connected between the rt pin and ground. the practical switching frequency can range from 300khz to 4mhz. overvoltage and undervoltage comparators will pull the pgood output low if the output voltage comes out of regulation by 7.5%. in an overvoltage condition, the top power mosfet is turned off and the bottom power mos- fet is switched on until either the overvoltage condition clears or the bottom mosfets current limit is reached. forced continuous mode connecting the sync/mode pin to sv in will disable burst mode operation and force continuous current operation. at light loads, forced continuous mode operation is less efficient than burst mode operation, but may be desirable in some applications where it is necessary to keep switch- operatio u block diagra w C + C + C + C + C + C + C + 16 19 17 4 2 5 18 7 14 slope compensation recovery slope compensation voltage reference oscillator logic 3 0.74v 0.86v run 13 12 9 8 sv in sgnd 21 exposed pad i th pv in pv in pmos current comparator bclamp v fb run/ss pgood rt sync/mode pgnd pgnd pgnd pgnd current reversal compartor nmos current comparator burst comparator error amplifier sw sw sw sw 10 11 20 1 3414 bd sync/mode + v 0.8v
ltc3414 7 3414fb ing harmonics out of a signal band. the output voltage ripple is minimized in this mode. burst mode operation connecting the sync/mode pin to a voltage in the range of 0v to 1v enables burst mode operation. in burst mode operation, the internal power mosfets operate intermit- tently at light loads. this increases efficiency by minimiz- ing switching losses. during burst mode operation, the minimum peak inductor current is externally set by the voltage on the sync/mode pin and the voltage on the i th pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. when the average inductor current is greater than the load current, the voltage on the i th pin drops. as the i th voltage falls below 150mv, the burst comparator trips and enables sleep mode. during sleep mode, the top power mosfet is held off and the i th pin is disconnected from the output of the error amplifier. the majority of the internal circuitry is also turned off to reduce the quiescent current to 64 a while the load current is solely supplied by the output capacitor. when the output voltage drops, the i th pin is reconnected to the output of the error amplifier and the top power mosfet along with all the internal circuitry is switched back on. this process repeats at a rate that is dependent on the load demand. pulse skipping operation is implemented by connecting the sync/mode pin to ground. this forces the burst clamp level to be at 0v. as the load current decreases, the peak inductor current will be determined by the voltage on the i th pin until the i th voltage drops below 400mv. at this point, the peak inductor current is determined by the minimum on-time of the current comparator. if the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output voltage in regulation. frequency synchronization the internal oscillator of the ltc3414 can be synchronized to an external clock connected to the sync/mode pin. the frequency of the external clock can be in the range of 300khz to 4mhz. for this application, the oscillator timing resistor should be chosen to correspond to a frequency that is 25% lower than the synchronization frequency. during synchronization, the burst clamp is set to 0v, and each switching cycle begins at the falling edge of the clock signal. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maxi- mum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. low supply operation the ltc3414 is designed to operate down to an input supply voltage of 2.25v. one important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases. the user should calculate the power dissipation when the ltc3414 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. slope compensation and inductor peak current slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscilla- tions at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, the maximum inductor peak current is reduced when slope compensation is added. in the ltc3414, however, slope compensation recovery is implemented to keep the maximum inductor peak current constant throughout the range of duty cycles. this keeps the maximum output current relatively constant regardless of duty cycle. short-circuit protection when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. to prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. if the inductor valley current increases larger than 7.8a, the top power mosfet will be held off and switching cycles will be skipped until the inductor current is reduced. operatio u
ltc3414 8 3414fb the basic ltc3414 application circuit is shown in figure 1. external component selection is determined by the maxi- mum load current and begins with the selection of the operating frequency and inductor value followed by c in and c out . operating frequency selection of the operating frequency is a tradeoff between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the ltc3414 is determined by an external resistor that is connected between pin r t and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capaci- tor within the oscillator and can be calculated by using the following equation: r f k osc = () 308 10 10 11 .? C although frequencies as high as 4mhz are possible, the minimum on-time of the ltc3414 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 110ns; therefore, the minimum duty cycle is equal to 100 ? 110ns ? f(hz). inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in or v out and decreases with higher inductance. = ? ? ? ? ? ? ? ? ? ? ? ? i v f ? l v v l out out in 1C having a lower ripple current reduces the core losses in the inductor, the esr losses in the output capacitors, and the output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: l v fi v v out l max out in max = ? ? ? ? ? ? ? ? ? ? ? ? () () C 1 the inductor value will also have an effect on burst mode operation. the transition to low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to in- crease. inductor core selection once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance re- quires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy mate- rials are small and dont radiate much energy, but gener- ally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price verus size require- ments and any radiated field/emi requirements. new designs for surface mount inductors are available from coiltronics, coilcraft, toko, and sumida. applicatio s i for atio wu uu
ltc3414 9 3414fb c in and c out selection the input capacitance, c in , is needed to filter the trapezoi- dal wave current at the source of the top mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current should be used. the maximum rms current is given by: ii v v v v rms out max out in in out = () C1 this formula has a maximum at v in = 2v out , where i rms = i out/2 . this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by: ?? + v i esr fc out l out 1 8 ? ? ? ? ? ? the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special poly- mer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capaci- tors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. output voltage programming the output voltage is set by an external resistive divider according to the following equation: vv r r out =+ ? ? ? ? ? ? 08 1 2 1 . the resistive divider allows pin v fb to sense a fraction of the output voltage as shown in figure 2. applicatio s i for atio wu uu 3414 f02 ltc3414 v fb sgnd v out r2 r1 figure 2. setting the output voltage
ltc3414 10 3414fb burst clamp programming if the voltage on the sync/mode pin is less than v in by 1v, burst mode operation is enabled. during burst mode operation, the voltage on the sync/mode pin determines the burst clamp level, which sets the minimum peak inductor current, i burst , for each switching cycle accord- ing to the following equation: i a v vv burst burst = ? ? ? ? ? ? () 69 06 0 383 . . ?. v burst is the voltage on the sync/mode pin. i burst can only be programmed in the range of 0a to 7a. for values of v burst greater than 1v, i burst is set at 7a. for values of v burst less than 0.4v, i burst is set at 0a. as the output load current drops, the peak inductor currents decrease to keep the output voltage in regulation. when the output load current demands a peak inductor current that is less than i burst , the burst clamp will force the peak inductor current to remain equal to i burst regardless of further reductions in the load current. since the average inductor current is greater than the output load current, the voltage on the i th pin will decrease. when the i th voltage drops to 150mv, sleep mode is enabled in which both power mosfets are shut off along with most of the circuitry to minimize power consumption. all circuitry is turned back on and the power mosfets begin switching again when the output voltage drops out of regulation. the value for i burst is determined by the desired amount of output voltage ripple. as the value of i burst increases, the sleep period between pulses and the output voltage ripple in- crease. the burst clamp voltage, v burst , can be set by a resistor divider from the v fb pin to the sgnd pin as shown in figure 1. pulse skipping, which is a compromise between low output voltage ripple and efficiency, can be implemented by connecting pin sync/modeto ground. this sets i burst to 0a. in this condition, the peak inductor current is limited by the minimum on-time of the current comparator. the lowest output voltage ripple is achieved while still operat- ing discontinuously. during very light output loads, pulse skipping allows only a few switching cycles to be skipped while maintaining the output voltage in regulation. frequency synchronization the ltc3414s internal oscillator can be synchronized to an external clock signal. during synchronization, the top mosfet turn-on is locked to the falling edge of the external frequency source. the synchronization frequency range is 300khz to 4mhz. synchronization only occurs if the external frequency is greater than the frequency set by the external resistor. because slope compensation is generated by the oscillators rc circuit, the external frequency should be set 25% higher than the frequency set by the external resistor to ensure that adequate slope compensation is present. soft-start the run/ss pin provides a means to shut down the ltc3414 as well as a timer for soft-start. pulling the run/ss pin below 0.5v places the ltc3414 in a low quiescent current shutdown state (i q < 1 a). the ltc3414 contains an internal soft-start clamp that gradually raises the clamp on i th after the run/ss pin is pulled above 2v. the full current range becomes available on i th after 1024 switching cycles. if a longer soft-start period is desired, the clamp on i th can be set externally with a resistor and capacitor on the run/ss pin as shown in figure 1. the soft-start duration can be calculated by using the following formula: trc v vv seconds ss ss ss in in = ? ? ? ? ? ? ln C. () 18 efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in quiescent current and i 2 r losses. applicatio s i for atio wu uu
ltc3414 11 3414fb the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(qt + qb) where qt and qb are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in ; thus, their effects will be more pro- nounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor r l . in con- tinuous mode the average output current flowing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on) top)(dc) + (r ds(on) bot)(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. thermal considerations in most applications, the ltc3414 does not dissipate much heat due to its high efficiency. however, in applications where the ltc3414 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150 c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3414 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the tempera- ture rise is given by: t r = (p d )( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. for the 20-lead exposed tssop package, the ja is 38 c/w. the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance (r ds(on) ). to maximize the thermal performance of the ltc3414, the exposed pad should be soldered to a ground plane. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load(esr) , where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability prob- lem. the i th pin external components and output capaci- tor shown in figure 1 will provide adequate compensation for most applications. applicatio s i for atio wu uu
ltc3414 12 3414fb design example as a design example, consider using the ltc3414 in an application with the following specifications: v in = 2.7v to 4.2v, v out = 2.5v, i out(max) = 4a, i out(min) = 100ma, f = 1mhz. because efficiency is important at both high and low load current, burst mode operation will be utilized. first, calculate the timing resistor: rkk osc == 308 10 110 10 298 11 6 .? ? C use a standard value of 294k. next, calculate the inductor value for about 40% ripple current at maximum v in : l v mhz a v v h = ? ? ? ? ? ? ? ? ? ? ? ? = 25 116 1 25 42 063 . ()(.) C . . . using a 0.47 h inductor results in a maximum ripple current of: = ? ? ? ? ? ? ? ? ? ? ? ? = i v mhz h v v a l 25 1047 1 25 42 215 . ()(. ) C . . . c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design, a 22 f ceramic capacitor and a 470 f tantalum capacitor will be used. c in should be sized for a maximum current rating of: ia v v v v a rms rms = ? ? ? ? ? ? = () . . . . C. 4 25 42 42 25 1196 decoupling the pv in and sv in pins with two 22 f capaci- tors and a 330 f tantalum capacitor is adequate for most applications. the burst clamp and output voltage can now be pro- grammed by choosing the values of r1, r2, and r3. the voltage on pin mode will be set to 0.49v by the resistor divider consisting of r2 and r3. a burst clamp voltage of 0.49v will set the minimum inductor current, i burst , as follows: iv v a v a burst burst = () ? ? ? ? ? ? = C. . . . 0 383 69 06 123 if we set the sum of r2 and r3 to 200k, then the following equations can be solved: rr k r r v v 2 3 200 1 2 3 08 049 += += . . the two equations shown above result in the following values for r2 and r3: r2 = 78.7k , r3 = 124k. the value of r1 can now be determined by solving the following equation. 1 1 202 7 25 08 1 432 += = r k v v rk . . . a value of 432k will be selected for r1. figure 4 shows the complete schematic for this design example. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3414. check the following in your layout: 1. a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small signal components returning to the sgnd pin at one point which is then connected to the pgnd pin close to the ltc3414. 2. connect the (+) terminal of the input capacitor(s), c in , as close as possible to the pv in pin. this capacitor provides the ac current into the internal power mosfets. 3. keep the switching node, sw, away from all sensitive small signal nodes. 4. flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. you can connect the copper areas to any dc net (pv in , sv in , v out , pgnd, sgnd, or any other dc rail in your system). 5. connect the v fb pin directly to the feedback resistors. the resistor divider must be connected between v out and sgnd. applicatio s i for atio wu uu
ltc3414 13 3414fb 3413 f04 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 c ith 470pf x7r c ss 1000pf x7r r ss 2.2m r osc 294k r ith 20k r pg 100k c1 10pf x7r r3 124k r2 78.7k pgnd rt sync/mode run/ss sgnd nc pv in sw sw pgnd pgnd v fb i th pgood sv in nc pv in sw sw pgnd ltc3414 c out1 ** 470 f c out2 22 f x5r l1* 0.47 h c in1 22 f x5r 2x c in2 *** 330 f r1 432k v out 2.5v 4a v in 2.7v to 5v pgood * ** *** vishay dale ihlp-2525cz-01 sanyo poscap 4tpd470m sanyo poscap 6tpb330m + + figure 4. 2.5v, 4a regulator at 1mhz, burst mode operation applicatio s i for atio wu uu figure 3. ltc3414 layout diagram top bottom
ltc3414 14 3414fb 3413 f06 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 c ith 470pf x7r c ss 1000pf x7r r ss 2.2m r osc 294k r ith 12.1k r pg 100k c c 100pf x7r r2 200k pgnd rt sync/mode run/ss sgnd nc pv in sw sw pgnd pgnd v fb i th pgood sv in nc pv in sw sw pgnd ltc3414 c out ** 100 f 2x l1* 0.47 h c in1 ** 100 f 2x c in2 *** 220 f c1 22pf x7r r1 422k v out 2.5v 4a v in 3.3v pgood * ** *** vishay dale ihlp-2525cz-01 tdk c4532x5roj107m sanyo poscap 4tpb220m 1.25mhz clock + 3.3v, 4a step-down regulator at 1mhz, forced continuous mode 3413 f05 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 c ith 470pf x7r c ss 1000pf x7r r ss 2.2m r osc 294k r ith 12.1k r pg 100k c c 100pf x7r r2 200k pgnd rt sync/mode run/ss sgnd nc pv in sw sw pgnd pgnd v fb i th pgood sv in nc pv in sw sw pgnd ltc3414 c out ** 100 f 2x l1* 0.68 h c in1 22 f x5r 2x c in2 *** 150 f c1 22pf x7r r1 634k v out 3.3v 4a v in 5v pgood * ** *** murata lqh66snr68m03l tdk c4532x5roj107m sanyo poscap 6tpe150m + 2.5v, 4a step-down regulator at 1.25mhz, synchronized to an external clock typical applicatio s u
ltc3414 15 3414fb package descriptio u fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation ca information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe20 (ca) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref recommended solder pad layout 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8910 11 12 14 13 6.40 C 6.60* (.252 C .260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.95 (.195) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
ltc3414 16 3414fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2003 lt 0607 rev b ? printed in usa related parts typical applicatio u 3413 ta01 1 2 3 4 5 20 19 18 17 16 c ith 470pf x7r c ss 1000pf, x7r r ss 2.2m r osc 294k r ith 15k r pg 100k c c 100pf x7r r2 200k pgnd rt sync/mode run/ss sgnd pgnd v fb i th pgood sv in ltc3414 c out1 ** 470 f c out2 22 f x5r l1* 0.44 h c in1 22 f x5r 2x c in2 ** 470 f c1 39pf x7r r1 178k v out 1.5v 4a v in 2.5v pgood * ** pulse p1166.68it sanyo poscap 4tpd470m 6 7 8 9 10 nc pv in sw sw pgnd 15 14 13 12 11 nc pv in sw sw pgnd + + part number description comments lt1616 500ma (i out ), 1.4mhz, high efficiency step-down 90% efficiency, v in : 3.6v to 25v, v out: 1.25v, dc/dc converter i q : 1.9ma, i sd : <1 a, thinsot package lt1676 450ma (i out ), 100khz, high efficiency step-down 90% efficiency, v in : 7.4v to 60v, v out: 1.24v, dc/dc converter i q : 3.2ma, i sd : 2.5 a, s8 package lt1765 25v, 2.75a (i out ), 1.25mhz, high efficiency step-down 90% efficiency, v in : 3v to 25v, v out: 1.2v, dc/dc converter i q : 1ma, i sd : 15 a, s8, tssop16e packages ltc1879 1.20a (i out ), 550khz, synchronous step-down 95% efficiency, v in : 2.7v to 10v, v out: 0.8v, dc/dc converter i q : 15 a, i sd : <1 a, tssop16 package ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous step-down 95% efficiency, v in : 2.75v to 6v, v out: 0.8v, dc/dc converter i q : 20 a, i sd : <1 a, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out: 0.6v, dc/dc converter i q : 20 a, i sd : <1 a, thinsot package ltc3407 dual 600ma (i out ), 1.5mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out: 0.6v, dc/dc converter i q : 40 a, i sd : <1 a, ms package ltc3411 1.25a (i out ), 4mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out: 0.8v, dc/dc converter i q : 60 a, i sd : <1 a, ms package ltc3412 2.5a (i out ), 4mhz, synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out: 0.8v dc/dc converter i q : 60 a, i sd : <1 a, tssop16e package ltc3413 3a (i out sink/source), 2mhz, monolithic synchronous 90% efficiency, v in : 2.25v to 5.5v, v out: v ref /2, regulator for ddr/qdr memory termination i q : 280 a, i sd : <1 a, tssop16e package ltc3430 60v, 2.75a (i out ), 200khz, high efficiency step-down 90% efficiency, v in : 5.5v to 60v, v out: 1.2v, dc/dc converter i q : 2.5ma, i sd : 25 a, tssop16e package ltc3440/ltc3441 600ma/1a (i out ), 2mhz/1mhz, synchronous buck-boost 95% efficiency, v in : 2.5v to 5.5v, v out: 2.5v, dc/dc converter i q : 25 a/50 a, i sd : <1 a, ms package 1.5v, 4a step-down regulator at 1mhz, burst mode

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