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p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller product specification 1999 mar 02 integrated circuits supersedes data of 1999 feb 15
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 2 1999 mar 02 1. features ? 80c51 central processing unit ? 32 k 8 rom respectively feeprom (flash-eeprom), expandable externally to 64 kbytes ? rom/feeprom code protection ? 1024 8 ram, expandable externally to 64 kbytes ? two standard 16-bit timer/counters ? an additional 16-bit timer/counter coupled to four capture registers and three compare registers ? a 10-bit adc with eight multiplexed analog inputs and programmable autoscan ? two 8-bit resolution, pulse width modulation outputs ? five 8-bit i/o ports plus one 8-bit input port shared with analog inputs ? i 2 c-bus serial i/o port with byte oriented master and slave functions ? full-duplex uart compatible with the standard 80c51 ? on-chip watchdog timer ? 15 interrupt sources with 2 priority levels (2 to 6 external sources possible) ? extended temperature range (40 to +85 c ) ? 4.5 to 5.5 v supply voltage range ? frequency range for 80c51-family standard oscillator: 3.5 mhz to 16 mhz ? pll oscillator with 32 khz reference and software-selectable system clock frequency ? seconds timer ? software enable/disable of ale output pulse ? electromagnetic compatibility improvements ? wake-up from power-down by external or seconds interrupt 2. general description the p80c557e4/p83c557e4/p89c557e4 (hereafter generically referred to as p8xc557e4) single-chip 8-bit microcontroller is manufactured in an advanced cmos process and is a derivative of the 80c51 microcontroller family. the p8xc557e4 has the same instruction set as the 80c51. three versions of the derivative exist: ? p83c557e4 e 32 kbytes mask programmable rom ? p80c557e4 e romless version of the p83c557e4 ? p89c557e4 e 32 kbytes feeprom (flash-eeprom) the p8xc557e4 contains a non-volatile 32 kbytes mask programmable rom (p83c557e4) or electrically erasable feeprom respectively (p89c557e4), a volatile 1024 8 read/write data memory, five 8-bit i/o ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80c51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input adc, a dual dac pulse width modulated interface, two serial interfaces (uart and i 2 c-bus), a awatchdogo timer, an on-chip oscillator and timing circuits. for systems that require extra capability the p8xc557e4 can be expanded using standard ttl compatible memories and logic. in addition, the p8xc557e4 has two software selectable modes of power reduction e idle mode and power-down mode. the idle mode freezes the cpu while allowing the ram, timers, serial ports, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. the device also functions as an arithmetic processor having facilities for both binary and bcd arithmetic as well as bit-handling capabilities. the instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three- byte. with a 16 mhz system clock, 58% of the instructions are executed in 0.75 m s and 40% in 1.5 m s. multiply and divide instructions require 3 m s.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 3 3. ordering information extended type package frequency range temperature number name description code (mhz) range ( c) romless p80c557e4ebb qfp80 plastic quad flat pack; 80 leads sot318-1 3.5 to 16 0 to +70 p80c557e4efb qfp80 plastic quad flat pack; 80 leads sot318-1 3.5 to 16 40 to +85 rom coded p83c557e4ebb/yyy 1 qfp80 plastic quad flat pack; 80 leads sot318-1 3.5 to 16 0 to +70 p83c557e4efb/yyy 1 qfp80 plastic quad flat pack; 80 leads sot318-1 3.5 to 16 40 to +85 feeprom p89c557e4ebb qfp80 plastic quad flat pack; 80 leads sot318-1 3.5 to 16 0 to +70 p89c557e4efb qfp80 plastic quad flat pack; 80 leads sot318-1 3.5 to 16 40 to +85 note: 1. yyy denotes the rom code number cpu adc 8-bit internal bus p0 p1 p2 p3 txd rxd p5 p4 ct0i-ct3i t2 rt2 cmsr0-cmsr5 cmt0, cmt1 rstout ew xtal1 xtal2 ea ale psen wr rd t0 t1 int0 int1 v dd v ss pwm0 pwm1 av ss av dd av ref + adexs adc0-7 sda scl 3 3 3 3 3 3 0 2 1 1 1 4 5 0 1 2 alternate function of port0 3 4 5 ad0-7 a8-15 3 3 16 t0, t1 two 16-bit timer/event counters program memory 32 k x 8 rom /feeprom, data memory 256 x 8 ram + 768 x 8 ram dual pwm i 2 c serial i/o 80c51 core excluding rom/ram parallel i/o ports and external bus serial uart port 8-bit ports four 16-bit capture latches t2 16-bit timer/ event count- ers t2 16-bit compara- tors with registers compara- tor output selection t3 watch dog timer alternate function of port1 alternate function of port2 alternate function of port 3 alternate function of port 4 alternate function of port 5 figure 1. block diagram p8xc557e4 1 k x 8 boot rom 6 not present in p80c557e4 7 only present in p89c557e4 6 7 pll oscillator + osecondso timer xtal3 xtal4 selxtal1 rstin 16
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 4 port 5 port 4 adc0-7 cmt0 cmt1 cmsr0-5 rstout ew xtal1 xtal2 ea ale/we psen avref+ avref adexs pwm0 pwm1 port 0 low order address and data bus ad07 port 1 port 2 port 3 ct0i/int2 ct1i/int3 ct2i/int4 ct3i/int5 t2 rt2 rxd/data txd/clock int0 int1 t0 t1 wr rd v ss v dd av ss av dd p8xc557e4 figure 2. functional diagram 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 scl sda *) only p89c557e4 with alternate function we * rstin xtal3 xtal4 selxtal1 high order address bus a815
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 5 4. pinning figure 3. pinning diagram for qfp80 (sot318) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p8xc557e4 av ref av ref+ av ss 1 av dd1 p5.7/adc7 p5.6/adc6 p5.5/adc5 p5.4/adc4 p5.3/adc3 p5.2/adc2 p5.1/adc1 p5.0/adc0 v ss1 v dd1 adexs pwm0 pwm1 ew p4.0/cmsr0 p4.1/cmsr1 p4.2/cmsr2 p4.3/cmsr3 rstout p4.4/csmr4 p4.5/cmsr5 p4.6/cmt0 p4.7/cmt1 dd2 v ss2 v rstin p1.0/ct0i/int2 p1.1/ct1i/int3 p1.2/ct2i/int4 p1.3/ct3i/int5 p1.4/t2 p1.5/rt2 p1.6 p1.7 scl sda p3.0/rxd ale/we * psen p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 v ss3 v dd3 n.c. n.c. p3.6/wr p3.5/t1 p3.4/t0 p3.3/int1 p3.2/int0 p3.1/txd selxtal1 xtal4 xtal3 ss4 v dd4 v p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea p3.7/rd xtal2 xtal1 p2.6/a14 p2.7/a15 * = only p89c557e4 with alternate function we dd2 av ss2 av 28 29 30 31 n.c. = not connected
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 6 4.1 pin description symbol pin description av ref av ref+ 1 2 low end of analog to digital conversion reference resistor high end of analog to digital conversion reference resistor. av ss1 av dd1 3 4 analog ground for adc analog power supply (+5 v) for adc av ss2 av dd2 77 76 analog ground; for pll oscillator analog power supply; (+5 v) for pll oscillator p5.7 p5.0 5 12 port 5 8-bit input port port pin alternative function p5.0p5.7 eight input channels to adc (adc0adc7) v dd1 , v dd2 , v dd3 , v dd4 14, 28, 53, 66 digital power supply: +5 v power supply pins during normal operation and power reduction modes. all pins must be connected. v ss1 , v ss2 v ss3 , v ss4 13, 29, 54, 67 digital ground: circuit ground potential. all pins must be connected. adexs 15 start adc operation: input starting analog to digital conversion triggered by a programmable edge (adc operation can also be started by software). this pin must not float pwm0 16 pulse width modulation output 0 pwm1 17 pulse width modulation output 1 ew 18 enable watchdog timer: enable for t3 watchdog timer and disable power-down mode.this pin must not float. p4.0 p4.7 19 22 24 27 port 4 8-bit quasi-bidirectional i/o port port pin alternative function p4.0 cmsr0 } p4.1 cmsr1 } p4.2 cmsr2 } compare and set/reset p4.3 cmsr3 } outputs on a match with timer t2 p4.4 cmsr4 } p4.5 cmsr5 } p4.6 cmt0 } compare and toggle outputs p4.7 cmt1 } on a match with timer t2 rstin 30 reset: input to reset the p8xc557e4. rstout 23 reset: output of the p8xc557e4 for resetting peripheral devices during initialization and watchdog timer overflow. p1.0 p1.7 31 38 port 1 8-bit quasi-bidirectional i/o port port pin alternative function p1.0 ct0i/int2} p1.1 ct1i/int3} : capture timer inputs for p1.2 ct2i/int4} timer t2 or external interrupt inputs p1.3 ct3i/int5} p1.4 t2 : t2 event input, rising edge triggered p1.5 rt2 : t2 timer reset input, rising edge triggered p1.6 p1.7 scl 39 i 2 c-bus serial clock i/o port sda 40 i 2 c-bus serial data i/o port if scl and sda are not used, they must be connected to v ss .
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 7 pin description (continued) symbol pin description p3.0 p3.7 41 48 8-bit quasi-bidirectional i/o port port pin alternative function p3.0 rxd : serial input port p3.1 txd : serial output port p3.2 int0 : external interrupt p3.3 int1 : external interrupt p3.4 t0 : timer 0 external input p3.5 t1 : timer 1 external input p3.6 wr : external data memory write strobe p3.7 rd : external data memory read strobe n.c. 49 50 not connected pins. xtal2 51 crystal pin 2 : output of the inverting amplifier that forms the oscillator. left open-circuit when an external oscillator clock is used. xtal1 52 crystal pin 1 : input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. receives the external oscillator clock signal when an external oscillator is used. must be connected to logic high if the pll oscillator is selected (selxtal1 = low). p2.0 p2.7 55 62 port2: 8-bit quasi-bidirectional i/o port with internal pull-ups.during access to external memories (ram/rom) that use 16-bit addresses (movx@dptr) port 2 emits the high order address byte. the alternative function of p2.7 for the p89c557e4 is the output enable signal for verify/read modes (active low). port 2 can sink/source one ttl (=4 lsttl) input. it can drive cmos inputs without external pull-ups. psen 63 program store enable output: read strobe to the external program memory via port 0 and 2. is activated twice each machine cycle during fetches from external program memory. when executing out of external program memory two activations of psen are skipped during each access to external data memory. psen is not activated (remains high) during no fetches from external program memory. psen can sink/source 8 lsttl inputs. it can drive cmos inputs without external pull-ups. ale/we 64 address latch enable output : latches the low byte of the address during access of external memory in normal operation. it is activated every six oscillator periods except during an external data memory access. ale/we can sink/-source 8 lsttl inputs. it can drive cmos inputs without an external pull-up. the alternative function for the p89c557e4 is the programming pulse input we . to prohibit the toggling of ale pin (rfi noise reduction) the bit rfi in the pcon register (pcon.5) must be set by software. this bit is cleared on reset and can be set and cleared by software. when set, ale pin will be pulled down internally, switching an external address latch to a quiet state. the movx instruction will still toggle ale if external memory is accessed. ale will retain its normal high value during idle mode and a low value during power-down mode while in the arfio mode. additionally during internal access (ea = 1) ale will toggle normally when the address exceeds the internal program memory size. during external access (ea = 0) ale will always toggle normally, whether the flag arfio is set or not. ea 65 external access input: if, during reset, ea is held at a ttl level high the cpu executes out of the internal program memory, provided the program counter is less than 32768. if, during reset, ea is held at a ttl level low the cpu executes out of external program memory via port 0 and port 2. ea is not allowed to float. ea is latched during reset and don't care after reset. p0.7p0.0 68 75 port 0: 8-bit open drain bidirectional i/o port. it is also the multiplexed low-order address and data bus during accesses to external memory (during theses accesses internal pull-ups are activated). port 0 can sink/source 8 lsttl inputs. xtal3 78 crystal pin , output of the inverting amplifier that forms the 32 khz oscillator xtal4 79 crystal pin , input to the inverting amplifier that forms the 32 khz oscillator. xtal3 and xtal4 are pulled low if the pll oscillator is not selected (selxtal1 = high) or if reset is active. selxtal1 80 must be connected to logic high level to select the hf oscillator, using the xtal1/xtal2 crystal. if pulled low the pll is selected for clocking of the controller, using the xtal3/ xtal4 crystal. note: 1. to avoid a `latch-up' effect at power-on, the voltage at any pin at any time must not be higher or lower than v dd + 0.5 v or v ss 0.5 v respectively.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 8 5. electromagnetic compatibility (emc) improvements primary attention was paid on the reduction of electromagnetic emission of the microcontroller p8xc557e4. the following features effect in reducing the electromagnetic emission and additionally improve the electromagnetic susceptibility: ? four supply voltage pins (v dd ) and four ground pins (v ss ) with pairs of v dd and v ss at two adjacent pins at each side of the package. ? separated v dd pins for the internal logic and the port buffers ? internal decoupling capacitance improves the emc radiation behavior and the emc immunity ? external capacitors are to be located as close as possible between pins v dd1 and v ss1, v dd2 and v ss2, v dd3 and v ss3 as well as v dd4 and v ss4 ; ceramic chip capacitors are recommended (100nf). useful in applications that require no external memory or temporarily no external memory: ? the ale output signal (pulses at a frequency of f clk /6) can be disabled under software control (bit 5 in the sfr pcon: arfio); if disabled, no ale pulse will occur. ale pin will be pulled down internally, switching an external address latch to a quiet state. the movx instruction will still toggle ale (external data memory is accessed). ale will retain its normal high value during idle mode and a low value during power-down mode while in the arfio reduction mode. additionally during internal access (ea = 1) ale will toggle normally when the address exceeds the internal program memory size. during external access (ea = 0) ale will always toggle normally, whether the flag arfio is set or not. 6. functional description 6.1 general the p8xc557e4 is a stand-alone high-performance microcontroller designed for use in real time applications such as instrumentation, industrial control, medium to high-end consumer applications and specific automotive control applications. in addition to the 80c51 standard functions, the device provides a number of dedicated hardware functions for these applications. the p8xc557e4 is a control-oriented cpu with on-chip program and data memory. it can be extended with external program memory up to 64 kbytes. it can also access up to 64 kbytes of external data memory. for systems requiring extra capability, the p8xc557e4 can be expanded using standard memories and peripherals. the p8xc557e4 has two software selectable modes of reduced activity for further power reduction idle and power-down. the idle mode freezes the cpu while allowing the ram, timers, serial ports and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator causing all other chip functions to be inoperative. the power-down mode can be terminated by an external reset, by the seconds interrupt and by any one of the two external interrupts. (see description wake-up from power-down mode.) 6.2 memory organization the central processing unit (cpu) manipulates operands in three memory spaces; these are the 64 kbytes external data memory, 1024 bytes internal data memory (consisting of 256 bytes standard ram and 768 bytes aux-ram) and the 32 kbytes internal and/or 64 kbytes external program memory (see figure 4). program memory 64 k direct and indirect internal data memory external 64 k internal (ea = 1) external (ea = 0) 255 127 0 special function registers overlapped space 0 external data memory 32768 32767 0 indirect only 0 32767 768 (ard = 1) (ard = 0) auxiliary ram figure 4. memory map & address space
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 9 6.2.1 program memory the program memory of the p8xc557e4 consists of 32 kbytes rom respectively feeprom (oflash memoryo) on-chip, externally expandable up to 64 kbytes. if, during reset, the ea pin was held high, the p8xc557e4 executes out of the internal program memory unless the address exceeds 7fffh. locations 8000h through 0ffffh are then fetched from the external program memory. if the ea pin was held low during reset the p8xc557e4 fetches all instructions from the external program memory. the ea input is latched during reset and is don't care after reset. the internal program memory content is protected, by setting a mask programmable security bit (rom) or by the software programmable security byte (feeprom) respectively, i.e. it cannot be read out at any time by any test mode or by any instruction in the external program memory space. the movc instructions are the only ones which have access to program code in the internal or external program memory. the ea input is latched during reset and is 'don't care' after reset. this implementation prevents from reading internal program code by switching from external program memory to internal program memory during movc instruction or an instruction that handles immediate data. table 1 lists the access to the internal and external program memory with movc instructions when the security feature has been activated. 6.2.2 internal data memory the internal data memory is divided into three physically separated parts: 256 bytes of ram, 768 bytes of aux-ram, and a 128 bytes special function area. these can be addressed each in a different way (see also table 2). ram 0 to 127 can be addressed directly and indirectly as in the 80c51. address pointers are r0 and r1 of the selected registerbank. ram 128 to 255 can only be addressed indirectly. address pointers are r0 and r1 of the selected registerbank. aux-ram 0 to 767 is also indirectly addressable as external data memory locations 0 to 767 via movx-datapointer instruction, unless it is disabled by setting ard = 1. aux-ram 0 to 767 is indirectly addressable via pageregister (xramp) and movx-ri instructions, unless it is disabled by setting ard = 1 (see figure 5). when executing from internal program memory, an access to aux-ram 0 to 767 will not affect the ports p0, p2, p3.6 and p3.7. an access to external data memory locations higher than 767 will be performed with the movx @ dptr instructions in the same way as in the 80c51 structure, so with p0 and p2 as data/address bus and p3.6 and p3.7 as write and read timing signals. note that the external data memory cannot be accessed with r0 and r1 as address pointer if the aux-ram is enabled (ard = 0, default). the special function registers (sfr) can only be addressed directly in the address range from 128 to 255 (see table 5). four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower ram area. only one of these banks may be enabled at a time. the next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations.the stack can be located anywhere in the internal 256 bytes ram.the stack depth is only limited by the available internal ram space of 256 bytes (see figure 7). all registers except the program counter and the four register banks reside in the special function register address space. table 1. memory access by the movc instruction for protected roms movc location access to internal program memory access to external program memory movc in internal program memory yes yes movc in external program memory no yes note: 1. if the security feature has not been activated, there are no restrictions for movc instructions . table 2. internal data memory map location addressed ram 0 to 127 direct and indirect aux-ram 0 to 767 indirect only with movx ram 128 to 255 indirect only sfr 128 to 255 direct only
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 10 movx @dptr,a movx a,@dptr movx a, @ri movx @ri, a 255 255 0 255 0 0 767 (xramp) = 02 h (xramp) = 01 h (xramp) = 00 h 0 figure 5. indirect addressing of aux-ram (768 bytes), ard bit in pcon = 0 512 511 256 255 6.2.2.1 aux-ram page register xramp the aux-ram page register is used to select one of three 256 bytes pages of the internal 768 bytes aux-ram for movx-accesses via r0 or r1. its reset value is (xxxxxx00). 7 6 5 4 3 2 1 0 x x x x x x xramp1 xramp0 xramp (fah) figure 6. aux-ram page register. x: undefined during read, a write operation must write a0o to these locations table 3. description of xramp bits bit symbol function xramp.27 xrampx reserved for future use xramp.1 xramp1 aux-ram page select bit 1 xramp.0 xramp0 aux-ram page select bit 0 table 4. memory locations for all possible movx accesses ard 1 xramp1 xramp0 movx @ri,a and movx a,@ri instructions access: 0 0 0 aux-ram locations 0 .. 255 (reset condition) 0 0 1 aux-ram locations 256 .. 511 0 1 0 aux-ram locations 512 .. 767 0 1 1 no valid memory access; reserved for future use 1 x x external ram locations 0 .. 255 movx @dptr,a and movx a,@dptr instructions access: 0 x x aux-ram locations 0 .. 767 (reset condition) external ram locations 768 .. 65535 1 x x external ram locations 0 .. 65535 note: 1. ard (aux-ram disable) is a bit in the special function register pcon
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 11 table 5. special function register memory map and reset values high nibble of sfr address low 8 9 a b c d e f 0 p0 % 11111111 p1 % 11111111 p2 % 11111111 p3 % 11111111 p4 % 11111111 psw % 00000000 acc % 00000000 b % 00000000 1 sp 00000111 2 dpl 00000000 3 dph 00000000 4 5 6 adrsl0 # xxxxxxxx adrsl1 # xxxxxxxx adrsl2 # xxxxxxxx adrsl3 # xxxxxxxx adrsl4 # xxxxxxxx adrsl5 # xxxxxxxx adrsl6 # xxxxxxxx adrsl7 # xxxxxxxx 7 pcon 00000000 p5 # xxxxxxxx adcon 00000000 adpss 00000000 adrsh # 000000xx 8 tcon % 00000000 s0con % 00000000 ien0 % 00000000 ip0 % x0000000 tm2ir % 00000000 s1con % 00000000 ien1 % 00000000 ip1 % 00000000 9 tmod 00000000 s0buf xxxxxxxx cml0 00000000 cmh0 00000000 s1sta # 1111 1000 pllcon 00001101 a tl0 00000000 cml1 00000000 cmh1 00000000 s1dat 00000000 tm2con 00000000 xramp xxxxxx00 b tl1 00000000 cml2 00000000 cmh2 00000000 s1adr 00000000 ctcon 00000000 fmcon * 000x0000 c th0 00000000 ctl0 # xxxxxxxx cth0 # xxxxxxxx tml2 # 00000000 pwm0 00000000 d th1 00000000 ctl1 # xxxxxxxx cth1 # xxxxxxxx tmh2 # 00000000 pwm1 00000000 e ctl2 # xxxxxxxx cth2 # xxxxxxxx ste 11000000 pwmp 00000000 f ctl3 # xxxxxxxx cth3 # xxxxxxxx rte 00000000 t3 00000000 notes: % = bit addressable register # = read only register x = undefined * = fmcon only in p89c557e4 6.3 addressing the p8xc557e4 has five methods for addressing: ? register ? direct ? register-indirect ? immediate ? base-register plus index-register-indirect the first three methods can be used for addressing destination operands. most instructions have a adestination/sourceo field that specifies the data type, addressing methods and operands involved. for operations other than movs, the destination operand is also a source operand. access to memory addresses is as follows: ? register in one of the four register banks through register, direct or register-indirect addressing ? 1024 bytes of internal ram through direct or register-indirect addressing. bytes 0127 of internal ram may be addressed directly/indirectly. bytes 128255 of internal ram share their address location with the sfrs and so may only be addressed indirectly as data ram. bytes 0767 of aux-ram can only be addressed indirectly via movx. ? special function register through direct addressing at address locations 128255 (see figure 8). ? external data memory through register-indirect addressing ? program memory look-up tables through base-register plus index-register-indirect addressing
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 12 ffh 68 69 6b 6a 6c 6d 6f 6e 78 79 7b 7a 7c 7d 7f 7e 2fh 2dh 2ch 2bh 2ah 29h 28h 27h 26h 23h 21h 20h 1fh 18h 17h 0fh 10h 08h 25h 07h 22h 24h 255 47 45 44 43 42 41 40 39 37 35 33 32 31 24 23 36 15 16 8 7 38 0 70 71 73 72 74 75 77 76 2eh 46 50 51 53 52 54 55 57 56 60 61 63 62 64 65 67 66 58 59 5b 5a 5c 5d 5f 5e 40 41 43 42 44 45 47 46 48 49 4b 4a 4c 4d 4f 4e 28 29 2b 2a 2c 2d 2f 2e 38 39 3b 3a 3c 3d 3f 3e 30 31 33 32 34 35 37 36 18 19 1b 1a 1c 1d 1f 1e 20 21 23 22 24 25 27 26 00 01 03 02 04 05 07 06 10 11 13 12 14 15 17 16 08 09 0b 0a 0c 0d 0f 0e 00h 34 bank 3 bank 2 bank 1 bank 0 (msb) (lsb) figure 7. ram bit addresses bit address (hex) byte address (hex) byte address (decimal)
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 13 f8h f0h e8h e0h d8h d0h b8h c0h a8h b0h a0h 98h 90h 80h ip1 b ien1 acc psw p4 ip0 p3 ien0 p2 s0con p0 p1 tcon tm2ir register mnemonic bit address (hex) direct byte address (hex) c8h 88h s1con f8 f9 fb fa fc fd ff fe f0 f1 f3 f2 f4 f5 f7 f6 ect0 ect1 ect3 ect2 ecm0 ecm1 et2 ecm2 e8 e9 eb ea ec ed ef ee e0 e1 e3 e2 e4 e5 e7 e6 cr0 cr1 si aa sto sta cr2 ens1 d8 d9 db da dc dd df de p f1 rs0 ov rs1 f0 cy ac d0 d1 d3 d2 d4 d5 d7 d6 cti0 cti1 cti3 cti2 cmi0 cmi1 t2ov cmi2 c8 c9 cb ca cc cd cf ce c0 c1 c3 c2 c4 c5 c7 c6 px0 pt0 pt1 px1 ps0 ps1 pad b8 b9 bb ba bc bd bf be b0 b1 b3 b2 b4 b5 b7 b6 ex0 et0 et1 ex1 es0 es1 ea ead a8 a9 ab aa ac ad af ae a0 a1 a3 a2 a4 a5 a7 a6 ri ti tb8 rb8 ren sm2 sm0 sm1 98 99 9b 9a 9c 9d 9f 9e 90 91 93 92 94 95 97 96 it0 ie0 ie1 it1 tr0 tf0 tf1 tr1 88 89 8b 8a 8c 8d 8f 8e 80 81 83 82 84 85 87 86 figure 8. special function register bit addresses (msb) (lsb) ffh pt2 pcm2 pcm1 pcm0 pct3 pct2 pct1 pct0
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 14 6.4 i/o facilities the p8xc557e4 has six 8-bit ports. ports 0 to 3 are the same as in the 80c51, with the exception of the additional functions of port 1. the parallel i/o function of port 4 is equal to that of ports 1, 2 and 3. port 5 has a parallel input port function, but has no function as an output port. the sda and scl lines serve the serial port sio1 (i 2 c). because the i 2 c-bus may be active while the device is disconnected from v dd, these pins, are provided with open drain drivers. ports 0, 1, 2, 3, 4 and 5 perform the following alternative functions: port 0 : provides the multiplexed low-order address and data bus used for expanding the p8xc557e4 with standard memories and peripherals. port 1 : port 1 is used for a number of special functions: 4 capture inputs (or external interrupt request inputs if capture information is not utilized) external counter input external counter reset input port 2 : provides the high-order address bus when the p8xc557e4 is expanded with external program memory and/or external data memory. port 3 : pins can be configured individually to provide: external interrupt request inputs counter inputs receiver input and transmitter output of seri port sio 0 (uart) control signals to read and write external data memory port 4 : can be configured to provide signals indicating a match between timer counter t2 and its compare registers. port 5 : may be used in conjunction with the adc interface. unused analog inputs can be used as digital inputs. as port 5 lines may be used as inputs to the adc, these digital inputs have an inherent hysteresis to prevent the input logic from drawing too much current from the power lines when driven by analog signals. channel to channel crosstalk should be taken into consideration when both digital and analog signals are simultaneously input to port 5 (see dc characteristics). all ports are bidirectional with the exception of port 5 which is an input port. pins of which the alternative function is not used may be used as normal bidirectional i/os. the generation or use of a port 1, port 3 or port 4 pin as an alternative function is carried out automatically by the p8xc557e4 provided the associated special function register bit is set high. the pull-up arrangements of ports 1 4 are shown in figure 9. figure 9. i/o buffers in the p8xc557e4 (ports 1, 2, 3 and 4) v dd qn 2 system clock periods port pin n from port latch v dd v dd p1 p2 p3 input data read port pin p1 is turned on for 2 system clock periods after qn makes a 1-to-0 transition. during this time, p1 also turns on p3 through the inverter to form an additional pull up.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 15 6.5 pulse width modulated outputs the p8xc557e4 contains two pulse width modulated output channels (see figure 13). these channels generate pulses of programmable length and interval. the repetition frequency is defined by an 8-bit prescaler pwmp, which supplies the clock for the counter. the prescaler and counter are common to both pwm channels. the 8-bit counter counts module 255, i.e., from 0 to 254 inclusive. the value of the 8-bit counter is compared to the contents of two registers: pwm0 and pwm1. provided the contents of either of these registers is greater than the counter value, the corresponding pwm0 or pwm1 output is set low. if the contents of these registers are equal to, or less than the counter value, the output will be high. the pulse-width-ratio is therefore defined by the contents of the registers pwm0 and pwm1. the pulse-width-ratio is in the range of 0/255 to 255/255 and may be programmed in increments of 1/255. buffered pwm outputs may be used to drive dc motors. the rotation speed of the motor would be proportional to the contents of pwmn. the pwm outputs may also be configured as a dual dac. in this application, the pwm outputs must be integrated using conventional operational amplifier circuitry. if the resulting output voltages have to be accurate, external buffers with their own analog supply should be used to buffer the pwm outputs before they are integrated. the repetition frequency fpwm, at the pwmn outputs is give by: fpwm f clk 2 (1 pwmp) 255 this gives a repetition frequency range of 123 hz to 31.4 khz (f clk = 16 mhz). by loading the pwm registers with either 00h or ffh, the pwm channels will output a constant high or low level, respectively. since the 8-bit counter counts modulo 255, it can never actually reach the value of the pwm registers when they are loaded with ffh. when a compare register (pwm0 or pwm1) is loaded with a new value, the associated output is updated immediately. it does not have to wait until the end of the current counter period. both pwmn output pins are driven by push-pull drivers. these pins are not used for any other purpose. pwmp (feh) pwmp.7 pwmp.6 pwmp.5 pwmp.4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 figure 10. prescaler frequency control register pwmp. 76543210 table 6. description of pwmp bits bit function pwmp.0 to 7 prescaler division factor = (pwmp) + 1 note: 1. reading pwmp gives the current reload value. the actual count of the prescaler cannot be read. pwm0 (fch) pwm0.7 pwm0.6 pwm0.5 pwm0.4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 figure 11. pulse width register pwm0. 76543210 table 7. description of pwm0 bits bit function pwm0.0 to 7 low/high ration of pwm0 signal = (pwm0) 255 (pwm0)
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 16 pwm1 (fdh) pwm1.7 pwm1.6 pwm1.5 pwm1.4 pwm1.3 pwm1.2 pwm1.1 pwm1.0 figure 12. pulse width register pwm1. 76543210 table 8. description of pwm1 bits bit function pwm1.0 to 7 low/high ration of pwm1 signal = (pwm1) 255 (pwm1) figure 13. functional diagram of pulse width modulated outputs. internal bus pwm0 f clk 8-bit comparator 8-bit counter 8-bit comparator pwm1 prescaler 1/2 output buffer pwmp output buffer pwm0 pwm1
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 17 6.6 analog/digital converter (adc) the p8xc557e4 a/d converter is a 10-bit, successive approximation adc with 8 multiplexed analog input channels. it additionally contains a high input impedance comparator, a dac built with 1024 series resistors and analog switches, registers and control logic. input voltage range is from av ref (typical 0v) to av ref+ (typical +5v). a set of 8 buffer registers (10-bit) store the conversion results of the proper analog input channel each. 11 special function registers (sfr) perform the user software interface to the adc: a control sfr (adcon), an analog port scan-select sfr (adpss), 8 input channel related conversion result sfr with the 8 lower result bits (adrsl0...adrsl7), one common result sfr for the upper 2 result bits (adrsh). an extra sfr (p5) allows for reading digital input port data as an alternative function of the 8 analog input pins. in order to have a minimum of adc service overhead in the microcontroller program, the adc is able to operate autonomously within its user configurable autoscan function. the functional diagram of the adc is shown in figure 15. feature overview: ? 10-bit resolution. ? 8 multiplexed analog inputs. ? programmable autoscan of the analog inputs. ? bit oriented 8-bit scan-select register to select analog inputs. ? continuous scan or one time scan configurable from 1 to 8 analog inputs. ? start of a conversion by software or with an external signal. ? eight 10-bit buffer registers, one register for each analog input channel. ? interrupt request after one channel scan loop. ? programmable prescaler (dividing by 2, 4, 6, 8) to adapt to different system clock frequencies. ? conversion time for one a/d conversion: 15 m s ... 50 m s ? differential non-linearity : dle 1 lsb. ? integral non-linearity : ile 2 lsb. ? offset error : ose 2lsb. ? gain error : ge 0.4 %. ? absolute voltage error : ae 3 lsb. ? channel to channel matching : mctc 1lsb. ? crosstalk between analog inputs : ct < 60db. @100 khz. ? monotonic and no missing codes. ? separated analog (av dd , av ss ) and digital (v dd , v ss ) supply voltages. ? reference voltage at two special pins : av ref and av ref+ . for further information on the adc characteristics, refer to the adc characteristicso section. 6.1.1 functional description: table 9. a/d special function registers symbol name access adcon a/d control register read/write adpss analog port scan-select register read/write adrsln 8 a/d result registers, the 8 lower bits (n: 0...7) read only adrsh a/d result register, the 2 higher bits read only p5 digital input port (shared with analog inputs) read only a/d control register adcon the special function register adcon contains control and status bits for the a/d converter peripheral block. the reset value of adcon is (00000000). its hardware address is d7h. adcon is not bit addressable. 76543210 adcon (d7h) adpr1 adpr0 adpos adint adsst adcsa adsre adsfe figure 14. adc control register.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 18 figure 15. functional diagram of ad converter. + 88 8 8 2 2 10 10 10 comparator sar dac 8x 10bit result registers scan logic adpss adcon 2 latches read adrsh read adrsl n analog mux. adc0 adc7 av ref+ av ref av dd1 av ss1 adexs internal bus table 10. description of adcon bits symbol bit function adcon.7 adpr1 control bit for the prescaler. adcon.6 adpr0 control bit for the prescaler. adpr1=0 adpr0=0 prescaler divides by 2 (default by reset) adpr1=0 adpr0=1 prescaler divides by 4 adpr1=1 adpr0=0 prescaler divides by 6 adpr1=1 adpr0=1 prescaler divides by 8 adcon.5 adpos adpos is reserved for future use. must be '0' if adcon is written. adcon.4 adint adc interrupt flag. this flag is set when all selected analog inputs are converted, as well in continuous scan as in one-time scan mode. an interrupt is invoked if this interrupt is enabled. adint must be cleared by software. it cannot be set by software. adcon.3 adsst adc start and status. setting this bit by software or by hardware (via adexs input) starts the a/d conversion of the selected analog inputs. adsst stays a `one' in continuous scan mode. in one-time scan mode, adsst is cleared by hardware when the last selected analog input channel has been converted. as long as adsst is '1', new start commands to the adc-block are ignored. an a/d conversion in progress is aborted if adsst is cleared by software. adcon.2 adcsa 1 = continuous scan of the selected analog inputs after a start of an a/d conversion. 0 = one-time scan of the selected analog inputs after a start of an a/d conversion. adcon.1 adsre 1 = a rising edge at input adexs will start the a/d conversion and generate a capture signal. 0 = a rising edge at input adexs has no effect. adcon.0 adsfe 1 = a falling edge at input adexs will start the a/d conversion and generate a capture signal. 0 = a falling edge at input adexs has no effect.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 19 a/d input port scan-select register adpss the special function register adpss contains control bits to select the analog input channel(s) to be scanned for a/d conversion. the reset value of adpss is (00000000). its hardware address is e7h. adpss is not bit addressable. if all bits are `0' then no a/d conversion can be started. if adpss is written while an a/d conversion is in progress (adsst in the adcon register is `1') then the autoscan loop with the previous selected analog inputs is completed first. the next autoscan loop is performed with the new selected analog inputs. 76543210 adpss (e7h) adpss7 adpss6 adpss5 adpss4 adpss3 adpss2 adpss1 adpss0 figure 16. a/d input port scan-select register. adpss70 for each individual bit position: 0 = the corresponding analog input is skipped in the auto-scan loop. 1 = the corresponding analog input is included in the auto-scan loop. a/d result registers adrsln and adrsh: the binary result code of a/d conversions is accessed by these special function registers. the result sfr are read only registers. the read value after reset is indeterminate. their data are not affected by chip reset. they are not bit addressable. there are 8 special function registers adrsln (adrsl0...adrsl7) a/d result low byte and one general sfr adrsh a/d result high byte . each of adrsln is associated with the coincidently indexed analog input channel adcn (adc0/p5.0...adc7/p5.7). reading an adrsln register by software copies at the same time the two highest bits of the 10-bit conversion result into two latches, thus preserving them until the next read of any adrsln register. these two latches form bit positions 0 and 1 of sfr adrsh, the upper 6 bits of adrsh are always read as '0'. thus it is ensured to get the 10-bit result of the same single a/d conversion by reading any register adrsln first and after it the register adrsh. 76543210 adrsh 0 0 0 0 0 0 adrsn.9 adrsn.8 figure 17. a/d result registers. 76543210 adrsln adrsn.7 adrsn.6 adrsn.5 adrsn.4 adrsn.3 adrsn.2 adrsn.1 adrsn.0 (n: 0...7)
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 20 digital input port register p5 port 5 special function register p5 always represents the binary value of the logic level at input pins p5.0/adc0...p5.7/adc7. p5 is not affected by chip reset. p5 is a read only register. its hardware address is c7h. p5 is not bit addressable. reading special function register p5 does not affect a/d conversions. but it is recommended to use the digital input port function of the hardware port 5 only as an alternative to analog input voltage conversions. simultaneous mixed operation is discouraged for the sake of a/d conversion result reliability and accuracy. for further information on port 5, refer to the ai/o facilitieso section. for further information on a/d special function registers, refer to the ainternal data memoryo section. 76543210 p5 (c7h) p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 figure 18. digital input port register p5. reset after a reset of the microcontroller the adcon and adpss register bits are initialized to zero. registers adrsln and adrsh are not initialized by a reset. idle and power-down mode the a/d converter is active only when the microcontroller is in normal operating mode. if the idle or power-down mode is activated, then the adc is switched off and put into a power saving idle state a conversion in progress is aborted, a previously set adsst flag is cleared and the internal clock is halted. the conversion result registers are not affected. the interrupt flag adint will not be set by activation of idle or power-down mode. a previously set flag adint will not be cleared by the hardware. (note: adint cannot be cleared by hardware at all, except for a reset it must be cleared by the user software.) after a wakeup from idle or power-down mode a set flag adint indicates that at least one autoscan loop was finished completely before the microcontroller was put into the respective power reduction mode and it indicates that the stored result data may be fetched now if desired. for further information on idle and power-down mode, refer to the apower reduction modeso section. timing a programmable prescaler is controlled by the bits adpr1 and adpr0 in register adcon to adapt the conversion time for different microcontroller clock frequencies. table 11 shows conversion times (tconv) for one a/d conversion at some convenient system clock frequencies (fclk) and adc prescaler divisors (m), which are user selectable by the bits adcon.7/adpr1 and adcon.6/adpr0. for conversion times outside the limits for tconv the specified adc characteristics are not guaranteed; (prohibited conversion times are put in brackets): table 11. conversion time configuration examples (tconv/ m s) f clk m 6 mhz 8 mhz 12 mhz 16 mhz 2 4 6 8 26 50 [74] [98] 19.5 37.5 [55.5] [73.5] [13] 25 37 49 [9.75] 18.75 27.75 36.75 conversion time tconv = (6 m + 1) machine cycles a conversion time tconv consists of one sample time period (which equals two bit conversion times), 10 bit conversion time periods and one machine cycle to store the result. after result storage an extra initializing time period follows to select the next analog input channel (according to the contents of sfr adpss), before the input signal is sampled. thus the time period between two adjacent conversions within an autoscan loop is larger than the pure time tconv. this autoscan cycle time is ( 7 m ) machine cycles. at the start of an autoscan conversion the time between writing to sfr adcon and the first analog input signal sampling depends on the current prescaler value (m) and the relative time offset between this write operation and the internal (divided) adc clock. this gives a variation range for the a/d conversion start time of ( m / 2 ) machine cycles.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 21 6.6.2 configuration and operation every a/d conversion is an autoscan conversion. the two user selectable general operation modes are continuous scan and one-time scan mode. the desired analog input port channel/s for conversion is/are selected by programming a/d input port scan-select bits in sfr adpss. an analog input channel is included in the autoscan loop if the corresponding bit in adpss is 1, a channel is skipped if the corresponding bit in adpss is 0. an autoscan is always started according to the lowest bit position of adpss that contains a 1. an autoscan conversion is started by setting the flag adsst in register adcon either by software or by an external start signal at input pin adexs, if enabled. either no edge (external start totally disabled), a rising edge or/and a falling edge of adexs is selectable for external conversion start by the bits adsre and adsfe in register adcon. after completion of an a/d conversion the 10-bit result is stored in the corresponding 10-bit buffer register. then the next analog input is selected according to the next higher set bit position in adpss, converted and stored, and so on. when the result of the last conversion of this autoscan loop is stored, flag adcon.4/adint, the adc interrupt flag, is set. it is not cleared by interrupt hardware it must be cleared by software. in continuous scan mode (adcon.2/adcsa=1) the adc start and status flag adcon.3/adsst retains the set state and the autoscan loop restarts from the beginning. in one-time scan mode (adcsa=0) conversions stop after the last selected analog input was converted, adint is set and adsst is cleared automatically. adsst cannot be set (neither externally nor by software) as long as adint=1, i.e. as long as adint is set, a new conversion start by setting flag adsst is inhibited; actually it is only delayed until adint is cleared. (if a `1' is written to adsst while adint=1, this new value is internally latched and preserved, not setting adsst until adcon.4/adint=0. in this state, a read of sfr adcon will display adcon.3/adsst=0, because always the effective adc status is read.) note that under software control the analog inputs can also be converted in arbitrary order, when one-time scan mode is selected and in sfr adpss only one bit is set at a time. in this case adint is set and adsst is cleared after every conversion. 6.6.3 resolution and characteristics the adc system has its own analog supply pins av dd and av ss . it is referenced by two special reference voltage input pins sourcing the resistance ladder of the dac: av ref+ and av ref . the voltage between av ref+ and av ref defines the full-scale range. due to the 10-bit resolution the full scale range is divided into 1024 unit steps. the unit step voltage is 1 lsb, which is typically 5 mv (av ref+ = 5.12 v, av ref = 0 v = av ss ). the dac's resistance ladder has 1023 equally spaced taps, separated by a unit resistance 'r'. the first tap is located 0.5 x r above av ref , the last tap is located 1.5 x r below av ref+ . this results in a total ladder resistance of 1024 x r. this structure ensures that the dac is monotonic and results in a symmetrical quantization error. for input voltages between av ref and (av ref + 1/2 lsb) the 10-bit conversion result code will be 00 0000 0000 b = 000h = 0d. for input voltages between (av ref+ 3/2 lsb) and av ref+ the 10-bit conversion result code will be 11 1111 1111 b = 3ffh = 1023d. the result code corresponding to an analog input voltage (av in ) can be calculated from the formula: resultcode 1024 av in av ref av ref av ref the analog input voltage should be stable when it is sampled for conversion. at any times the input voltage slew rate must be less than 10 v/ms (5 v conversion range) in order to prevent an undefined result. this maximum input voltage slew rate can be ensured by an rc low pass filter with r = 2k2 and c = 100 nf. the capacitor between analog input pin and analog ground pin shall be placed close to the pins in order to have maximum effect in minimizing input noise coupling. 6.7 timer/counters the p8xc557e4 contains three 16-bit timer/event counters: timer 0, timer 1 and timer t2 and one 8-bit timer, t3. timer 0 and timer 1 may be programmed to carry out the following functions: ? measure time intervals and pulse durations ? count events ? generate interrupt requests 6.7.1 timer 0 and timer 1 timers 0 and 1 each have a control bit in sfr tmod that selects the timer or counter function of the corresponding timer. in the timer function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. in the counter function, the register is incremented in response to a 1-to-0 transition at the corresponding external input pin, t0 or t1. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the counter is incremented. thus, it takes two machine cycles (24 oscillator periods) to recognize a 1-to-0 transition. there are no restrictions on the duty cycle of the external input signal, but to insure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. timer 0 and timer 1 can be programmed independently to operate in one of four modes: ? mode 0: 8-bit timer or 8-bit counter each with divide-by-32 prescaler ? mode 1: 16-bit time-interval or event counter ? mode 2: 8-bit time-interval or event counter with automatic reload upon overflow ? mode 3: timer 0: one 8-bit time-interval or event counter and one 8-bit time-interval counter timer 1: stopped
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 22 when timer 0 is in mode 3, timer 1 can be programmed to operate in modes 0, 1 or 2 but cannot set an interrupt request flag or generate an interrupt. however the overflow from timer 1 can be used to pulse the serial port baud-rate generator. with a 16 mhz crystal, the counting frequency of these timer/counters is as follows: ? in the timer function, the timer is incremented at a frequency of 1.33 mhz a division by 12 of the system clock frequency ? 0 hz to an upper limit of 0.66 mhz (1/24 of the system clock frequency) when programmed for external inputs both internal and external inputs can be gated to the counter by a second external source for directly measuring pulse durations. when configured as a counter, the register is incremented on every falling edge on the corresponding input pin, t0 or t1. the incremented register value can be read earliest during the second machine cycle after that one, during which the incrementing pulse occurred. the counters are started and stopped under software control. each one sets its interrupt request flag when it overflows from all highs to all lows (or automatic reload value), with the exception of mode 3 as previously described. figure 19. timer/counter mode control (tmod) register. 76543210 tmod (89h) gate c/t m1 m0 gate c/t m1 m0 timer 1 timer 0 table 12. description of tmod bits symbol bit function gate tmod.7 tmod.3 gating control when set. timer/counter axo is enabled only while aintx o pin is high and atrxo control pin is set. when cleared timer axo is enabled whenever atrxo control bit is set. c/t tmod.6 tmod.2 timer or counter selector cleared for timer operation (input from internal system clock). set for counter operation (input from atxo input pin). m1 m0 tmod.5 tmod.1 tmod.4 tmod.0 timer 0, timer 1 mode select see table 13. table 13. timer 0 / timer 1 operation select m1 m0 operating 0 0 8048 timer atlxo serves as 5-bit prescaler. 0 1 16-bit timer/counter athxo and atlxo are cascaded; there is no prescaler. 1 0 8-bit auto-reload timer/counter athxo holds a value which is to be reloaded into atlxo each time it overflows. 1 1 (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. 1 1 (timer 1) timer/counter 1 stopped.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 23 figure 20. timer/counter mode control (tcon) register. 76543210 tcon (88h) tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 table 14. description of tcon bits symbol bit function tf1 tcon.7 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. tr1 tcon.6 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. tf0 tcon.5 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. tr0 tcon.4 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. ie1 tcon.3 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. it1 tcon.2 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. ie0 tcon.1 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. it0 tcon.0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 24 6.7.2 timer t2 timer t2 is a 16 bit timer/counter which has capture and compare facilities. the operational diagram is shown in figure 21. the 16 bit timer/counter is clocked via a prescaler with a programmable division factor of 1, 2, 4 or 8. the input of the prescaler is clocked with 1/12 of the clock frequency, or by an external source connected to the t2 input, or it is switched off. the maximum repetition rate of the external clock source is f clk /12, twice that of timer 0 and timer 1. the prescaler is incremented on a rising edge. it is cleared if its division factor or its input source is changed, or if the timer/counter is reset (see also figure 22: tm2con). t2 is readable 'on the fly', without any extra read latches; this means that software precautions have to be taken against misinterpretation at overflow from least to most significant byte while t2 is being read. t2 is not loadable and is reset by the rst signal or at the positive edge of the input signal rt2, if enabled. in the idle or power-down mode the timer/counter and prescaler are reset and halted. t2 is connected to four 16-bit capture registers: ct0, ct1, ct2 and ct3. a rising or falling edge on the inputs ct0i, ct1i, ct2i or ct3i (alternative function of port 1) results in loading the contents of t2 into the respective capture registers and an interrupt request. using the capture register ctcon (see figure 23), these inputs may invoke capture and interrupt request on a positive, a negative edge or on both edges. if neither a positive nor a negative edge is selected for capture input, no capture or interrupt request can be generated by this input. int int figure 21. block diagram of timer 2. ct0 ct1 ct2 ct3 cti0 int ct0i cti1 ct1i cti2 ct2i cti3 ct3i 1/12 prescaler t2 counter 8-bit overflow interrupt 16-bit overflow interrupt external reset enable off f clk t2 rt2 t2er comp cmo (s) int comp cm1 (r) int comp cm2 (t) int p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 r r r r r r t t s s s s s s tg tg ste rte i/o port 4 s = set r = reset t = toggle tg = toggle status t2 sfr address: tml2 = lower 8 bits tmh2 = higher 8 bits int
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 25 figure 22. t2 control register (tm2con). 76543210 tm2con (eah) t2is1 t2is0 t2er t2bo t2p1 t2p0 t2ms1 t2ms0 table 15. description of tm2con bits symbol bit function t2is1 tm2con.7 timer t2 16-bit overflow interrupt select t2is0 tm2con.6 timer t2 byte overflow interrupt select t2er tm2con.5 timer t2 external reset enable. when this bit is set, timer t2 may be reset by a rising edge on rt2 (p1.5). t2bo tm2con.4 timer t2 byte overflow interrupt flag t2p1 tm2con.3 timer t2 prescaler select t2p0 tm2con.2 t2ms1 tm2con.1 timer t2 mode select t2ms0 tm2con.0 table 16. timer 2 prescaler select t2p1 t2p0 timer t2 clock 0 0 clock source 0 1 clock source/2 1 0 clock source/4 1 1 clock source/8 table 17. timer 2 mode select t2ms1 t2ms0 mode selected 0 0 timer t2 halted (off) 0 1 t2 clock source = f clk /12 1 0 test mode; do not use 1 1 t2 clock source = pin t2
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 26 figure 23. capture control register (ctcon). 76543210 ctcon (ebh) ctn3 ctp3 ctn2 ctp2 ctn1 ctp1 ctn0 ctp0 table 18. description of ctcon bits symbol bit function ctn3 ctcon.7 capture register 3 triggered by a falling edge on ct3i ctp3 ctcon.6 capture register 3 triggered by a rising edge on ct3i ctn2 ctcon.5 capture register 2 triggered by a falling edge on ct2i ctp2 ctcon.4 capture register 2 triggered by a rising edge on ct2i ctn1 ctcon.3 capture register 1 triggered by a falling edge on ct1i ctp1 ctcon.2 capture register 1 triggered by a rising edge on ct1i ctn0 ctcon.1 capture register 0 triggered by a falling edge on ct0i ctp0 ctcon.0 capture register 0 triggered by a rising edge on ct0i the contents of the compare registers cm0, cm1 and cm2 are continuously compared with the counter value of timer t2. when a match occurs, an interrupt may be invoked. a match of cm0 sets the bits 05 of port 4, a cm1 match resets these bits and a cm2 match toggles bits 6 and 7 of port 4, provided these functions are enabled by the ste respectively rte registers. a match of cm0 and cm1 at the same time results in resetting bits 05 of port 4. cm0, cm1 and cm2 are reset by the rstin signal. figure 24. interrupt flag register (tm2ir). 76543210 tm2ir (c8h) t2ov cmi2 cmi1 cmi0 cti3 cti2 cti1 cti0 table 19. description of tm2ir bits symbol bit function t2ov tm2ir.7 timer t2 16-bit overflow interrupt flag cmi2 tm2ir.6 cm2 interrupt flag cmi1 tm2ir.5 cm1 interrupt flag cmi0 tm2ir.4 cm0 interrupt flag cti3 tm2ir.3 ct3 interrupt flag cti2 tm2ir.2 ct2 interrupt flag cti1 tm2ir.1 ct1 interrupt flag cti0 tm2ir.0 ct0 interrupt flag
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 27 figure 25. set enable register (ste). 76543210 ste (eeh) tg47 tg46 sp45 sp44 sp43 sp42 sp41 sp40 table 20. description of ste bits symbol bit function tg47 ste.7 if a1o then p4.7 is reset on the next toggle, if low p4.7 is set on the next toggle tg46 ste.6 if a1o then p4.6 is reset on the next toggle, if low p4.6 is set on the next toggle sp45 ste.5 if a1o then p4.5 is set on a match between cm0 and timer t2 sp44 ste.4 if a1o then p4.4 is set on a match between cm0 and timer t2 sp43 ste.3 if a1o then p4.3 is set on a match between cm0 and timer t2 sp42 ste.2 if a1o then p4.2 is set on a match between cm0 and timer t2 sp41 ste.1 if a1o then p4.1 is set on a match between cm0 and timer t2 sp40 ste.0 if a1o then p4.0 is set on a match between cm0 and timer t2 figure 26. reset/toggle enable register (rte). 76543210 rte (efh) tp47 tp46 rp45 rp44 rp43 rp42 rp41 rp40 table 21. description of rte bits symbol bit function tp47 rte.7 if a1o then p4.7 toggles on a match between cm2 and timer t2 tp46 rte.6 if a1o then p4.6 toggles on a match between cm2 and timer t2 rp45 rte.5 if a1o then p4.5 toggles on a match between cm1 and timer t2 rp44 rte.4 if a1o then p4.4 toggles on a match between cm1 and timer t2 rp43 rte.3 if a1o then p4.3 toggles on a match between cm1 and timer t2 rp42 rte.2 if a1o then p4.2 toggles on a match between cm1 and timer t2 rp41 rte.1 if a1o then p4.1 toggles on a match between cm1 and timer t2 rp40 rte.0 if a1o then p4.0 toggles on a match between cm1 and timer t2 for more information concerning the tm2con, ctcon, tm2ir and the ste/rte registers see ic20 handbook, chapter a80c51 family hardware descriptiono. port 4 can be read and written by software without affecting the toggle, set and reset signals. at a byte overflow of the least significant byte, or at a 16-bit overflow of the timer/counter, an interrupt sharing the same interrupt vector is requested. either one or both of these overflows can be programmed to request an interrupt. all interrupt flags must be reset by software.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 28 6.8 watchdog timer t3 in addition to timer t2 and the standard timers, a watchdog timer (t3) consisting of an 11-bit prescaler and an 8-bit timer is also incorporated (see figure 27). the timer is incremented every 1.5 ms, derived from the system clock frequency of 16 mhz by the following: f timer f clk 12 2048 when a timer overflow occurs, the microcontroller is reset and a reset output pulse is generated at pin rstout. also the pll control register is reset. to prevent a system reset the timer must be reloaded in time by the application software. if the processor suffers a hardware/software malfunction, the software will fail to reload the timer. this failure will produce a reset upon overflow thus preventing the processor running out of control. the watchdog timer can only be reloaded if the condition flag wle = pcon.4 has been previously set by software. at the moment the counter is loaded the condition flag is automatically cleared. the time interval between the timer's reloading and the occurrence of a reset depends on the reloaded value. for example, this may range from 1.5 ms to 0.375 s when using an oscillator frequency of 16 mhz. in the idle state the watchdog timer and reset circuitry remain active. the watchdog timer is controlled by the watchdog enable pin (ew ). a low level enables the watchdog timer and disables the power-down mode. a high level disables the watchdog timer and enables the power-down mode. figure 27. watchdog timer. internal bus timer t3 (8-bit) load loaden prescaler (11-bit) clear f clk /12 ew wle clear pd loaden internal bus write t3 pcon.4 pcon.1 to reset circuitry (see figure 46)
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 29 6.9 serial i/o the p8xc557e4 is equipped with two independent serial ports: sio0 and si01. sio0 is the full duplex uart port, identical to the pcb80c51 serial port. sio1 is an i 2 c-bus serial i/o interface with byte oriented master and slave functions. 6.9.1 sio0 (uart) sio 0 is a full duplex serial i/o port it can transmit and receive simultaneously. this serial port is also receive-buffered. it can commence reception of a second byte before the previously received byte has been read from the receive register. if, however, the first byte has still not been read by the time reception of the second byte is complete, one of the bytes will be lost. the sio0 receive and transmit registers are both accessed via the s0buf special function register. writing to s0buf loads the transmit register, and reading s0buf accesses to a physically separate receive register. sio0 can operate in 4 modes: mode 0: serial data is transmitted and received through rxd. txd outputs the shift clock. 8 data bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 of the oscillator frequency. a write into s0con should be avoided during a transmission to avoid spikes on rxd/txd. mode 1: 10 bits are transmitted via txd or received through rxd: a start bit (0), 8 data bits (lsb first), and a stop bit(1). on receive, the stop bit is put into rb8 (s0con special function register). the baud rate is variable. mode 2: 11 bits are transmitted through txd or received through rxd: a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in s0con) can be assigned the value of 0 or 1. with nominal software, tb8 can be the parity bit (p in psw). during a receive, the 9th data bit is stored in rb8 (s0con), and the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. mode 3: 11 bits are transmitted through txd or received through rxd: a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). mode 3 is the same as mode 2 except the baud rate which is variable in mode 3. in all four modes, transmission is initiated by any instruction that writes to the s0buf function register. reception is initiated in mode 0 when ri = 0 and ren = 1. in the other three modes, reception is initiated by the incoming start bit provided that ren = 1. modes 2 and 3 are provided for multiprocessor communications. in these modes, 9 data bits are received with the 9th bit written to rb8. the 9th bit is followed by the stop bit. the port can be programmed so that with receiving the stop bit, the serial port interrupt will be activated if, and only if rb8 = 1. this feature is enabled by setting bit sm2 in s0con. this feature may be used in multiprocessor systems. for more information about how to use the uart in combination with the registers s0con, pcon, ien0, s0buf and timer register refer to the 80c51 data handbook ic20. figure 28. serial port control (s0con) register. 76543210 s0con (98h) sm0 sm1 sm2 ren tb8 rb8 ti ri table 22. description of s0con bits symbol bit function sm0 s0con.7 this bit is used to select the serial port mode. see table 23. sm1 s0con.6 this bit is used to select the serial port mode. see table 23. sm2 s0con.5 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2 = 1, then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be 0. ren s0con.4 enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 s0con.3 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 s0con.2 in modes 2 and 3, rb8 is the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti s0con.1 the transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. ri s0con.0 the receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 30 table 23. description of s0con bits sm0 sm1 mode description baud rate 0 0 0 shift register f clk /12 0 1 1 8-bit uart variable 1 0 2 9-bit uart f clk /64 or f clk /32 1 1 3 9-bit uart variable 6.9.2 sio1 (i 2 c-bus interface) the sio1 of the p8xc557e4 provides the fast-mode, which allows a fourthfold increase of the bitrate up to 400 khz. nevertheless it is downward compatible, i.e. it can be used in a 0 to 100 kbit/s i 2 c bus system. except from the bit rate selection (see table 25) and the timing of the scl and sda signals (see ac electrical characteristics in section 11) the sio circuit is the same as described in detail in the 80c51 data handbook ic20 for the 8xc552 microcontroller. the i 2 c-bus is a simple bidirectional 2-wire bus for efficient inter-ic data exchange. features of the i 2 c-bus are: ? only two bus lines are required: a serial clock line (scl) and a serial data line (sda) ? each device connected to the bus is software addressable by a unique address ? masters can operate as master-transmitter or as master-receiver ? it's a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer ? serial clock synchronization allows devices with different bit rates to communicate via the same serial bus ? ics can be added to or removed from an i 2 c-bus system without affecting any other circuit on the bus ? fault diagnostics and debugging are simple; malfunctions can be immediately traced for more information on the i 2 c-bus specification (including fast-mode) please refer to the philips publication number 9398 393 40011 and/or the 80c51 data handbook ic20. the on-chip i 2 c logic provides a serial interface that meets the i 2 c-bus specification, supporting all i 2 c-bus modes of operation, they are: ? master transmitter ? master receiver ? slave transmitter ? slave receiver the si01 logic performs a byte oriented data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. via two pins the external i 2 c-bus is interfaced to the sio1 logic: scl serial clock i/o and sda serial data i/o, (see special function register bit s1con.6/ens1 for enabling the sio1 logic). the sio1 logic handles byte transfer autonomously. it keeps track of the serial transfers, and a status register (s1sta) reflects the status of sio1 and the i 2 c-bus. via the following four special function registers the cpu interfaces to the i 2 c logic. s1con control register. bit addressable by the cpu s1sta status register whose contents may be used as a vector to service routines. s1dat data shift register. the data byte is stable as long as s1con.3/si=1. s1adr slave address register. it's lsb enables/ disables general call address recognition.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 31 figure 29. block diagram of i 2 c serial i/o interface. internal bus slave address s1adr shift register s1dat bus clock generator s1con s1sta arbitration + sync logic sda scl 710 7 0 gc 7 0 7 0
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 32 the control register, s1con: the cpu can read from and write to this 8-bit, directly addressable sfr. two bits are affected by the sio1 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c bus. the sto bit is also cleared when ens1 = 0. figure 30. serial control (s1con) register. 76543210 s1con (d8h) cr2 ens1 sta sto si aa cr1 cr0 table 24. description of s1con bits symbol bit function cr2 s1con.7 clock rate bit 2, see table 25. ens1 s1con.6 ens1 = 0: serial i/o disabled and reset. sda and scl outputs are high-z. ens1 = 1: serial i/o enabled. sta s1con.5 start flag. when this bit is set in slave mode, the hardware checks the i 2 c bus and generates a start condition if the bus is free or after the bus becomes free. if the device operates in master mode it will generate a repeated start condition. sto s1con.4 stop flag. if this bit is set in a master mode a stop condition is generated. a stop condition detected on the i 2 c bus clears this bit. this bit may also be set in slave mode in order to recover from an error condition. in this case no stop condition is generated to the i 2 c bus, but the hardware releases the sda and scl lines and switches to the not selected receiver mode. the stop flag is cleared by the hardware. si s1con.3 serial interrupt flag. this flag is set, and an interrupt request is generated, after any of the following events occur: a start condition is generated in master mode. the own slave address has been received during aa = 1. the general call address has been received while s1adr.0 and aa = 1. a data byte has been received or transmitted in master mode (even if arbitration is lost). a data byte has been received or transmitted as selected slave. a stop or start condition is received as selected slave receiver or transmitter. while the si flag is set, scl remains low and the serial transfer is suspended. si must be reset by software. aa s1con.2 assert acknowledge flag. when this bit is set, an acknowledge is returned after any one of the following conditions: own slave address is received. general call address is received (s1adr.0 = 1). a data byte is received, while the device is programmed to be a master receiver. a data byte is received. while the device is a selected slave receiver. when the bit is reset, no acknowledge is returned. consequently, no interrupt is requested when the own address or general call address is received. cr1 cr0 s1con.1 s1con.0 clock rate bits 1 and 0, see table 25.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 33 when sio1 is in a master mode serial clock frequency is determined by the clock rate bits cr2, cr1 and cr0. the various bit rates are shown in table 25. table 25. selection of i 2 c-bus bit rate bit rate (khz) at f clk cr2 cr1 cr0 12mhz 16mhz 1 0 0 50 66.7 1 0 1 3.75 5 1 1 0 75 100 1 1 1 100 0 0 0 200 1 266.7 1 0 0 1 7.5 10 0 1 0 300 1 400 1 0 1 1 400 1 note: 1. these bit rates are for afast-modeo i 2 c bus applications and cannot be used for bit rates up to 100 kbit/sec. the data shown in table 25 do not apply to sio1 in a slave mode. in the slave modes, sio1 will automatically synchronize with any clock frequency up to 400khz. serial status register s1sta s1sta is a read only register. the contents of the status register may be used as a vector to a service routine. this optimizes the response time of the software and consequently that of the i 2 c-bus. figure 31. serial status (s1sta) register. 76543210 s1sta (d9h) sc4 sc3 sc2 sc1 sc0 0 0 0 table 26. description of s1sta bits bit function s1sta.7 to 3 5-bit status code s1sta.2 to 0 these bits are held low (for service routine vector increment 8) the following is a list of the status codes: table 27. mst/trx mode s1sta value description 08h a start condition has been transmitted 10h a repeated start condition has been transmitted 18h sla and w have been transmitted, ack has been received 20h sla and w have been transmitted, ack received 28h data and s1dat has been transmitted, ack received 30h data and s1dat has been transmitted, ack received 38h arbitration lost in sla, r/w or data
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 34 table 28. mst/rec mode s1sta value description 38h arbitration lost while returning ack 40h sla and r have been transmitted, ack received 48h sla and r have been transmitted, ack received 50h data has been received, ack returned 58h data has been received, ack returned table 29. slv/rec mode s1sta value description 60h own sla and w have been received, ack returned 68h arbitration lost in sla, r/w as mst. own sla and w have been received, ack returned 70h general call has been received, ack returned 78h arbitration lost in sla, r/w as mst. general call has been received 80h previously addressed with own sla. data byte received, ack returned 88h previously addressed with own sla. data byte received, ack returned 90h previously addressed with general call. data byte has been received, ack has been returned 98h previously addressed with general call. data byte has been received, ack has been returned a0h a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx table 30. slv/trx mode s1sta value description a8h own sla and r have been received, ack returned b0h arbitration lost in sla, r/w as mst. own sla and r have been received, ack returned b8h data byte has been transmitted, ack returned c0h data byte has been transmitted, ack returned c8h last data byte has been transmitted (aa = logic 0), ack received table 31. miscellaneous s1sta value description 00h bus error during mst mode or selected slv mode, due to an erroneous start or stop condition f8h no relevant information available, si not set abbreviations used: sla : 7-bit slave address r : read bit w : write bit ack : acknowledgement (acknowledge bit = 0) ack : not acknowledgement (acknowledge bit = 1) data : 8-bit data byte to or from i 2 c-bus mst : master slv : slave trx : transmitter rec : receiver
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 35 the data shift register s1dat this register contains the serial data to be transmitted or data which has been received. bit 7 is transmitted or received first; i.e., data is shifted from right to left. figure 32. data shift register. 76543210 s1dat (dah) s1dat.7 s1dat.6 s1dat.5 s1dat.4 s1dat.3 s1dat.2 s1dat.1 s1dat.0 the address register s1adr this 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receiver/transmitter. the lsb (gc) is used to determine whether the general call address is recognized. figure 33. address register. 76543210 s1adr (dbh) sla6 sla5 sla4 sla3 sla2 sla1 sla0 gc table 32. description of s1adr bits symbol bit function sla6 to 0 s1adr.7 to 1 own slave address gc s1adr.0 0 = general call address is not recognized 1 = general call address is recognized
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 36 6.10 interrupt system external events and the real-time-driven on-chip peripherals require service by the cpu asynchronously to the execution of any particular section of code. to tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. interrupt response time in a single-interrupt system is in the range from 2.25 m s to 6.75 m s when using a 16mhz crystal. the latency time depends on the sequence of instructions executed directly after an interrupt request. the p8xc557e4 acknowledges interrupt requests from 15 sources as follows (see figure 34): ? int0 and int1 external interrupts ? timer 0 and timer 1 internal timer/counter interrupts ? timer 2 internal timer/counter byte and/or 16-bit overflow, 3 compare and 4 capture interrupts (or 4 additional external interrupts) 1 ? uart serial i/o port receive/transmit interrupt ? i 2 c-bus interface serial i/o interrupt ? adc autoscan completion interrupt ? `seconds' timer interrupt sec (ored with int1 ). for details about seconds timer interrupts, please refer to chapter 6.13.4. the external interrupts int0 and int1 can each be either level-activated or transition-activated, depending on bits it0 and it1 in register tcon. the flags that actually generate these interrupts are bits ie0 and ie1 in tcon. when an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. if the interrupt was level-activated then the interrupt request flag remains set until the external interrupt pin intx goes high. consequently the external source has to hold the request active until the requested interrupt is actually generated. then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. as these external interrupts are active low a awire-oringo of several interrupt sources to one input pin allows expansion. the timer 0 and timer 1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter register (except for timer 0 in mode 3 of the serial interface). when a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. the eight timer/counter t2 interrupt sources are: 4 capture interrupts (1) , 3 compare interrupts and an overflow interrupt. the appropriate interrupt request flags must be cleared by software. the uart serial port interrupt is generated by the logical or of ri and ti. neither of these flags is cleared by hardware. the service routine will normally have to determine whether it was ri or ti that generated the interrupt, and the bit will have to be cleared by software. the i 2 c interrupt is generated by bit si in register s1con. this flag has to be cleared by software. the adc interrupt is generated by bit adint, which is set when of all selected analog inputs to be scanned, the conversion is finished. adint must be cleared by software. it cannot be set by software. the 'seconds' timer interrupt is generated by bit secint in register pllcon. this flag has to be cleared by software. note that the 'seconds' timer can only be used with the 32 khz pll oscillator. all of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware (except the adc interrupt request flag adint, which cannot be set by software). that is, interrupts can be generated or pending interrupts can be cancelled in software. the interrupts x0, t0, x1, t1, sec, s0 and s1 are capable to terminate the idle mode. interrupt enable registers each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable special function registers ien0 and ien1. all interrupt sources can also be globally disabled by clearing bit ea in ien0. the interrupt enable registers are described in figures 34 and 36. interrupt priority structure each interrupt source can be assigned one of two priority levels. interrupt priority levels are defined by the interrupt priority special function registers ip0 and ip1. ip0 and ip1 are described in figures 37 and 38. interrupt priority levels are as follows: a0oelow priority a1oehigh priority a low priority interrupt may be interrupted by a high priority interrupt. a high priority interrupt cannot be interrupted by any other interrupt source. if two requests of different priority occur simultaneously, the high priority level request is serviced. if requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. thus, within each priority level, there is a second priority structure determined by the polling sequence. this second priority structure is shown in table 37. interrupt handling the interrupt sources are sampled at s5p2 of every machine cycle. the samples are polled during the following machine cycle. if one of the flags was in a set condition at s5p2 of the previous machine cycle, the polling cycle will find it and the interrupt system will generate an lcall to the appropriate service routine, provided this hardware- generated lcall is not blocked by any of the following conditions: 1. an interrupt of higher or equal priority level is already in progress. 2. the current machine cycle is not the final cycle in the execution of the instruction in progress. (no interrupt request will be serviced until the instruction in progress is completed.) 3. the instruction in progress is reti or any access to the interrupt priority or interrupt enable registers. (no interrupt will be serviced after reti or after a read or write to ip0, ip1, ie0, or ie1 until at least one other instruction has been subsequently executed.) note: 1. if a capture register is unused and it's contents is of no interest, then the corresponding input pin ctni/p1.n (n: 0...3) ma y be used as a (configurable) positive and/or negative edge triggered additional external interrupt input (int2, int3, int4, int5).
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 37 the polling cycle is repeated with every machine cycle, and the values polled are the values present at s5p2 of the previous machine cycle. note that if an interrupt flag is active but is not being responded to because of one of the above conditions, and if the flag is inactive when the blocking condition is removed, then the blocked interrupt will not be serviced. thus, the fact that the interrupt flag was once active but not serviced is not remembered. every polling cycle is new. the processor acknowledges an interrupt request by executing a hardware-generated lcall to the appropriate service routine. in some cases it also clears the flag which generated the interrupt, and in others it does not. it clears the timer 0, timer 1, and external interrupt flags. an external interrupt flag (ie0 or ie1) is cleared only if it was transition-activated. all other interrupt flags are not cleared by hardware and must be cleared by the software. the lcall pushes the contents of the program counter on to the stack (but it does not save the psw) and reloads the pc with an address that depends on the source of the interrupt being vectored to as shown in table 38. execution proceeds from the vector address until the reti instruction is encountered. the reti instruction clears the apriority level activeo flip-flop that was set when this interrupt was acknowledged. it then pops the top two bytes from the stack and reloads the program counter. execution of the interrupted program continues from where it was interrupted. figure 34. interrupt enable register (ien0). 76543210 ien0 (a8h) ea ead es1 es0 et1 ex1 et0 ex0 table 33. description of ien0 bits symbol bit function ea ien0.7 global enable/disable control 0 = no interrupt is enabled 1 = any individually enabled interrupt will be accepted ead ien0.6 enable adc interrupt es1 ien0.5 enable sio1 (i 2 c) interrupt es0 ien0.4 enable sio0 (uart) interrupt et1 ien0.3 enable timer 1 interrupt ex1 ien0.2 enable external interrupt 1 / seconds interrupt et0 ien0.1 enable timer 0 interrupt ex0 ien0.0 enable external interrupt 0
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 38 figure 35. the interrupt system. global enable interrupt priority registers polling hardware high priority interrupt request external interrupt request 0 int0 a1 a2 source identification vector a1 b1 source enable interrupt enable registers interrupt sources i 2 c serial port b1 b2 c1 d1 adc c1 c2 e1 f1 timer 0 overflow d1 d2 g1 h1 timer 2 capture 0 e1 e2 i1 j1 timer 2 compare 0 f1 f2 k1 l1 external interrupt request 1 g1 g2 m1 n1 timer 2 capture 1 h1 h2 o1 i1 i2 j1 j2 k1 k2 l1 l2 m1 m2 n1 n2 o1 o2 low priority interrupt request source identification vector a2 b2 c2 d2 e2 f2 g2 h2 i2 j2 k2 l2 m2 n2 o2 timer 2 compare 1 timer 1 overflow timer 2 capture 2 timer 2 compare 2 timer 2 capture 3 timer t2 overflow int1 uart serial port t r ct0i ct1i ct2i ct3i 'seconds' interrupt
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 39 figure 36. interrupt enable register (ien1). 76543210 ien1 (e8h) et2 ecm2 ecm1 ecm0 ect3 ect2 ect1 ect0 table 34. description of ien1 bits symbol bit function et2 ien1.7 enable t2 overflow interrupt(s) ecm2 ien1.6 enable t2 comparator 2 interrupt ecm1 ien1.5 enable t2 comparator 1 interrupt ecm0 ien1.4 enable t2 comparator 0 interrupt ect3 ien1.3 enable t2 capture register 3 interrupt ect2 ien1.2 enable t2 capture register 2 interrupt ect1 ien1.1 enable t2 capture register 1 interrupt ect0 ien1.0 enable t2 capture register 0 interrupt if the enable bit is 0, then the interrupt is disabled, if the enable bit is 1, then the interrupt is enabled. figure 37. interrupt priority register (ip0). 76543210 ip0 (b8h) pad ps1 ps0 pt1 px1 pt0 px0 table 35. description of ip0 bits symbol bit function ip0.7 reserved for future use pad ip0.6 adc interrupt priority level ps1 ip0.5 sio1 (i 2 c) interrupt priority level ps0 ip0.4 sio0 (uart) interrupt priority level pt1 ip0.3 timer 1 interrupt priority level px1 ip0.2 external interrupt 1/seconds interrupt priority level pt0 ip0.1 timer 0 interrupt priority level px0 ip0.0 external interrupt 0 priority level
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 40 figure 38. interrupt priority register (ip1). 76543210 ip1 (f8h) pt2 pcm2 pcm1 pcm0 pct3 pct2 pct1 pct0 table 36. description of ip1 bits symbol bit function pt2 ip1.7 t2 overflow interrupt(s) priority level pcm2 ip1.6 t2 comparator 2 interrupt priority level pcm1 ip1.5 t2 comparator 1 interrupt priority level pcm0 ip1.4 t2 comparator 0 interrupt priority level pct3 ip1.3 t2 capture register 3 interrupt priority level pct2 ip1.2 t2 capture register 2 interrupt priority level pct1 ip1.1 t2 capture register 1 interrupt priority level pct0 ip1.0 t2 capture register 0 interrupt priority level table 37. interrupt priority structure source name priority within level external interrupt 0 x0 (highest) sio1 (i 2 c) s1 adc completion adc timer 0 overflow t0 timer 2 capture 0 ct0 timer 2 compare 0 cm0 external interrupt 1/seconds interrupt x1/sec timer 2 capture 1 ct1 timer 2 compare 1 cm1 timer 1 overflow t1 timer 2 capture 2 ct2 timer 2 compare 2 cm2 sio0 (uart) s0 timer 2 capture 3 ct3 timer 2 overflow t2 (lowest) table 38. interrupt vector addresses source name vector address external interrupt 0 x0 0003h timer 0 overflow t0 000bh external interrupt 1/seconds interrupt x1/sec 0013h timer 1 overflow t1 001bh sio0 (uart) s0 0023h sio1 (i 2 c) s1 002bh timer 2 capture 0 ct0 0033h timer 2 capture 1 ct1 003bh timer 2 capture 2 ct2 0043h timer 2 capture 3 ct3 004bh adc completion adc 0053h timer 2 compare 0 cm0 005bh timer 2 compare 1 cm1 0063h timer 2 compare 2 cm2 006bh timer 2 overflow t2 0073h
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 41 figure 39. power control register (pcon). 76543210 pcon (87h) smod ard rfi wle gf1 gf0 pd idl table 39. description of pcon bits symbol bit function smod pcon.7 double baud rate bit. when set to logic 1 the baud rate is doubled when the serial port sio0 is being used in modes 1, 2, or 3. ard pcon.6 aux-ram disable bit. when set to a 1 the internal 768 bytes aux-ram is disabled, so that all movx-instructions access the external data memory as it is with the standard pcb80c51. rfi pcon.5 reduced radio frequency interference bit. when set to a 1 the toggling of ale pin is prohibited. this bit is cleared on reset (see also sections features (emc) and pinning). wle pcon.4 watchdog load enable. this flag must be set by software prior to loading timer t3 (watchdog timer). it is cleared when timer t3 is loaded. gf1 pcon.3 general-purpose flag bit gf0 pcon.2 general-purpose flag bit pd pcon.1 power-down bit. setting this bit activates the power-down mode. it can only be set if input ew is high. idl pcon.0 idle mode bit. setting this bit activates the idle mode. 6.11 power reduction modes two software-selectable modes of reduced power consumption are implemented. these are the idle mode and the power-down mode. idle mode operation permits the interrupt, serial ports and timer blocks t0, t1 and t3 to function while the cpu is halted. the following functions are switched off when the microcontroller enters the idle mode: ? cpu (halted) ? timer 2 (stopped and reset) ? pwm0, pwm1 (reset, output = high) ? adc (aborted if conversion in progress) the following functions remain active during idle mode. these functions may generate an interrupt or reset and thus terminate the idle mode: ? timer 0, timer 1, timer 3 (watchdog timer) ? uart ? i 2 c ? external interrupt ? seconds timer in power-down mode the system clock is halted. if the pll oscillator is selected (selxtal1 = 0) and the run32 bit is set, the 32 khz oscillator keeps running, otherwise it is stopped. if the hf-oscillator (selxtal1 = 1) is selected, it is stopped after setting the bit pd in the pcon register. table 40. external pin status during idle and power-down modes mode memory ale psen port 0 port 1 port 2 port 3 port 4 scl/sda pwm0 /pwm1 idle internal 1 1 data data data data data operative (1) high idle external 1 1 high-z data address data data operative (1) high power-down internal 0 0 data data data data data high-z high power-down external 0 0 high-z data data data data high-z high note: 1. in idle mode scl and sda can be active as outputs only if sio1 is enabled; if sio1 is disabled (s1con.6/ens1 = 0) these pins are in a high-impedance state.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 42 clock gen. interrupts, serial ports, t0, t1, t3 xtal4 xtal3 figure 40. idle and power down hardware for clock generation xtal1 xtal2 3.5 to 16 mhz osc f clk cpu t2 adc pwm 32 khz pll osc seconds timer pd idl selxtal1 figure 41. wake-up by interrupt int0 int1 set external interrupt latch int0 : 2 cycles int1 : 1 cycle internal timing stopped c1 c1 c1 c2 power-down mode idle mode lcall oscillator stopped oscillator start_up interrupts are polled interrupt routine > 10 ms > 560 ms > 10 ms xtal1,2 32 khz oscillator stopped running 6.11.1 power control register the modes idle and power-down are activated by software via the special function register pcon. its hardware address is 87h. pcon is not bit addressable. the reset value of pcon is (00000000). 6.11.2 idle mode the instruction that sets pcon.0 is the last instruction executed in the normal operating mode before idle mode is activated. once in the idle mode, the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle mode. the status of external pins during idle mode is shown in table 40. there are three ways to terminate the idle mode: activation of any enabled interrupt x0, t0, x1, sec, t1, s0 or s1 will cause pcon.0 to be cleared by hardware terminating idle mode but only, if there is no interrupt in service with the same or higher priority. the interrupt is serviced, and following return from interrupt instruction reti, the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to pcon.0. the flag bits gf0 and gf1 may be used to determine whether the interrupt was received during normal execution or during idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. the second way of terminating the idle mode is with an external hardware reset. since the oscillator is still running, the hardware reset is required to be active for two machine cycles (24 hf oscillator periods) to complete the reset operation if the hf oscillator is selected. when the pll oscillator is selected a hardware reset of > 1 m sec (but no longer than 10 ms) is required and the microcontroller will typically restart within 63 msec after the reset has finished. the third way of terminating the idle mode is by internal watchdog reset. the microcontroller restarts after 3 machine cycles in all cases.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 43 6.11.3 power-down mode the instruction that sets pcon.1 is the last executed prior to going into the power-down mode. once in power-down mode, the hf oscillator is stopped. the 32 khz oscillator may stay running. the content of the on-chip ram and the special function registers are preserved. note that the power-down mode can not be entered when the watchdog has been enabled. the power-down mode can be terminated by an external reset in the same way as in the 80c51 (ram is saved, but sfrs are cleared due to reset) or in addition by any one of the external interrupts (int0 , int1 ) or seconds interrupt. the status of the external pins during power-down mode is shown in table 40. if the power-down mode is activated while in external program memory, the port data that is held in the special function register p2 is restored to port 2. if the data is a logic1, the port pin is held high during the power-down mode by the strong pull-up transistor p1 (see figure 9). the power-down mode should not be entered within an interrupt routine because wake-up with an external or `seconds' interrupt is not possible in that case. 6.11.4 wake-up from power-down mode the power-down mode of the p8xc557e4 can also be terminated by any one of the three enabled interrupts, int0 , int1 or seconds interrupt. if there is an interrupt already in service, which has same or higher priority as the wake-up interrupt, power-down mode will switch over to idle mode and stay there until an interrupt of higher priority terminates idle mode. a termination with these interrupts does not affect the internal data memory and does not affect the special function registers. this gives the possibility to exit power-down without changing the port output levels. to terminate the power-down mode with an external interrupt, int0 or int1 must be switched to be level-sensitive and must be enabled. the external interrupt input signal int0 or int1 must be kept low till the oscillator has restarted and stabilized (see figure 41). a seconds interrupt will terminate the power-down mode if it is enabled and int1 is level sensitive. in order to prevent any interrupt priority problems during wake-up, the priority of the desired wake-up interrupt should be higher than the priorities of all other enabled interrupt sources. the instruction following the one that put the device into the power-down mode will be the first one which will be executed after the interrupt routine has been serviced. 6.12 oscillator circuits the input signal selxtal1 connected to logic a1o selects the xtal1, 2 oscillator (standard 80c51) instead of the xtal3, 4 oscillator, which is halted and xtal3, 4 must not be connected. 6.12.1 xtal1, 2 oscillator circuit (standard 80c51) the oscillator circuit of the p8xc557e4 is a single-stage inverting amplifier in a pierce oscillator configuration. the circuitry between the xtal1 and xtal2 is basically an inverter biased to the transfer point. either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuitry. both are operated in parallel resonance. xtal1 is the high gain amplifier input, and xtal2 is the output (see figure 42). to drive the p8xc557e4 externally, xtal1 is driven from an external source and xtal2 left open-circuit (see figure 43). 6.12.2 xtal3, 4 circuitry please refer to chapter 6.13.1 figure 42. using the on-chip oscillator. quartz crystal or ceramic resonator c1 c2 xtal1 xtal2 v ss c1 = c2 = 20pf external clock signal xtal2 xtal1 v ss figure 43. using an external clock. selxtal1 1 selxtal1 1 (nc)
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 44 6.13 32khz pll oscillator with seconds timer 6.13.1 xtal3,4 oscillator circuitry the input signal selxtal1 connected to logic a0o selects the 32khz oscillator together with the pll instead of the xtal1,2 oscillator, which is halted. xtal2 is floating in that case. the 32khz oscillator consists of an inverter, which forms a pierce oscillator with the on-chip components c1,c2,rf and an external crystal of 32768 hz. during the following situations, the inverter is switched to tristate and xtal3 is pulled to vss : ? during power-down mode, when the pll control register bit run32 (pllcon.7) was set to '0'; ? during reset (rstin = high) ; ? when the xtal1,2 oscillator is selected (selxtal1 = high). 6.13.2 pll cco a current controlled oscillator (cco) generates a clock frequency f cco of approx. 32 , 38 , 44 or 50 mhz , controlled by the pll, with the 32khz oscillator as the reference clock. the system clock frequency f clk can be varied under software control by changing the contents of the pll control register (pllcon): f cco can be changed via the pllcon bits fsel(1:0) (see table 41). the maximum locking time is 10 ms 1 . during the stabilization phase, no time critical routines should be executed. the system clock frequency f clk is derived from f cco under control of the pllcon bits fsel(4:0) (see table 41). if only fsel(4:2) is changed but not fsel(1:0), then it takes about 1us until the new frequency is available. changing the system clock frequency has to be done in two steps. from high to low frequencies: first change (fsel(4:2), then fsel (1:0). from low to high frequencies: first change only fsel (1:0) and after a stabilization phase of 10 ms change fsel (4:2). 6.13.3 pll control register pllcon pllcon is a special function register, which can be read and written by software. it contains the control bits: ? to select one of several system clock frequencies (see table 41); ? the seconds interrupt flag: secint ? to enable the seconds interrupt flag: enseci ? the run32 bit, which defines if during power-down mode the 32khz oscillator is halted or stays running. pllcon is initialized to 0dh upon reset (rstin = `1') or watchdog timer overflow. pllcon = 0dh corresponds to a system clock frequency of 11.01 mhz. figure 44. pll control register (pllcon). 76543210 pllcon (f9h) run32 enseci secint fsel.4 fsel.3 fsel.2 fsel.1 fsel.0 table 41. pllcon symbol bit function run32 pllcon.7 run32 = 0: the 32 khz oscillator halts during power-down. run32 = 1: the 32 khz oscillator stays running during power-down. enseci pllcon.6 enable the seconds interrupt. (enabling int1 is also required) secint pllcon.5 seconds interrupt requested by an overflow of the seconds timer (which occurs every second) or via writing a `1' to this bit. secint can only be cleared by writing a '0' to this bit . fsel.4 pllcon.4 system clock frequency in mhz to fsel.0 to pllcon.0 11 fsel[1:0] 10 01 00 15.73 7.86 9.44 11.01 12.58 3.93 4.72 5.51 6.29 010 011 100 fsel[4:2] other combinations, than mentioned above, are reserved and may not be selected. this allows to generate the standard baudrates 19200, 9600, 4800, 2400 and 1200 baud, when using the uart and timer1. note: 1. this parameter is characterized.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 45 6.13.4 seconds timer this counter provides an overflow signal every second, when the 32khz oscillator is running. the overflow output sets the interrupt flag secint. this interrupt can be disabled/enabled by enseci. if secint is enabled, it is logically ored with int1 (external interrupt 1). seconds interrupt and int1 therefor share the same priority and vector. the software has to check both flags secint (pllcon.5) and ie1 (tcon.3), to distinguish between the two interrupt sources. secint can only be cleared via writing a `0' to this bit . the external interrupts int0 , int1 or the seconds interrupt can wake-up the pll oscillator and the microcontroller as described in chapter awake-up from power-down modeo. for a wake-up via int1 or seconds interrupt, ie1 must be enabled and level-sensitive. a further function of the seconds timer is to control the start-up timing of the microcontroller after reset or after wake-up from power-down. it controls the stretching of the reset pulse to the microcontroller and controls releasing the system clock to the microcontroller. a rstin signal of 1us at minimum will reset the microcontroller. in case of reset or wake-up with halted 32khz oscillator: from rstin falling edge or wake-up interrupt it takes 560ms at maximum for the start-up of the 32khz oscillator itself and the stabilization of the pll's. in case of wake-up with running 32khz oscillator: from wake-up interrupt it takes about 1ms for the stabilization of the pll's. after this start-up time, the microcontroller is supplied with the system clock and in case of a reset the internally stretched reset signal overlaps about 45us, to guarantee a proper initialization of the microcontroller. for further information refer to section 6.11 power reduction modes . xtal3 figure 45. block diagram pll oscil- lator 32.768 khz c 1 32 khz phase comparator loop filter cco pd internal bus seconds timer pllcon rstin programmable divider system clock reset to controller 'seconds' interrupt request pd = power down stretched reset run32 pd r f c 2 xtal4
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 46 6.14 reset circuitry the reset input pin rstin is connected to a schmitt trigger for noise reduction (see figure 46). is the hf-oscillator selected a reset is accomplished by holding the rstin pin high for at least 2 machine cycles (24 system clock periods). is the pll-oscillator selected the rstin-pulse must have a width of 1 m s at least, independent of the 32 khz-oscillator is running or not (see pll description). the cpu responds by executing an internal reset. the rstout pin represents the signal resetting the cpu and can be used to reset peripheral devices. the rstout level also could be high due to a watchdog timer overflow. the length of the output pulse from t3 is 3 machine cycles. a pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible. during reset, ale and psen output a high level. in order to perform a correct reset, this level must not be affected by external elements. a reset leaves the internal registers as shown in table 5. the internal ram is not affected by reset. at power-on, the ram content is indeterminate. 6.15 power-on reset an automatic reset can be obtained by switching on v dd , if the rstin pin is connected to v dd via a capacitor, as shown in figure 47. is the hf oscillator selected the v dd rise time must not exceed 10 ms and the capacitor should be at least 2.2 m f. the decrease of the rstin pin voltage depends on the capacitor and the internal resistor r rst . that voltage must remain above the lower threshold for at minimum the hf-oscillator start-up time plus 2 machine cycles. is the pll-oscillator selected a 0.1 m f capacitor is sufficient to obtain an automatic reset. 8xc557e4 v dd rst r rst hf-osc.: 2.2 m f v dd figure 46. on-chip reset configuration r rst rstin schmitt trigger on-chip resistor overflow timer t3 figure 47. power-on reset mux rstout internal reset selxtal1 pll-osc.: 0.1 m f pll osc capacitor for
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 47 7. instruction set the p8xc557e4 uses the powerful instruction set of the pcb80c51. it consists of 49 single-byte, 45 two-byte and 17 three-byte instructions. using a 16 mhz quartz, 64 of the instructions are executed in 0.75 m s, 45 in 1,5 m s and the multiply, divide instructions in 3 m s. a summary of the instruction set is given in table 43. the p8xc557e4 has additional special function registers to control the on-chip peripherals. 7.1 addressing modes most instructions have a adestination, sourceo field that specifies the data type, addressing modes and operands involved. for all these instructions, except for movs, the destination operand is also the source operand (e.g., add a,r7). there are five kinds of addressing modes: ? register addressing r0 r7 (4 banks) a,b,c (bit), ab (2 bytes), dptr (double byte) ? direct addressing lower 128 bytes of internal main ram (including the 4 r0r7 register banks) special function registers 128 bits in a subset of the internal main ram 128 bits in a subset of the special function registers ? register-indirect addressing internal main ram (@r0, @r1, @sp [push/pop]) internal auxiliary ram (@r0, @r1, @dptr) external data memory (@r0, @r1, @dptr) ? immediate addressing program memory (in-code 8 bit or 16 bit constant) ? base-register-plus index-register-indirect addressing program memory look-up table (@dptr+a, @pc+a) the first three addressing modes are usable for destination operands. 7.1.1 80c51 family instruction set table 42. instruction that affect flag settings 1 instruction flag c ov ac add addc subb mul div da rrc rlc setb c x x x 0 0 x x x 1 x x x x x x x x x clr c cpl c anl c, bit anl c,/bit anl c, bit orl c, bit mov c, bit cjne 0 x x x x x x x notes: 1. note that operations on sfr byte address 208 or bit addresses 209-215 (i.e., the psw or bits in the psw) will also affect flag settings. notes on instruction set and addressing modes: rn register r7-r0 of the currently selected register bank. direct 8-bit internal data location's address. this could be an internal data ram location (0-127) or a sfr [i.e., i/o port, control register, status register, etc. (128-255)]. @ri 8-bit ram location addressed indirectly through register r1 or r0 of the actual register bank. #data 8-bit constant included in the instruction. #data 16 16-bit constant included in the instruction addr 16 16-bit destination address. used by lcall and ljmp. a branch can be anywhere within the 64 kbytes program memory address space. addr 11 11-bit destination address. used by acall and ajmp. the branch will be within the same 2 kbytes page of program memory as the first byte of the following instruction. rel signed (two's complement) 8-bit offset byte. used by sjmp and all conditional jumps. range is 128 to +127 bytes relative to first byte of the following instruction. bit direct addressed bit in internal data ram or special function register. hexadecimal opcode cross-reference to table 43: * : 8, 9, a, b, c, d, e. f. ** : 11, 31, 51, 71, 91, b1, d1, f1. *** : 01, 21, 41, 61, 81, a1, c1, e1.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 48 table 43. 80c51 instruction set summary mnemonic description byte / cycles opcode (hex.) arithmetic operations add a,rn add register to accumulator 1 1 2* add a,direct add direct byte to accumulator 2 1 25 add a,@ri add indirect ram to accumulator 1 1 26, 27 add a,#data add immediate data to accumulator 2 1 24 addc a,rn add register to accumulator with carry 1 1 3* addc a,direct add direct byte to accumulator with carry 2 1 35 addc a,@ri add indirect ram to accumulator with carry 1 1 36, 37 addc a,#data add immediate data to acc with carry 2 1 34 subb a,rn subtract register from acc with borrow 1 1 9* subb a,direct subtract direct byte from acc with borrow 2 1 95 subb a,@ri subtract indirect ram from acc with borrow 1 1 96, 97 subb a,#data subtract immediate data from acc with borrow 2 1 94 inc a increment accumulator 1 1 04 inc rn increment register 1 1 0* inc direct increment direct byte 2 1 05 inc @ri increment indirect ram 1 1 06, 07 dec a decrement accumulator 1 1 14 dec rn decrement register 1 1 1* dec direct decrement direct byte 2 1 15 dec @ri decrement indirect ram 1 1 16, 17 inc dptr increment data pointer 1 2 a3 mul ab multiply a and b 1 4 a4 div ab divide a by b 1 4 84 da a decimal adjust accumulator 1 1 d4 logical operations anl a,rn and register to accumulator 1 1 5* anl a,direct and direct byte to accumulator 2 1 55 anl a,@ri and indirect ram to accumulator 1 1 56, 57 anl a,#data and immediate data to accumulator 2 1 54 anl direct,a and accumulator to direct byte 2 1 52 anl direct,#data and immediate data to direct byte 3 2 53 orl a,rn or register to accumulator 1 1 4* orl a,direct or direct byte to accumulator 2 1 45 orl a,@ri or indirect ram to accumulator 1 1 46, 47 orl a,#data or immediate data to accumulator 2 1 44 orl direct,a or accumulator to direct byte 2 1 42 orl direct,#data or immediate data to direct byte 3 2 43 xrl a,rn exclusive-or register to accumulator 1 1 6* xrl a,direct exclusive-or direct byte to accumulator 2 1 65 xrl a,@ri exclusive-or indirect ram to accumulator 1 1 66, 67
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 49 table 43. 80c51 instruction set summary (continued) mnemonic description byte / cycles opcode (hex.) logical operations (continued) xrl a,#data exclusive-or immediate data to accumulator 2 1 64 xrl direct,a exclusive-or accumulator to direct byte 2 1 62 xrl direct,#data exclusive-or immediate data to direct byte 3 2 63 clr a clear accumulator 1 1 e4 cpl a complement accumulator 1 1 f4 rl a rotate accumulator left 1 1 23 rlc a rotate accumulator left through the carry 1 1 33 rr a rotate accumulator right 1 1 03 rrc a rotate accumulator right through the carry 1 1 13 swap a swap nibbles within the accumulator 1 1 c4 data transfer mov a,rn move register to accumulator 1 1 e* mov a,direct move direct byte to accumulator 2 1 e5 mov a,@ri move indirect ram to accumulator 1 1 e6, e7 mov a,#data move immediate data to accumulator 2 1 74 mov rn,a move accumulator to register 1 1 f* mov rn,direct move direct byte to register 2 2 a* mov rn,#data move immediate data to register 2 1 7* mov direct,a move accumulator to direct byte 2 1 f5 mov direct,rn move register to direct byte 2 2 8* mov direct,direct move direct byte to direct 3 2 85 mov direct,@ri move indirect ram to direct byte 2 2 86, 87 mov direct,#data move immediate data to direct byte 3 2 75 mov @ri,a move accumulator to indirect ram 1 1 f6, f7 mov @ri,direct move direct byte to indirect ram 2 2 a6, a7 mov @ri,#data move immediate data to indirect ram 2 1 76, 77 mov dptr,#data16 load data pointer with a 16-bit constant 3 2 90 movc a,@a+dptr move code byte relative to dptr to acc 1 2 93 movc a,@a+pc move code byte relative to pc to acc 1 2 83 movx a,@ri move aux-ram (8-bit addr) to acc 1 2 e2, e3 movx a,@dptr move aux-ram (16-bit addr) to a cc 1 2 e0 movx @ri,a move acc to aux-ram (8-bit addr) 1 2 f2, f3 movx @dptr,a move acc to aux-ram (16-bit addr) 1 2 f0 push direct push direct byte onto stack 2 2 c0 pop direct pop direct byte from stack 2 2 d0 xch a,rn exchange register with accumulator 1 1 c* xch a,direct exchange direct byte with accumulator 2 1 c5 xch a,@ri exchange indirect ram with accumulator 1 1 c6, c7 xchd a,@ri exchange low-order digit indirect ram with acc 1 1 d6, d7
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 50 table 43. 80c51 instruction set summary (continued) mnemonic description byte / cycles opcode (hex.) boolean variable manipulation clr c clear carry 1 1 c3 clr bit clear direct bit 2 1 c2 setb c set carry 1 1 d3 setb bit set direct bit 2 1 d2 cpl c complement carry 1 1 b3 cpl bit complement direct bit 2 1 b2 anl c,bit and direct bit to carry 2 2 b2 anl c,/bit and complement of direct bit to carry 2 2 b0 orl c,bit or direct bit to carry 2 2 72 orl c,/bit or complement of direct bit to carry 2 2 a0 mov c,bit move direct bit to carry 2 1 a2 mov bit,c move carry to direct bit 2 2 92 jc rel jump if carry is set 2 2 40 jnc rel jump if carry not set 2 2 50 jb rel jump if direct bit is set 2 2 20 jnb rel jump if direct bit is not set 2 2 30 jbc bit,rel jump if direct bit is set and clear bit 3 2 10 program branching acall addr11 absolute subroutine call 2 2 **1addr lcall addr16 long subroutine call 3 2 12 ret return from subroutine 1 2 22 reti return from interrupt 1 2 32 ajmp addr11 absolute jump 2 2 ***1addr ljmp addr16 long jump 3 2 02 sjmp rel short jump (relative addr) 2 2 80 jmp @a+dptr jump indirect relative to the dptr 1 2 73 jz rel jump if accumulator is zero 2 2 60 jnz rel jump if accumulator is not zero 2 2 70 cjne a,direct,rel compare direct byte to acc and jump if not equal 3 2 b5 cjne a,#data,rel compare immediate to acc and jump if not equal 3 2 b4 cjne rn,#data,rel compare immediate to register and jump if not equal 3 2 b* cjne @ri,#data,rel compare immediate to indirect and jump if not equal 3 2 b6, b7 djnz rn,rel decrement register and jump if not zero 2 2 d* djnz direct,rel decrement direct byte and jump if not zero 3 2 d5 nop no operation 1 1 00 note: 1. all mnemonics copyrighted ? intel corporation 1980
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 51 table 44. instruction map p8xc557e4 second hexadecimal character of opcode 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 nop ajmp ljmp rr inc inc inc @ ri inc rr addr11 addr16 a a dir 0 1 0 1 2 3 4 5 6 7 1 jbc acall lcall rrc dec dec dec @ ri dec rr bit, rel addr11 addr16 a a dir 0 1 0 1 2 3 4 5 6 7 2 jb ajmp ret rl add add add a, @ ri add a, rr bit, rel addr11 a a, #data a, dir 0 1 0 1 2 3 4 5 6 7 3 jnb acall reti rlc addc addc addc a, @ ri addc a, rr bit, rel addr11 a a, #data a, dir 0 1 0 1 2 3 4 5 6 7 4 jc ajmp orl orl orl orl orl a, @ ri orl a, rr rel addr11 dir, a dir, #data a, #data a, dir 0 1 0 1 2 3 4 5 6 7 5 jnc acall anl anl anl anl anl a, @ ri anl a, rr rel addr11 dir, a dir, #data a, #data a, dir 0 1 0 1 2 3 4 5 6 7 6 jz ajmp xrl xrl xrl xrl xrl a, @ ri xrl a, rr rel addr11 dir, a dir, #data a, #data a, dir 0 1 0 1 2 3 4 5 6 7 7 jnz acall orl jmp mov mov mov @ ri, #data mov rr, #data rel addr11 c, bit @a+dptr a, #data dir,#data 0 1 0 1 2 3 4 5 6 7 8 sjmp ajmp anl movc div mov mov dir, @ ri mov dir, rr rel addr11 c, bit a, @a+pc ab dir, dir 0 1 0 1 2 3 4 5 6 7 9 mov acall mov movc subb subb subb a, @ ri subb a, rr dptr,#data16 addr11 bit, c a,@a+dptr a, #data a, dir 0 1 0 1 2 3 4 5 6 7 a orl ajmp mov inc mul mov @ ri, dir mov rr, dir c,/bit addr11 c, bit dptr ab 0 1 0 1 2 3 4 5 6 7 b anl acall cpl cpl cjne cjne cjne @ri,#data,rel cjne rr, #data, rel c,/bit addr11 bit c a,#data,rel a,dir, rel 0 1 0 1 2 3 4 5 6 7 c push ajmp clr clr swap xch xch a, @ ri xch a, rr dir addr11 bit c a a, dir 0 1 0 1 2 3 4 5 6 7 d pop acall setb setb da dnjz xchd a, @ ri djnz rr, rel dir addr11 bit c a dir, rel 0 1 0 1 2 3 4 5 6 7 e movx ajmp movx a, @ri clr mov mov a, @ ri mov a, rr a, @dptr addr11 0 1 a a, dir *) 0 1 0 1 2 3 4 5 6 7 f movx acall movx a, @ri, a cpl mov mov @ ri, a mov rr, a @dptr, a addr11 0 1 a dir, a 0 1 0 1 2 3 4 5 6 7 *) mov a, acc is not a valid instruction first hexadecimal character of opcode
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 52 8. flash eeprom 8.1 general ? 32 kbytes electrically erasable internal program memory with block-and page-erase option (oflash memoryo). ? internal fixed boot rom. ? up to 32 kbytes external program memory in combination with the internal feeprom (ea =1). ? up to 64 kbytes external program memory if the internal program memory is switched off (ea =0). the feeprom can be read and written byte-wise. full erase, block erase, and page erase will erase 32 kbytes, 256 bytes and 32 bytes respectively. in-circuit programming and out-of-circuit programming is possible. on-chip erase and write timing generation and on chip high voltage generation contribute to a user friendly interface. 8.2 features ? read: byte-wise ? write: byte-wise within 2.5 ms. (previously erased by a page, block or full erase). ? erase: page erase (32 bytes) within 5 ms. block erase (256 bytes) within 5 ms. full erase (32 kbytes) within 5 ms. erased bytes contain ffh. ? endurance: 100 erase and write cycles each byte at t amb = 22 c ? retention: 10 years ? out-of-circuit programming: parallel programming with 87c51 compatible hardware interface to programmer. ? in-circuit programming: serial programming via rs232 interface under boot rom program control. auto baud rate selection. intel hex object file format. the user program can call routines in the boot rom for erase, write and verify of the feeprom. ? high programming voltage generation: on chip ? zero point on-chip oscillator and timer to generate the write and erase time durations. ? programmable security for the code in the feeprom to prevent software piracy. the security byte is located in the highest address (7fffh) of the feeprom. ? supply voltage monitoring circuit on-chip to prevent loss of information in the feeprom during power-on and power-off. 8.3 memory map figure 48 shows the memory map of the user program memory and the boot rom. they are located in the same program address space. two bits ubs1 and ubs0 of the feeprom control special function register fmcon select between the two memory blocks. user program memory selection if ubs1 and ubs0 are both 0, then the user program memory is mapped into the 64 k program memory space and the boot rom cannot be selected. this is the situation after a reset when psen and ale have not been pulled down during reset. program execution starts at 0000h in the internal feeprom or in the external program memory dependent on the level of ea during reset. boot rom selection after a reset program execution starts in the boot rom when during reset psen and ea are pulled down while ale stay high. the boot rom size is 1 kbyte. besides the serial in-circuit programming routine the boot rom contains the routines for erase, write and verify of the feeprom, which can be called by the user program (lcall to the address space between 63 k and 64 k). switching between user program memory and boot rom switching between user program memory (internal or external) and boot rom is possible if ubs1 and ubs0 are 0,1. then in the program memory address space between 0 and 63k the user program memory is selected and in the memory space between 63 k and 64 k the boot rom is selected. to switch from user program memory to boot rom first ubs0 must be set (ubs1 stay 0) and a jump or call instruction to a location >63 k must be executed. at the moment of crossing the 63 k address border by a return instruction the switching from boot rom to user memory (internal or external) is performed. after crossing the 63 k address border ubs1 and ubs0 are cleared and the total 64 k memory space is mapped as user program memory. by clearing ubs1 and ubs0, no special requirements to the user program are necessary to do that after a read or erase or write routine. a small restriction for memory switching is that no memory switching is allowed from or to the address space between 63 k and 64 k of the user program memory because the ubs bits must stay 0 in this range. this restriction can be avoided if the memory switching is always done by a subroutine in the address range between 0 and 63 k. description the user program code in the feeprom is executed as in the standard 80c51 microcontroller. erase and write cycles in the feeprom are always performed under control of the boot program in the boot rom in the address space between 63 k and 64 k. address and data parameters are passed via dptr and accumulator a respectively. during an erase or write cycle in the feeprom no other access or program execution in the feeprom is possible. all interrupts must be disabled when the user program calls a user routine in the boot rom. the boot routine for serial programming takes care of addressing, data transfer, verify, high voltage control, error message and return to the user program memory. it also contains the serial communication routine. the feeprom control register fmcon is a special function register. it contains the control bits for verify, write, erase and boot rom switching.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 53 figure 48. program memory map and operation modes * in the program execution between 63k and 64k setting of ubs bits is not allowed. user mode boot mode rst psen ale/we ea internal external start at 0000h in user program start in bootrom ubs1, ubs0 0,0 1,1 external program memory (ea = 0) external program memory (ea = x) internal program memory (ea = 1) security byte bootrom 0,0 0,1 64 k 63 k 32 k 7fffh 00 64 k 63 k 32 k x,x = ubs1, ubs0 user-boot selection bits in fmcon high level low level external program memory (ea = 0) external program memory (ea = x) security byte internal program memory (ea = 1) *
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 54 figure 49. feeprom control register. 76543210 fmcon (fb) ubs1 ubs0 hv 1) fcb3 fcb2 fcb1 fcb0 note: 1. reserved for future use; a write operation must write a0o to the location. table 45. description of fmcon bits ubs1 ubs0 user - boot selection bits 0 0 user memory mapped from 0 to 64 k. 0 1 user memory mapped from 0 to 63 k. boot rom mapped from 63 k to 64 k. 1 0 user memory mapped from 0 to 63 k, but ubs1 bit cleared by hardware in this user address range. boot rom mapped from 63 k to 64 k. user software should not write a1o ubs1. 1 1 boot rom mapped from 0 to 64 k. user software should not write a1o ubs1. hv high voltage indication bit. read only. is a1o as long as the high voltage for an erase or write operation is present. fcb3 fcb2 fcb1 fcb0 function code bits 0 0 0 0 value after reset. 0 1 0 1 byte write or byte read (verify) 1 1 0 0 page erase (32 bytes boundaries). 0 0 1 1 block erase (256 bytes boundaries). 1 0 1 0 full erase (32 kbytes). the four fcb bits are write protected if the security feature is activated. then only instructions in the internal program memory (feeprom) are able to write fcb (30), boot rom and external program memory instructions cannot change fcb (30) except the full erase code can be loaded. the duration of a write or erase operation is determined by the feeprom timer. this timer includes a zero point rc oscillator and cannot be controlled by software. for calling a user routine in the boot rom first all interrupts must be disabled and the dptr and a have to be loaded with the desired values. after setting ubs0 = 1 and ubs1 = 0 and selecting the function via fcb-bits the respective user routine has to be called. the table below lists the boot rom user routines, which can be called by the user program. the content of fmcon, a and dptr before the call is described by a(in)o and the contents after the return is described by a(out)o. the boot rom user routines do not change other registers or data memory. boot-rom routine call address fmcon (in) fmcon (out) acc (in) acc (out) dptr (in) dptr (out) byte_read ffbah 45h 15h xxh byte byte address byte address byte_write ffadh 45h 15h byte byte (v) byte address byte address page_erase ffaah 4ch 1ch xxh 08h page address 1) page address 2) block_erase ffa5h 43h 13h xxh 02h block address 3) block address 4) full_erase ffa0h 4ah 1ah xxh 0ah xxxxh 0018h x = don't care or not defined v = verified byte (read back) 1) = 5 lsb's of dptr are don't care 2) = 5 lsb's of dptr are a0o 3) = 8 lsb's of dptr are don't care 4) = 8 lsb's of dptr contain 08h.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 55 example of user software (internal or external) that calls the page erase routine in the boot rom to erase a page in the feeprom (32 bytes) starting at address location 1260h. clr ea ; disable all interrupts mov dptr, # 1260h ; load page-address mov fmcon, # 4ch ; load page-erase code lcall 0ffaah ; call page-erase routine ; in boot rom (inherent delay 5 ms) mov fmcon, #00h ; clear fmcon for security setb ea ; enable interrupts again example of user software (internal or external) that calls the byte-write routine in the boot rom to write the content of r5 into the feeprom address location 1263h. clr ea ; disable all interrupts mov dptr, # 1263h ; load byte address mov a, r5 ; load byte to be written mov fmcon, # 45h ; load byte-write code lcall 0ffadh ; call byte-write routine ; in boot rom (inherent delay 2.5 ms) mov fmcon, #00h ; clear fmcon for security setb ea ; enable interrupts again xrl a, r5 ; compare the aread-backo byte jnz error ; jump if verify error 8.4 security the security feature protects against software piracy and prevents that the content of the feeprom can be read undesirable. the security byte is located in the highest address location 7fffh of the feeprom. the security byte should be 50h to activate and 00h or ffh to deactivate the security feature. this security code is chosen in such a way that single bit failures will not deactivate the security feature. if the security feature is deactivated, then there are no access restrictions to the feeprom. if the security feature is activated, then the external program memory has no access to the feeprom with the movc instructions. also bits fcb (30) of fmcon cannot be written by external program code or boot rom code. this prevents in-circuit programming and verification. only the full erase code can be written to fcb (03) of fmcon. note that for the internal program code no restrictions exist if the security feature is activated. at the end of a full erase operation the security feature is deactivated. also parallel programming and verify is inhibited if the security feature is activated, only a full erase is possible. note that the security mode does not change immediately when the security code is written into the security byte 7fffh, but after a reset or power-on. this allows the verification of the loaded code in the feeprom, including the security byte. 8.5 parallel programming unlike standard eprom programming, no high programming supply voltage must be applied to the ea pin and only one programming pulse must be applied to the ale/we pin. the parallel programming mode is entered with the steady signals rst=1, psen=0, ea =1 and selxtal1 = 1. the xtal1,2 clock must have a frequency between 4 and 6mhz. the following table shows the logic levels for programming, erasing, verifying and read signature. mode ale/we p2.7 p2.6 p3.7 p3.6 full erase 1 1 0 1 program feeprom 1 0 1 1 verify feeprom 1 0 0 1 1 read signature 1 0 0 0 0 ale/we write enable signal (program/erase), active low p2.6, p2.7, p3.6, p3.7 control signals data and address bits: p0.0 p0.7 : d0 d7 program data input / verify or read data output p1.0 p1.7 : a0 a7 input low order address bits. p2.0 p2.5, p3.4 : a8 a14 input high order address bits. the p89c557e4 contains two signature bytes that can be read and used by an eprom programming system to identify the device. these bytes are read by the same procedure as for a normal verification of locations 30h and 31h, except that p3.6 and p3.7 need to be pulled to low. address content meaning 30h 31h 15h b5h philips p89c557e4
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 56 figure 50. erase configuration don't care 1 1 0 4-6mhz +5 v don't care 1 5 ms low pulse 0 1 1 don't care p1 rstin p3.6 p3.7 xtal2 xtal1 v ss v dd p0 ea ale/we psen p2.7 p2.6 p2.0-p2.5 p89c557e4 don't care p3.4 1 selxtal1 figure 51. programming configuration a0a7 1 1 1 4-6mhz +5 v pgm data 1 2.5 ms low pulse 0 1 0 a8a13 p1 rstin p3.6 p3.7 xtal2 xtal1 v ss v dd p0 ea ale/we psen p2.7 p2.6 p2.0-p2.5 p89c557e4 a14 p3.4 1 selxtal1 a0-a7 1 1 1 4-6mhz +5 v pgm data 1 1 0 0 (enable) 0 a8-a13 p1 rstin p3.6 p3.7 xtal2 xtal1 v ss v dd p0 ea ale/we psen p2.7 p2.6 p2.0-p2.5 p89c557e4 figure 52. program verification 8 x 10 k p3.4 a14 1 selxtal1
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 57 feeprom programming and verification characteristics t amb = 40 c to +85 c, v dd = 5 v 10%, v ss = 0 v (see figure 53) symbol parameter min max unit 1/t clk system clock frequency (standard oscillator) 4 6 mhz t avwl address setup to we low 48t clk t whax address hold after we high 48t clk t dvwl data setup to we low 48t clk t whdx data hold after we high 48t clk t ehwl p2.7 (enable ) high to we low 48t clk t whel we high to p2.7 (enable ) low 48t clk t wlwhp we width (programming) 2.25 2.75 ms t wlwhe we width (erase) 4.5 5.5 ms t avqv address to data valid 48t clk t elqv p2.7 (enable) low to data valid 48t clk t ehqz data float after p2.7 (enable) high 0 48t clk t ehwl figure 53. feeprom programming/erase and verification waveforms programming*/erase* verification* address (programming) address data in (programing) data out t avqv t ehqz t elqv t avwl t whax t dvwl t whdx p0.0p0.7 ale/we p2.7 enable * for erase conditions see figure 50. for program conditions see figure 51. for verify conditions see figure 52. t whel t wlwhp t wlwhe p1.0p1.7 p2.0p2.5 p3.4
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 58 figure 54. serial programming (boot mode) configuration 32.768 khz +5 v 1 xtal3 xtal4 v dd ew psen p3.0/rxd ale p89c557e4 ea p3.1/txd output of ale pulses rs232 interface 3k3 0 all other pins are don't care rst selxtal1 1) v ss 1) alternative xtal1, 2 may be selected (selxtal1 = 1) 8.6 serial programming of feeprom serial in-circuit programming (boot-mode) is entered if during and after reset psen and ea are pulled down, psen via a resistor of 3.3 k ohm to vss. the two ubs bits are set to 1 by hardware and program execution starts at 0000h of the boot rom. p3.0 (rxd) and p3.1 (txd) form the serial rs232 interface. a baud rate of 4800 or 9600 baud is possible, if the pll oscillator is selected. the receive and transmit channel have the same baudrate. the format is: startbit, 8 data bits (last bit always 0), no parity bit and at least one stopbit. the boot routine inputs the intel hex object format. the baud rate will be selected automatically after reception of the first character (:) of the object file. no other characters are allowed to preceed the first (:) character. programming is only started if the first received record has the right type indication (tt). if the security feature is activated (contents of the security byte = 50h) then the programming starts with a full erase, otherwise only the addressed page(s) will be erased and the not altered bytes are rewritten. during the erase or write operation the next string of bytes can be received. xon and xoff handshake codes are used to control the serial transfer. at the end of the programming a message that indicates a successful or not successful programming, will be returned over the rs232 interface channel. if the programming was successful then the user program can be started up at 0000h in feeprom by a reset for user mode (ea = high, psen not affected). if the programming was not successful the boot program halts and a retry can be started by a reset for the boot mode. 8.7 boot routine the boot routine transmits the next aone ascii charactero messages via the rs232 interface: a . o after each record type tt = 00h indication in the hex file. a x o checksum error of a record in the hex file detected. a y o wrong record type received a z o buffer overflow error (check xon/xoff of terminal) a r o verification error (of last written byte) a v o end record received and programming of feeprom was successful no messages are transmitted if the baud rate of the first character (:) can not be detected. the boot routine can also be started by the internal or external user program (ljmp fc07h). fmcon must be loaded previously with 40h. interrupt registers, stack pointer, timer 0, uart, p3.0 and p3.1 must be in the reset state. ea and psen must not be affected. a reset is needed to restart the user program after programming. the following baudrates will be detected automatically within the specified m c clock range in mhz. baudrate f clk (min) f clk (max) 1200 1 1) 3.6 2400 2 1) 7.3 4800 4 14.7 9600 7.9 29.5 1) 19200 15.7 59 1) note: 1. value outside the specified clock range note that the boot routines can (re) program any number of bytes from 1 byte to 32 kbytes, independent in which order or at which location, but if the security feature is activated, a full erase is performed and all not programmed bytes become ffh.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 59 definitions: : record start character bc byte count. the hexadecimal number of data bytes in the record. this may theoretically be any number from 0 to 255, although many assemblers prefer to deal with 16 data bytes per record (as shown in the example below). aaaa load address in hexadecimal of first data byte in this record. tt record type. the record type is 00 for data records and 01 for the end record. hh one hexadecimal data byte. cc record checksum. this is the 2's complement of the summation of all of the bytes in the record from the byte count through the last data byte. while the summation is calculated, it is always truncated to a one byte result. thus, if all of the bytes in th e record are summed, including the checksum itself, the result will always be 00 if the record is valid. construction of data records (using the notation defined above, each letter corresponds to one hexadecimal digit in ascii repre sentation) is as follows: : bcaaaatthhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhcc the last record in a file is the end record and contains no data. usually the end record will appear as shown in the first exam ple below. however, in some cases a 16 bit checksum of all of the data bytes in the entire file may be inserted in the address field of th e end record. this checksum would correspond to one generated by an eprom programmer during file load, and its inclusion does not violate the rule s for this format. this is shown in the second example. :00000001ff :00b12c0122 successive hex records need not appear in sequential address order . for instance, a record for address 0000h might appear afte r a record for address 7fe0h. all of the bytes in a single record, however, must be in sequence. any characters that appear outside of a recor d (i.e. after a checksum, but before the next a:o) will be ignored, if present. an example of a valid hex file follows: :10010000c2f0e53030e704f404d2f08531f030f786 :100110000763f0ff05f0b2f0a430f00a63f0fff4db :0c0120002401500205f085f032f5332276 :00000001ff 9. absolute maximum ratings absolute maximum ratings 1, 2, 3 parameter rating unit storage temperature range 65 to +150 c voltage on v dd to v ss and scl, sda to v ss 0.5 to +6.5 v input / output current on any i/o pin 10 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1.0 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions are taken to avoid applying greater than the rated maxima. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 60 10. dc characteristics dc electrical characteristics v dd = 5v ( 10%), v ss = 0v, t amb = 0 c to +70 c (p8xc557e4ebx). all voltages with respect to v ss unless otherwise specified. test limits symbol parameter conditions min max unit v dd supply voltage 4.5 5.5 v i dd supply current operating : see notes 1 and 2 p89c557e4 f clk = 16mhz 40 ma p83c557e4 v dd = 5.5 v 40 ma i id supply current idle mode : see notes 1 and 3 p89c557e4 f clk = 16mhz 15 ma p83c557e4 v dd = 5.5 v 12 ma i supply current power-down mode see note 4 2 v < v pd < v ddmax 100 m a i pd supply current power-down mode: 32 khz / pll operation see note 17 v dd = 5.5 v 100 m a inputs v il input low voltage, except ea , scl, sda 0.5 0.2v dd 0.1 v v il1 input low voltage to ea 0.5 0.2v dd 0.3 v v il2 input low voltage to scl, sda 5 0.5 0.3v dd v v ih input high voltage, except xtal1, rstin, scl, sda, adexs 0.2v dd +0.9 v dd +0.5 v v ih1 input high voltage, xtal1, rstin, adexs 0.7v dd v dd +0.5 v v ih2 input high voltage, scl, sda 5 0.7v dd 6.0 v i il input current low level, ports 1, 2, 3, 4 v in = 0.45 v 50 m a i tl transition current high to low, ports 1, 2, 3, 4 see note 6 650 m a i li1 input leakage current, port 0, ea , adexs, ew, selxtal1 0.45 v < v i < v dd 10 m a i li2 input leakage current, scl, sda 0 v < v i < 6 v 0 v < v dd < 5.5 v 10 m a i li3 input leakage current, port 5 0.45 v < v i < v dd 1 m a outputs v ol output low voltage, ports 1, 2, 3, 4 i ol = 1.6ma 7 0.45 v v ol1 output low voltage, port 0, ale, psen , pwm0 , pwm1 , rstout i ol = 3.2ma 7 0.45 v v ol2 output low voltage, scl, sda i ol = 3.0ma 7, 19 0.4 v i ol = 6.0ma 7, 19 0.6 v oh output high voltage, ports 1, 2, 3, 4 v dd = 5 v 10% i oh = 60 m a 2.4 v i oh = 25 m a 0.75v dd v i oh = 10 m a 0.9v dd v v oh1 output high voltage (port 0 in external bus mode, ale, psen , pwm0 , pwm1 , rstout) 8 v dd = 5 v 10% i oh = 800 m a 2.4 v i oh = 300 m a 0.75v dd v i oh = 80 m a 0.9v dd v v hys hysteresis of schmitt trigger inputs scl, sda (fast-mode) 0.05v dd 20 v notes: see page 62.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 61 dc electrical characteristics (continued) v dd = 5 v ( 10%), v ss = 0 v, t amb = 40 c to +85 c (p8xc557e4efx). dc parameters not included here are the same as in the p8xc557e4ebx, dc electrical characteristics all voltages with respect to v ss unless otherwise specified. test limits symbol parameter conditions min max unit r rst internal reset pull-down resistor 50 150 k w c io pin capacitance test freq = 1mhz, t amb = 25 c 10 pf inputs v il input low voltage, except ea , scl, sda 0.5 0.2v dd 0.15 v v il1 input low voltage to ea 0.5 0.2v dd 0.35 v v ih input high voltage, except xtal1, rstin, scl, sda, adexs 0.2v dd +1.0 v dd +0.5 v v ih1 input high voltage, xtal1, rstin, adexs 0.7v dd +0.1 v dd +0.5 v i il input current low level, ports 1, 2, 3, 4 v in = 0.45 v 75 m a i tl transition current high to low, ports 1, 2, 3, 4 see note 6 750 m a notes: see page 62. dc electrical characteristics analog av dd = 5 v ( 10%), av ss = 0 v, tamb = 0 c to +70 c (p8xc557e4ebx). av dd = 5 v ( 10%), av ss = 0 v, tamb = 40 c to +85 c (p8xc557e4efx). all voltages with respect to v ss unless otherwise specified. test limits symbol parameter conditions min max unit av dd analog supply voltage av dd = v dd 0.2 v 4.5 5.5 v ai analog supply current operating port 5 = 0 to av dd see notes 1 and 2 1.2 ma ai dd analog supply current operating: 32 khz/pll operation port 5 = 0 to av dd see note 17, 18 7.2 ma analog supply current idle mode see notes 1 and 3 70 a ai id analog supply current idle mode: 32 khz/pll operation see note 17 6.0 ma ai supply current power-down mode 2 v < v pd < v ddmax see note 4 50 m a ai pd supply current power-down mode: 32 khz / pll operation v dd = 5.5v see note 17 200 m a analog inputs av in analog input voltage av ss 0.2 av dd +0.2 v av ref reference voltage: av ref av ss 0.2 v av ref+ av dd +0.2 v r ref resistance between av ref+ and av ref 10 50 k w c ia analog input capacitance 15 pf dl e differential non-linearity 9, 10, 11, 1 lsb il e integral non-linearity 9, 12 2 lsb os e offset error 9, 13 2 lsb g e gain error 9, 14 0.4 % a e absolute voltage error 9, 15 3 lsb m ctc channel to channel matching 1 lsb c t crosstalk between inputs of port 5 16 0100khz 60 db notes: see page 62.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 62 notes for dc electrical characteristics: 1. see figures 55 and 57 through 59 for i dd test conditions. 2. the operating supply current is measured with all output pins disconnected; xtal1 driven with t r = t f = 5ns; v il = v ss + 0.5 v; v ih = v dd 0.5 v; xtal2, xtal3 not connected; ea = rstin = port 0 = ew = scl = sda = selxtal1 = v dd ; adexs = xtal4 = v ss . 3. the idle mode supply current is measured with all output pins disconnected; xtal1 driven with t r = t f = 5ns; v il = v ss + 0.5 v; v ih = v dd 0.5 v; xtal2, xtal3 not connected; port 0 = ew = scl = sda = selxtal 1 = v dd ; ea = rstin = adexs = xtal4 = v ss . 4. the power-down current is measured with all output pins disconnected; xtal2 not connected; port 0 = ew = scl = sda = selxtal 1 = v dd ; ea = rstin = adexs = xtal1 = xtal4 = v ss . 5. the input threshold voltage of scl and sda (sio1) meets the i 2 c specification, so an input voltage below 0.3 v dd will be recognized as a logic 0 while an input voltage above 0.7 v dd will be recognized as a logic 1. 6. pins of ports 1, 2, 3, and 4 source a transition current when they are being externally driven from high to low. the transiti on current reaches its maximum value when v in is approximately 2 v. 7. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol of ale and ports 1, 3 and 4. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desir able to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 8. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v dd specification when the address bits are stabilizing. 9. conditions: av ref = 0 v; av dd = 5.0 v, av ref+ = 5.12 v. v dd = 5.0 v, v ss = 0 v, adc is monotonic with no missing codes. measurement by continuous conversion of av in = 20mv to 5.12 v in steps of 0.5mv, derivating parameters from collected conversion results of adc. adc prescaler programmed according to the actual oscillator frequency, resulting in a conversion time within the specified rang e for t conv (15 m s ... 50 m s). 10. the differential non-linearity (dl e ) is the difference between the actual step width and the ideal step width. 11. the adc is monotonic; there are no missing codes. 12. the integral non-linearity (il e ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. 13. the offset error (os e ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. the offset error is constant at every point of the actual transfer curve. 14. the gain error (g e ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset erro r), and the straight line which fits the ideal transfer curve. gain error is constant at every point on the transfer curve. 15. the absolute voltage error (a e ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. 16. this should be considered when both analog and digital signals are simultaneously input to port 5. 17. the supply current with 32 khz oscillator running and pll operation (selxtal1 = 0) is measured with all output pins disconne cted; xtal4 driven with t r = t f = 5ns; v il = v ss + 0.5 v; v ih = v dd 0.5 v; xtal2 not connected; port 0 = ew = scl = sda = v dd ; ea = rstin = adexs = selxtal 1 = xtal1 = v ss . 18. not 100% tested; sum of a iid (pll) and a idd (hf-oscillator). 19. the parameter meets the i 2 c bus specification for standard-mode and fast-mode devices. 20. not 100% tested.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 63 40 30 20 10 12 416 8 f (mhz) (1) figure 55. supply current (i dd ) as a function of frequency at xtal1 i dd (ma) 50 0 0 (2) (3) (4) (1) maximum operating mode p89c557e4 : v dd = 5.5 v (2) maximum operating mode p83c557e4/p80c557e4 : v dd = 5.5 v (3) maximum idle mode p89c557e4 : v dd = 5.5 v (4) maximum idle mode p83c557e4/p80c557e4 : v dd = 5.5 v
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 64 1 0 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 code out (2) (1) (5) (4) (3) 1 lsb (ideal) offset error os e offset error os e gain error g e av in (lsb ideal ) 1 lsb = av ref+ av ref 1024 (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential non-linearity (dl e ). (4) integral non-linearity (il e ). (5) center of a step of the actual transfer curve. figure 56. adc conversion characteristic
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 65 11. ac characteristics ac electrical characteristics v dd = 5 v 10% (ebx), v ss = 0 v, t clk min = 1/fmax (maximum operating frequency) v dd = 5 v 10% (efx), v ss = 0 v, t clk min = 1/fmax (maximum operating frequency) t amb = 0 c to +70 c, t clk min = 63 ns for p8xc557e4ebx t amb = 40 c to +85 c, t clk min = 63 ns for p8xc557e4efx c1 = 100 pf for port 0, ale and psen ; c1 = 80 pf for all other outputs unless otherwise specified. 12mhz clock 16mhz clock variable clock symbol figure parameter min max min max min max unit 1/t clk 60 system clock frequency 3.5 16 mhz t lhll 60 ale pulse width 127 85 2t clk 40 ns t avll 60 address valid to ale low 43 23 t clk 40 ns t llax 60 address hold after ale low 53 33 t clk 30 ns t lliv 60 ale low to valid instruction in 234 150 4t clk 100 ns t llpl 60 ale low to psen low 53 33 t clk 30 ns t plph 60 psen pulse width 205 143 3t clk 45 ns t pliv 60 psen low to valid instruction in 145 83 3t clk 105 ns t pxix 60 input instruction hold after psen 0 0 0 ns t pxiz 60 input instruction float after psen 59 38 t clk 25 ns t aviv 60 address to valid instruction in 312 208 5t clk 105 ns t plaz 60 psen low to address float 10 10 10 ns data memory t avll 61, 62 address valid to ale low 43 23 t clk 40 ns t llax 61, 62 address hold after ale low 48 28 t clk 35 ns t rlrh 61 rd pulse width 400 275 6t clk 100 ns t wlwh 62 wr pulse width 400 275 6t clk 100 ns t rldv 61 rd low to valid data in 252 148 5t clk 165 ns t rhdx 61 data hold after rd 0 0 0 ns t rhdz 61 data float after rd 97 55 2t clk 70 ns t lldv 61 ale low to valid data in 517 350 8t clk 150 ns t avdv 61 address to valid data in 585 398 9t clk 165 ns t llwl 61, 62 ale low to rd or wr low 200 300 138 238 3t clk 50 3t clk +50 ns t avwl 61, 62 address valid to wr low or rd low 203 120 4t clk 130 ns t qvwx 62 data valid to wr transition 33 13 t clk 50 ns t qvwh 62 data before wr 433 288 7t clk 150 ns t whqx 62 data hold after wr 33 13 t clk 50 ns t rlaz 61 rd low to address float 0 0 0 ns t whlh 61, 62 rd or wr high to ale high 43 123 23 103 t clk 40 t clk +40 ns uart timing shift register mode (test conditions: t amb = 0 c to +70 c; v ss = 0 v; load capacitance = 80pf) t xlxl 64 serial port clock cycle time 1.0 0.75 12t clk m s t qvxh 64 output data setup to clock rising edge 700 492 10t clk 133 ns t xhqx 64 output data hold after clock rising edge 50 8 2t clk 117 ns t xhdx 64 input data hold after clock rising edge 0 0 0 ns t xhdv 64 clock rising edge to input data valid 700 492 10t clk 133 ns
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 66 ac electrical characteristics (continued) symbol parameter standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max i 2 c interface timing (refer to figure 63) f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 1.3 m s t hd; sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 0.6 m s t low low period of the scl clock 4.7 1.3 m s t high high period of the scl clock 4.0 0.6 m s t su; sta set-up time for a repeated start condition 4.7 0.6 m s t hd; dat data hold time: for cbus competible masters (see section 9, notes 1, 3) for i 2 c-bus devices 5.0 0 1 0 1 0.9 2 m s t su; dat data set-up time 250 100 3 ns t fd , t fc rise time of both sda and scl signals 1000 20 + 0.1c b 4 300 ns t fd , t fc fall time of both sda and scl signals 300 20 + 0.1c b 4 300 ns t su ; sto set-up time for stop condition 4.0 0.6 m s c b capacitive load for each bus line 400 400 pf t sp pulse width of spikes which must be suppressed by the input filter 0 50 ns all values referred to v ih and v il max levels. notes: 1. a device must internally provide a hold time of at least 300 ns from the sda signal (referred to the v ih min of the scl signal) in order to bridge the undefined region of the falling edge of scl. 2. the maximum t hd,dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 3. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su,dat > 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch t he low period of the scl signal, it must output the next data bit to the sda line t rmax + t su,dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. 4. c b = total capacitance of one bus line in pf. table 46. external clock drive xtal1 (refer to figure 57) symbol parameter variable clock f clk = 3.5 to 16 mhz unit min max t clk xtal1 period 63 286 ns t clkh xtal1 high time 20 ns t clkl xtal1 low time 20 ns t clkr xtal1 rise time 20 ns t clkf xtal1 fall time 20 ns t cyc 1) controller cycle time 0.75 3.4 m s note: 1. t cyc = 12 f clk
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 67 t clkl figure 57. external clock drive waveform v ih1 v ih1 0.8v t clk v ih1 v ih1 0.8v t clkh t clkr t clkf 2.4 v 0.45 v 2.0 v 0.8 v note: figure 58. ac testing input/output 2.4 v note: figure 59. ac testing, float waveform ac inputs during testing are driven at 2.4v for a logic `high' and 0.45v for a logic `low'. timing measurements are made at 2.0 v for a logic `high' and 0.8 v for a logic `low'. 2.4 v 0.45 v 0.45 v float 2.0 v 0.8 v 2.0 v 0.8 v test points 2.0 v 0.8 v sources 400 a at the voltage test levels. the float state is defined as the point at which a port 0 pins sinks 3.2 ma or t pxiz figure 60. external program memory read cycle ale psen port 0 port 2 a8a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t pliv t lhll t plph t lliv t plaz t llpl t aviv
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 68 ale psen port 0 port 2 figure 61. external data memory read cycle rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dph a8a15 from pch t whlh t lldv t llwl t rlrh t llax t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv t llax ale psen port 0 port 2 figure 62. external data memory write cycle wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dph a8a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx t qvwh
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 69 figure 63. timing sio1 (i 2 c) interface t rd t su;sta t buf t su; sto 0.3 v dd 0.7 v dd 0.3 v dd t fd t rc t fc t high t low t hd;sta t su;dat1 t hd;dat t su;dat2 t su;dat3 start condition repeated start condition sda (input/output) scl (input/output) stop condition start or repeated start condition 0.7 v dd t sp figure 64. uart waveforms in shift register mode 012 345 678 instruction ale clock output data write to sbuf input data clear ri valid valid valid valid valid valid valid valid set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv 0 123 4 567
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 70 figure 65. instruction cycle timing xtal1 input s1 p1 p2 s2 p1 p2 s3 p1 p2 s4 p1 p2 s5 p1 p2 s6 p1 p2 s1 p1 p2 s2 p1 p2 s3 p1 p2 s4 p1 p2 s5 p1 p2 s6 p1 p2 one machine cycle one machine cycle ale psen rd wr int. in address a0a7 int. in int. in int. in address a0a7 address a0a7 address a0a7 address a8a15 address a8a15 address a8a15 address a8a15 address a8a15 address a8a15 or port2 out address a8a15 old data new data sampling time of i/o port pins during input (including int0 and int1 ) bus (port 0) port 2 bus (port 0) port 2 port output port input serial port clock dotted lines are valid when rd or wr are active only active during a read from external data memory only active during a write to external data memory external program memory fetch read or write of external data memory int. in address a0a7 int. in address a0a7 data output or data input address a0a7 purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011.
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 71 qfp80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height sot318-1
philips semiconductors product specification p83c557e4/p80c557e4/p89c557e4 single-chip 8-bit microcontroller 1999 mar 02 72 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1999 all rights reserved. printed in u.s.a. date of release: 03-99 document order number: 9397 750 05357
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.
1 of 4 go to philips semiconductors' home page select & go... start part catalog & datasheets catalog by function discrete semiconductors audio clocks and watches data communications microcontrollers peripherals standard analog video wired communications wireless communications catalog by system automotive consumer multimedia systems communications pc/pc-peripherals cross reference models packages application notes selection guides other technical documentation end of life information datahandbook system relevant links about catalog tree about search about this site subscribe to enews catalog & datasheets search p83c557e4, p80c557e4, p89c557e4 p83c557e4, information as of 2000-08-29 p83c557e4, p80c557e4, p89c557e4; single-chip 8-bit microcontroller ? description ? features ? datasheet ? products, packages, availability and ordering ? find similar products ? subscribe to enews to be kept informed on p83c557e4, p80c557e4, p89c557e4, subscribe to enews. description the p80c557e4/p83c557e4/p89c557e4 (hereafter generically referred to as p8xc557e4) single-chip 8-bit microcontroller is manufactured in an advanced cmos process and is a derivative of the 80c51 microcontroller family. the p8xc557e4 has the same instruction set as the 80c51. three versions of the derivative exist: l p83c557e4 - 32 kbytes mask programmable rom l p80c557e4 - romless version of the p83c557e4 l p89c557e4 - 32 kbytes feeprom (flash-eeprom) the p8xc557e4 contains a non-volatile 32 kbytes mask programmable rom (p83c557e4) or electrically erasable feeprom respectively (p89c557e4), a volatile 1024 8 read/write data memory, five 8-bit i/o ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80c51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input adc, a dual dac pulse width modulated interface, two serial interfaces (uart and i2c-bus), a "watchdog" timer, an on-chip oscillator and timing circuits. for systems that require extra capability the p8xc557e4 can be expanded using standard ttl compatible memories and logic. in addition, the p8xc557e4 has two software selectable modes of power reduction - idle mode and power-down mode. the idle mode freezes the cpu while allowing the ram, timers, serial ports, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. the device also functions as an arithmetic processor having facilities for both binary and bcd arithmetic as well as bit-
2 of 4 p83c557e4, p80c557e4, p89c557e4 handling capabilities. the instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three- byte. with a 16 mhz system clock, 58% of the instructions are executed in 0.75 s and 40% in 1.5 s. multiply and divide instructions require 3 s. p8xc557ex factsheet features l 80c51 central processing unit l 32 k 8 rom respectively feeprom (flash-eeprom), expandable externally to 64 kbytes l rom/feeprom code protection l 1024 8 ram, expandable externally to 64 kbytes l two standard 16-bit timer/counters l an additional 16-bit timer/counter coupled to four capture registers and three compare registers l a 10-bit adc with eight multiplexed analog inputs and programmable autoscan l two 8-bit resolution, pulse width modulation outputs l five 8-bit i/o ports plus one 8-bit input port shared with analog inputs l i2c-bus serial i/o port with byte oriented master and slave functions l full-duplex uart compatible with the standard 80c51 l on-chip watchdog timer l 15 interrupt sources with 2 priority levels (2 to 6 external sources possible) l extended temperature range (-40 to +85c) l 4.5 to 5.5 v supply voltage range l frequency range for 80c51-family standard oscillator: 3.5 mhz to 16 mhz l pll oscillator with 32 khz reference and software-selectable system clock frequency l seconds timer l software enable/disable of ale output pulse l electromagnetic compatibility improvements l wake-up from power-down by external or seconds interrupt datasheet type nr. title publication release date datasheet status page count file size (kb) datasheet p83c557e4, single-chip 8-bit microcontroller 02-mar-99 product 72 525 download
3 of 4 p80c557e4, p89c557e4 specification products, packages, availability and ordering partnumber north american partnumber order code (12nc) marking/packing package device status buy online p80c557e4efb/01 p80c557e4b- t 9352 631 56518 standard marking * reel dry pack, smd, 13" sot318 full production - p80c557e4b- s 9352 631 56551 standard marking * tray dry pack, bakeable, single sot318 full production - p80c557e4b 9352 631 56557 standard marking * tray dry pack, bakeable, multiple sot318 full production p83c557e4efb/114 9352 632 08557 standard marking * tray dry pack, bakeable, multiple sot318 full production - p83c557e4efb/123 9352 632 61557 standard marking * tray dry pack, bakeable, multiple sot318 full production - p83c557e4efb/132 9352 632 62557 standard marking * tray dry pack, bakeable, multiple sot318 full production - p83c557e4efb/142 9352 632 06557 standard marking * tray dry pack, bakeable, multiple sot318 full production - p83c557e4efb/147 9352 632 63557 standard marking * tray dry pack, bakeable, multiple sot318 full production - p83c557e4efb/201 9352 639 92557 standard marking * tray dry pack, bakeable, multiple sot318 full production - p83c557e4efb/202 9352 667 05557 standard marking * tray dry pack, bakeable, multiple sot318 full production - p83c557e4efb/203 9352 679 25557 standard marking * tray dry pack, sot318 full production -
4 of 4 bakeable, multiple p83c557e4efb/204 9352 680 65557 standard marking * tray dry pack, bakeable, multiple sot318 full production - p89c557e4efb/01 p89c557e4b- t 9352 631 22518 standard marking * reel dry pack, smd, 13" sot318 full production - p89c557e4b- s 9352 631 22551 standard marking * tray dry pack, bakeable, single sot318 full production - p89c557e4b 9352 631 22557 standard marking * tray dry pack, bakeable, multiple sot318 full production please read information about some discontinued variants of this product . find similar products: p83c557e4, p80c557e4, p89c557e4 links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. the similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category. copyright ? 2000 royal philips electronics all rights reserved. terms and conditions .

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