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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? 100 percent bus utilization no wait cycles between read and write internal self-timed write cycle individual byte write control single r/w (read/write) control pin clock controlled, registered address, data and control interleaved or linear burst sequence control using mode input power down mode common data inputs and data outputs cke pin to enable clock and suspend operation jedec 119-ball pbga (x36) and 209-ball (x72) pbga packages single +1.8v ( 5%) power supply jtag boundary scan industrial temperature available description the 16 meg 'nvvp' product family feature high-speed, low-power synchronous static rams designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. they are organized as 256k words by 72 bits, 512k words by 36 bits and are fabricated with issi 's advanced cmos technology. incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. this device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. operations may be suspended and all synchronous inputs ignored when clock enable, cke is high. in this state the internal device will hold their previous values. all read, write and deselect cycles are initiated by the adv input. when the adv is high the internal burst counter is incremented. new external addresses can be loaded when adv is low. write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when we is low. separate byte enables allow individual bytes to be written. a burst mode pin (mode) defines the order of the burst sequence. when tied high, the interleaved burst sequence is selected. when tied low, the linear burst sequence is selected. 256k x 72 and 512k x 36, 18mb pipeline 'no wait' state bus sram advance information july 2002 fast access time symbol p arameter -250 -200 units t kq clock access time 2.6 3.2 ns t kc cycle time 4 5 ns frequency 250 200 mhz
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? block diagram adv we } bw ? x (x=a,b,c,d or a,b) ce ce2 ce2 control logic 256kx72; 512kx36 memory array write address register write address register control logic output register buffer address register a [0:17] or a [0:18] clk cke a2-a17 or a2-a18 a0-a1 a'0-a'1 burst address counter mode data-in register data-in register control register oe zz 72 or 36 k k dqa0-dqd7 or dqa0-dqb8 dqpa-dqpd k k
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? pin descriptions a synchronous address inputs a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. adv synchronous burst address advance bw a- bw h synchronous byte write enable ce , ce2 , ce2 synchronous chip enable clk synchronous clock cke clock enable dqa-dqh synchronous data input/output dqpa-dqph parity data input/output gnd ground mode burst sequence mode selection oe output enable tck, tdi jtag boundary scan pins tdo, tms v cc +1.8v power supply v ccq i solated output buffer supply: 1.8v we write enable zz snooze enable pin configuration ? 256k x 72, 209-ball pbga (top view) 1234567891011 a dqg dqg a ce2 a adv a ce2 a dqb dqb b dqg dqg bw c bw gnc we a bw b bw f dqb dqb c dqg dqg bw h bw dnc ce nc bw e bw a dqb dqb d dqg dqg gnd nc nc oe nc nc gnd dqb dqb e dqpg dqpc v ccq v ccq v cc v cc v cc v ccq v ccq dqpf dqpb f dqc dqc gnd gnd gnd nc gnd gnd gnd dqf dqf g dqc dqc v ccq v ccq v cc nc v cc v ccq v ccq dqf dqf h dqc dqc gnd gnd gnd nc gnd gnd gnd dqf dqf j dqc dqc v ccq v ccq v cc nc v cc v ccq v ccq dqf dqf knc nc clk nc gnd cke gndncncncnc l dqh dqh v ccq v ccq vcc nc v cc v ccq v ccq dqa dqa m dqh dqh gnd gnd gnd nc gnd gnd gnd dqa dqa n dqh dqh v ccq v ccq vcc nc v cc v ccq v ccq dqa dqa p dqh dqh gnd gnd gnd zz gnd gnd gnd dqa dqa r dqpd dqph v ccq v ccq v cc v cc v cc v ccq v ccq dqpa dqpe t dqd dqd gnd nc nc mode nc nc gnd dqe dqe u dqd dqd nc a nc a nc a nc dqe dqe v dqd dqd a a a a1 a a a dqe dqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe 11 x 19 ball bga?14 x 22 mm 2 body?1 mm ball pitch
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? pin configuration 119-pin pbga (top view) 512k x 36 pin descriptions a synchronous address inputs a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. adv synchronous burst address advance bw a- bw h synchronous byte write enable ce , ce2 , ce2 synchronous chip enable clk synchronous clock cke clock enable dqa-dqd synchronous data input/output dqpa-dqpd parity data input/output gnd ground mode burst sequence mode selection oe output enable tck, tdi jtag boundary scan pins tdo, tms v cc 1.8v power supply v ccq i solated output buffer supply: 1.8v we write enable zz snooze enable a b c d e f g h j k l m n p r t u vccq nc nc dqc dqc vccq dqc dqc vccq dqd dqd vccq dqd dqd nc nc vccq a ce2 a dqpc dqc dqc dqc dqc vcc dqd dqd dqd dqd dqpd a nc tms a a a gnd gnd gnd bw c gnd nc gnd bw d gnd gnd gnd mode a tdi a adv vcc nc ce oe a we vcc clk nc cke a1 a0 vcc a tck a a a gnd gnd gnd bw b gnd nc gnd bw a gnd gnd gnd nc a tdo a ce2 a dqpb dqb dqb dqb dqb vcc dqa dqa dqa dqa dqpa a nc nc vccq nc nc dqb dqb vccq dqb dqb vccq dqa dqa vccq dqa dqa nc zz vccq 1 2 3 4 5 6 7
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? synchronous truth table (1) address operation used cs cs cs cs cs 1 cs2 cs cs cs cs cs 2 adv we we we we we bw bw bw bw bw x oe oe oe oe oe cke cke cke cke cke clk not selected continue n/a x x x h x x x l not selected n/a h x x l x x x l not selected n/a x l x l x x x l not selected n/a x x h l x x x l begin burst read external address l h l l h x l l continue burst read next address x x x h x x l l nop/dummy read external address l h l l h x h l dummy read next address x x x h x x h l begin burst write external address l h l l l l x l continue burst write next address x x x h x l x l nop/write abort n/a l h l l l h x l write abort next address x x x h x h x l ignore clock current address x x x x x x x h notes: 1. "x" means don't care. 2. the rising edge of clock is symbolized by 3. a continue deselect cycle can only be entered if a deselect cycle is executed first. 4. we = l means write operation in write truth table. we = h means read operation in write truth table. 5. operation finally depends on status of asynchronous pins (zz and oe ). state diagram burst read deselect burst write begin read begin write read write read write burst burst burst ds ds ds read ds ds read write write burst burst write read
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? asynchronous truth table (1) operation zz oe oe oe oe oe i/o status sleep mode h x high-z read ll dq l h high-z write l x din, high-z deselected l x high-z notes: 1. x means "don't care". 2. for write cycles following read cycles, the output buffers must be disabled with oe , otherwise data bus contention will occur. 3. sleep mode means power sleep mode where stand-by current does not depend on cycle time. 4. deselected means power sleep mode where stand-by current depends on cycle time. write truth table (x36) operation we we we we we bw bw bw bw bw a bw bw bw bw bw b bw bw bw bw bw c bw bw bw bw bw d read h x x x x write byte a l l h h h write byte b l h l h h write byte c l h h l h write byte d l h h h l write all bytes l l l l l write abort/nop l h h h h notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? interleaved burst address table (mode = v cc ) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 write truth table (x72) operation we we we we we bw bw bw bw bw a bw bw bw bw bw b bw bw bw bw bw c bw bw bw bw bw d bw bw bw bw bw e bw bw bw bw bw f bw bw bw bw bw g bw bw bw bw bw h read h x x x x x x x x write byte a l l h h h h h h h write byte b l h l h h h h h h write byte c l h h l h h h h h write byte d l h h h l h h h h write byte e l h h h h l h h h write byte f l h h h h h l h h write byte g l h h h h h h l h write byte h l h h h h h h h l write all bytes l l l l l l l l l write abort/nop l h h h h h h h h notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk. linear burst address table (mode = gnd) 0,0 1,0 0,1 a1', a0' = 1,1
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? operating range range ambient temperature v cc v ccq commercial 0c to +70c 1.8v 5% 1.8v 5% industrial -40c to +85c 1.8v 5% 1.8v 5% dc electrical characteristics (over operating range) 1.8v symbol param eter test conditions min. max. unit v oh output high voltage i oh = ?4.0 ma v ccq ?0.4 ? v v ol output low voltage i ol = 4.0 ma ? 0.4 v v ih input high voltage 1.1 v cc + 0.3 v v il input low voltage ?0.3 0.6 v i li input leakage current gnd v in v cc (1) ?5 5 a i lo output leakage current gnd v out v ccq , oe = v i ?10 10 a absolute maximum ratings (1) symbol parameter value unit t opr operating temperature com ?0 to +70 c ind -40 to +85 t stg storage temperature ?65 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ?0.5 to v ccq + 0.3 v v in voltage relative to gnd for ?0.5 to v ccq + 0.3 v for address and control inputs notes: 1. stress greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi- cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? power supply characteristics (1) (over operating range) -250 -200 max max symbol param eter test conditions x36 x72 x36 x72 uni t i cc ac operating device selected, com. 450 500 400 450 ma supply current oe = v ih , zz v il ,i nd . 500 550 450 500 all inputs 0.2v or v cc ? 0.2v, cycle time t kc min. i sb standby current device deselected, c om . 225 250 175 200 ma ttl input v cc = max., ind. ? ? 200 230 all inputs 0.2v or v cc ? 0.2v, zz v il , f = max. i sbi standby current device deselected, com. 150 150 150 150 ma cmos input v cc = max., ind. ? ? 200 200 v in gnd + 0.2v or v cc ? 0.2v f = 0 note: 1. mode pin has an internal pullup and should be tied to vcc or gnd. it exhibits 30 a maximum leakage current when tied to gnd + 0.2v or vcc ? 0.2v. capacitance (1,2) symbol parameter conditi ons max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, vcc = 3.3v.
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? 1.8v i/o ac test conditions parameter unit input pulse level 0.4v to 1.4v input rise and fall times 2v/ ns input and output timing 0.9v and reference level output load see figures 1 and 2 figure 1 figure 2 1.8v i/o output load equivalent z o = 50 ? 0.9v 50 ? output 317 ? 5 pf including jig and scope 351 ? output +1.8v
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? read/write cycle switching characteristics (1) (over operating range) -250 -200 symbol parameter min. max. min. max. unit fmax clock frequency ? 250 ? 200 mhz t kc cycle time 4.0 ? 5 ? ns t kh clock high time 1.7 ? 2 ? ns t kl clock low time 1.7 ? 2 ? ns t kq clock access time ? 2.6 ? 3.0 ns t kqx (2) clock high to output invalid 0.8 ? 1.5 ? ns t kqlz (2,3) clock high to output low-z 0.8 ? 1 ? ns t kqhz (2,3) clock high to output high-z ? 2.6 ? 3.0 ns t oeq output enable to output valid ? 2.6 ? 3.0 ns t oelz (2,3) output enable to output low-z 0 ? 0 ? ns t oehz (2,3) output disable to output high-z ? 2.6 ? 3.0 ns t as address setup time 1.0 ? 1.2 ? ns t ws read/write setup time 1.0 ? 1.2 ? ns t ces chip enable setup time 1.0 ? 1.2 ? ns t se clock enable setup time 1.0 ? 1.2 ? ns t advs address advance setup time 1.0 ? 1.2 ? ns t ds data setup time 1.0 ? 1.2 ? ns t ah address hold time 0.5 ? 0.5 ? ns t he clock enablehold time 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? ns t advh address advance hold time 0.5 ? 0.5 ? ns t dh data hold time 0.5 ? 0.5 ? ns t pds zz high to power down ? 2 ? 2 cyc t pus zz low to power down ? 2 ? 2 cyc notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? sleep mode timing sleep mode electrical characteristics symbol parameter conditions min. max. unit i sb 2 current during sleep mode zz vih 150 ma t pds zz active to input ignored zz vih 2 cycle t pus zz inactive to input sampled zz vil 2 cycle t zzi zz active to sleep current zz vih 2 cycle t rzzi zz inactive to exit sleep current zz vil 0 ns don't care deselect or read only deselect or read only t rzzi k zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? read cycle timing t ds clock adv address we cke ce oe data out a1 a2 a3 t kh t kl t kc q3-3 q3-4 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 don't care undefined notes: we = h and bw x = h ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l t oehz t se t he t as t ah t ws t wh t ces t ceh t advs t advh t kqhz t kq t oeq t oehz q1-1
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? write cycle timing t ds t dh clock adv address we cke ce oe data in data out a1 a2 a3 t kh t kl t kc t se t he d3-3 d3-4 d3-2 d3-1 d2-4 d2-3 d2-2 d2-1 d1-1 don't care undefined notes: we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l t oehz q0-3 q0-4
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? single read/write cycle timing clock cke address write cs adv oe data out data in d5 t se t he t kh t kl t kc don't care undefined notes: write = l means we = l and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l and cs 2 = l d2 t oelz t oeq a1 a2 a3 a4 a5 a6 a7 a8 a9 q1 q3 q4 q6 q7 t ds t dh
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? cke cke cke cke cke operation timing a1 a2 a3 a4 a5 a6 q1 q3 q4 clock cke address write cs adv oe data out data in d2 t se t he t kh t kl t kc t kqlz t kqhz t kq t dh t ds don't care undefined notes: write = l means we = l and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l and cs 2 = l
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? cs cs cs cs cs operation timing don't care undefined clock cke address write cs adv oe data out data in t se t he t kh t kl t kc notes: write = l means we = l and bw x = l cs = l means cs 1 = l, cs 2 = h and cs 2 = l cs = h means cs 1 = h, or cs 1 = l and cs 2 = h, or cs 1 = l and cs 2 = l d5 d3 t dh t ds t oelz t oeq q1 q2 q4 t kqhz t kqlz t kq a1 a2 a3 a4 a5
18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? ieee 1149.1 serial boundary scan (jtag) the is61nvvp51236 and is61nvvp25672 have a serial boundary scan test access port (tap) in the pbga package only. this port operates in accordance with ieee standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because they place added delay in the critical speed path of the sram. the tap controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 1.8v i/o logic levels. disabling the jtag feature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (gnd) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be disconnected. they may alternately be connected to v cc through a pull-up resistor. tdo should be left disconnected. on power-up, the device will start in a reset state which will not interfere with the device operation. test access port (tap) - test clock the test clock is only used with the tap controller. all inputs are captured on the rising edge of tck and outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. this pin may be left disconnected if the tap is not used. the pin is internally pulled up, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information to the registers and can be connected to the input of any register. the register between tdi and tdo is chosen by the instruction loaded into the tap instruction register. for information on instruction register loading, see the tap controller state diagram. tdi is internally pulled up and can be disconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. tap controller block diagram 31 30 29 . . . 2 1 0 2 1 0 0 x . . . . . 2 1 0 bypass register instruction register identification register boundary scan register* tap controller selection circuitry selection circuitry tdo tdi tck tms
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending on the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck and tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v cc ) for five rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power-up, the tap is internally reset to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry . only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins. (see tap controller block diagram) at power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as previously described. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (gnd) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all input and output pins on the sram . several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 configuration has a 84-bit-long register and the x72 configuration has a 123-bit-long reg- ister. the boundary scan register is loaded with the con- tents of the ram input and output ring when the tap controller is in the capture-dr state and then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded to the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has vendor code and other information described in the identification register definitions table. scan register sizes register name bit size (x36) bit size (x72) instruction 3 3 bypass 1 1 id 32 32 boundary scan 84 123
20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register contents die i/o issi technology revision not used configuration jedec vendor code id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x72 xxxx00 00 00 000 00 011 00 0001 1 010 10 1 1 x36 xxxx00000000000010 0000011010101 1
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? tap instruction set eight instructions are possible with the three-bit instruction register and all combinations are listed in the instruction code table. three instructions are listed as reserved and should not be used and the other five instructions are described below. the tap controller used in this sram is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. the tap controller cannot be used to load address, data or control signals and cannot preload the input or output buffers. the sram does not implement the 1149.1 com- mands extest or intest or the preload portion of sample/preload ; instead it performs a capture of the inputs and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted from the instruction register through the tdi and tdo pins. to execute an instruction once it is shifted in, the tap controller must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. because extest is not implemented in the tap controller, this device is not 1149.1 standard compliant. the tap controller recognizes an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is a difference between the instructions, unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not imple- mented, so the tap controller is not fully 1149.1 compli- ant. when the sample/preload instruction is loaded to the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. it is important to realize that the tap controller clock operates at a frequency up to 10 mhz, while the sram clock runs more than an order of magnitude faster. because of the clock frequency differences, it is possible that during the capture-dr state, an input or output will under-go a transition. the tap may attempt a signal capture while in transition (metastable state). the device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. to guarantee that the boundary scan register will capture the correct signal value, the sram signal must be stabilized long enough to meet the tap controller?s capture set-up plus hold times (t cs and t ch ). to insure that the sram clock input is captured correctly, designs need a way to stop (or slow) the clock during a sample/ preload instruction. if this is not an issue, it is possible to capture all other signals and simply ignore the value of the clk and clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? tap electrical characteristics over the operating range (1,2) symbol parameter test conditions min. max. units v oh1 output high voltage i oh = ?100 a vcc ?0.1 ? v v oh2 output high voltage i oh = ?8 ma vcc ?0.4 ? v v ol1 output low voltage i ol = 100 a ? 0.1 v v ol2 output low voltage i ol = 8 ma ? 0.4 v v ih input high voltage 1.2 v cc +0.3 v v il input low voltage i olt = 2ma ?0.3 0.6 v i x input leakage current gnd v i v ddq ?10 10 a notes: 1. all voltage referenced to ground. 2. overshoot: v ih (ac) v dd +1.5v for t t tcyc /2, undershoot:v il (ac) 0.5v for t t tcyc /2, power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ms. jtag tap instruction set summary instruction code description extest (1) 000 places the boundary scan register between tdi and tdo. when extest is selected, data will be driven out of the dq pad. idcode (1,2) 001 preloads id register and places it between tdi and tdo. sample-z (1) 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all data and clock output drivers to high-z. rfu (1) 011 do not use this instruction; reserved for future use. replicates bypass instruc- tion. places bypass register between tdi and tdo. sample/preload (1) 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. private (1) 101 private instruction. rfu (1) 110 do not use this instruction; reserved for future use. bypass (1) 111 places bypass register between tdi and tdo. notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? tap ac electrical characteristics (1) (over operating range) symbol parameter min. max. unit t tcyc tck clock cycle time 100 ? ns f tf tck clock frequency ? 10 mhz t th tck clock high 40 ? ns t tl tck clock low 40 ? ns t tmss tms setup to tck clock rise 10 ? ns t tdis tdi setup to tck clock rise 10 ? ns t cs capture setup to tck rise 10 ? ns t tmsh tms hold after tck clock rise 10 ? ns t tdih tdi hold after clock rise 10 ? ns t ch capture hold after clock rise 10 ? ns t tdov tck low to tdo valid ? 20 ns t tdox tck low to tdo invalid 0 ? ns notes: 7. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 8. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. tap controller state diagram select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test/idle 11 1 11 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 10
24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? tap timing tap output load equivalent tap ac test conditions input pulse levels 0.2 to 1.6v input rise and fall times 1ns input timing reference levels 0.9v output reference levels 0.9v test load termination supply voltage 0.9v 20 pf tdo gnd 50 ? 0.9v z 0 = 50 ? don't care undefined tck tms tdi tdo t thtl t tlth t thth t mvth t thmx t dvth t thdx 1 2 3 4 5 6 t tlox t tlov
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? boundary scan order assignments (by exit sequence) ph =place holder x72 x36 sequence pkg. ball ball location sequence pkg. ball ball location 1a0w6 1a0 2av7 2a 3av8 3a 4au8 4a 5av9 5a 6au6 6a 7ph (1) u5 7 ph (1) 8aw7 8a 9ph (1) u7 9 ph (1) 10 mode t6 10 mode 11 nc (2) m6 11 nc (2) 12 nc (2) j6 12 nc (2) 13 cke k6 13 cke 14 oe d6 14 oe 15 ph (1) c7 15 ph (1) 16 be c8 17 ba c9 16 ba 18 bb b8 17 bb 19 bf b9 20 w b6 18 w 21 adv a6 19 adv 22 a b7 20 a 23 ce2 a8 21 ce2 24 a a9 22 a 25 nc (2) f6 23 nc 26 a a3 24 a 27 ce2 a4 25 ce2 28 a a5 26 a 29 a a7 27 a b5 28 a 30 bc b3 29 bc 31 bg b4 32 bh c3 33 bd c4 30 bd 34 ph (1) c5 31 ph (1) 35 ce c6 32 ce 36 nc (2) g6 33 nc notes: 1.input of ph register connected to vss 2. nc = don't care
26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? boundary scan order assignments (by exit sequence) continued: x72 x36 sequence pkg. ball ball location sequence pkg. ball ball location 37 nc (2) h6 34 nc (2) 38 ck k3 35 ck 39 nc (2) l6 36 nc (2) 40 nc (2) n6 37 nc (2) 41 zz p6 38 zz 42 a v3 39 a 43 a u4 40 a 44 a v4 41 a 45 a v5 42 a 46 a w5 43 a 47 a v6 44 a1 48 dqd w2 45 dqd 49 dqd w1 46 dqd 50 dqd v2 47 dqd 51 dqd v1 48 dqd 52 dqd u2 49 dqd 53 dqd u1 50 dqd 54 dqd t2 51 dqd 55 dqd t1 52 dqd 56 dqpd r1 53 dqpd 57 dqph r2 58 dqh p2 59 dqh p1 60 dqh n2 61 dqh n1 62 dqh m2 63 dqh m1 64 dqh l2 65 dqh l1 66 nc (2) k2 54 nc (2) 67 nc (2) k1 55 nc (2) 68 dqc j2 56 dqc 69 dqc j1 57 dqc 70 dqc h2 58 dqc 71 dqc h1 59 dqc 72 dqc g2 60 dqc 73 dqc g1 61 dqc notes: 1.input of ph register connected to vss 2. nc = don't care
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 27 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? boundary scan order assignments (by exit sequence) continued: x72 x36 sequence pkg. ball ball location sequence pkg. ball ball location 74 dqc f2 62 dqc 75 dqc f1 63 dqc 76 dqpc e2 64 dqpc 77 dqpg e1 78 dqg d2 79 dqg d1 80 dqg c2 81 dqg c1 82 dqg b2 83 dqg b1 84 dqg a2 85 dqg a1 86 dqb a10 65 dqb 87 dqb a11 66 dqb 88 dqb b10 67 dqb 89 dqb b11 68 dqb 90 dqb c10 69 dqb 91 dqb c11 70 dqb 92 dqb d10 71 dqb 93 dqb d11 72 dqb 94 dqpb e11 73 dqpb 95 dqpf e10 96 dqf f10 97 dqf f11 98 dqf g10 99 dqf g11 100 dqf h10 101 dqf h11 102 dqf j10 103 dqf j11 104 nc (2) k11 74 nc (2) 105 nc (2) k10 75 nc (2) 106 dqa l10 76 dqa 107 dqa l11 77 dqa 108 dqa m10 78 dqa 109 dqa m11 79 dqa 110 dqa n10 80 dqa notes: 1.input of ph register connected to vss 2. nc = don't care
28 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? boundary scan order assignments (by exit sequence) continued: x72 x36 sequence pkg. ball ball location sequence pkg. ball ball location 111 dqa n11 81 dqa 112 dqa p10 82 dqa 113 dqa8 p11 83 dqa8 114 dqpa9 r10 84 dqpa9 115 dqpe r11 116 dqe t10 117 dqe t11 118 dqe u10 119 dqe u11 120 dqe v10 121 dqe v11 122 dqe w10 123 dqe w11 notes: 1.input of ph register connected to vss 2. nc = don't care
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 29 advanced information rev. 00a 07/17/02 is61nvvp25672 is61nvvp51236 issi ? ordering information commercial range: 0c to +70c frequency order part number package 256kx72 250 is61nvvp25672-250b pbga 200 is61nvvp25672-200b pbga 512kx36 250 is61nvvp51236-250b pbga 200 is61nvvp51236-200b pbga industrial range: -40c to +85c frequency order part number package 256kx72 250 is61nvvp25672-250bi pbga 200 is61nvvp25672-200bi pbga 512kx36 250 is61nvvp51236-250bi pbga 200 IS61NVVP51236-200BI pbga

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