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6/9/03 preliminary powerpc 405ep embedded processor data sheet page 1 of 52 features ? ibm powerpc ? 405 32-bit risc processor core operating up to 333mhz with 16kb d- and i- caches ? pc-133 synchronous dram (sdram) interface - 32-bit interface for non-ecc applications ? 4kb on-chip memory (ocm) ? external peripheral bus - flash rom/boot rom interface - direct support for 8- or 16-bit sram and external peripherals - up to five devices ? dma support for memory and uarts. - scatter-gather chaining supported - four channels ? pci revision 2.2 compliant interface (32-bit, up to 66mhz) - asynchronous pci bus interface - internal or external pci bus arbiter ? two ethernet 10/100mbps (full-duplex) ports with media independent interface (mii) ? programmable interrupt controller supports seven external and 19 internal edge-triggered or level-sensitive interrupts ? programmable timers ? software accessible event counters ? two serial ports (16750 compatible uart) ? one iic interface ? general purpose i/o (gpio) available ? supports jtag for board level testing ? internal processor local bus (plb) runs at sdram interface frequency ? supports powerpc processor boot from pci memory description designed specifically to address embedded applications, the powerpc 405ep (ppc405ep) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. this chip contains a high-performance risc processor core, sdram controller, pci bus interface, ethernet interface, control for external rom and peripherals, dma with scatter-gather support, serial ports, iic interface, and general purpose i/o. technology: ibm cmos sa-27e, 0.18 m (0.11 m l eff ) package: 31mm, 385-ball, enhanced plastic ball grid array (e-pbga) power (typical): 1.2w at 200mhz while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
preliminary powerpc 405ep embedded processor data sheet page 2 of 52 6/9/03 contents ordering, pvr, and jtag information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 address map support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 on-chip memory (ocm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 plb to pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10/100 mbps ethernet mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 tables system memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dcr address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 clocking specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 i/o specificationsgroup 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 i/o specificationsgroup 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 3 of 52 figures ppc405ep embedded controller functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 31mm, 385-ball e-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5v-tolerant input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 input setup and hold timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
preliminary powerpc 405ep embedded processor data sheet page 4 of 52 6/9/03 ordering, pvr, and jtag information this section provides the part number nomenclature. for availability, contact your local ibm sales office. the part number contains a part modifier. included in the modifier is a revision code. this refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. the pvr (processor version register) and the jtag id register are software accessible (read-only) and contain information that uniquely identifies the part. refer to the powerpc 405ep embedded processor users manual for details on accessing these registers. order part number key product name order part number 1 processor frequency package rev level pvr value jtag id ppc405ep ibm25ppc405ep-3gb133c 133mhz 31mm, 385 e-pbga b 0x51210950 0x20267049 ppc405ep ibm25ppc405ep-3gb133cz 133mhz 31mm, 385 e-pbga b 0x51210950 0x20267049 ppc405ep IBM25PPC405EP-3GB200C 200mhz 31mm, 385 e-pbga b 0x51210950 0x20267049 ppc405ep IBM25PPC405EP-3GB200Cz 200mhz 31mm, 385 e-pbga b 0x51210950 0x20267049 ppc405ep ibm25ppc405ep-3gb266c 266mhz 31mm, 385 e-pbga b 0x51210950 0x20267049 ppc405ep ibm25ppc405ep-3gb266cz 266mhz 31mm, 385 e-pbga b 0x51210950 0x20267049 ppc405ep ibm25ppc405ep-3gb333c 333mhz 31mm, 385 e-pbga b 0x51210950 0x20267049 ppc405ep ibm25ppc405ep-3gb333cz 333mhz 31mm, 385 e-pbga b 0x51210950 0x20267049 note 1: z at the end of the order part number indicates a tape and reel shipping package. otherwise, the chips are shipped in a tray. ibm part number ibm25ppc405ep-3gb333cx package processor speed grade 3 reliability operational case temperature shipping package blank = tray z = tape and reel (-40c to +85c) range 266 = 266mhz 31mm, 385 e-pbga 200 = 200mhz revision level 333 = 333mhz 133 = 133mhz
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 5 of 52 ppc405ep embedded controller functional block diagram the ppc405ep is designed using the ibm microelectronics blue logic tm methodology in which major functional blocks are integrated together to create an application-specific asic product. this approach provides a consistent way to create complex asics using ibm coreconnect tm bus architecture. ppc405 processor core docm iocm dcu icu ocm control ocm sram dcr bus 16kb on-chip peripheral bus (opb) gpio iic gpt uart mal ethernet dma bridge processor local bus (plb) sdram pci bridge external bus controller controller clock control reset power mgmt jtag trace timers mmu mii controller opb interrupt controller arb 29-bit addr 16-bit data 13-bit addr 32-bit data universal i-cache d-cache (4-channel) 66 mhz max (async) dcrs 16kb arb x2 x2 event counters
preliminary powerpc 405ep embedded processor data sheet page 6 of 52 6/9/03 address map support the ppc405ep incorporates two address maps. the first address map defines the possible use of addressable memory regions that the processor can access. the second address map defines device configuration register (dcr) addresses (numbers). the dcrs are accessed by software running on the ppc405ep processor through the use of mtdcr and mfdcr instructions. system memory address map 4gb system memory function subfunction start address end address size general use sdram, external peripherals, and pci memory note: any of the address ranges listed at right may be use for any of the above functions. 0x00000000 0xe7ffffff 3712mb 0xe8010000 0xe87fffff 8mb 0xec000000 0xeebfffff 44mb 0xeee00000 0xef3fffff 6mb 0xef500000 0xef5fffff 1mb 0xef900000 0xffffffff 263mb boot-up peripheral bus boot 1 0xffe00000 0xffffffff 2mb pci boot 2 0xfffe0000 0xffffffff 128kb pci pci i/o 0xe8000000 0xe800ffff 64kb pci i/o 0xe8800000 0xebffffff 56mb configuration registers 0xeec00000 0xeec00007 8b interrupt acknowledge and special cycle 0xeed00000 0xeed00003 4b local configuration registers 0xef400000 0xef40003f 64b internal peripherals uart0 0xef600300 0xef600307 8b uart1 0xef600400 0xef600407 8b iic0 0xef600500 0xef60051f 32b opb arbiter 0xef600600 0xef60063f 64b gpio controller registers 0xef600700 0xef60077f 128b ethernet 0 controller registers 0xef600800 0xef6008ff 256b ethernet 1 controller registers 0xef600900 0xef6009ff 256b notes: 1. when peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed abov e. 2. if pci boot is selected, a plb-to-pci mapping is automatically configured at reset to the address range listed above. 3. after the boot process, software may reassign the boot memory regions for other uses. 4. all address ranges not listed above are reserved.
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 7 of 52 dcr address map 4kb device configuration registers function start address end address size total dcr address space 1 0x000 0x3ff 1kw (4kb) 1 by function: reserved 0x000 0x00f 16w memory controller registers 0x010 0x011 2w external bus controller registers 0x012 0x013 2w reserved 0x014 0x017 2w on-chip memory controller registers 0x018 0x01f 8w reserved 0x020 0x07f 96w plb registers 0x080 0x08f 16w reserved 0x090 0x09f 16w opb bridge out registers 0x0a0 0x0a7 8w reserved 0x0a8 0x0af 6w clock, control, and reset 0x0b0 0x0b7 8w power management 0x0b8 0x0bf 8w interrupt controller 0x0c0 0x0cf 16w reserved 0x0d0 0x0ff 48w dma controller registers 0x100 0x13f 64w reserved 0x140 0x17f 64w ethernet mal registers 0x180 0x1ff 128w event counters0x200 0x203 4w reserved 0x204 0x3ff 508w notes: 1. dcr address space is addressable with up to 10 bits (1024 or 1k unique addresses). each unique address represents a single 32-bit (word) register, or 1 kiloword (kw) (which equals 4 kb).
preliminary powerpc 405ep embedded processor data sheet page 8 of 52 6/9/03 on-chip memory (ocm) the ocm feature comprises a memory controller and a one-port 4kb static ram (sram) accessed by the processor core. features include: ? low-latency access to critical instructions and data ? performance identical to cache hits without misses ? contents change only under program control plb to pci interface the plb to pci interface core provides a mechanism for connecting pci devices to the local powerpc processor and local memory. this interface is compliant with version 2.2 of the pci specification. features include: ? internal pci bus arbiter for up to six external devices at pci bus speeds up to 66mhz. internal arbiter use is optional and can be disabled for systems which employ an external arbiter. ? pci bus frequency up to 66mhz - asynchronous operation from 1/8 plb frequency to 66mhz maximum ? 32-bit pci address/data bus ? power management: - pci bus power management v1.1 compliant ? supports 1:1, 2:1, 3:1, 4:1 clock ratios from plb to pci ? buffering between plb and pci: - pci target 64-byte write post buffer - pci target 96-byte read prefetch buffer - plb slave 32-byte write post buffer - plb slave 64-byte read prefetch buffer ? error tracking/status ? supports pci target side configuration ? supports processor access to all pci address spaces: - single-byte pci i/o reads and writes - pci memory single-beat and prefetch-burst reads and single-beat writes - single-byte pci configuration reads and writes (type 0 and type 1) - pci interrupt acknowledge
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 9 of 52 - pci special cycle ? supports pci target access to all plb address spaces ? supports powerpc processor boot from pci memory sdram memory controller the ppc405ep memory controller core provides a low latency access path to sdram memory. a variety of system memory configurations are supported. the memory controller supports up to two physical banks. up to 256mb per bank are supported, up to a maximum of 512mb. memory timings, address and bank sizes, and memory addressing modes are programmable. features include: ? 11x8 to 13x11 addressing for sdram (2 banks) ? 32-bit memory interface support ? programmable address compare for each bank of memory ? industry standard 168-pin dimms are supported (some configurations) ? up to 133mhz memory supported by 266mhz processor ? 4mb to 256mb per bank ? programmable address mapping and timing ? auto refresh ? page mode accesses with up to 4 open pages ? power management (self-refresh) external peripheral bus controller (ebc) ? supports five banks of rom, eprom, sram, flash memory, or slave peripherals ? up to 66mhz operation ? burst and non-burst devices ? 8- and 16-bit byte-addressable data bus width support ? latch data on ready, synchronous or asynchronous ? programmable 2k clock time-out counter with disable for ready ? programmable access timing per device - 0C255 wait states for non-bursting devices - 0C31 burst wait states for first access and up to 7 wait states for subsequent accesses - programmable cson, csoff relative to address
preliminary powerpc 405ep embedded processor data sheet page 10 of 52 6/9/03 - programmable oeon, weon, weoff (0 to 3 clock cycles) relative to cs ? programmable address mapping ? peripheral device pacing with external ready dma controller ? supports memory-to-memory transfers ? four channels ? scatter/gather capability for programming multiple dma operations ? 32-bit addressing ? address increment or decrement ? internal 32-byte data buffering capability serial interface ? one 8-pin uart and one 2-pin (tx and rx only) uart interface provided ? internal serial clock to allows a wide range of baud rates ? register compatibility with ns16750 register set ? complete status reporting capability ? transmitter and receiver are each buffered with 16-byte fifos when in fifo mode ? fully programmable serial-interface characteristics ? supports dma using internal dma engine iic bus interface ? compliant with phillips? semiconductors i 2 c specification, dated 1995 ? operation at 100khz or 400khz ? 8-bit data ? 10- or 7-bit address ? slave transmitter and receiver ? master transmitter and receiver ? multiple bus masters ? supports fixed v dd iic interface ? two independent 4 x 1 byte data buffers
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 11 of 52 ? twelve memory-mapped, fully programmable configuration registers ? one programmable interrupt request signal ? provides full management of all iic bus protocol ? programmable error recovery general purpose io (gpio) controller ? controller functions and gpio registers are programmed and accessed via memory-mapped opb bus master accesses ? all gpios are pin-shared with other functions. dcrs control whether a particular pin that has gpio capabilities acts as a gpio or is used for another purpose. ? each gpio output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three- stated if output bit is 1) universal interrupt controller (uic) the universal interrupt controller (uic) provides the control, status, and communications necessary between the various sources of interrupts and the local powerpc processor. features include: ? supports seven external and 19 internal interrupts ? edge-triggered or level-sensitive ? positive or negative active ? non-critical or critical interrupt to processor core ? programmable critical interrupt priority ordering ? programmable critical interrupt vector for faster vector processing 10/100 mbps ethernet mac ? two ports capable of handling full/half duplex 100mbps and 10mbps operation ? uses the medium independent interface (mii) to the physical layer (phy not included on chip) jtag ? ieee 1149.1 test access port ? ibm riscwatch debugger support ? jtag boundary scan description language (bsdl)
preliminary powerpc 405ep embedded processor data sheet page 12 of 52 6/9/03 31mm, 385-ball e-pbga package a s 1.27 typ 0.65 0.05 solderball x 385 31.0 0.2 27.98 31.0 b a c 0.20 ? 0.30 ? 0.15 s c a b s s 15.5 typ gold gate release corresponds to 0.20 c c 2.49 ref 0.6 0.1 pcb substrate mold compound b c d e f g h j k l m aa n p r t u v w y ab ac thermal balls a1 ball location 135 7 911131517 19 2 4 6 810 12 14 16 18 21 23 20 22 top view bottom view 0.25 0.35 c c note: all dimensions are in mm. 2.65 max
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 13 of 52 pin lists the ppc405ep embedded controller is available in a 31 millimeter, 385-ball e-pbga package. the following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. multiplexed signals appear alphabetically multiple times in the listonce for each signal name on the ball. the page number listed gives the page in signal functional description on page 33 where the signals in the indicated interface group begin. signals listed alphabetically (part 1 of 12) signal name ball interface group page agnd ab21 system 37 av dd ac20 ba0 y15 sdram 35 ba1 ac16 banksel0 ab13 sdram 35 banksel1 ac13 cas y14 sdram 35 clken0 ab14 sdram 35 clken1 ac14 dqm0 ac10 sdram 35 dqm1 aa7 dqm2 w04 dqm3 u02 emcmdclk y06 ethernet 34 emcmdio aa5 ethernet 34 emc0tx0d0 u03 ethernet 34 emc0tx0d1 n03 emc0tx0d2 l01 emc0tx0d3 p03 emc0tx0en w01 ethernet 34 emc0tx0err v03 ethernet 34 emc0tx1d0 b15 ethernet 34 emc0tx1d1 c14 emc0tx1d2 a15 emc0tx1d3 d14 emc0tx1en a16 ethernet 34 emc0tx1err c15 ethernet 34 extreset a03 external slave peripheral 35
preliminary powerpc 405ep embedded processor data sheet page 14 of 52 6/9/03 gnd a01 ground note: k10-k14, l10-l14, m10-m14, n10-n14, and p10-p14 are also thermal balls. 38 gnd a02 gnd a07 gnd a12 gnd a17 gnd a22 gnd a23 gnd b01 gnd b02 gnd b22 gnd b23 gnd c03 gnd c21 gnd d04 gnd d20 gnd e05 gnd e09 gnd e12 gnd e15 gnd e19 gnd g01 gnd g23 gnd j05 gnd j19 gnd k10-k14 gnd l10-l14 signals listed alphabetically (part 2 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 15 of 52 gnd m01 power note: k10-k14, l10-l14, m10-m14, n10-n14, and p10-p14 are also thermal balls. 38 gnd m05 gnd m10-m14 gnd m19 gnd m20 gnd m23 gnd n10-n14 gnd p10-p14 gnd r05 gnd r19 gnd u01 gnd u23 gnd w05 gnd w09 gnd w12 gnd w15 gnd w19 gnd y04 gnd y20 gnd aa03 gnd aa21 gnd ab01 gnd ab02 gnd ab22 gnd ab23 gnd ac01 gnd ac02 gnd ac07 gnd ac12 gnd ac17 gnd ac22 gnd ac23 signals listed alphabetically (part 3 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet page 16 of 52 6/9/03 gpio00[perblast ]a09 system 37 gpio01[ts1e] aa23 gpio02[ts2e] y22 gpio03[ts1o] y23 gpio04[ts2o] w21 gpio05[ts3] u20 gpio06[ts4] v23 gpio07[ts5] u21 gpio08[ts6] u22 gpio09[trcclk] t21 gpio10[percs1 ]c02 gpio11[percs2 ]e03 gpio12[percs3 ]d03 gpio13[percs4 ]d05 gpio14[peraddr03] b04 gpio15[peraddr04] a04 gpio16[peraddr05] a05 gpio17[irq0] w22 gpio18[irq1] w23 gpio19[irq2] v21 gpio20[irq3] v22 gpio21[irq4] t22 gpio22[irq5] r20 gpio23[irq6] t23 gpio24[uart0_dcd ]m04 gpio25[uart0_dsr ]k01 gpio26[uart0_ri ] l04 gpio27[uart0_dtr ]j01 gpio28[uart1_rx] j02 gpio29[uart1_tx] j03 gpio30[rejectpkt0] w20 gpio31[rejectpkt1] y21 halt c22 system 37 iicscl ab4 internal peripheral 36 iicsda y01 [irq0]gpio17 w22 interrupts 36 [irq1]gpio18 w23 [irq2]gpio19 v21 [irq3]gpio20 v22 [irq4]gpio21 t22 [irq5]gpio22 r20 [irq6]gpio23 t23 signals listed alphabetically (part 4 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 17 of 52 memaddr00 ab15 sdram note: during a cas cycle memaddr00 is the least significant bit (lsb) on this bus. 35 memaddr01 ab16 memaddr02 ab17 memaddr03 aa17 memaddr04 ac18 memaddr05 aa18 memaddr06 ac19 memaddr07 ab19 memaddr08 y18 memaddr09 aa19 memaddr10 y19 memaddr11 aa20 memaddr12 ac21 memclkout0 aa14 sdram 35 memclkout1 y13 signals listed alphabetically (part 5 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet page 18 of 52 6/9/03 memdata00 ab12 sdram note: memdata00 is the most significant bit (msb) on this bus. 35 memdata01 aa12 memdata02 ac11 memdata03 aa11 memdata04 y11 memdata05 aa10 memdata06 ac9 memdata07 ab9 memdata08 ac8 memdata09 y09 memdata10 aa8 memdata11 ab7 memdata12 ab6 memdata13 y07 memdata14 aa6 memdata15 ac5 memdata16 ab5 memdata17 ac4 memdata18 y05 memdata19 aa4 memdata20 ab3 memdata21 y03 memdata22 w03 memdata23 v04 memdata24 w02 memdata25 u04 memdata26 v02 memdata27 t04 memdata28 t02 memdata29 r04 memdata30 r03 memdata31 r02 ov dd b11 power 38 ov dd b09 ov dd b19 ov dd c17 ov dd d13 ov dd e06 ov dd e07 ov dd e08 signals listed alphabetically (part 6 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 19 of 52 ov dd e16 power 38 ov dd e17 ov dd e18 ov dd e21 ov dd f05 ov dd f19 ov dd f23 ov dd g05 ov dd g19 ov dd h05 ov dd h19 ov dd h22 ov dd k04 ov dd k20 ov dd k23 ov dd m22 ov dd n01 ov dd p20 ov dd p23 ov dd t05 ov dd t19 ov dd t20 ov dd u05 ov dd u19 ov dd v01 ov dd v05 ov dd v19 ov dd w06 ov dd w07 ov dd w08 ov dd w16 ov dd w17 ov dd w18 ov dd y12 ov dd ac06 signals listed alphabetically (part 7 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet page 20 of 52 6/9/03 pciad00 b16 pci note : pciad31 is the most significant bit (msb) on this bus. 33 pciad01 c16 pciad02 b17 pciad03 d16 pciad04 b18 pciad05 d17 pciad06 c18 pciad07 a19 pciad08 d18 pciad09 c19 pciad10 a20 pciad11 b20 pciad12 c20 pciad13 c23 pciad14 d21 pciad15 d22 pciad16 j22 pciad17 j23 pciad18 k21 pciad19 k22 pciad20 l21 pciad21 l22 pciad22 l23 pciad23 m21 pciad24 n23 pciad25 n22 pciad26 n21 pciad27 p22 pciad28 p21 pciad29 r23 pciad30 r22 pciad31 r21 pcic0/be0 a18 pci 33 pcic1/be1 d19 pcic2/be2 l20 pcic3/be3 n20 pciclk b21 pci 33 pcidevsel h21 pci 33 pciframe f22 pci 33 pcignt0 /req d23 pci 33 pcignt1 e23 pci 33 pcignt2 f21 pciidsel a21 pci 33 signals listed alphabetically (part 8 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 21 of 52 pciint [perwe ]d15pci 33 pciirdy h20 pci 33 pciparity j21 pci 33 pciperr h23 pci 33 pcireq0 /gnt e20 pci 33 pcireq1 f20 pcireq2 e22 pcireset g20 pci 33 pciserr j20 pci 33 pcistop g22 pci 33 pcitrdy g21 pci 33 [peraddr03]gpio14 b04 external slave peripheral note: peraddr3 is the most significant bit (msb) on this bus. 35 [peraddr04]gpio15 a04 [peraddr05]gpio16 a05 peraddr06 d07 peraddr07 b06 peraddr08 a06 peraddr09 d08 peraddr10 c07 peraddr11 b07 peraddr12 c08 peraddr13 b08 peraddr14 d09 peraddr15 a08 peraddr16 c09 peraddr17 d10 peraddr18 c10 peraddr19 b10 peraddr20 d11 peraddr21 a10 peraddr22 c11 peraddr23 a11 peraddr24 d12 peraddr25 b12 peraddr26 c12 peraddr27 a13 peraddr28 b13 peraddr29 c13 peraddr30 a14 peraddr31 b14 [perblast ]gpio00 a09 external slave peripheral 35 perclk c04 external slave peripheral 35 signals listed alphabetically (part 9 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet page 22 of 52 6/9/03 percs0 e04 external slave peripheral 35 [percs1 ]gpio10 c02 [percs2 ]gpio11 e03 [percs3 ]gpio12 d03 [percs4] gpio13 d05 perdata00 p02 external slave peripheral note: perdata00 is the most significant bit (msb) on this bus. 35 perdata01 n04 perdata02 p01 perdata03 m02 perdata04 m03 perdata05 l02 perdata06 l03 perdata07 k02 perdata08 k03 perdata09 h01 perdata10 j04 perdata11 g02 perdata12 g04 perdata13 h04 perdata14 f01 perdata15 d01 peroe f04 external slave peripheral 35 perready b03 external slave peripheral 35 perr/w d02 external slave peripheral 35 perwbe0 f03 external slave peripheral 35 perwbe1 e01 [perwe ]pciint d15 external slave peripheral 35 phy0col0 ab8 ethernet 34 phy0col1 c05 phy0crs0 aa9 ethernet 34 phy0crs1 b05 phy0rx0clk ab10 ethernet 34 phy0rx0d0 y16 ethernet 34 phy0rx0d1 aa22 phy0rx0d2 aa16 phy0rx0d3 aa13 phy0rx0dv y10 ethernet 34 phy0rx0err ab11 ethernet 34 phy0rx1clk e02 ethernet 34 phy0rx1d0 r01 ethernet 34 phy0rx1d1 h03 phy0rx1d2 g03 phy0rx1d3 f02 signals listed alphabetically (part 10 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 23 of 52 phy0rx1dv d06 ethernet 34 phy0rx1err c01 ethernet 34 phy0tx0clk y08 ethernet 34 phy0tx1clk c06 sysclk ab18 system 37 ras aa15 sdram 35 [rejectpkt0]gpio30 w20 system 37 [rejectpkt1]gpio31 y21 system 37 reserved C other 38 syserr y17 system 37 sysreset ab20 system 37 tck y02 jtag 37 tdi aa1 jtag 37 tdo aa2 jtag 37 testen v20 system 37 tms ac3 jtag 37 trst h02 jtag 37 [ts1e]gpio01 aa23 trace 38 [ts2e]gpio02 y22 [ts1o]gpio03 y23 [ts2o]gpio04 w21 [ts3]gpio05 u20 [ts4]gpio06 v23 [ts5]gpio07 u21 [ts6]gpio08 u22 [trcclk]gpio09 t21 trace 38 uart0_cts t03 internal peripheral 36 [uart0_dcd ]gpio24 m04 [uart0_dsr ]gpio25 k01 [uart0_dtr ]gpio27 j01 [uart0_ri ]gpio26 l04 uart0_rts n02 uart0_rx t01 uart0_tx p04 [uart1_rx]gpio28 j02 internal peripheral 36 [uart1_tx]gpio29 j03 signals listed alphabetically (part 11 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet page 24 of 52 6/9/03 v dd e10 power 38 v dd e11 v dd e13 v dd e14 v dd k05 v dd k19 v dd l05 v dd l19 v dd n05 v dd n19 v dd p05 v dd p19 v dd w10 v dd w11 v dd w13 v dd w14 we ac15 sdram 35 signals listed alphabetically (part 12 of 12) signal name ball interface group page
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 25 of 52 signals listed by ball assignment (part 1 of 6) ball signal name ball signal name ball signal name ball signal name a01 gnd b01 gnd c01 phy0rx1err d01 perdata15 a02 gnd b02 gnd c02 gpio10[percs1] d02 perr/w a03 extreset b03 perready c03 gnd d03 gpio12[percs3] a04 gpio15[peraddr04] b04 gpio14[peraddr03] c04 perclk d04 gnd a05 gpio16[peraddr05] b05 phy0crs1 c05 phy0col1 d05 gpio13[percs4] a06 peraddr08 b06 peraddr07 c06 phy0tx1clk d06 phy0rx1dv a07 gnd b07 peraddr11 c07 peraddr10 d07 peraddr06 a08 peraddr15 b08 peraddr13 c08 peraddr12 d08 peraddr09 a09 gpio00[perblast ] b09 ov dd c09 peraddr16 d09 peraddr14 a10 peraddr21 b10 peraddr19 c10 peraddr18 d10 peraddr17 a11 peraddr23 b11 ov dd c11 peraddr22 d11 peraddr20 a12 gnd b12 peraddr25 c12 peraddr26 d12 peraddr24 a13 peraddr27 b13 peraddr28 c13 peraddr29 d13 ov dd a14 peraddr30 b14 peraddr31 c14 emc0tx1d1 d14 emc0tx1d3 a15 emc0tx1d2 b15 emc0tx1d0 c15 emc0tx1err d15 pciint [perwe ] a16 emc0tx1en b16 pciad00 c16 pciad01 d16 pciad03 a17 gnd b17 pciad02 c17 ov dd d17 pciad05 a18 pcic0/be0 b18 pciad04 c18 pciad06 d18 pciad08 a19 pciad07 b19 ov dd c19 pciad09 d19 pcic1/be1 a20 pciad10 b20 pciad11 c20 pciad12 d20 gnd a21 pciidsel b21 pciclk c21 gnd d21 pciad14 a22 gnd b22 gnd c22 halt d22 pciad15 a23 gnd b23 gnd c23 pciad13 d23 pcignt0 /req
preliminary powerpc 405ep embedded processor data sheet page 26 of 52 6/9/03 e01 perwbe1 f01 perdata14 g01 gnd h01 perdata09 e02 phy0rx1clk f02 phy0rx1d3 g02 perdata11 h02 trst e03 gpio11[percs2] f03 perwbe0 g03 phy0rx1d2 h03 phy0rx1d1 e04 percs0 f04 peroe g04 perdata12 h04 perdata13 e05 gnd f05 ov dd g05 ov dd h05 ov dd e06 ov dd f06 no ball g06 no ball h06 no ball e07 ov dd f07 no ball g07 no ball h07 no ball e08 ov dd f08 no ball g08 no ball h08 no ball e09 gnd f09 no ball g09 no ball h09 no ball e10 v dd f10 no ball g10 no ball h10 no ball e11 v dd f11 no ball g11 no ball h11 no ball e12 gnd f12 no ball g12 no ball h12 no ball e13 v dd f13 no ball g13 no ball h13 no ball e14 v dd f14 no ball g14 no ball h14 no ball e15 gnd f15 no ball g15 no ball h15 no ball e16 ov dd f16 no ball g16 no ball h16 no ball e17 ov dd f17 no ball g17 no ball h17 no ball e18 ov dd f18 no ball g18 no ball h18 no ball e19 gnd f19 ov dd g19 ov dd h19 ov dd e20 pcireq0 /gnt f20 pcireq1 g20 pcireset h20 pciirdy e21 ov dd f21 pcignt2 g21 pcitrdy h21 pcidevsel e22 pcireq2 f22 pciframe g22 pcistop h22 ov dd e23 pcignt1 f23 ov dd g23 gnd h23 pciperr signals listed by ball assignment (part 2 of 6) ball signal name ball signal name ball signal name ball signal name
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 27 of 52 j01 gpio27[uart0_dtr ] k01 gpio25[uart0_dsr ] l01 emc0tx0d2 m01 gnd j02 gpio28[uart1_rx] k02 perdata07 l02 perdata05 m02 perdata03 j03 gpio29[uart1_tx] k03 perdata08 l03 perdata06 m03 perdata04 j04 perdata10 k04 ov dd l04 gpio26[uart0_ri ] m04 gpio24[uart0_dcd ] j05 gnd k05 v dd l05 v dd m05 gnd j06 no ball k06 no ball l06 no ball m06 no ball j07 no ball k07 no ball l07 no ball m07 no ball j08 no ball k08 no ball l08 no ball m08 no ball j09 no ball k09 no ball l09 no ball m09 no ball j10 no ball k10 gnd l10 gnd m10 gnd j11 no ball k11 gnd l11 gnd m11 gnd j12 no ball k12 gnd l12 gnd m12 gnd j13 no ball k13 gnd l13 gnd m13 gnd j14 no ball k14 gnd l14 gnd m14 gnd j15 no ball k15 no ball l15 no ball m15 no ball j16 no ball k16 no ball l16 no ball m16 no ball j17 no ball k17 no ball l17 no ball m17 no ball j18 no ball k18 no ball l18 no ball m18 no ball j19 gnd k19 v dd l19 v dd m19 gnd j20 pciserr k20 ov dd l20 pcic2/be2 m20gnd j21 pciparity k21 pciad18 l21 pciad20 m21 pciad23 j22 pciad16 k22 pciad19 l22 pciad21 m22 ov dd j23 pciad17 k23 ov dd l23 pciad22 m23 gnd signals listed by ball assignment (part 3 of 6) ball signal name ball signal name ball signal name ball signal name
preliminary powerpc 405ep embedded processor data sheet page 28 of 52 6/9/03 n01 ov dd p01 perdata02 r01 phy0rx1d0 t01 uart0_rx n02 uart0_rts p02 perdata00 r02 memdata31 t02 memdata28 n03 emc0tx0d1 p03 emc0tx0d3 r03 memdata30 t03 uart0_cts n04 perdata01 p04 uart0_tx r04 memdata29 t04 memdata27 n05 v dd p05 v dd r05 gnd t05 ov dd n06 no ball p06 no ball r06 no ball t06 no ball n07 no ball p07 no ball r07 no ball t07 no ball n08 no ball p08 no ball r08 no ball t08 no ball n09 no ball p09 no ball r09 no ball t09 no ball n10 gnd p10 gnd r10 no ball t10 no ball n11 gnd p11 gnd r11 no ball t11 no ball n12 gnd p12 gnd r12 no ball t12 no ball n13 gnd p13 gnd r13 no ball t13 no ball n14 gnd p14 gnd r14 no ball t14 no ball n15 no ball p15 no ball r15 no ball t15 no ball n16 no ball p16 no ball r16 no ball t16 no ball n17 no ball p17 no ball r17 no ball t17 no ball n18 no ball p18 no ball r18 no ball t18 no ball n19 v dd p19 v dd r19 gnd t19 ov dd n20 pcic3/be3 p20 ov dd r20 gpio22[irq5] t20 ov dd n21 pciad26 p21 pciad28 r21 pciad31 t21 gpio09[trcclk] n22 pciad25 p22 pciad27 r22 pciad30 t22 gpio21[irq4] n23 pciad24 p23 ov dd r23 pciad29 t23 gpio23[irq6] signals listed by ball assignment (part 4 of 6) ball signal name ball signal name ball signal name ball signal name
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 29 of 52 u01 gnd v01 ov dd w01 emc0tx0en y01 iicsda u02 dqm3 v02 memdata26 w02 memdata24 y02 tck u03 emc0tx0d0 v03 emc0tx0err w03 memdata22 y03 memdata21 u04 memdata25 v04 memdata23 w04 dqm2 y04 gnd u05 ov dd v05 ov dd w05 gnd y05 memdata18 u06 no ball v06 no ball w06 ov dd y06 emc0mdclk u07 no ball v07 no ball w07 ov dd y07 memdata13 u08 no ball v08 no ball w08 ov dd y08 phy0tx0clk u09 no ball v09 no ball w09 gnd y09 memdata09 u10 no ball v10 no ball w10 v dd y10 phy0rx0dv u11 no ball v11 no ball w11 v dd y11 memdata04 u12 no ball v12 no ball w12 gnd y12 ov dd u13 no ball v13 no ball w13 v dd y13 memclkout1 u14 no ball v14 no ball w14 v dd y14 cas u15 no ball v15 no ball w15 gnd y15 ba0 u16 no ball v16 no ball w16 ov dd y16 phy0rx0d0 u17 no ball v17 no ball w17 ov dd y17 syserr u18 no ball v18 no ball w18 ov dd y18 memaddr08 u19 ov dd v19 ov dd w19 gnd y19 memaddr10 u20 gpio05[ts3] v20 testen w20 gpio30[rejectpkt0] y20 gnd u21 gpio07[ts5] v21 gpio19[irq2] w21 gpio04[ts2o] y21 gpio31[rejectpkt1] u22 gpio08[ts6] v22 gpio20[irq3] w22 gpio17[irq0] y22 gpio02[ts2e] u23 gnd v23 gpio06[ts4] w23 gpio18[irq1] y23 gpio03[ts1o] signals listed by ball assignment (part 5 of 6) ball signal name ball signal name ball signal name ball signal name
preliminary powerpc 405ep embedded processor data sheet page 30 of 52 6/9/03 aa01 tdi ab01 gnd ac01 gnd aa02 tdo ab02 gnd ac02 gnd aa03 gnd ab03 memdata20 ac03 tms aa04 memdata19 ab04 iicscl ac04 memdata17 aa05 emc0mdio ab05 memdata16 ac05 memdata15 aa06 memdata14 ab06 memdata12 ac06 ov dd aa07 dqm1 ab07 memdata11 ac07 gnd aa08 memdata10 ab08 phy0col0 ac08 memdata08 aa09 phy0crs0 ab09 memdata07 ac09 memdata06 aa10 memdata05 ab10 phy0rx0clk ac10 dqm0 aa11 memdata03 ab11 phy0rx0err ac11 memdata02 aa12 memdata01 ab12 memdata00 ac12 gnd aa13 phy0rx0d3 ab13 banksel0 ac13 banksel1 aa14 memclkout0 ab14 clken0 ac14 clken1 aa15 ras ab15 memaddr00 ac15 we aa16 phy0rx0d2 ab16 memaddr01 ac16 ba1 aa17 memaddr03 ab17 memaddr02 ac17 gnd aa18 memaddr05 ab18 sysclk ac18 memaddr04 aa19 memaddr09 ab19 memaddr07 ac19 memaddr06 aa20 memaddr11 ab20 sysreset ac20 av dd aa21 gnd ab21 agnd ac21 memaddr12 aa22 phy0rx0d1 ab22 gnd ac22 gnd aa23 gpio01[ts1e] ab23 gnd ac23 gnd signals listed by ball assignment (part 6 of 6) ball signal name ball signal name ball signal name ball signal name
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 31 of 52 signal list the following table provides a summary of the number of package pins associated with each functional interface group. in the table signal functional description on page 33, each external signal is listed along with a short description of the signal function. active-low signals (for example, ras ) are marked with an overline. please see signals listed alphabetically on page 13 for the pin (ball) number to which each signal is assigned. multiplexed pins some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. in most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. if you need to know what, if any, signals are multiplexed with a particular signal, look up the name in signals listed alphabetically on page 13. it is expected that in any single application a particular pin will always be programmed to serve the same function. the flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. in addition to multiplexing, many pins are also multi-purpose. for example, in the pci interface pcic3:0/be3:0 serves as both command and byte enable signals. in this example, the pins are also bidirectional, serving as both inputs and outputs. initialization strapping one group of pins is used as strapped inputs during system reset. these pins function as strapped inputs only during reset and are used for other functions during normal operation (see initialization on page 50). note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. pull-up and pull-down resistors pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. the recommended pull-up value of 3k ? to +3.3v (10k ? to +5v can be used on 5v tolerant i/os) and pull-down value of 1k ? to gnd, applies only to individually terminated signals. to prevent possible damage to the device, i/os capable of becoming outputs must never be tied together and terminated through a common resistor. pin summary group no. of pins non multiplexed 215 multiplexed 33 total signal pins 248 ov dd 43 v dd 16 gnd 53 thermal (and gnd) 25 reserved 0 total pins 385
preliminary powerpc 405ep embedded processor data sheet page 32 of 52 6/9/03 if your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3v or gnd. when a resistor is used, its value must ensure that the grouped i/os reach a valid logic zero or logic one state when accounting for the total input current into the ppc405ep. unused i/os strapping of some pins may be necessary when they are unused. although the ppc405ep requires only the pull-up and pull-down terminations as specified in the signal functional description on page 33, good design practice is to terminate all unused inputs or to configure i/os such that they always drive. if unused, the peripheral, sdram, and pci buses should be configured and terminated as follows: ? peripheral interfaceperaddr03:31, perdata00:15, and all of the control signals are driven by default. terminate perready high. ? sdramprogram sdram0_cfg[emdulr]=1 and sdram0_cfg[dce]=1. this causes the ppc405ep to actively drive all of the sdram address, data, and control signals. ? pcithe pci pull-up requirements given in the signal functional description apply only when the pci interface is being used. when the pci bridge is unused, configure the pci controller to park on the bus and actively drive pciad31:00, pcic3:0/be3:0 , and the remaining pci control signals by doing the following: - strap the ppc405ep to disable the internal pci arbiter. - individually connect pciserr , pciperr , pcitrdy , and pcistop through 3.3k ? resistors to +3.3v. - terminate pcireq1:2 to +3.3v. - terminate pcireq0 /gnt to gnd. for selected interfaces, it is possible to turn off input receivers for some or all of the signals on that interface. control for this receiver gating is in register cpc0_cr1. when this gating capability is applied to unused signals, it is not necessary to strap them. refer to the powerpc 405ep embedded processor users manual for details. external bus control signals all peripheral bus control signals (percs0:4 , perr/w , perwbe0:1 , peroe , perwe , perblast ) are set to the high-impedance state when extreset =0. in addition, as detailed in the powerpc 405ep embedded processor users manual , the peripheral bus controller can be programmed via ebc0_cfg to float some of these control signals between transactions. as a result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. the following table lists all of the i/o signals provided by the ppc405ep. please refer to signals listed alphabetically on page 13 for the pin number to which each signal is assigned.
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 33 of 52 signal functional description (part 1 of 6) secondary multiplexed signals are shown in brackets. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 31 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 31 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 32. signal name description i/o type notes pci interface pciad31:00 pci address/data bus. multiplexed address and data bus. i/o 5v tolerant 3.3v pci pcic3:0/be3:0 pci bus command and byte enables. i/o 5v tolerant 3.3v pci pciclk pciclk is used as the asynchronous pci clock when in asynch mode. i 5v tolerant 3.3v pci pciframe pciframe is driven by the current pci bus master to indicate the beginning and duration of a pci access. i/o 5v tolerant 3.3v pci 2 pciparity pci parity. parity is even across pciad00:31 and pcic3:0/be3:0 . pciparity is valid one cycle after either an address or data phase. the pci device that drove pciad00:31 is responsible for driving pciparity on the next pci bus clock. i/o 5v tolerant 3.3v pci pciirdy pciirdy is driven by the current pci bus master. assertion of pciirdy indicates that the pci initiator is ready to transfer data. i/o 5v tolerant 3.3v pci 2 pcitrdy the target of the current pci transaction drives pcitrdy . assertion of pcitrdy indicates that the pci target is ready to transfer data. i/o 5v tolerant 3.3v pci 2 pcistop the target of the current pci transaction can assert pcistop to indicate to the requesting pci master that it wants to end the current transaction. i/o 5v tolerant 3.3v pci 2 pcidevsel pcidevsel is driven by the target of the current pci transaction. a pci target asserts pcidevsel when it has decoded an address and command encoding and claims the transaction. i/o 5v tolerant 3.3v pci 2 pciidsel pciidsel is used during configuration cycles to select the pci slave interface for configuration. i 5v tolerant 3.3v pci pciint pci interrupt. open-drain output (two states; 0 or open circuit) or peripheral write enable. low when any of the four perwbe0:3 write byte enables are low. o 5v tolerant 3.3v pci pciserr pciserr is used for reporting address parity errors or catastrophic failures detected by a pci target. i/o 5v tolerant 3.3v pci 2 pciperr pciperr is used for reporting data parity errors on pci transactions. pciperr is driven active by the device receiving pciad00:31, pcic3:0/be3:0 , and pciparity, two pci clocks following the data in which bad parity is detected. i/o 5v tolerant 3.3v pci 2 pcireset pci specific reset. o 5v tolerant 3.3v pci pcireq0 /gnt multipurpose signal, used as pcireq0 when internal arbiter is used, and as gnt when external arbiter is used. i 5v tolerant 3.3v pci
preliminary powerpc 405ep embedded processor data sheet page 34 of 52 6/9/03 pcireq1:2 pcireq input when internal arbiter is used. i 5v tolerant 3.3v pci pcignt0 /req gnt0 when internal arbiter is used or req when external arbiter is used. o 5v tolerant 3.3v pci pcignt1:2 pcignt output when internal arbiter is used. o 5v tolerant 3.3v pci ethernet interface phy0rx0:1d3:0 received data. this is a nibble wide bus from the phy. the data is synchronous with the phy0rxclk. i 5v tolerant 3.3v lvttl 1 emc0tx0:1d3:0 transmit data. a nibble wide data bus towards the net. the data is synchronous to the phy0txclk. o 5v tolerant 3.3v lvttl phy0rx0:1err receive error. this signal comes from the phy and is synchronous to the phy0rxclk. i 5v tolerant 3.3v lvttl 1 phy0rx0:1clk receive medium clock. this signal is generated by the phy. i 5v tolerant 3.3v lvttl 1 phy0rx0:1dv receive data valid. data on the data bus is valid when this signal is activated. deassertion of this signal indicates end of the frame reception. i 5v tolerant 3.3v lvttl 1 phy0crs0:1 carrier sense signal from the phy. this is an asynchronous signal. i 5v tolerant 3.3v lvttl 1 emc0tx0:1err transmit error. this signal is generated by the ethernet controller, is connected to the phy and is synchronous with the phytxclk. it informs the phy that an error was detected. o 5v tolerant 3.3v lvttl emc0tx0:1en transmit enable. this signal is driven by the emac to the phy. data is valid during the active state of this signal. deassertion of this signal indicates end of frame transmission. this signal is synchronous to the phy0txclk. o 5v tolerant 3.3v lvttl phy0tx0:1clk this clock comes from the phy and is the medium transmit clock. i 5v tolerant 3.3v lvttl 1 phy0col0:1 collision signal from the phy. this is an asynchronous signal. i 5v tolerant 3.3v lvttl 1 emc0mdclk management data clock. the mdclk is sourced to the phy. management information is transferred synchronously with respect to this clock. o 5v tolerant 3.3v lvttl emc0mdio management data input/output is a bidirectional signal between the ethernet controller and the phy. it is used to transfer control and status information. i/o 5v tolerant 3.3v lvttl 1 signal functional description (part 2 of 6) secondary multiplexed signals are shown in brackets. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 31 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 31 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 32. signal name description i/o type notes
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 35 of 52 sdram interface memdata00:31 memory data bus. notes: 1. memdata00 is the most significant bit (msb). 2. memdata31 is the least significant bit (lsb). i/o 3.3v lvttl memaddr12:00 memory address bus. notes: 1. memaddr12 is the most significant bit (msb). 2. memaddr00 is the least significant bit (lsb). o3.3v lvttl ba1:0 bank address supporting up to 4 internal banks. o 3.3v lvttl ras row address strobe. o 3.3v lvttl cas column address strobe. o 3.3v lvttl dqm0:3 dqm for byte lane: 0 (memdata00:7), 1 (memdata08:15), 2 (memdata16:23), and 3 (memdata24:31) o3.3v lvttl banksel0:1 select up to two external sdram banks. o 3.3v lvttl we write enable. o 3.3v lvttl clken0:1 sdram clock enable. o 3.3v lvttl memclkout0:1 two copies of an sdram clock allows, in some cases, glueless sdram attach without requiring this signal to be repowered by a pll or zero-delay buffer. o3.3v lvttl external slave peripheral interface perdata00:15 peripheral data bus. note: perdata00 is the most significant bit (msb) on this bus. i/o 5v tolerant 3.3v lvttl 1 peraddr03:05 peraddr06:31 peripheral address bus. note: peraddr03 is the most significant bit (msb) on this bus. i/o 5v tolerant 3.3v lvttl 1 perwbe0:1 these pins act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. o 5v tolerant 3.3v lvttl 7 [perwe ] peripheral write enable. low when either of the two perwbe0:1 write byte enables are low. to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl percs0 peripheral chip select bank 0. o 5v tolerant 3.3v lvttl 7 [percs1:4 ] four additional peripheral chip selects to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl 1, 7 signal functional description (part 3 of 6) secondary multiplexed signals are shown in brackets. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 31 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 31 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 32. signal name description i/o type notes
preliminary powerpc 405ep embedded processor data sheet page 36 of 52 6/9/03 peroe peripheral output enable. o 5v tolerant 3.3v lvttl 7 perr/w peripheral read/write . high indicates a read from memory, low indicates a write to memory. o 5v tolerant 3.3v lvttl perready ready to transfer data. i 5v tolerant 3.3v lvttl 1 [perblast ] used to indicates the last transfer of a memory access. to access this function, software must toggle a dcr bit. i/o 5v tolerant 3.3v lvttl 1, 7 perclk peripheral clock to be used by peripheral slaves. o 5v tolerant 3.3v lvttl extreset peripheral reset to be used by peripheral slaves. o 5v tolerant 3.3v lvttl internal peripheral interface uart0_rx uart0 serial data in. i 5v tolerant 3.3v lvttl 1 uart0_tx uart0 serial data out. o 5v tolerant 3.3v lvttl 6 [uart0_dcd ] uart0 data carrier detect. to access this function, software must toggle a dcr bit. i 5v tolerant 3.3v lvttl 1 [uart0_dsr ] uart0 data set ready. to access this function, software must toggle a dcr bit. i 5v tolerant 3.3v lvttl 1 uart0_cts uart0 clear to send. i 5v tolerant 3.3v lvttl 1 [uart0_dtr ] uart0 data terminal ready. to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl uart0_rts uart0 request to send. o 5v tolerant 3.3v lvttl 6 [uart0_ri ] uart0 ring indicator. to access this function, software must toggle a dcr bit. i 5v tolerant 3.3v lvttl 1 [uart1_rx] uart1 serial data in. to access this function, software must toggle a dcr bit. i 5v tolerant 3.3v lvttl 1 [uart1_tx] uart1 serial data out. to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl iicscl iic serial clock. i/o 3.3v iic 1, 2 iicsda iic serial data. i/o 3.3v iic 1, 2 interrupts interface [irq0:6] interrupt requests to access this function, software must toggle a dcr bit. i 5v tolerant 3.3v lvttl 1 signal functional description (part 4 of 6) secondary multiplexed signals are shown in brackets. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 31 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 31 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 32. signal name description i/o type notes
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 37 of 52 jtag interface tdi test data in. i 5v tolerant 3.3v lvttl 1, 4 tms jtag test mode select. i 5v tolerant 3.3v lvttl 1, 4 tdo test data out. o 5v tolerant 3.3v lvttl tck jtag test clock. the frequency of this input can range from dc to 25mhz. i 5v tolerant 3.3v lvttl 1, 4 trst jtag reset. trst must be low at power-on to initialize the jtag controller and for normal operation of the ppc405ep. i 5v tolerant 3.3v lvttl 5 system interface sysreset main system reset. external logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. a system reset can also be initiated by software. implemented as an open- drain output (two states; 0 or open circuit). i/o 5v tolerant 3.3v lvttl 1, 2 syserr set to 1 when a machine check is generated. o 5v tolerant 3.3v lvttl 6 halt halt from external debugger. i 5v tolerant 3.3v lvttl 1, 2 gpio00:31 general purpose i/o. all of the gpio signals are multiplexed with other signals. i/o 5v tolerant 3.3v lvttl 1 testen test enable. used only for manufacturing tests. pull down for normal operation. i 1.8v cmos w/pull-down sysclk main system clock input. i 3.3v lvttl [rejectpkt0:1] external request to reject a packet. i 5v tolerant 3.3v lvttl av dd clean voltage input for the pll. i agnd clean ground input for the pll. i signal functional description (part 5 of 6) secondary multiplexed signals are shown in brackets. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 31 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 31 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 32. signal name description i/o type notes
preliminary powerpc 405ep embedded processor data sheet page 38 of 52 6/9/03 trace interface [ts1e] [ts2e] even trace execution status. to access this function, software must toggle a dcr bit o 5v tolerant 3.3v lvttl 1 [ts1o] [ts2o] odd trace execution status. to access this function, software must toggle a dcr bit o 5v tolerant 3.3v lvttl 1 [ts3:6] trace status. to access this function, software must toggle a dcr bit o 5v tolerant 3.3v lvttl 1 [trcclk] trace interface clock. operates at half the cpu core frequency. to access this function, software must toggle a dcr bit note: initialization strapping must hold this pin low (0) during reset. o 5v tolerant 3.3v lvttl 1 power gnd ground note: k10-k14, l10-l14, m10-m14, n10-n14, and p10-p14 are also thermal balls. na na na ov dd output driver voltage3.3v. na na na v dd logic voltage1.8v. na na na other pins reserved reserved pins. do not make voltage, ground, or signal connections to these pins. na na na signal functional description (part 6 of 6) secondary multiplexed signals are shown in brackets. notes: 1. receiver input has hysteresis. 2. must pull up. see pull-up and pull-down resistors on page 31 for recommended termination values. 3. must pull down. see pull-up and pull-down resistors on page 31 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. 7. pull-up may be required. see external bus control signals on page 32. signal name description i/o type notes
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 39 of 52 note: 1. for a chip mounted on a jedec 2s2p card without a heat sink. 2. for a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. case temperature, t c , is measured at top center of case surface with device soldered to circuit board. b. t a = t c C p ca , where t a is ambient temperature and p is power consumption. c. t cmax = t jmax C p jc , where t jmax is maximum junction temperature and p is power consumption. absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to the device. none of the performance specification contained in this document are guaranteed when operating at these maximum ratings. characteristic symbol value unit supply voltage (internal logic) v dd 0 to +1.95 v supply voltage (i/o interface) ov dd 0 to +3.6 v pll supply voltage av dd 0 to +1.95 v input voltage (1.8v cmos receivers) v in 0 to +1.95 v input voltage (3.3v lvttl receivers) v in 0 to +3.6 v input voltage (5.0v lvttl receivers) v in 0 to +5.5 v storage temperature range t stg -55 to +150 c case temperature under bias t c -40 to +120 c note: all specified voltages are with respect to gnd. package thermal specifications the ppc405ep is designed to operate within a case temperature range of -40c to +85c. thermal resistance values for the e-pbga packages in a convection environment are as follows: packagethermal resistance symbol airflow ft/min (m/sec) unit 0 (0) 100 (0.51) 200 (1.02) 31mm, 385-ballsjunction-to-case jc 222c/w 31mm, 385-ballscase-to-ambient 1 ca 17.8 16.8 16.1 c/w recommended dc operating conditions (part 1 of 2) device operation beyond the conditions specified is not recommended. extended operation beyond the recommended conditions can affect device reliability. notes: 1. pci drivers meet pci specifications. 2. see 5v-tolerant input current on page 41. parameter symbol minimum typical maximum unit notes logic supply voltage (133, 200, 266mhz) v dd +1.65 +1.8 +1.95 v logic supply voltage (333mhz) v dd +1.7 +1.8 +1.9 v i/o supply voltage ov dd +3.0 +3.3 +3.6 v
preliminary powerpc 405ep embedded processor data sheet page 40 of 52 6/9/03 pll supply voltage (133, 200, 266mhz) av dd +1.65 +1.8 +1.95 v pll supply voltage (333mhz) av dd +1.7 +1.8 +1.9 v input logic high (1.8v cmos receivers) v ih 0.65v dd v dd v input logic high (3.3v pci receivers) v ih 0.5ov dd ov dd +0.5 v input logic high (3.3v lvttl, 5v tolerant receivers) v ih +2.0 +5.5 v input logic low (1.8v cmos receivers) v il 0 0.65v dd v input logic low (3.3v pci receivers) v il -0.5 0.35ov dd v input logic low (3.3v lvttl, 5v tolerant receivers) v il 0+0.8v output logic high (3.3v pci receivers) v oh 0.9ov dd ov dd v output logic high (3.3v lvttl, 5v tolerant receivers) v oh +2.4 ov dd v output logic low (3.3v pci receivers) v ol -0.5 0.35ov dd v output logic low (3.3v lvttl, 5v tolerant receivers) v ol 0+0.4v input leakage current (no pull-up or pull-down) i il1 00 a input leakage current (with internal pull-down) i il2 0 200 a 5v tolerant i/o input current i il4 10 -325 a 2 input max allowable overshoot (1.8v cmos receivers) v imao1.8 v dd + 0.6 v input max allowable overshoot (3.3v lvttl, 5v tolerant receivers) v imao +5.5 v input max allowable undershoot (3.3v lvttl, 5v tolerant receivers) v imau -0.6 v output max allowable overshoot (3.3v lvttl, 5v tolerant receivers) v omao +5.5 v output max allowable undershoot (3.3v lvttl, 5v tolerant receivers) v omau -0.6 v case temperature t c -40 +85 c recommended dc operating conditions (part 2 of 2) device operation beyond the conditions specified is not recommended. extended operation beyond the recommended conditions can affect device reliability. notes: 1. pci drivers meet pci specifications. 2. see 5v-tolerant input current on page 41. parameter symbol minimum typical maximum unit notes
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 41 of 52 5v-tolerant input current input capacitance parameter symbol maximum unit notes 3.3v lvttl i/o c in1 12 pf 5v tolerant, 3.3v lvttl i/o c in2 12 pf pci i/o c in3 12 pf rx only pins c in4 9pf iic pads c in5 6.7 pf -350 -300 -250 -200 -150 -100 -50 0 50 1.0 2.0 3.0 4.0 5.0 0.0 input current ( a) input voltage (v)
preliminary powerpc 405ep embedded processor data sheet page 42 of 52 6/9/03 test conditions clock timing and switching characteristics are specified in accordance with operating conditions shown in the table recommended dc operating conditions. for all signals other than pci signals, ac specifications are characterized at ov dd = 3v and t c = 85c with the 50pf test load shown in the figure at right. for pci signals there are two different test load circuits, one for the rising edge and one the falling edge as shown in the figures at right. dc electrical characteristics parameter symbol minimum typical maximum unit active operating current (v dd )i dd 440 520 606 ma active operating current (ov dd )i odd 59 70 81 ma active operating current (av dd )i add 14 17 19 ma total power p t 1.2 1.4 w note: 1. av dd should be derived from v dd using the following circuit: v dd c1 c2 c3 av dd l1 l1 C 2.2 h smt inductor (equivalent to murata lqh3c2r2m34) or smt chip ferrite bead (equivalent to murata blm31a700s) c1 C 3.3 f smt tantalum c2 C 0.1 f smt monolithic ceramic capacitor with x7r dielectric or equivalent c3 C 0.01 f smt monolithic ceramic capacitor with x7r dielectric or equivalent + agnd gnd output pin 50pf all signals other than pci output pin 10pf 25 ? output pin 10pf 25 ? ov dd pci rising edge pci falling edge
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 43 of 52 clocking specifications symbol parameter min max units cpu pf c processor clock frequency 133.33, 200, 266.66, or 333.33 mhz pt c processor clock period 7.5, 5, 3.75 or 3 ns sysclk input scf c frequency 25 100 mhz sct c period 10 40 ns sct cs edge stability (phase jitter, cycle to cycle) C 0.15 ns sct ch input high time 40% of nominal period 60% of nominal period ns sct cl input low time 40% of nominal period 60% of nominal period ns note: input slew rate > 2v/ns memclkout output mcof c frequency plbf c mhz mcot c period 1/plbf c ns mcot cs edge stability (phase jitter, cycle to cycle) C 0.2 ns mcot ch output high time 45% of nominal period 55% of nominal period ns mcot cl output low time 45% of nominal period 55% of nominal period ns trcclk output tcf c clock output frequency pf c /2 mhz tct c clock period pt c x2 ns tct cs clock edge stability (phase jitter, cycle to cycle) 0.2 ns tct ch clock output high time 45% of nominal period 55% of nominal period ns tct cl clock output low time 45% of nominal period 55% of nominal period ns other clocks vcof c vco frequency @ pf c = 133, 200, 266, or 333mhz 500 1000 mhz plbf c plb frequency @ pf c = 133.33mhz 33.33 133.33 mhz plbf c plb frequency @ pf c = 266.66mhz 66.66 133.33 mhz plbf c plb frequency @ pf c = 333.33mhz 83.33 111.11 mhz plbf c plb frequency @ pf c = 200mhz 50 100 mhz opbf c opb frequency @ pf c = 133.33mhz 8.33 66.66 mhz opbf c opb frequency @ pf c = 266.66mhz 16.66 66.66 mhz opbf c opb frequency @ pf c = 333.33mhz 20.83 55.55 mhz opbf c opb frequency @ pf c = 200mhz 12.5 50 mhz
preliminary powerpc 405ep embedded processor data sheet page 44 of 52 6/9/03 clocking waveform spread spectrum clocking care must be taken when using a spread spectrum clock generator (sscg) with the ppc405ep. this controller uses a pll for clock generation inside the chip. the accuracy with which the pll follows the sscg is referred to as tracking skew. the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the ppc405ep the following conditions must be met: ? the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the ppc405ep with one or more internal clocks at their maximum supported frequency, the sscg can only lower the frequency. ? the maximum frequency deviation cannot exceed ? 3%, and the modulation frequency cannot exceed 40khz. in some cases, on-board ppc405ep peripherals impose more stringent requirements (see note 1). ? use the peripheral bus clock (perclk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation. ? use the sdram memclkout since it also tracks the modulation. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is running at precise baud rates. if an external serial clock is used the baud rate is unaffected by the modulation 2. operation of the ppc405ep pci bridge is unaffected by the use of an sscg. the pci controller must be operated in asynchronous mode. when in asynchronous mode, the pci bus clock must be driven into the ppc405ep pciclk input. in this configuration the pci controller supports the 66.66 mhz pci clock specification which specifies a maximum frequency deviation of -1% at a modulation of between 30 khz and 33 khz. 3. ethernet operation is unaffected. 4. iic operation is unaffected. caution: it is up to the system designer to ensure that any sscg used with the ppc405ep meets the above requirements and does not adversely affect other aspects of the system. t cl t ch t c 2.0v 1.5v 0.8v
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 45 of 52 peripheral interface clock timings parameter min max units pciclk input frequency (asynchronous mode) note 1 66.66 mhz pciclk period (asynchronous mode) 15 note 1 ns pciclk input high time 40% of nominal period 60% of nominal period ns pciclk input low time 40% of nominal period 60% of nominal period ns emc0mdclk output frequency C 2.5 mhz emc0mdclk period 400 C ns emc0mdclk output high time 160 C ns emc0mdclk output low time 160 C ns phy0tx0:1clk input frequency 2.5 25 mhz phy0tx0:1clk period 40 400 ns phy0tx0:1clk input high time 35% of nominal period C ns phy0tx0:1clk input low time 35% of nominal period C ns phy0rx0:1clk input frequency 2.5 25 mhz phy0rx0:1clk period 40 400 ns phy0rx0:1clk input high time 35% of nominal period C ns phy0rx0:1clk input low time 35% of nominal period C ns perclk output frequency C 66.66 mhz perclk period 15 C ns perclk output high time 45% of nominal period 55% of nominal period ns perclk output low time 45% of nominal period 55% of nominal period ns perclk clock edge stability (phase jitter, cycle to cycle) 0.3 ns note: 1. in asynchronous pci mode the minimum pciclk frequency is 1/8 the plb clock. refer to the powerpc 405ep embedded proces- sor users manual for more information.
preliminary powerpc 405ep embedded processor data sheet page 46 of 52 6/9/03 input setup and hold timing waveform output delay and float timing waveform system clock t is t ih min min inputs valid 1.5 v 1.5v valid t ov t oh min outputs system clock outputs t of min max max 1.5v 1.5v 1.5v
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 47 of 52 notes: 1. in the following i/o specifications tables a timing value of na means not applicable and dc means dont care. 2. see test conditions on page 42 for output capacitive loading. i/o specificationsgroup 1 (part 1 of 2) notes: 1. pci timings are for asynchronous operation up to 66.66mhz. pci output hold time requirement is 1ns for 66.66mhz and 2ns for 33.33mhz. 2. ethernet interface meets timing requirements as defined by ieee 802.3 standard. timing shown is with emac noise filter selected. see the cpc0_epctl register powerpc 405ep embedded processor users manual . 3. for pci, i/o h is specified at 0.9ov dd and i/o l is specified at 0.1ov dd . for all other interfaces, i/o h is specified at 2.4 v and i/o l is specified at 0.4 v. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (min) i/o l (min) pci interface pciad31:00 3 0 6 1 0.5 1.5 pciclk 1 pcic3:0/be3:0 3 0 6 1 0.5 1.5 pciclk 1 pciclk na na na na na na async pcidevsel 3 0 6 1 0.5 1.5 pciclk 1 pciframe 3 0 6 1 0.5 1.5 pciclk 1 pcignt0 /req pcignt1:2 na na 6 1 0.5 1.5 pciclk 1 pciidsel 3 0 na na na na pciclk 1 pciint [perwe ] na na na na 0.5 1.5 pciclk 1 pciirdy 3 0 6 1 0.5 1.5 pciclk 1 pciparity 3 0 6 1 0.5 1.5 pciclk 1 pciperr 3 0 6 1 0.5 1.5 pciclk 1 pcireq0 /gnt pcireq1:2 5 0 na na na na pciclk 1 pcireset na na na na 0.5 1.5 pciclk 1 pciserr na na na na 0.5 1.5 pciclk 1 pcistop 3 0 6 1 0.5 1.5 pciclk 1 pcitrdy 3 0 6 1 0.5 1.5 pciclk 1 ethernet interface emc0mdclk na na settable 2 10.3 7.1 async 2 emc0mdio 100 0 1 opb clock period + 10ns 1 opb clock period 10.3 7.1 emc0mdclk 2 emc0tx0:1d3:0 na na 14 5 10.3 7.1 phy0txclk 2 emc0tx0:1en na na 14 5 10.3 7.1 phy0txclk 2 emc0tx0:1err na na 14 5 10.3 7.1 phy0txclk 2 phy0col0:1 2 3 na na na na phy0rxclk 2 phy0crs0:1 2 3 na na na na phy0rxclk 2 phy0rx0:1clk na na na na na na async 2 phy0rx0:1d3:0 2 4 na na na na phy0rxclk 2 phy0rx0:1dv 2 4 na na na na phy0rxclk 2 phy0rx0:1err 2 4 na na na na phy0rxclk 2 phy0tx0:1clk na na na na na na async 2
preliminary powerpc 405ep embedded processor data sheet page 48 of 52 6/9/03 internal peripheral interface iicscl na na na na 15.3 10.2 iicsda na na na na 15.3 10.2 uart0_cts na na na na na na uart0_rts na na na na 10.3 7.1 uart0_rx na na na na na na uart0_tx na na na na 10.3 7.1 uart1_rx na na na na na na uart1_tx na na na na 10.3 7.1 interrupts interface [irq0:6] 10.3 7.1 jtag interface tck nanananananaasync tdi na na na na na na async tdo na na na na 10.3 7.1 async tms nanananananaasync trst na na na na na na async system interface gpio00:31 na na na na 10.3 7.1 halt na na na na na na async syserr na na na na 10.3 7.1 async sysreset na na na na 10.3 7.1 async testen na na na na na na async [rejectpkt0:1] 3 1 na na na na async sysclk na na na na na na i/o specificationsgroup 1 (part 2 of 2) notes: 1. pci timings are for asynchronous operation up to 66.66mhz. pci output hold time requirement is 1ns for 66.66mhz and 2ns for 33.33mhz. 2. ethernet interface meets timing requirements as defined by ieee 802.3 standard. timing shown is with emac noise filter selected. see the cpc0_epctl register powerpc 405ep embedded processor users manual . 3. for pci, i/o h is specified at 0.9ov dd and i/o l is specified at 0.1ov dd . for all other interfaces, i/o h is specified at 2.4 v and i/o l is specified at 0.4 v. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (min) i/o l (min)
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 49 of 52 i/o specificationsgroup 2 notes: 1. the sdram command interface is configurable through sdram0_tr[ldf] to provide a 2 to 4 cycle delay before the command is used by sdram. 2. sdram i/o timings are specified relative to a memclkout terminated into a lumped 10pf load. 3. sdram interface hold times are guaranteed at the ppc405ep package pin. system designers must use the ppc405ep ibis model (available from www.chips.ibm.com ) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other sdram signal wiring. 4. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. 5. i/o h is specified at 2.4 v and i/o l is specified at 0.4 v. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) sdram interface ba1:0 na na 4.7 2 15.3 10.2 memclkout 1, 2 banksel 3:0 na na 4.5 1.7 15.3 10.2 memclkout 1, 2 cas na na 4.8 2 15.3 10.2 memclkout 1, 2 clken0:1 na na 4.1 1.6 28.7 19.3 memclkout 1, 2 dqm0:3 na na 4.7 1.9 15.3 10.2 memclkout 1, 2 memaddr12:00 na na 4.8 2.1 15.3 10.2 memclkout 1, 2 memdata00:31 1.6 1 4 1.2 15.3 10.2 memclkout 1, 2 ras na na 5 2.1 15.3 10.2 memclkout 1, 2 we na na 4.9 2 15.3 10.2 memclkout 1, 2 external slave peripheral interface peraddr06:31 na na 3.8 1.6 15.3 10.2 perclk [perblast ] 418 0128perclk percs0 [percs1:4 ] na na 4.1 1.5 10.3 7.1 perclk perdata00:31 5 1 6.4 1.5 15.3 10.2 perclk peroe na na 4.1 1.5 10.3 7.1 perclk perr/w na na 4.1 1.6 10.3 7.1 perclk perready 6.5 1 na na na na perclk perwbe0:3 na na 4.1 1.6 10.3 7.1 perclk extreset na na na na 15.3 10.2 perclk perclk na na 0.4 -0.2 15.3 10.2 plb clk 4
preliminary powerpc 405ep embedded processor data sheet page 50 of 52 6/9/03 initialization the following describes the method by which initial chip settings are established when a system reset occurs. strapping when the sysreset input is driven low (system reset), the state of certain i/o pins is read to enable default initial conditions prior to ppc405ep start-up. the actual capture instant is the nearest system clock edge before the deassertion of reset. these pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. the recommended pull-up is 3k ? to +3.3v or 10k ? to +5v. the recommended pull-down is 1k ? to gnd. these pins are use for strap functions only during reset. they are used for other signals during normal operation. the following table lists the strapping pins along with their functions and strapping options. the signal names assigned to the pins for normal operation appear below the pin number. eeprom during reset, configuration values other than the internal default values can be read from a serial eeprom connected to the iic port. the association of bits in the eeprom with the configuration values and their default values are covered in detail in the powerpc 405ep embedded processor users manual . caution: if p04 is strapped to 1, and the eeprom is not connected or is defective, the ppc405ep remains in the reset state and will not boot. revision log strapping pin assignments function option ball strapping iic eeprom controller if the controller is enabled, 32 bytes of configuration data are read from the eeprom. p04 uart0_tx disable 0 enable 1 eeprom address (p04 = 1) or boot rom width (p04 = 0) n02 uart0_rts y17 syserr when p04 = 1, these pins set the high-order two bits of the eeprom base address. high order eeprom base address bits address bit address bit when p04 = 0, these pins indicated the width of the boot rom. 8 bits0 0 16 bits0 1 reserved 1 0 reserved 1 1 date contents of modification 01/30/2003 add revision log. 03/18/2003 update revision level of chip. 05/13/2003 add 333mhz part numbers. 06/09/2003 add new supply voltage specs for 333mhz.
preliminary powerpc 405ep embedded processor data sheet 6/9/03 page 51 of 52 inside of back cover
preliminary powerpc 405ep embedded processor data sheet ? (c) copyright international business machines corporation 1999, 2003 all rights reserved printed in the united states of america, 6/9/03 the following are trademarks of international business machines corporation in the united states, or other countries, or both: other company, product, and service names may be trademarks or service marks of others. preliminary edition (6/9/03) this document contains information on a new product under development by ibm. ibm reserves the right to change or discontinue this product without notice. this document is a preliminary edition of the powerpc 405ep data sheet . make sure you are using the correct edition for the level of the product. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is subject to change or withdrawal at any time without notice and is being provided on an "as is" basis without warranty or indemnity of any kind, whether express or implied, including without limitation, the implied warranties of non- infringement, merchantability, or fitness for a particular purpose. any products, services, or programs discussed in this document are sold or licensed under ibm's standard terms and conditions, copies of which may be obtained from your local ibm representative. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. without limiting the generality of the foregoing, any performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal ibm test. therefore, the results obtained in other operating environments may vary significantly. under no circumstances will ibm be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein. ibm microelectronics division 1580 route 52 hopewell junction, ny 12533-6351 the ibm home page is www. ibm.com . the ibm microelectronics division home page is www.chips.ibm.com . sa14-2704-04 52 blue logic ibm powerpc coreconnect ibm logo

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