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? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? 1 ? ? ? ? ? ? device highlights low power programmable logic ? as low as 2.2 a ? 0.18 m, six layer metal cmos process ? 1.8 v core voltage, 1.8/2.5/3.3 v drive capable i/os ? 36 kilobits of sram ? 48 i/os available ? 100,000 system gates ? nonvolatile, instant-on ? ieee 1149.1 boundary scan testing compliant embedded dual-port sram ? eight dual-port 4-kilobit high performance sram blocks ? true dual-port capability ? embedded synchronous/asynchronous fifo controller ? configurable and cascadable aspect ratio programmable i/o ? bank programmable drive strength ? bank programmable slew rate control ? independent i/o banks capable of supporting multiple i/o standards in one device ? bank programmable i/o standards: lvttl, lvcmos, lvcmos18, pci, sstl2, sstl3 and ssdl18 advanced clock network ? multiple low skew clock networks ? 1 dedicated global clock network ? 4 programmable global clock networks ? quadrant-based segmentable clock networks ? 16 quad clock networks per device ? 4 quad clock networks per quadrant ? one user configurable clock manager (ccm) very low power (vlp) mode ? quicklogic polarpro has a special vlp pin which can enable a low power sleep mode that significantly reduces the overall power consumption of the device by placing the device in standby ? enter vlp mode from normal operation in less than 250 s (typical) ? exit from vlp mode to normal operation in less than 250 s (typical) security links there are several security links to disable jtag access to the device. programming these optional links completely disables ac cess to the device from the outside world and provides an extra level of design security not possib le in sram-based fpgas. figure 1: quicklogic polarpro block diagram embedded ram blocks fabric embedded ram blocks fifo controller ccm ddr/gpio gpio gpio gpio gpio gpio gpio gpio gpio gpio ddr/gpio ddr/gpio ddr/gpio fifo controller gpio gpio gpio ccm combining low power, perform ance, density, and embedded ram quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 2 ultra-low power fpga combining performance, density, and embedded ram process data the quicklogic polarpro is fabricated on a 0.18, six la yer metal cmos process. the core voltage is 1.8 v. the i/o voltage input tolerance and output dr ive can be set as 1.8 v, 2.5 v, and 3.3 v. programmable logic architectural overview the quicklogic polarpro logic cell structure presented in figure 2 is a single register, multiplexer-based logic cell. it is designed for wide fan-in and multiple, simultaneous output functi ons. the cell has a high fan-in, fits a wide range of functions with up to 24 simultaneous in puts (including register control lines), and four outputs (three combinatorial and one registered). the high logi c capacity and fan-in of the logic cell accommodates many user functions with a si ngle level of logic delay. the quicklogic polarpro logic cell can implement: ? two independent 3-input functions ? any 4-input function ? 8 to 1 mux function ? independent 2 to 1 mux function ? single dedicated register with clock en able, active high set and reset signals ? direct input selection to the register, which allows co mbinatorial and register logic to be used separately ? combinatorial logic that can also be configur ed as an edge-triggered master-slave d flip-flop table 1: polarpro 86-pin tfbga product information features ql1p100 max gates 100,000 logic cells 640 max i/o 48 distributed clocks 5 ram modules 8 fifo controllers 8 ram bits 36,864 ccm 1 package tfbga (0.5 mm) (6 mm x 6 mm) 86
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 3 figure 2: polarpro logic cell ram modules the polarpro family of devices includes up to eight 4 kilobits of dual-port ra m modules for implementing ram and fifo functions. the ram features include: ? independently configurable read and write data bus widths ? independent read and write clocks ? horizontal and vertical concatenation ? write byte enables ? selectable pipelined or non-pipelined read data 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 d e q r s tz cz qz fz qds qst tbs tab tsl ti ta1 ta2 tb1 tb2 bab bsl bi ba1 ba2 bb1 bb2 fs f1 f2 qdi qen qck qrt
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 4 figure 3: 4-kilobit dual-port ram block the read and write data buses of a ram block can be a rranged to variable bus widths. the bus widths can be configured using the ram wizard avai lable in quickworks, quicklogic?s development software. the selection of the ram depth and width determin es how the data is addressed. the ram blocks also support data concatenation. desi gners can cascade multiple ram modules to increase the depth or width by connecting co rresponding address lines together and dividing the words between modules. generally, this requires the use of additi onal programmable logic resources. however, when concatenating only two 4-kilobit ram blocks, they can be concatenated horizontally or vertically without using any additional programmable fabric resources. for example, two internal 4-kilobit dual-port ram bloc ks can be concatenated vertically to create a 512x18 ram block or horizontally to create a 256x36 ram bloc k. a block diagram of horizontal and vertical concatenation is displayed in figure 4 . table 2: ram interface signals signal name function inputs wd [17:0] write data wa [8:0] write address wen [1:0] write enable (two 9-bit enables) wd_sel write chip select wclk write clock ra [8:0] read address rd_sel read chip select rclk read clock output rd [17:0] read data rd[17:0] wd[17:0] wa[8:0] wen[1:0] wd_sel wclk ra[8:0] rd_sel rclk
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 5 figure 4: horizontal and vertical concatenation examples table 3 shows the various ram configurations su pported by the polarpro ram modules. true dual-port ram polarpro dual-port ram modules can also be concatenat ed to generate true dual -port rams. the true dual- port ram module?s port1 and port2 have completely independent read and write ports, and separate read and write clocks. this allows port1 and port2 to have di fferent data widths and clock domains. it is important to note that there is no circuitry preventing a write an d read operation to the same address space at the same time. therefore, it is up to the designer to ensure that the same address is not read from and written to simultaneously, otherwise the data is considered invali d. likewise, the same address must not be written to from both ports at the same time. however, it is possible to read from the same address. figure 5 shows an example of a 512x18 true dual-port ram. table 3: available dual-port ram configurations device number of ram blocks depth width ql1p100 1 256 1-18 1 512 1-9 2 256 1-36 2 512 1-18 2 1024 1-9 256x36 dual-port ram rd[35:0] horizontal concatenation 512x18 dual-port ram vertical concatenation wd[35:0] wa[8:0] wen[3:0] wd_sel wclk ra[8:0] rd_sel rclk wd[17:0] wa[8:0] wen[1:0] wd_sel wclk ra[8:0] rd_sel rclk rd[17:0]
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 6 figure 5: 512x18 4-kilobit true dual-port ram block table 5: true dual-port ram interface signals port signal name function port1 inputs port1_wd[17:0] write data port1_a[8:0] write address port1_wen[1:0] write enable port1_cs chip select port1_clk clock output port1_rd[17:0] read data port2 inputs port2_wd[17:0] write data port2_a[8:0] write address port2_wen[1:0] write enable port2_cs chip select port2_clk clock output port2_rd[17:0] read data table 6: available true dual-port ram configurations device depth width ql1p100 512 1-18 1024 1-9 rd[17:0] wd[17:0] wa[8:0] wen[1:0] wd_sel wclk ra[8:0] rd_sel rclk
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 7 embedded fifo controllers every 4-kilobit ram block can be implemented as a synchro nous or asynchronous fifo. there are built-in fifo controllers that allow for varying depths and wi dths without requiring programmable fabric resources. the polarpro fifo controller features include: ? x9, x18 and x36 data bus widths ? independent push and pop clocks ? independent programmable data width on push and pop sides ? configurable synchronous or asynchronous fifo operation ? 4-bit push and pop level indicators to provide fifo status outputs for each port ? pipelined read data to improve timing figure 6: fifo module table 7: available fifo configurations device number of ram blocks depth supported widths ql1p100 1 256 1-18 bits 1 512 1-9 bits 2 256 1-36 bits 2 512 1-18 bits 2 1024 1-9 bits din[x:0] push fifo_push_flush push_clk pop fifo_pop_flush pop_clk dout[x:0] almost_full almost_empty push_flag[3:0] pop_flag[3:0] a a a. x = {1,2,3,....35}.
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 8 table 8 lists the fifo controller interface signals. table 9 and table 10 highlight the corresponding fifo level indi cator for each 4-bit value of the push_flag and pop_flag outputs. table 8: fifo interface signals signal name width (bits) direction function push signals din 1 to 36 i data bus input push 1 i initiates a data push fifo_push_flush 1 i empties the fifo push_clk 1 i push data clock pop signals dout 1 to 36 o data bus output pop 1 i initiates a data pop fifo_pop_flush 1 i empties the fifo pop_clk 1 i pop data clock status flags almost_full 1 o asserted when fifo has one location available almost_empty 1 o asserted when fifo has one location used push_flag[3:0] 4 o fifo push level indicator pop_flag[3:0] 4 o fifo pop level indicator table 9: fifo push level indicator values value status 0000 full 0001 empty 0010 room for more than one-half 0011 room for more than one-forth 1000 room for 8 or more 1001 room for 7 1010 room for 6 1011 room for 5 1100 room for 4 1101 room for 3 1110 room for 2 1111 room for 1 others reserved
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 9 fifo flush procedure when a flush is triggered from one side of the fifo, th e signal propagates and re-synchronizes internally to the other clock domain. during a flush operation, the valu es of the fifo flags are invalid for a specific number of cycles (see figure 7 and figure 8 ). as shown in figure 7 , when the fifo_push_flush asserts, the almost_full and push_flag signals become invalid until the fifo can flush the data with re gards to the push clock domain as well as the pop clock domain. after the fifo_push_flush is asserted, the next rising edge of the pop clock starts the pop flush routine. figure 7 illustrates a fifo flush operation. after the fifo_push_flush is asserted at 2 ( push_clk ), four pop clock cycles (12 through 15) are required to update the pop_flag , and push_flag signals. the almost_empty signal is asserted to indicate that the pu sh flush operation has been completed. on the following rising edge of the push_clk (8), the push_flag is accordingly updated to reflect the successful flush operation. table 10: fifo pop level interface signals value status 0000 empty 0001 1 entry in fifo 0010 2 entries in fifo 0011 3 entries in fifo 0100 4 entries in fifo 0101 5 entries in fifo 0110 6 entries in fifo 0111 7 entries in fifo 1000 8 or more entries in fifo 1101 one-forth or more full 1110 one-half or more full 1111 full others reserved
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 10 figure 7: fifo flush from push side figure 8 illustrates a pop flush operation. after the fifo_pop_flush is asserted at 2 ( pop_clk ), four push clock cycles (12 through 15) are required to update the pop_flag , and push_flag signals. the almost_empty signal is asserted to indicate that the po p flush operation has been completed. on the following rising edge of the pop_clk (8), the pop_flag is updated accordingly to reflect the successful flush operation. figure 8: fifo flush from pop side figure 7 and figure 8 are only true for this particular push-p op clock frequency combination. the clock frequency and phase difference between pop_clk and pu sh_clk can cause an additional flush delay of one clock cycle in either domain because of the as ynchronous relationship between the two clocks. push_clk fifo_push_flush pop_clk almost_full push_flag valid almost_empty pop_flag 0000 (empty) earliest push valid valid 12 3456 8 7910 11 12 13 14 15 16 invalid invalid invalid pop_clk fifo_pop_flush push_clk almost_empty pop_flag 0000 (empty) almost_full push_flag valid invalid valid valid earliest push invalid 1 10 23456789 11 12 13 14 15 16 invalid
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 11 86-pin tfbga ql1p100 clock network architecture clock network architecture the polarpro clock network architectu re consists of a 2-leve l h-tree network as shown in figure 9. the first level of each clock tree (high-lighted in red) spans from the clock input pad to the global clock network and to the center of each quadrant of the chip. the second le vel (high-lighted in blue) sp ans from the quadrant clock network to every logic cell inside that quadrant. there ar e five global clocks in th e global clock network, and five quadrant clocks in each quadrant clock network. all global clocks drive the quadrant clock network inputs. the quadrant clocks output to clock in version muxes, which pass either the original input clock or an inverted version of the input clock to the logic cells in that quadrant. the global cl ocks can drive ram block clock inputs and reset, set, enable, and clock inputs to i/o registers. furthermore, the quadrant cl ock outputs can be routed to all logic cell inputs. figure 9: polarpro clock architecture of the five global clock networks, four can be either driven directly by clock pads, configurable clock manager (ccm) outputs, or internally generated signals. these fo ur global clocks go through 3-input global clock muxes located in the middle of the die. see figure 10 for a diagram of a 3-input glob al clock mux. the fifth is a dedicated global clock network that goes directly to the quadrant clock network and is used as a dedicated fast clock. quadrant clock network global clock network x4 x4 x4 x4 x4 inversion mux quadrant clock network quadrant clock network quadrant clock network
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 12 figure 10: global clock structure figure 11 illustrates the quadrant clock 2-input mux. figure 11: quadrant clock structure it is important to note that the select lines for the gl obal clock and quadrant clock muxes are static signals and cannot be changed dynamically during device operation. for more information about global and quadrant clock networks and how to use them, refer to application note 85 clock networks in polarpro devices . inte r na l ly ge ne ra te d c loc k , or cloc k from general routing network global clock (clk ) input pad t o quadrant c loc k s tructure g loba l c loc k b uffer ccm output 2-bit select inte r na l ly ge ne ra te d c loc k , or cloc k from general routing network t o invers ion mux, then logic cells logic cell q ua dra nt c loc k b uffer f rom g lobal clock buffer 1-bit select
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 13 configurable clock manager (ccm) the ccm features include: ? input frequency range from 10 mhz to 200 mhz ? output frequency range from 25 mhz to 200 mhz ? output jitter is less than 200 ps peak-to-peak ? two outputs: pullout0 (with 0 ph ase shift), and pullout1 (with an op tion of 0, 90, 180, or 270 phase shift plus a programmable delay). ? programmable delay allows delays up to 2.5 ns at 250 ps intervals ? fixed feedback path ? output frequency lock time in less than 10 s figure 12: configurable clock manager the reset signal can be routed from a clock pad or gene rated using internal logic. the lock_out signal can be routed to internal logic and/or an output pad. ccm cl ock outputs can drive the glob al clock networks, as well as any general purpose i/o pin. once the ccm has sync hronized the output clock to the incoming clock, the lock_out signal will be asserted to indicate that the outp ut clock is valid. lock detection requires at least 10 s after reset to assert lock_out. the polarpro ccms have three modes of operation, based on the input frequency and desired output frequency. table 11 indicates the features of each mode. table 11: ccm pll mode frequencies output frequency input frequency range output frequency range pll mode x1 25 mhz to 200 mhz 25 mhz to 200 mhz pll_mult1 x2 15 mhz to 100 mhz 30 mhz to 200 mhz pll_mult2 x4 10 mhz to 50 mhz 40 mhz to 200 mhz pll_mult4 pllout0 ded_in pgm_in n_cnt ded_fd pgm_fd fd_cnt rst_in fc[1:0] s[1:0] tdctl[3:0] pllout1 lock_out
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 14 ccm signals table 12 provides the name, direction, functi on and description of the ccm ports. table 13 , table 14 and table 15 give the values used to configure the set mode, phase shift control and time delay control bits. table 12: ccm signals signal name direction function description routable ports ded_in i dedicated input clock pad ccm input source. ded_fd i dedicated feedback automatically calculated and routed by the software tools. rst_in i reset active high reset: if rst_in is asserted, pllout0 and pllout1 are reset to 0. this signal must be asserted and then released for lock_out to assert. pllout0 o 0 phase clock 0 phase clock output. pllout1 o configurable phase clock 0, 90,180, or 270 phase clock output with programmable delay. lock_out o lock detect active high lock detection signal. active when the pllout signals correctly output t he configured functionality. static ports fc[1:0] i phase shift control determines whether pllout1 is 0, 90, 180, or 270 degrees out of phase with pllout0 a . a. the pllout1 output can vary up to -5% with respect to t he pllout0 output. therefore, quicklogic recommends thorough post-lay out simulation in order to verify satisfactory operation of the ccms. s[1:0] i set mode determines pllout1 and pllout0 frequency multiplier (x1, x2, or x4). tdctl[3:0] i time delay control pllout1 programmable delay, configurable in 250 ps increments up to a maximum of 2.5 ns. note: 250 ps can vary depending on process variation. table 13: set mode values s[1:0] multiplier 00 x1 01 x2 10 x4 11 reserved table 14: phase shift control values fc[1:0] phase shift (deg.) 00 0 01 90 10 180 11 270
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 15 ccm configurations the main purpose of the ccm is to align the clock arri val times of two separate clock destinations, whether it is within the fpga or external to the chip. the diffe rence between the two clock destinations is referred to as clock skew. to correct for clock skew the ccms can be configured to shift the phase and/or delay of the pllout1 clock output. in most cases the desired phase or added delay can be ac complished by configuring bo th the clock source input and feedback input as dedicated. in the case of a dedicated clock source and dedicated feedback, the quicklogic development software calcul ates and generates all of the requir ed routing delays to produce the requested configuration. for more information on ccms and how to use them in quickworks, refer to application note 87 configurable clock managers . table 15: time delay control values tdctl[3:0] time delay (ps) 0000 0 0001 250 0010 500 0011 750 0100 1000 0101 1250 0110 1500 0111 1750 1000 2000 1001 2250 1010 2500 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 16: available configurations clock feedback example usage comments dedicated clock pad dedicated feedback standard pll application. reduce set-up or clock-to-out time. if the clock pad and destination are in phase.
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 16 general purpose input output (gpio) cell structure the gpio features include: ? direct or registered input with input path select ? direct or registered output with output path select ? direct or registered output enable with oe path select ? input buffer enable to reduce power ? programmable weak keeper, programmable pull-up/pull-down control ? programmable drive strength ? configurable slew rate ? support for jtag boundary scan figure 13: polarpro gpio cell fixhold logic dq d q dq outz outrz_en osel oez esel inz isel inrz_en fixhold rst clk di_en pbe pbd pbk i/o pad slew[1:0] p[3:0] weak pull-up/pull-down controller slew rate & drive strength logic
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 17 with bi-directional i/o pins and global clock input pins, the polarpro device maximizes i/o performance, functionality, and flexibility. all input and i/o pins are 1.8 v, 2.5 v, and 3.3 v tolerant and comply with the specific i/o standard selected. for single-ended i/o standard s, the corresponding vcci o bank input specifies the input tolerance and the output drive voltage. drive strength and slew rate are configured for an entire bank. weak keeper, pull-up, and pull-down functions can be c onfigured for individual i/o. the default configuration for quicklogic quickworks softwar e has the drive strength set to 4 and the slew rate set to wow. table 17: gpio interface signals signal name direction function routable signals outz i data out from internal logic outrz_en i enable for registered outz oez i tristate enable for the output signal inz o input signal to the internal logic inrz_en i enable for registered inz rst i reset for optional registers clk i clock signal for optional registers di_en i enable for i/o input signal. drives a 1 to internal logic when disabled. static signals slew[1:0] i 2-bit slew rate control p[3:0] i programmable drive strength osel i select signal for registered or flow through outz esel i select signal for registered or flow-through oez isel i select signal for registered or flow-through inz fixhold i enable control for i/o input delay for hold fixing pbe i input signals for the weak keeper, pull-up/pull-down controller, see table 18 for functional behavior pbd i pbk i
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 18 programmable weak keeper, pull-up, and pull-down a programmable weak keeper, pull-up or pull-down contro ller is also available on each general purpose i/o bank. when implementing the weak keeper, pull-up, an d pull-down functions, eac h i/o can be configured separately. the i/o weak pull-up and pull-down eliminates the need for external resistors. when pbk=1 the keeper block is placed into keeper mode. in the keeper mode , the pad pin (if the driver is tristated), will be kept at whichever level it was last forced, either by the driver itself, or by an external driver. programmable drive strength every gpio has independent drive strength control. twel ve different drive strength levels are available for designers to choose from. for additional info rmation about corresponding drive strength see dc characteristics on page 20. programmable slew rate each i/o has programmable slew rate capability. the po larpro gpios allow up to four different slew rate speeds (slow, fast, vfast, and wow). sl ower slew rates can be used to redu ce noise caused by i/o switching. i/o interface standards are programmable on a per bank basis. table 19 illustrates the i/o bank configurations available. each i/o bank is independent of other i/o banks and each i/o bank has its own vccio supply inputs. a mixture of diffe rent i/o standards can be used on a polarpro device. however, there is a limitation as to which i/o standards can be supp orted within a given bank. on ly standards that share a common vccio can be shared within the same bank (e.g., pci and lvttl). table 18: weak pull-up, and pull-down controller pbk pbd pbe function 0 0 0 tristate (floating) 0 0 1 weak pull-down 0 1 1 weak pull-up 1 x x weak keeper (retains state) 0 1 0 reserved table 19: i/o standards and applications i/o standard vccio voltage application lvttl 3.3 v general purpose lv c m o s 2 5 2.5 v general purpose lvcmos18 1.8 v general purpose pci 3.3 v pci bus applications
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 19 very low power (vlp) mode the quicklogic polarpro devices have a unique feat ure, referred to as vlp mode, which reduces power consumption by placing the device in standby. specific ally, vlp mode can bring the total standby current down to less than 10 a at room temperature when no incoming signals are toggled. vlp mode is controlled by the vlp pin. the vlp pin is active low, so vlp mode is activated by pulling the vlp pin to ground. conversely, the vlp pin must be pulled to 3.3 v for normal operation. when a polarpro device goes into vlp mode, the following occurs: ? all logic cell registers and gpio registers values are held ? all ram cell data is retained ? the outputs from all gpio to the in ternal logic are tied to a weak ?1? ? gpio outputs drive the previous values ? gpio output enables retain the previous values ? ddrio outputs are pulled down through a weak pull down circuit ? clock pad inputs are gated ? ccms are held in the reset state the entire operation from normal mode to vlp mode requires 250 s (300 s maximum). as mentioned in the vlp behavioral description above, the output of the gpio to the internal logic is a weak ?1?. therefore, to preserve data retention gpio should not be used for a set, reset, or clock signal. during the transition from vlp mode to normal operation, the vlp pin can draw up to 1.5 ma. consequently, if using a pull-up resistor, use a pull-up resistor with a value that is less than 2 k . as the device exits out of vlp mode, the data from the registers, ram, and gpio will be used to recover the functionality of the device. furthermore, since the ccms we re in a reset state during vlp mode, they will have to re-acquire the correct output signals before assertin g lock_out. the time required to go from vlp mode to normal operation is 250 s (300 s maximum). figure 14 displays the delays asso ciated with entering and exiting vlp mode. figure 14: typical vlp mode timing ?
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 20 electrical specifications dc characteristics the dc specifications are provided in table 20 through table 23 . table 20: absolute maximum ratings parameter value parameter value vcc voltage -0.5 v to 2.2 v latch-up immunity 100 ma vccio voltage -0.5 v to 4.0 v esd pad protection 2 kv vref voltage -0.5 v to 2.0 v leaded package storage temperature -65 c to + 150 c input voltage -0.5 v to 4.0 v laminate package (bga) storage temperature -55 c to + 125 c table 21: recommended operating range symbol parameter military industrial commercial unit min. max. min. max. min. max. vcc supply voltage 1.71 1.89 1.71 1.89 1.71 1.89 v vccio i/o input tolerance voltage 1.71 3.60 1.71 3.60 1.71 3.60 v tj junction temperature -55 125 -40 100 0 85 c table 22: dc characteristics symbol parameter conditions min. typ. max. units i l i or i/o input leakage current vi = vccio or gnd - - 1 a i oz 3-state output leakage curr ent vi = vccio or gnd - - 1 a c i i/o input capacitance vccio = 3.6 v - - 10 pf c clock clock input capacitance vccio = 3.6 v - - 10 pf i ref quiescent current on inref - - - 5 a i pd current on programmable pull-down vccio = 3.6 v -200 - -50 a vccio = 2.75 v -150 - -25 a vccio = 1.89 v -100 - -10 a i pu current on programmable pull-up vccio = 3.6 v 50 - 200 a vccio = 2.75 v 25 - 150 a vccio = 1.89 v 10 - 100 a i vlp quiescent current on vlp pin vlp=3.3 - 1 10 a i ccm quiescent current on each ccmvcc vcc=1.89 v - 1 10 a i vcc quiescent current a a. quiescent current values correspond to the ql1p100. vlp=gnd - 2.2 40 a vlp=3.3v - 40 100 a i vccio quiescent current on vccio vccio = 3.6 v - 2 10 a vccio = 2.75 v - 2 10 a vccio = 1.89 v - 2 10 a
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 21 table 24 lists the worst case process (t j =125c) output currents (in ma) ac ross the output driver at three levels of i/o voltages. al l drive strength data was measured at i/o voltages of 0.4 v and vccio - 0.4 v. table 23: dc input and output levels a a. the data provided in table 23 represents the jedec and pc i specification. quicklogic devices either meet or exceed these requirements. symbol inref v il v ih v ol v oh i ol i oh v min v max v min v max v min v max v max v min ma ma lv t t l n/a n/a -0.3 0.8 2.2 vccio + 0.3 0.4 2.4 2.0 -2.0 lv c m o s 2 n/a n/a -0.3 0.7 1.7 vccio + 0.3 0.7 1.7 2.0 -2.0 lv c m o s 1 8 n/a n/a -0.3 0.63 1.2 vccio + 0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 inref - 0.2 inref + 0.2 vccio + 0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3 x vccio 0.6 x v ccio vccio + 0.5 0.1 x vccio 0.9 x vccio 1.5 -0.5 sstl2 1.15 1.35 -0.3 inref - 0.18 inref + 0.18 vccio + 0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 inref - 0.2 inref + 0.2 vccio + 0.3 1.10 1.90 8 -8 table 24: gpio programmable drive strength drive strength ioh (ma) iol (ma) 1.8v 2.5v 3.3v 1.8v 2.5v 3.3v 1 2.2 2.8 3.2 1.7 2.3 2.7 2 4.1 5.2 5.9 3.4 4.4 5 3 6.2 7.8 8.8 5.1 6.7 7.6 4 8 10 11.2 6.6 8.6 9.7 5 10 12.4 13.9 8.3 10.7 12.1 6 11.8 14.6 16.3 9.8 12.7 14.2 7 13.7 16.9 18.9 11.5 14.7 16.6 8 15.3 18.9 21 12.9 16.5 18.5 9 17.1 21.1 23.4 14.5 18.5 20.7 10 18.8 23 25.5 15.9 20.2 22.6 11 20 25 27.6 17.4 22 24.6 12 21.7 26.4 29.1 18.6 23.5 26.1 n/a reserved
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 22 figure 15 and figure 16 illustrate quiescent current for ql1p100 with vlp = 0 v and 3.3 v. figure 15: quiescent current for ql1p100 with vlp = 0 v figure 16: quiescent current for ql1p100 with vlp = 3.3 v polarpro quiescent current 0 5 10 15 20 25 30 35 40 -40c 0c 25c 70c 85c 90c ambient temperature (c) current ( icc: vcc = 1.8v iccio: vccio = 3.6v iccm: ccmvcc = 1.8v polarpro quiescent current 0 20 40 60 80 100 120 140 -40c 0c 25c 70c 85c 90c ambient temperature (c) current ( icc: vcc = 1.8v iccio: vccio = 3.6v iccm: ccmvcc = 1.8v
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 23 ac characteristics ac specifications are provided in table 25 through table 37 . logic cell diagrams and waveforms are provided in figure 17 through figure 30 . all of the following ac timing nu mbers are for worst case commercial (t = 85c junction, v= 1.71v), and worst case indu strial (t = 100c juncti on, v=1.71v) conditions. figure 17: polarpro logic cell 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 d e q r s tz cz qz fz qds qst tbs tab tsl ti ta1 ta2 tb1 tb2 bab bsl bi ba1 ba2 bb1 bb2 fs f1 f2 qdi qen qck qrt
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 24 figure 18: logic cell flip-flop timings?first waveform table 25: logic cell delays symbol parameter commercial industrial min. max. min. max. t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output 0.32 ns 0.59 ns 0.34 ns 0.62 ns t su setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 0.23 ns 0.56 ns 0.24 ns 0.58 ns t hl hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns n/a 0 ns n/a t esu enable setup time: time the enable input of the flip-flop must be stable before the active clock edge 0.23 ns 0.85 ns 0.89 ns 0.24 ns t ehl enable hold time: time the enable input of the flip-flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t co clock-to-out delay: the amount of time taken by the flip- flop to output after the active clock edge. 0.48 ns 0.52 ns 0.50 ns 0.55 ns t cwhi clock high time: required minimum time the clock stays high 0.46 ns 0.46 ns 0.46 ns 0.46 ns t cwlo clock low time: required minimum time that the clock stays low 0.46 ns 0.46 ns 0.46 ns 0.46 ns t set set delay: time between when the flip-flop is ?set? (high) and when the output is consequently ?set? (high) 0.60 ns 0.60 ns 0.61 ns 0.61 ns t reset reset delay: time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) 0.68 ns 0.68 ns 0.71 ns 0.71 ns t sw set width: time that the set signal must remain high/low 0.30 ns 0.30 ns 0.30 ns 0.30 ns t rw reset width: time that the reset signal must remain high/low 0.30 ns 0.30 ns 0.30 ns 0.30 ns t reset t sw t rw t set clk qst (set) qrt (reset) q t cwhi (min) t cwlo (min)
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 25 figure 19: logic cell flip-flop timings?second waveform figure 20: polarpro clock network table 26: polarpro tree clock delay clock segment parameter commercial industrial min. max. min. max. t pgck delay from global clock pad input to quadrant network 1.54 ns 1.86 ns 1.56 ns 1.88 ns t pdck delay from dedicated clock pad input to quadrant network 1.4 ns 1.66 ns 1.42 ns 1.68 ns t bgck global clock tree delay (quad net to flip-flop) 20 ps 200 ps 30 ps 220 ps t gskew global delay clock skew 30 ps 190 ps 40 ps 200 ps t dskew dedicated clock skew 30 ps 190 ps 40 ps 200 ps t su t co clk d q t hl quadrant clock network global clock network x4 x4 x4 x4 x4 inversion mux quadrant clock network quadrant clock network quadrant clock network
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 26 ram timing figure 21: ram module table 27: ram cell synchronous write timing symbol parameter commercial industrial min. max. min. max. t swa wa setup time to wclk: time the write address must be stable before the active edge of the write clock 0.29 ns 1.10 ns 0.31 ns 1.28 ns t hwa wa hold time to wclk: ti me the write address must be stable after the active edge of the write clock 0 ns 0.21 ns 0 ns 0.20 ns t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 0.31 ns 1.74 ns 0.40 ns 2.21 ns t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0 ns 0.22 ns 0 ns 0.17 ns t sws wd_sel setup time to wc lk: time write chip select must be stable before the active edge of the write clock 0.42 ns 1.10 ns 0.49 ns 1.28 ns t hws wd_sel hold time to wclk : time write chip select must be stable after the acti ve edge of the write clock 0 ns 0.04 ns 0 ns 0.04 ns t swe wen setup time to wclk: time the write enable must be stable before the active edge of the write clock 0.63 ns 1.10 ns 0.74 ns 1.28 ns t hwe wen hold time to wclk: time the write enable must be stable after the active edge of the write clock 0 ns 0 ns 0 ns 0 ns rd[17:0] wd[17:0] wa[8:0] wen[1:0] wd_sel wclk ra[8:0] rd_sel rclk
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 27 figure 22: ram cell write timing table 28: ram cell synchronous read timing symbol parameter commercial industrial min. max. min. max. t sra ra setup time to rclk: time the read address must be stable before the active edge of the read clock 0.29 ns 1.10 ns 0.31 ns 1.28 ns t hra ra hold time to rclk: time the read address must be stable after the active edge of the read clock 0 ns 0.21 ns 0 ns 0.20 ns t srs rd_sel setup time to rclk: time the read chip select must be stable before the active edge of the read clock 0.42 ns 1.10 ns 0.49 ns 1.28 ns t hrs rd_sel hold time to rclk: time the read chip select must be stable after the active edge of the read clock 0 ns 0.04 ns 0 ns 0.04 ns t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd 2.62 ns 5.67 ns 2.69 ns 5.88 ns t swa t hwa t swd t hwd t sws t hws wclk wa wd wd_sel t swe t hwe wen
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 28 figure 23: ram cell read timing fifo timing figure 24: fifo module t sra t hra t srs t hrs t rcrd rclk ra rd_sel rd new data old data din[x:0] push fifo_push_flush push_clk pop fifo_pop_flush pop_clk dout[x:0] almost_full almost_empty push_flag[3:0] pop_flag[3:0] a a a. x = {1,2,3,....35}.
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 29 figure 25: fifo push timing table 29: fifo push timing symbol parameter commercial industrial min. max. min. max. t spushd din setup time to push_clk: time din must be stable before the active edge of the fifo push clock 0.31 ns 1.74 ns 0.40 ns 2.21 ns t hpushd din hold time to push_clk: time din must be stable after the active edge of the fifo push clock 0 ns 0.22 ns 0 ns 0.17 ns t spushen push setup time to push_clk : time push must be stable before the active edge of the fifo push clock 1.07 ns 1.57 ns 1.38 ns 2.0 ns t hpushen push hold time to push_clk: time push must be stable after the active edge of the fifo push clock 0 ns 0 ns 0 ns 0 ns t spushflush flush setup time to push_clk: time fifo_push_flush must be stable before the active edge of the fifo push clock 1.11 ns 1.74 ns 1.43 ns 2.21 ns t hpushflush flush hold time to push_clk: time fifo_push_flush must be stable after the active edge of the fifo push clock 0 ns 0 ns 0 ns 0 ns t coaf clock-to-out of almost full 2.66 ns 3.34 ns 2.72 ns 3.42 ns t copushflag clock-to-out of fifo push level indicator 2.36 ns 4.20 ns 2.41 ns 4.32 ns push_clk din[x:0] push push_flag new status old status fifo_push_flush almost_full t spushd t hpushd t spushen t hpsuhen t hpush flush t spush flush t coaf t copushflag
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 30 figure 26: fifo pop timing table 30: fifo pop timing symbol parameter commercial industrial min. max. min. max. t spopen pop setup time to pop_clk: time pop must be stable before the active edge of the fifo pop clock 1.01 ns 1.13 ns 1.19 ns 1.32 ns t hpopen pop hold time to pop_clk: time pop must be stable after the active edge of the fifo pop clock 0 ns 0 ns 0 ns 0 ns t spopflush flush setup time to pop_clk: time fifo_pop_flush must be stable before the active edge of the fifo pop clock 1.11 ns 1.74 ns 1.43 ns 2.21 ns t hpopflush flush hold time to pop_clk: time fifo_pop_flush must be stable after the active edge of the fifo pop clock 0 ns 0 ns 0 ns 0 ns t fpop pop_clk to pop: clock-to-out from the active fifo clock edge and the time when the data is popped from the fifo at dout 2.32 ns 5.61 ns 2.37 ns 5.88 ns t coae clock-to-out of almost empty 2.64 ns 3.58 ns 2.70 ns 3.66 ns t copopflag clock-to-out of fifo pop level indi cator 2.32 ns 3.93 ns 2.38 ns 4.03 ns pop_clk dout[x:0] pop pop_flag new status old status fifo_pop_flush almost_empty t spopen t hpopen t spop flush t hpop flush t copop t coae t copopflag
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 31 gpio cell timing figure 27: polarpro i/o cell output path figure 28: polarpro i/o cell output enable timing fixhold logic dq d q dq outz outrz_en osel oez esel inz isel inrz_en fixhold rst clk di_en i/o pad enrz_en t outhl t outlh t pzl t pzh t plz t phz
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 32 table 34 lists the typical output slew rates (in v/ns) across th ree levels of output voltages, with a drive strength of 4, and a load capacitor of 10 pf. table 31: output timing characteristics @ vccio = 3.3 v, t = 25 ? c symbol parameter value (ns) slowest slew max. fastest slew max. t outlh output delay low to high (90% of h) 8.10 1.00 t outhl output delay high to low (10% of l) 9.60 0.90 t pzh output delay tri-state to high (90% of h) 3.40 0.30 t pzl output delay tri-state to low (10% of l) 3.90 0.30 t phz output delay high to tri-state 3.60 0.36 t plz output delay low to tri-state 4.1 0.41 table 32: output timing characteristics @ vccio = 2.5 v, t = 25 ? c symbol parameter value (ns) slowest slew max. fastest slew max. t outlh output delay low to high (90% of h) 12.20 1.10 t outhl output delay high to low (10% of l) 18.80 1.00 t pzh output delay tri-state to high (90% of h) 4.50 0.45 t pzl output delay tri-state to low (10% of l) 8.40 0.52 t phz output delay high to tri-state 8.10 0.52 t plz output delay low to tri-state 5.30 0.53 table 33: output timing characteristics @ vccio = 1.8 v, t = 25 ? c symbol parameter value (ns) slowest slew max. fastest slew max. t outlh output delay low to high (90% of h) 2.50 2.20 t outhl output delay high to low (10% of l) 1.70 1.40 t pzh output delay tri-state to high (90% of h) 8.30 0.70 t pzl output delay tri-state to low (10% of l) 24.70 1.05 t phz output delay high to tri-state 23.50 1.25 t plz output delay low to tri-state 10.80 0.78 table 34: gpio output slew rate slew output slew rate (v/ns) at vccio = 1.8 v 2.5 v 3.3 v slow n/a 0.20 0.36 fast n/a 0.31 0.66 vfast0.170.611.32 wow 0.25 1.18 2.03
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 33 table 35: i/o output register cell timing symbol parameter commercial industrial min. max. min. max. t osu output register setup time : time the synchronous outz input of the flip-f lop must be stable before the active clock edge 0.33 ns 0.38 ns 0.34 ns 0.36 ns t ohl output register hold time: time the synchronous outz input of the flip-flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t oco output register clock-to-out: time taken by the flip-flop to output after the active clock edge 5.25 ns 5.99 ns 5.46 ns 6.29 ns t orst output register reset delay: time between when the flip- flop is ?reset? (low) and when the output is consequently ?reset? (low) 5.85 ns 5.85 ns 6.03 ns 6.03 ns t oesu output register clock enable setup time: time outrz_en must be stable before the active clock edge 0.33 ns 0.51 ns 0.30 ns 0.54 ns t oeh output register clock enable hold time: time outrz_en must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t oezsu output register clock enable setup time: time oez must be stable before the active clock edge 0.14 ns 0.20 ns 0.15 ns 0.18 ns t oezh output register clock enable hold time: time oez must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t opd output signal propagation delay: propagation delay of outz to the output pad 4.82 ns 5.44 ns 5.03 ns 5.72 ns
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 34 figure 29: polarpro i/o cell input path figure 30: polarpro input register cell timing fixhold logic dq d q dq outz outrz_en osel oez esel inz isel inrz_en fixhold rst clk di_en i/o pad enrz_en clk rst d q e t irst t ieh t iesu t ico t ihl t isu
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 35 table 36: i/o in put register cell timing symbol parameter commercial industrial min. max. min. max. t isu input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 2.51 ns 2.85 ns 2.80 ns 2.82 ns t ihl input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t ico input register clock-to-out: time taken by the flip-flop to output after the active clock edge 1.68 ns 2.66 ns 1.58 ns 2.70 ns t irst input register reset delay: time between when the flip- flop is ?reset? (low) and when the output is consequently ?reset? (low) 1.59 ns 1.59 ns 1.53 ns 1.53 ns t iesu input register clock enable setup time: time inrz_en must be stable before the active clock edge 0.25 ns 0.40 ns 0.23 ns 0.43 ns t ieh input register clock enable hold time: time inrz_en must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t idiensu input data enable setup time: time di_en must be stable before the active clock edge 2.39 ns 5.38 ns 2.28 ns 5.63 ns t idienh input data enable hold time: time di_en must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t ifhsu input fixhold setup time: ti me fixhold must be stable before the active clock edge 2.39 ns 5.38 ns 2.28 ns 5.63 ns t ifhh input fixhold hold time: time fixhold must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns table 37: i/o input buffer delays symbol parameter value to get the total input delay add this delay to t isu min. max. t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications tbd tbd t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications tbd tbd t sid (lvcmos18) lvcmos18 input delay: low volta ge cmos for 1.8 v applications tbd tbd t sid (gtl+) gtl+ input delay: gunning transceiver logic tbd tbd t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v tbd tbd t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5 v tbd tbd t sid (pci) pci input delay: peripheral co mponent interconnect for 3.3 v tbd tbd
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 36 package thermal characteristics the polarpro device is available for commercial (0c to 85c junction), industrial (-40c to 100c junction), and military (-55c to 125c junction) temperature ranges. thermal resistance equations: ? ja = (tj - ta)/p p max = (t jmax - t amax )/ ? ja parameter description: ? ja : junction-to-ambient thermal resistance t j : junction temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power dissipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: maximum junction temperature (t jmax ) is 125c. to calculate the maximum power dissipation for a device package look up ? ja from table 38 , pick an appropriate t amax and use: p max = (125c - t amax ) / ? ja moisture sensitivity level all polarpro devices are moisture sensitivity level 3. table 38: package thermal characteristics package description theta-ja ( c/w) device package code package type pin count 0 lfm 200 lfm 400 lfm ql1p100 pu tfbga a a. thin profile fine pitch ball grid array 86 58 50 48 table 39: solder and lead finish composition lead included lead-free bga solder 63% pb, 37% sn sn3agcu:sn4agcu a a. sn3agcu:sn4agcu means that ag can r ange from 3% to 4%. cu is always 0.5%.
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 37 power-up sequencing figure 31: power-up sequencing figure 31 shows an example where all vccio = 3.3 v. when powering up a polarp ro device, vcc, vccio rails must take 10 s or longer to reach the maximum value (refer to figure 31 ). ramping vcc and vccio faster than 10 s can cause the device to behave improperly . it is also important to ensure vccio and vlp ar e within 500 mv of vcc when ramping up the power supplies. in the case where vccio or vlp are greater than vcc by more than 500 mv an additional current draw can occur as vcc passes its threshold voltage. in a case where vcc is greater than vccio by more than 500 mv the protection diodes between the power su pplies become forward biased . if this occurs then there will be an additional current load on the powe r supply. having the diodes on can cause a reliability problem, since it can wear out the di odes and subsequently damage the internal transistors. as noted in the vlp section, during the transition from vlp mode to normal operation, the vlp pin can draw up to 1.5 ma. consequently, if using a pull-up re sistor, use a pull-up resistor with a value that is less than 2 k . programming stipulation for polarpro devices to correctly program, there must not be any race conditions or internally generated free- running oscillators in the design. this will cause an icc programming failure during the programming process. quicklogic cannot guarantee the operation of any device that fails programming. therefore, race conditions and free-running oscillators must be removed from de signs so that polarpro devices can correctly pass programming. voltage v ccio ,vlp v cc |v ccio - v cc | max time 10 us v cc ?
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 38 pin descriptions table 40: pin descriptions pin direction function description dedicated pin descriptions gpio(c:a) i/o general purpose input/output pin the i/o pin is a bi-directional pin, configurable to either an input-only, output-only, or bi -directional pin. the letter inside the parenthesis means that the i/o is located in the bank with that letter. if an i/ o is not used, the development software provides the option of tying that pin to gnd, vccio, or hi-z. clk(c:a) i global clock network pin low skew global clock this pin provides access to a distributed network capable of driving the cloc k, set, reset, all in puts to the logic cell, read and write clocks, read and write enables of the embedded ram blocks, and i/o inputs. the voltage tolerance of this pin is specified by vccio(c:a). dedclk(d) i dedicated clock network pin low skew clock this pin provides access to a distributed network capable of driving the cloc k, set, reset, all in puts to the logic cell, read and write clocks, read and write enables of the embedded ram blocks, and i/o inputs. the voltage tolerance of this pin is specified by vccio(d). ccmin(1:0) i ccm clock input input clock for ccm. the voltage tolerance for this pin is specified by the vccio of the same bank. ccmvcc (1:0) i power supply pin for ccm ccm input voltage level. configurable as 1.8 v only. ccmgnd(1:0) i ground pin for ccm connect to ground. vlp i voltage low power active low. therefore, when vlp pin is low, the device will go into low power mode. tie vlp to 3.3 v to disable low power mode. vcc i power supply pin connect to 1.8 v supply. vccio(d:a) i input voltage tolerance pin this pin provides the flexibility to interface the device with either a 3.3 v, 2.5 v, or 1.8 v device. the letter inside the parenthesis means t hat the vccio is located in the bank with that letter. every i/o pin in the same bank will be tolerant of the same vcci o input signals and will drive vccio level output signals. this pin must be connected to either 3.3 v, 2.5 v, or 1.8 v. gnd i ground pin connect to ground.
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 39 recommended unused pin terminations for polarpro devices all unused, general purpose i/o pins can be tied to vccio, gnd, or hi-z (high impedance) internally. by default, quicklogic quickworks so ftware ties unused i/os to gnd. terminate the rest of the pins at the board level as recommended in table 41 . table 41: recommended unused pin terminations signal name recommended termination clk a a. x represents a, b, c or d. connect to gnd or vccio(x) if unused. vlp tie vlp to 3.3 v to disable low power mode. ccmvcc(1:0) if a ccm is not used, the corresponding ccmvcc may be tied to gnd to reduce power consumption. if a ccm is used, do not try to disable the ccm by tying the ccmvcc to gnd.
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 40 packaging pinout table polarpro ql1p100 ? 86 tfbga pinout table table 42: polarpro ql1p100 ? 86 tfbga pinout table pin function pin function pin function pin function a1 vcc c10 gpio(a) f9 gpio(a) j10 gpio(a) a2 gpio(d) d1 gpio(c) g1 clk(c) k1 gnd a3 gpio(d) d4 vccio(d) g2 vccio(b) k2 gpio(b) a5 gpio(d) d5 vcc g3 gpio(c) k3 gpio(b) a6 dedclk(d) d6 gpio(d) g4 vcc k4 gpio(b) a8 gpio(d) d7 gpio(d) g5 vccio(c) k6 gpio(b) a9 gpio(d) d9 gpio(a) g6 gnd k7 gpio(b) a11 vcc d11 gpio(a) g7 gnd k8 gpio(b) b1 gnd e1 gpio(c) g8 vcc k10 gpio(a) b2 gpio(c) e4 gpio(c) g10 gpio(a) k11 gpio(a) b3 gpio(d) e5 vccio(d) g11 clk(a)/ccmin(1) l1 vcc b4 gpio(d) e6 gnd h1 gpio(c) l2 gpio(b) b5 gpio(d) e7 gnd h2 gpio(c) l4 gpio(b) b6 gpio(d) e8 vccio(a) h5 vccio(c) l5 clk(b) b7 gpio(d) e9 vccio(a) h6 gnd l6 clk(b) b8 gpio(d) e11 gpio(a) h7 vccio(b) l7 gpio(b) b9 gpio(d) f1 gpio(c) h8 vccio(b) l8 gpio(b) b10 ccmgnd(1) f2 gpio(c) h9 vccio(b) l9 vlp b11 gnd f4 gnd h10 gpio(a) l10 gnd c2 gpio(c) f5 gnd h11 gpio(a) l11 vcc c3 gpio(c) f7 gnd j2 gpio(c) c9 ccmvcc(1) f8 vcc j4 gpio(b)
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 41 packaging pinout diagram polarpro ql1p100 ? 86 tfbga pinout diagram top bottom ql1p100-7pun86c
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 42 package mechanical drawing 86-pin tfbga packaging drawing
? 2010 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 rev. g 43 ordering information * lead-free packaging is denoted by the ch aracter 'n' preceding the number of pins. contact information phone: (408) 990-4000 (us) (647) 367-1014 (canada) +(44) 1932-21-3160 (europe) +(886) 2-2345-5600 (taiwan) +(86) 21-5116-0532 (china) e-mail: info@quicklogic.com sales: america-sales@quicklogic.com europe-sales@quicklogic.com asia-sales@quicklogic.com japan-sales@quicklogic.com support: www.quicklogic.com/support internet: www.quicklogic.com ql 1p100 -6 pu86 c operating range: c = commercial i = industrial m = military package lead count: pu86 (pun86)* = 86-pin tfbga (0.5mm) speed grade: -6 - fast -7 - faster -8 - fastest part number: 1p100 quicklogic device
www.quicklogic.com ? 2010 quicklogic corporation ? ? ? ? ? ? quicklogic ? polarpro ? device data sheet ? 86-pin tfbga ql1p100 44 revision history notice of disclaimer quicklogic is providing this design, produc t or intellectual property "as is." by providing the de sign, product or intellectual property as one possible implementation of your desired system-level feature, application, or standard, quicklogic makes no representation that this implementation is free from any claims of infringement and any implied warranties of merchantabil ity or fitness for a particula r purpose. you are responsible for obtaining any rights you may require for your system implementa tion. quicklogic shall not be liable for any damages arising out of or in connection with the use of the de sign, product or intellectual prop erty including liability for lo st profit, business interruption, or any other damages whatsoever . quicklogic products are not designed fo r use in life-support equipment or applic ations that would cause a life-threatening situation if any such products failed . do not use quicklogic pro ducts in these types of equ ipment or applications. quicklogic does not assume any liability for errors which may ap pear in this document. however, quicklogic attempts to notify customers of such errors. quicklogic retain s the right to make changes to either the documentation, specification, or product w ithout notice. verify with quicklogic that you have the latest specifications before finalizing a product design. copyright and trademark information copyright ? 2010 quicklogic corpor ation. all rights reserved. the information contained in this document is protected by copyright. all righ ts are reserved by quicklogic corporation. quickl ogic corporation reserves the right to modify this document without an y obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized rep resentative of quicklogic is prohibited. quicklogic, polarpro, and the polarpro design are registered trad emarks of quicklogic corporation; spde and quickworks and the quicklogic logo are trademarks of quicklogic corporation. ot her trademarks are the property of their respective companies. revision date originator and comments a july 2007 jason lew and kathleen murchek - first release. b august 2007 jason lew and kathleen murchek - updated mechanical drawing. c september 2007 jason lew and kathleen murchek - merged with other polarpro data sheets using conditional text. d january 2008 jason lew and kathleen murchek - logic cell delays table change t hl max. to n/a. e july 2008 jason lew and kathleen murchek - updated contact information. - updated copyright and trademark information. - added notice of disclaimer. f january 2010 kathleen murchek - added values for quiescent current in dc characteristics table. g september 2010 kathleen bylsma - updated contact information.

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