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document # sram110 rev c revised may 2009 p4c116/p4c116l ultra high speed 2k x 8 static cmos rams features full cmos, 6t cell high speed (equal access and cycle times) C 10/12/15/20/25/35 ns (commercial) C 12/15/20/25/35 ns (industrial) C 15/20/25/35 ns (military) low power operation output enable control function single 5v10% power supply common data i/o fully ttl compatible inputs and outputs produced with pace ii technology tm standard pinout (jedec approved) C 24-pin 300 mil dip, soic, soj C 24-pin 600 mil dip C 24-pin solder seal flat pack C 24-pin rectangular lcc (300 x 400 mils) C 28-pin square lcc (450 x 450 mils) C 32-pin rectangular lcc (450 x 550 mils) C 40-pin square lcc (480 x 480 mils) functional block diagram pin config urations lcc confgurations at end of datasheet dip (c4, c12, d4, p4), soj (j4), soic (s4) solder seal flat pack (fs-1) similar description the p4c116/p4c116l are 16,384-bit ultra high-speed static rams organized as 2k x 8. the cmos memories require no clocks or refreshing and have equal access and cycle times. inputs are fully ttl-compatible. the rams operate from a single 5v10% tolerance power supply. current drain is typically 10 a from a 2.0v supply. access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. cmos is used to reduce power consumption. the p4c116 is available in 24-pin 300 and 600 mil dip, soj and soic packages, a solder seal fatpack and 4 different lcc packages (24, 28, 32, and 40 pin).
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 2 document # sram110 rev c dc electrical characteristics (over recommended operating temperature & supply voltage) (2) sym parameter value unit v cc power supply pin with respect to gnd -0.5 to +7 v v term terminal voltage with respect to gnd (up to 7.0v) -0.5 to vcc + 0.5 v t a operating temperature -55 to +125 c t bias temperature under bias -55 to +125 c t stg storage temperature -65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma maximum r atings (1) recommen ded operating conditions grade (2) ambient temp gnd v cc commercial 0c to 70c 0v 5.0v 10% industrial -40c to +85c 0v 5.0v 10% military -55c to +125c 0v 5.0v 10% capacita nces (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) sym parameter conditions typ unit c in input capacitance v in =0v 5 pf c out output capacitance v out =0v 7 pf sym parameter test conditions p4c116 p4c116l unit min max min max v ih input high voltage 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il input low voltage -0.5 (3) 0.8 -0.5 (3) 0.8 v v hc cmos input high voltage v cc - 0.2 v cc + 0.5 v cc - 0.2 v cc + 0.5 v v lc cmos input low voltage -0.5 (3) 0.2 -0.5 (3) 0.2 v v cd input clamp diode voltage v cc = min, i in = -18 ma -1.2 -1.2 v v ol output low voltage (ttl load) i ol = +8 ma, v cc = min 0.4 0.4 v v oh output high voltage (ttl load) i oh = - 4 ma, v cc = min 2.4 2.4 v i li input leakage current v cc = max, v in = gnd to v cc mil -10 +10 -5 +5 a ind/com -5 +5 n/a n/a i lo output leakage current v cc = max, ce = v ih , v out = gnd to v cc mil -10 +10 -5 +5 a ind/com -5 +5 n/a n/a i sb standby power supply current (ttl input levels) ce v ih , v cc = max, f = max, outputs open mil 30 20 ma ind/com 20 n/a i sb1 standby power supply current (cmos input levels) ce v hc , v cc = max, f = 0, outputs open v in v lc or v in v hc mil 15 1 ma ind/com 10 n/a n/a = not applicable
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 3 document # sram110 rev c data rete ntion characteristics (p4c116l military temperature only) data rete ntion waveform sym parameter test conditions min typ* v cc = max v cc = unit 2.0v 3.0v 2.0v 3.0v v dr v cc for data retention 2.0 v i ccdr data retention current ce v cc -0.2v, v in v cc -0.2v or v in 0.2v 10 15 600 900 a t cdr chip deselect to data retention time 0 ns t r ? operation recovery time t rc ns * t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested power dissipatio n characteristics vs. speed sym parameter temperature range -10 -12 -15 -20 -25 -35 unit i cc dynamic operating current* commercial 180 170 160 155 150 140 ma industrial n/a 180 170 160 155 150 ma military n/a n/a 170 160 155 150 ma * v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih . sym parameter -10 -12 -15 -20 -25 -35 unit min max min max min max min max min max min max t rc read cycle time 10 12 15 20 25 35 ns t aa address access time 10 12 15 20 25 35 ns t ac chip enable access time 10 12 15 20 25 35 ns t oh output hold from address change 2 2 2 2 2 2 ns t lz chip enable to output in low z 2 2 2 2 3 3 ns t hz chip disable to output in high z 5 6 7 8 10 15 ns t oe output enable low to data valid 6 8 10 10 15 20 ns t olz output enable low to low z 0 0 0 0 0 0 ns t ohz output enable high to high z 6 7 8 9 12 15 ns t pu chip enable to power up time 0 0 0 0 0 0 ns t pd chip disable to power down 10 12 15 20 20 25 ns ac electrical characteristicsread cycle (v cc = 5v 10%, all temperature ranges) (2)
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 4 document # sram110 rev c timing waveform of read cycle no. 1 ( oe controlled) (5) timing waveform of read cycle no. 2 (address controlled) (5,6) timing waveform of read cycle no. 3 ( ce controlled) notes: 1. stresses greater than those listed under maximum r atings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air fow. 3. transient inputs with v il and i il not more negative than C3.0v and C100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specifed in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the frst transitioning address.
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 5 document # sram110 rev c ac characteristicswrite cycle (v cc = 5v 10%, all temperature ranges) (2) sym parameter -10 -12 -15 -20 -25 -35 unit min max min max min max min max min max min max t wc write cycle time 10 12 15 20 25 35 ns t cw chip enable time to end of write 8 10 12 15 18 25 ns t aw address valid to end of write 8 10 12 15 18 25 ns t as address setup time 0 0 0 0 0 0 ns t wp write pulse width 8 10 12 15 18 20 ns t ah address hold time 0 0 0 0 0 0 ns t dw data valid to end of write 7 8 10 12 15 20 ns t dh data hold time 0 0 0 0 0 0 ns t wz write enable to output in high z 6 7 8 10 15 15 ns t ow output active from end of write 0 0 0 0 0 0 ns timing waveform of write cycle no. 1 ( we controlled) (10,11) notes: 10. ce and we must be low for write cycle. 11. oe is low for this write cycle to show t wz and t ow . 12. if ce goes high simultaneously with we high, the output remains in a high impedance state 13. write cycle time is measured from the last valid address to the frst transitioning address.
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 6 document # sram110 rev c ac test conditions truth table timing w aveform of write cycle no. 2 ( ce controlled) (10) input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce oe we i/o power standby h x x high z standby d out disabled l h h high z active read l l h d out active write l x l high z active figure 1. output load figure 2. thevenin equivalent * including scope and test fxture. note: because of the ultra-high speed of the p4c116/l, care must be taken when testing this device; an inadequate setup can cause a normal function - ing part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fngers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal refections, proper termination must be used; for example, a 50? test environment should be terminated into a 50? load with 1.73v (thevenin voltage) at the comparator input, and a 116? resistor must be used in series with d out to match 166? (thevenin resistance).
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 7 document # sram110 rev c 24-pin lcc (l8) 28-pin lcc (l5-1) lcc pin config urations 32-pin lcc (l6) 40-pin lcc (l10)
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 8 document # sram110 rev c ordering in formation
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 9 document # sram110 rev c sidebrazed dual i n-lin e package pkg # c4 # pins 24 (300 mil) symbol min max a - 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.280 e 0.220 0.310 ea 0.300 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - sidebrazed dual i n-lin e package pkg # c12 # pins 24 (600 mil) symbol min max a - 0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.290 e 0.500 0.610 ea 0.600 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 -
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 10 document # sram110 rev c solder seal flatpac k cerdip dual i nlin e package pkg # fs-1 # pins 24 symbol min max a 0.045 0.115 b 0.015 0.022 b1 0.015 0.019 c 0.004 0.009 c1 0.004 0.006 d - 0.640 e 0.350 0.420 e1 - 0.450 e2 0.180 - e3 0.030 - e 0.050 bsc k 0.008 0.015 l 0.250 0.370 q 0.026 0.045 s1 0.000 - m - 0.002 n 24 pkg # d4 # pins 24 (300 mil) symbol min max a - 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.280 e 0.220 0.310 ea 0.300 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0 15
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 11 document # sram110 rev c soj small outli n e ic package square leadless chip carrier pkg # j4 # pins 24 (300 mil) symbol min max a 0.128 0.148 a1 0.082 - b 0.016 0.020 c 0.007 0.010 d 0.620 0.630 e 0.050 bsc e 0.335 bsc e1 0.292 0.300 e2 0.267 bsc q 0.025 - pkg # l5-1 # pins 28 symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d/e 0.442 0.460 d1/e1 0.300 bsc d2/e2 0.150 bsc d3/e3 - 0.460 e 0.050 bsc h 0.040 ref j 0.020 ref l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd 7 ne 7
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 12 document # sram110 rev c pkg # l6 # pins 32 symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.442 0.458 d1 0.300 bsc d2 0.150 bsc d3 - 0.458 e 0.540 0.560 e1 0.400 bsc e2 0.200 bsc e3 - 0.558 e 0.050 bsc h 0.040 ref j 0.020 ref l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd 7 ne 9 recta ng ular leadless chip carrier pkg # l10 # pins 40 symbol min max a 0.060 0.080 a1 0.050 0.075 b1 0.015 0.025 d/e 0.475 0.492 d1/e1 0.360 bsc d2/e2 0.180 bsc d3/e3 - 0.492 e 0.040 bsc h r = .0075 j 0.026 ref l 0.030 0.050 l1 0.030 0.050 l2 0.080 0.090 nd 10 ne 10 square leadless chip carrier
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 13 document # sram110 rev c pkg # p4 # pins 24 (300 mil) symbol min max a - 0.210 a1 0.015 - b 0.014 0.022 b2 0.045 0.070 c 0.008 0.014 d 1.230 1.280 e1 0.240 0.280 e 0.280 0.325 e 0.100 bsc eb - 0.430 l 0.115 0.160 0 15 plastic dual i n-lin e package pkg # l8 # pins 24 symbol min max a 0.064 0.076 a1 0.054 0.066 b1 0.022 0.028 d 0.292 0.308 d1 0.200 bsc d2 0.100 bsc d3 - 0.308 e 0.392 0.408 e1 0.300 bsc e2 0.150 bsc e3 - 0.408 e 0.050 bsc h 0.025 ref j 0.015 ref l 0.040 0.050 l1 0.040 0.050 l2 0.077 0.093 nd 5 ne 7 recta ng ular leadless chip carrier
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 14 document # sram110 rev c pkg # s4 # pins 24 (300 mil) symbol min max a 0.093 0.104 a1 0.004 0.012 b2 0.013 0.020 c 0.009 0.012 d 0.598 0.614 e 0.050 bsc e 0.291 0.299 h 0.394 0.419 h 0.010 0.029 l 0.016 0.050 0 8 soic/sop small outli n e ic package
p4c116/p4c116l - ultra high speed 2k x 8 static cmos rams page 15 document # sram110 rev c revisions document number sram 110 document title p4c116 / p4c116l ultra high speed 2k x 8 static cmos rams rev issue date origin ator description of change or 1997 dab new data sheet a oct-2005 jdb changed logo to pyramid b feb-2009 jdb added industrial temperature range c may-2009 jdb added 300 mil cerdip and 600 mil sidebrazed packages

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