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| is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 1 2mx18, 1mx36 36mb ddr-iip (burst 2) cio synchronous sram (2.0 cycle read latency) features ? 1mx36 and 2mx18 conf iguration available. ? on-chip delay-locked loop (dll) for wide data valid window. ? common i/o read and write ports. ? synchronous pipeline read with self-timed late write operation. ? double data rate (ddr) interface for read and write input ports. ? 2.0 cycle read latency. ? fixed 2-bit burst for read and write operations. ? clock stop support. ? two input clocks (k and k#) for address and control registering at rising edges only. ? two echo clocks (cq and cq#) that are delivered simultaneously with data. ? +1.8v core power supply and 1.5, 1.8v vddq, used with 0.75, 0.9v vref. ? hstl input and output levels. ? registered addresses, write and read controls, byte writes, data in, and data outputs. ? full data coherency. ? boundary scan using limi ted set of jtag 1149.1 functions. ? byte write capability. ? fine ball grid array (fbga) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array ? programmable impedance ou tput drivers via 5x user-supplied precision resistor. ? odt(on-die termination) feature is supported optionally on input clocks, data input, and control signals. description the 36mb is61ddpb21m36a and is61ddpb22m18a are synchronous, high-performance cmos static random access memory (sram) devices. these srams have a common i/o bus. the rising edge of k clock initiates the read/write operation, and all internal operat ions are self-timed. refer to the timing reference diagram for truth table for a description of the basic operati ons of these ddr-iip (burst of 2) cio srams. read and write addresses are registered on alternating rising edges of the k clock. reads and writes are performed in double data rate. the following are registered internally on the rising edge of the k clock: ? read/write address ? read enable ? write enable ? byte writes ? data-in for first burst addresses ? data-out for second burst addresses the following are registered on the rising edge of the k# clock: ? byte writes ? data-in for second burst addresses ? data-out for first burst addresses byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. an internal write buffer enables the data-ins to be registered one cycle after the write address. the first data- in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the k# clock. during the burst read operation, the data-outs from the first bursts are updated from output registers of the third rising edge of the k clock (starting 2.0 cycles later after read command). the data-outs from the second burst are updated with the third rising edge of the k# clock where read command receives at the first rising edge of k. the device is operated with a single +1.8v power supply and is compatible with hstl i/o interfaces. advanced information september 2010 copyright ? 2010 integrated silicon solution, inc. all rights rese rved. issi reserves the right to make changes to this specifi cation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, produc ts or services descri bed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fail ure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect it s safety or effectiveness. prod ucts are not authorized for use in such applications unless integrated silicon solution, inc. re ceives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c. ) p otential liabilit y of inte g rated silicon solution , inc is ade q uatel y p rotected under the circumstances
is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 2 package ballout and description x36 fbga ball configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 a cq# nc/sa 1 sa r/w# bw 2 # k# bw 1 # ld# sa nc/sa 1 cq b nc dq27 dq18 sa bw 3 # k bw 0 # sa nc nc dq8 c nc nc dq28 v ss sa nc sa v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss vss v ss nc nc dq16 e nc nc dq20 v ddq v ss v ss vss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 h d off # v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq32 v ddq v dd v ss v dd v ddq nc dq13 dq4 k nc nc dq23 v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc dq34 v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss sa sa sa v ss nc nc dq10 p nc nc dq26 sa sa qv ld sa sa nc dq9 dq0 r tdo tck sa sa sa odt sa sa sa tms tdi notes: 1. the following balls are reserved for higher densities: 10a for 72mb, and 2a for 144mb. x18 fbga ball configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 a cq# nc/sa 1 sa r/w# bw 1 # k# nc/sa 1 ld# sa sa cq b nc dq9 nc sa nc/sa 1 k bw 0 # sa nc nc dq8 c nc nc nc v ss sa nc sa v ss nc dq7 nc d nc nc dq10 v ss v ss v ss vss v ss nc nc nc e nc nc dq11 v ddq v ss v ss vss v ddq nc nc dq6 f nc dq12 nc v ddq v dd v ss v dd v ddq nc nc dq5 g nc nc dq13 v ddq v dd v ss v dd v ddq nc nc nc h d off # v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq4 nc k nc nc dq14 v ddq v dd v ss v dd v ddq nc nc dq3 l nc dq15 nc v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc nc v ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss sa sa sa v ss nc nc nc p nc nc dq17 sa sa qv ld sa sa nc nc dq0 r tdo tck sa sa sa odt sa sa sa tms tdi notes: 1. the following balls are reserved for higher densities: 2a for 72mb, 7a for 144mb, and 5b for 288mb. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 3 ball descriptions symbol type description k, k# input input clock: this input clock pair registers addr ess and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of k#. k# is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. these balls cannot remain vref level. cq, cq# output synchronous echo clock outputs: the edges of thes e outputs are tightly matched to the synchronous data outputs and can be used as a data valid indi cation. these signals run freely and do not stop when q tri-states. doff# input dll disable and reset input : when low, this input causes the dll to be bypassed and reset the previous dll information. when high, dll will st art operating and lock the frequency after tck lock time. the device behaves in 1.0 read latency mode when the dll is turned off. in this mode, the device can be operated at a frequency of up to 167 mhz. qvld output valid output indicator: the q valid indicates valid output data. qvld is edge aligned with cq and cq#. sa input synchronous address inputs: these inputs are regi stered and must meet the setup and hold times around the rising edge of k. these inputs are ignored when device is deselected. dq0 - dqn bidir data input and output signals. i nput data must meet setup and hold times around the rising edges of k and k# during write operations. these pins driv e out the requested dta when the read operation is active. valid output data is synchronized to t he respective c and c#, or to the respective k and k# if c and /c are tied to high. when read access is desel ected, q0 - qn are automatically tri-stated. see ball configuration figures for ball site location of individual signals. the x18 device uses dq0~dq17. dq18~ dq35 should be treated as nc pin. the x36 device uses dq0~dq35. r/w# input synchronous read or write input. when ld# is low, this input designates the access type (read when it is high, write when it is low) for load ed address. r/w# must meet the setup and hold times around edge of k. ld# input synchronous load. this input is brought low when a bus cycle sequence is defined. this definition includes address and read/write direction. bw x # input synchronous byte writes: when low, these inputs cause their respective byte to be registered and written during write cycles. these signals are sampled on the same edge as the corresponding data and must meet setup and hold times around t he rising edges of k and #k for each of the two rising edges comprising the write cycle. see write truth table for signal to data relationship. v ref - hstl input reference voltage: nominally vddq/2 , but may be adjusted to improve system noise margin. provides a reference voltage for the hstl input buffers. v dd supply power supply: 1.8 v nominal. see dc char acteristics and operating conditions for range. v ddq supply power supply: isolated output buffer supply. nomina lly 1.5 v. see dc charac teristics and operating conditions for range. v ss supply ground zq input output impedance matching input: this input is us ed to tune the device outputs to the system data bus impedance. q and cq output impedance are set to 0.2xrq, where rq is a resistor from this ball to ground. this ball can be connected directly to vddq, which enables the minimum impedance mode. this ball cannot be connected directly to vss or left unconnected. in odt (on die termination) enable devices, the odt termination values tr acks the value of rq. the odt range is selected by odt control input. tms, tdi, tck input ieee1149.1 test inputs: 1.8 v i/o levels. these balls may be left not connected if the jtag function is not used in the circuit. tdo input ieee1149.1 clock input: 1.8 v i/o levels. this ball mu st be tied to vss if the jtag function is not used in the circuit. nc - no connect: these signals should be left floating or connected to ground to improve package heat dissipation. odt input odt control; refer to sram features for the details. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 4 sram features description block diagram data register burst2 control logic 19 (or 20) addresses : sa 4 (or 2) ld# r/w# bw x # clock generator k k# 1m x 36 (2m x 18) memory array write driver select output control 19 (20) 36x2(or 18x2) 36x2 (or 18x2) 36x2 (or 18x2) 36 (or 18) dq(data-out &data-in) cq, cq# (echo clocks) /d off add reg & burst control 72 (or 36) output reg 36 (or 18) 36(or 18) note: numerical values in parentheses refer to the x18 device configuration . read operations the sram operates continuously in a burst-of-two mode. read cycles are started by regist ering r/w# in active high state at the rising edge of the k clock. k and k#, are al so used to control the timing to the outputs. the data corresponding to the first address is clocked 2.0 cycles la ter by the rising edge of the k clock. the data corresponding to the second burst is clocked 2.5 cy cles later by the following rising edge of the k# clock. a set of free-running echo clocks, cq and cq#, are produced internally with timings id entical to the data-outs. the echo clocks can be used as data capture clocks by the receiver device. whenever ld# is low, a new address is registered at the ri sing edge of the k clock. a nop operation (ld# is high) does not terminate the previous r ead. the output drivers disable aut omatically to a high-z state. write operations write operations can also be initiated at every other ri sing edge of the k clock whenever r/w# is low. the write address is also registered at that ti me. when the address needs to change, ld# needs to be low simultaneously to be registered by the rising edge of k. again, the write always occurs in bursts of two. because of its common i/o architecture, the data bus must be tri-stated at least one cycle before the new data-in is presented at the dq bus. the write data is provided in a ?late write? mode; that is, t he data-in corresponding to the first address of the burst, is presented 1 cycle later or at the rising edge of the followi ng k clock. the data-in corresponding to the second write burst address follows next, regist ered by the rising edge of k#. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 5 the data-in provided for writing is initially kept in write buffers. the information on these buffers is written into the array on the third write cycle. a read cycle to the la st two write address produces data from the write buffers. similarly, a read address followed by the same write address produces the latest write data. the sram maintains data coherency. during a write, the byte writes independ ently control which byte of any of t he two burst addresses is written. (see x18/x36 write truth tables and timing reference diagram for truth table ) whenever a write is disabled (r/w# is high at the ri sing edge of k), data is not written into the memory. rq programmable impedance an external resistor, rq, must be connec ted between the zq pin on the sram and v ss to enable the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. for example, an rq of 250 ? results in a driver impedance of 50 ? . the allowable range of rq to guarantee impedance matching is between 175 ? and 350 ? with v ddq =1.5v. the rq resistor shou ld be placed less than two inches away from the zq ball on the sram module. the ca pacitance of the loaded zq trace must be less than 7.5pf. the zq pin can also be directly connected to v ddq to obtain a minimum impedance setting. zq must never be connected to v ss . programmable impedance and power-up requirements periodic readjustment of the output driver impedance is nece ssary as the impedance is greatly affected by drifts in supply voltage and temperature. at power- up, the driver impedance is in the middle of allowable impedances values. the final impedance value is achieved within 1024clock cycles. valid data indicator (qvld) a data valid pin (qvld) is available to assist in high-speed data output capture. this output signal is edge-aligned with the echo clock and is asserted high half a cycle before va lid read data is available and asserted low half a cycle before the final valid read data arrives. delay lock loop (dll) delay lock loop (dll) is a new system to align the output data coincident with clock rising or falling edge to enhance the output valid timing characteristics. it is locked to the clock frequency and is constantly adjusted to match the clock frequency. therefore device can have stable outpu t over the temperature and voltage variation. dll has a limitation of locking range and jitter adjustment whic h are specified as tkhkh and tkcvar respectively in the ac timing characteristics. in order to tu rn this feature off, applying logic low to the doff# pin will bypass this. in the dll off mode, the device behaves with 1.0 cycle latency and a longer access time which is known in ddr-i or old quad mode. the dll can also be reset without power down by toggling do ff# pin low to high or stopping the input clocks k and k# for a minimum of 30ns.(k and k# must be stayed either at high er than vih or lower than vil level. remaining vref is not permitted.) dll reset must be issued when power up or when clock frequency changes abruptly. after dll being reset, it gets locked after 2048 cycles of stable clock. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 6 odt (on die termination) on die termination (odt) is a feature that allows a sram to turn on/off termination resistance for odt pins. the odt feature is designed to improve signal integrity of the memory channel by allowing the sram controller to independently turn on/off termination resistance for any or all sram devices. odt can have three status, high, low, and floating. each status can have different odt termination values which tracks the value of rq (see the picture below) in ddr-ii+ devices having common i/o bus, odt is automatically enabled when the device inputs data and disabled when the device outputs data. fig. functional representation of odt notes 1. allowable range of rq to guarantee impedanc e matching a tolerance of 20% is 175 ? is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 8 power-up and power-down sequences the recommendation of voltage apply sequence is : v dd v ddq 1) v ref 2) v in notes: v ddq can be applied concurrently with v dd . v ref can be applied concurrently with v ddq . after power and clock signals are stabili zed, device can be ready for normal oper ation after tkc-lock cycles. in tkc- lock cycle period, device initializes internal logics and locks dll. depending on /doff status, locking dll will be skipped. the following timing pictures are pos sible examples of power up sequence. sequence1. /doff is fixed low after tkc-lock cycle of stable clock, device is ready for normal operation. power on stage unstable clock period stable clock period read to use k k# vdd vddq vref vin note) all inputs including clocks must be either logically high or low during power on stage. timing above shows only one of ca ses. sequence2. /doff is controlled and goes high after clock being stable. power on stage unstable clock period stable clock period read to use k k # doff# vdd vddq vref vin note) all inputs including clocks must be either logically high or low during power on stage. timing above shows only one of ca ses. >tkc-lock for device initialization >tkc-lock for device initialization is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 9 sequence3. /doff is controlled but goes high before clock being stable. because dll has a risk to be locked with the unstable cl ock, dll needs to be reset and locked with the stable input. a) k-stop to reset. if k or k# stays at vih or vil for mo re than 30ns, dll will be reset and ready to re-lock. in tkc- lock period, dll will be locked with a new stable value. device can be ready for normal operation after that. power on stage unstable clock period k-stop stable clock period read to use k k# doff# vdd vddq vref vin note) all inputs including clocks must be either logically high or low during power on stage. timing above shows only one of ca ses. a) /doff low to reset. if /doff toggled low to high, dll will be reset and ready to re-lock. in tkc-lock period, dll will be locked with a new stable value. device can be ready for normal operation after that. power on stage unstable clock period doff reset dll stable clock period read to use k k # doff# vdd vddq vref vin note) applying dll reset sequences (sequence 3a, 3b) are also required when operating frequency is changed without power off. note) all inputs including clocks must be either logically high or low during power on stage. timing above shows only one of ca ses. >30ns >tkc-lock for device initialization >tdofflowtoreset >tkc-lock for device initialization is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 10 application example the following figure depicts an implementation of four 2m x 18 ddr-iip srams with common i/os. sram #1 sa r/w# ld# bw x # k/k# dq cq/cq# zq rq = 250 ? sram #4 zq rq = 250 ? data-in&data out address sram #1 cq input sram #4 cq input read&write control new address control byte write control source clk memory controller v t v t r r = 50 ? r v t = v ref sa r/w# ld# bw x # k/k# dq cq/cq# v t r is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 11 state diagram power-up nop load new read address ddr-ii read ddr-ii write load load load read write /load /load /load notes: 1. internal burst counter is fixed as two-bit linear; that is, w hen first address is a0+0, next in ternal burst address is a0+1. 2. read refers to read active status with r/w# = high. 3. write refers to write active status with r/w# = low. 4. load refers to read new address active status with ld# = low. 5. load is read new address inactive status with ld = high. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 12 timing reference diagram for truth table the timing reference diagram for truth table is helpful in understanding the clock and write truth tables , as it shows the cycle relationship between cl ocks, address, data in, data out, and cont rol signals. read command is issued at the beginning of cycle ?t?. write command is issued at the beginning of cycle ?t+1?. db db+1 qa qa+1 t + 1 t t + 2 t + 3 t + 4 t + 5 a b cycle k clock k# clock ld# r/w# bw x # address data- in/out(dq) cq cq# tchqv 2.0 cycles t + 2.5 clock truth table (use the following table with the timing reference diagram for truth table .) mode clock controls data out / data in k ld# r/w# q a / d b q a+1 / d b+1 stop clock stop x x previous state previous state no operation (nop) l h h x high-z high-z read a l h l h d out at k# (t+2.0) d out at k (t+2.5) write b l h l l d b at k (t+5.0) d b at k# (t+5.5) notes: 1. x = ?don?t care?; h = logic ?1?; l = logic ?0?. 2. a read operation is started when c ontrol signal r/w# is active high. 3. a write operation is started when control signal r/w# is active low. 4. before entering into stop clock, all pending read and write commands must be completed. 5. for timing definitions, refer to the ac timing characteristics table. signals must meet ac specifications at timings indicated in parenthesis with respect to switching clocks k and k# is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 13 x18 write truth table (use the following table with the timing reference diagram for truth table .) operation k (t+1.0) k (t+1.5) bw 0 bw 1 d b d b+1 write byte 0 l h l h d0-8 (t+4.0) write byte 1 l h h l d9-17 (t+4.0) write all bytes l h l l d0-17 (t+4.0) abort write l h h h don't care write byte 0 l h l h d0-8 (t+4.5) write byte 1 l h h l d9-17 (t+4.5) write all bytes l h l l d0-17 (t+4.5) abort write l h h h don't care notes: 1. for all cases, r/w# needs to be active low during the rising edge of k occurring at time t. 2. for timing definitions refer to the ac timing characteristics table. signals must meet ac specificati ons with respect to switching clocks k and k#. x36 write truth table (use the following table with the timing reference diagram for truth table .) operation k (t+1.0) k (t+1.5) bw 0 bw 1 bw 2 bw 3 d b d b+1 write byte 0 l h l h h h d0-8 (t+4.0) write byte 1 l h h l h h d9-17 (t+4.0) write byte 2 l h h h l h d18-26 (t+4.0) write byte 3 l h h h h l d27-35 (t+4.0) write all bytes l h l l l l d0-35 (t+4.0) abort write l h h h h h don't care write byte 0 l h l h h h d0-8 (t+4.5) write byte 1 l h h l h h d9-17 (t+4.5) write byte 2 l h h h l h d18-26 (t+4.5) write byte 3 l h h h h l d27-35 (t+4.5) write all bytes l h l l l l d0-35 (t+4.5) abort write l h h h h h don't care notes: 1. for all cases, r/w# needs to be active low during the rising edge of k occurring at time t. 2. for timing definitions refer to the ac timing characteristics table. signals must meet ac specificati ons with respect to switching clocks k and k#. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 14 electrical specifications absolute maximum ratings parameter symbol min max units power supply voltage v dd ? 0.5 2.9 v i/o power supply voltage v ddq ? 0.5 2.9 v dc input voltage v in ? 0.5 v dd +0.3 v data out voltage v dout ? 0.5 2.6 c junction temperature t j - 110 c storage temperature t stg ? 55 +125 c note: stresses greater than those listed in this table can cause perm anent damage to the device. this is a stress rating only and fun ctional operation of the device at these or any other conditions above those indicated in the operational se ctions of this datasheet is not implied. exposure to absolute maximum rating conditions for ext ended periods may affect reliability. operating temperature range temperature range symbol min max units commercial t a 0 +70 c industrial t a ? 40 +85 c dc electrical characteristics (over the operating temperature range, v dd =1.8v5% ) parameter symbol min max units notes x36 average power supply operating current (i out =0, v in =v ih or v il ) i dd22 i dd25 i dd30 i dd33 ? 1100 960 900 800 ma 1,2 x18 average power supply operating current (i out =0, v in =v ih or v il ) i dd22 i dd25 i dd30 i dd33 ? 1050 910 850 750 ma 1,2 power supply standby current (r=v ih , w=v ih . all other inputs=v ih or v il , i ih =0) i sb22 i sb25 i sb30 i sb33 ? 380 360 340 320 ma 1,2 input leakage current ( 0 v in v ddq for all input balls except v ref , zq, tck, tms, tdi ball) i li ? 2 +2 a 3,4 output leakage current (0 v out v ddq for all output balls except tdo ball; output must be disabled.) i lo ? 2 +2 a output ?high? level voltage (i oh =-0.1ma, zqnorm) v oh v ddq ? 0.2 v ddq v output ?low? level voltage (i ol =+0.1ma, zqnorm) v ol v ss v ss +0.2 v notes: 1. i out = chip output current. 2. the numeric suffix indicates the part operating at speed, as indicated in ac timing characteristics table (that is, i dd25 indicates 2.5ns cycle time). 3. odt must be disabled. 4. balls with odt and doff# do not follow this spec, i li = 100ua. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 15 recommended dc operating conditions ( over the operating temperature range) parameter symbol min typical max units notes supply voltage v dd 1.8?5% 1.8 1.8+5% v 1 output driver supply voltage v ddq 1.4 1.5 v dd v 1 input high voltage v ih v ref +0.1 - v ddq +0.2 v 1, 2 input low voltage v il ?0.2 - v ref ?0.1 v 1, 3 input reference voltage v ref 0.68 0.75 0.95 v 1, 5 clock signal voltage v in-clk ?0.2 - v ddq +0.2 v 1, 4 notes: 1. all voltages are referenced to v ss . all v dd , v ddq , and v ss pins must be connected. 2. v ih (max) ac = see 0vershoot and undershoot timings . 3. v il (min) ac = see 0vershoot and undershoot timings . 4. v in-clk specifies the maximum allowable dc ex cursions of each clock (k and k#). 5. peak-to-peak ac component superimposed on vref may not exceed 5% of vref . overshoot and undershoot timings is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 16 typical ac input characteristics parameter symbol min max units notes ac input logic high v ih (ac) v ref +0.2 v 1, 2, 3, 4 ac input logic low v il (ac) v ref ?0.2 v 1, 2, 3, 4 clock input logic high v ih-clk (ac) v ref +0.2 v 1, 2, 3 clock input logic low v il-clk (ac) v ref ?0.2 v 1, 2, 3 notes: 1. the peak-to-peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. performance is a function of v ih and v il levels to clock inputs. 3. see the ac input definition diagram. 4. see the ac input definition diagram. the signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past v ih (ac) and v il (ac) during the input setup and input hold window. v ih (ac) and v il (ac) are used for timing purposes only. ac input definition k# v ref k v rail v ih (ac) v ref v il (ac) v -rail setup time hold time pbga thermal characteristics parameter symbol rating units thermal resistance from junction to ambient (airflow = 1m/s) r ja tbd c/w thermal resistance from junction to pins r jb tbd c/w thermal resistance from junction to case r jc tbd c/w note: these parameters are guaranteed by design and tested by a sample basis only. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 17 pin capacitance parameter symbol test condition max units input or output capacitanc e except dq pins c in ,c o t a = 25 c, f = 1 mhz, v dd = 1.8v, v ddq = 1.5v 5 pf dq capacitance (dq0?dqx) c dq 6 pf clocks capacitance (k, k, c, c) c clk 4 pf note: these parameters are guaranteed by design and tested by a sample basis only. programmable impedance output driver dc electrical characteristics (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v ) parameter symbol min max units notes output logic high voltage v oh v ddq /2 -0.12 v ddq /2 + 0.12 v 1, 3 output logic low voltage v ol v ddq /2 -0.12 v ddq /2 + 0.12 v 2, 3 notes: 1. for 175 ? rq 350 ? : ? ? ? ? ? ? ? ? ? ? ? ? ? 5 rq 2 v | i | ddq oh 2. for 175 ? rq 350 ? : ? ? ? ? ? ? ? ? ? ? ? ? ? 5 rq 2 v | i | ddq ol 3. parameter tested with rq=250 ? and v ddq =1.5v ac test conditions (over the operating temperature range, v dd =1.8v5%) parameter symbol conditions units notes output drive power supply voltage v ddq 1.5 v 2 input logic high voltage v ih 1.25 v input logic low voltage v il 0.25 v input reference voltage v ref 0.75 v input rise time t r 2 v/ns input fall time t f 2 v/ns output timing reference level v ddq /2 v clock reference level 0.75 v output load conditions 1, 2 notes: 1. see ac test loading. 2. parameters are tested with rq=250 ? and vddq=1.5v, but issi devices are able to support v ddq =1.4v to v dd is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 18 ac test loading (a) unless otherwise noted, ac test loading assume this condition. (b) tchqz and tchqx1 are specified with 5pf load capaci tance and measured when transition occurs 100mv from the steady state voltage. (c)tdo is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 19 ac timing characteristics (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v) parameter symbol 22 (450mhz) 25 (400mhz) 30 (333mhz) 33 (300mhz) unit notes min max min max min max min max clock clock cycle time (k, k#,c,c#) tkhkh 2.2 8.40 2.50 8.40 3.00 8.4 3.33 8.4 ns clock phase jitter (k, k#,c,c#) tkc var 0.15 0.20 0.3 0.3 ns 3 clock high time (k, k#,c,c#) tkhkl 0.4 0.4 0.4 0.4 cycle clock low time (k, k#,c,c#) tklkh 0.4 0.4 0.4 0.4 cycle clock to clock (k h k# h , c h c# h ) tkhk#h 0.99 1.13 1.35 3.33 8.4 ns dll lock time (k,c) tkc lock 2048 2048 2048 2048 cycles 4 doff low period to dll reset tdofflowtoreset 5 5 5 5 ns k static to dll reset tkcreset 30 30 30 30 ns output times c,c# high to output valid tchqv 0.45 0.45 0.45 0.45 ns 1 c,c# high to output hold tchqx -0.45 -0.45 -0.45 -0.45 ns 1 c,c# high to echo clock valid tchcqv 0.45 0.45 0.45 0.45 ns 1 c,c# high to echo clock hold tchcqx -0.45 -0.45 -0.45 -0.45 ns 1 cq, cq# high to output valid tcqhqv 0.2 0.2 0.30 0.30 ns 1 cq, cq# high to output hold tcqhqx -0.2 -0.2 -0.30 -0.30 ns 1 c,c# high to output high-z tchqz 0.45 0.45 0.45 0.45 ns 1 c,c# high to output low-z tchqx1 -0.45 -0.45 -0.45 -0.45 ns 1 cq, cq# high to qvld valid tqvld -0.20 0.20 -0.20 0.20 -0.20 0.20 -0.20 0.20 ns setup times address valid to k rising edge tavkh 0.30 0.40 0.40 0.40 ns 2 ld#, r/w# control inputs valid to k rising edge tivkh 0.30 0.40 0.40 0.40 ns 2 bw x # control inputs valid to k rising edge tivkh2 0.25 0.28 0.30 0.30 ns 2 data-in valid to k, k# rising edge tdvkh 0.25 0.28 0.30 0.30 ns 2 hold times k rising edge to address hold tkhax 0.30 0.40 0.40 0.40 ns 2 k rising edge to ld#, r/w# control inputs hold tkhix 0.30 0.40 0.40 0.40 ns 2 k rising edge to bw x # control inputs hold tkhix2 0.25 0.28 0.30 0.30 ns 2 k, k# rising edge to data-in hold tkhdx 0.25 0.28 0.30 0.30 ns 2 notes: 1. all address inputs must meet the specified se tup and hold times for all latching clock edges. 2. during normal operation, vih, vil, trise, and tfall of inputs must be within 20% of vih, vil, trise, and tfall of clock. 3. clock phase jitter is the variance from clock ri sing edge to the next expected clock rising edge. 4. v dd slew rate must be less than 0.1v dc per 50ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 5. the data sheet parameters reflect tester guard bands and test setup variations. 6. to avoid bus contention, at a given voltage and temperature tchqx1 is bigger than tchqz. the specs as shown do not imply bus co ntention because tchqx1 is a min parameter that is worst case at totally different test conditions (0 c, 1.9v) than tchqz, which is a ma x parameter (worst case at 70 c, 1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 20 read, write, and nop timing diagram notes: 1. q1-0 refers to the output from address a1. q1-1 refers to the output from the next burst address following a1. 2. the nop cycle is not necessary for correct device operation, however, at high clock frequencies, it might be req uired to prevent bus contention. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 21 ieee 1149.1 tap and boundary scan the sram provides a limited set of jtag functions to test the interconnection between sram i/os and printed circuit board traces or other components. there is no multip lexer in the path from i/o pins to the ram core. in conformance with ieee standard 1149.1, the sram contains a tap controll er, instruction register, boundary scan register, bypass register, and id register. the tap controller has a standard 16-state machine that rese ts internally on power-up. therefore, a trst signal is not required disabling the jtag feature the sram can operate without using t he jtag feature. to disable the tap controller, tck must be tied low (vss) to prevent clocking of the device. tdi and tms are in ternally pulled up and may be left disconnected. they may alternately be connected to vdd through a pull-up resistor . tdo should be left disconnected. on power-up, the device will come up in a reset state, which w ill not interfere with device operation. test access port signal list: 1. test clock (tck) this signal uses vdd as a power supply. the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs ar e driven from the falling edge of tck. 2. test mode select (tms) this signal uses vdd as a power supply. the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. 3. test data-in (tdi) this signal uses vdd as a power supply. t he tdi input is used to serially input test instructions and information into the registers and can be connect ed to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into t he tap instruction register. tdi is connect ed to the most significant bit (msb) of any register. for more information regarding instruction r egister loading, please see the tap controller state diagram. 4. test data-out (tdo) this signal uses vddq as a power supply. the tdo output ball is used to serially clock te st instructions and data out from the registers. the tdo output driver is only active dur ing the shift-ir and shift-dr tap controller states. in all other states, the tdo pin is in a high- z state. the output changes on the falli ng edge of tck. tdo is connected to the least significant bit (lsb) of any register. for more information, please see the tap controller state diagram. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 22 tap controller state and block diagram tap controller state machine test logic reset select dr run test idle 0 11 capture dr 0 1 0 0 1 0 1 1 0 shift dr exit1 dr pause dr exit2 dr 1 1 update dr 0 select ir 1 capture ir 0 1 0 0 1 0 1 shift ir exit1 ir pause ir exit2 ir 1 1 update ir 0 0 0 10 10 is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 23 performing a tap reset a reset is performed by forcing tms high (vdd) for five rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at pow er-up, the tap is internally reset to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. 1. instruction register this register is loaded during the update-ir state of the tap controller. at power-up, the in struction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two lsbs are loaded with a binary ?01? pattern to allow for fault isolat ion of the board-level serial test data path. 2. bypass register the bypass register is a single-bit regist er that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. 3. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. several balls are also included in the scan register to reserved balls. the boundar y scan register is loaded with the contents of the sram input and output ring when the tap controller is in the c apture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr stat e. each bit corresponds to one of the balls on the sram package. the msb of the register is connecte d to tdi, and the lsb is connected to tdo. 4. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hard wired into the sram and can be shifted out when the tap controller is in the shift-dr state. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 109 tap instruction set many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the tap instruction code table. all other instru ction codes that are not listed on this table are reserved and should not be used. instructions are loaded into the tap controller during the shi ft-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted fr om the instruction register through the tdi and tdo pins. to execute an instruction once it is shifted in, the t ap controller must be moved into the update-ir state. 1. extest the extest instruction allows circuitry external to the co mponent package to be tested. boundary-scan register cells at output balls are used to apply a test vector, while those at input balls capture test resu lts. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan register using the preload is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 24 instruction. thus, during the update-ir state of extest, the output driver is turned on, and the preload data is driven onto the output balls. 2. idcode the idcode instruction causes a vendor- specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be sh ifted out of the device when the tap controller enters the shift-dr stat e. the idcode instruction is loaded in to the instruction register upon power- up or whenever the tap controller is given a test logic reset state. 3. sample z if the sample-z instruction is loaded in the instruction regi ster, all sram outputs are forced to an inactive drive state (high-z), moving the tap controller into the capture-dr state loads the data in the srams input into the boundary scan register, and the boundary scan register is connect ed between tdi and tdo when the tap controller is moved to the shift-dr state. 4. sample/preload when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that the tap c ontroller clock can only operate at a frequency up to 50 mhz, while the sram clock operates significantly faster. because there is a large difference between the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition. this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to ensure that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time. the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/ preload instruction. if this is an issue, it is still possible to capt ure all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. 6. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. 7. private do not use these instructions. they are reserved for future use and engineering mode. jtag dc operating characteristics (over the operating temperature range, v dd =1.8v5%) parameter symbol min max units notes jtag input high voltage v ih1 1.3 v dd +0.3 v jtag input low voltage v il1 ?0.3 0.5 v jtag output high voltage v oh1 1.4 - v |i oh1 |=2ma jtag output low voltage v ol1 - 0.4 v i ol1 =2ma jtag output high voltage v oh2 1.6 - v |i oh2 |=100ua jtag output low voltage v ol2 - 0.2 v i ol2 =100ua jtag input leakage current i lijtag -100 +100 ? a 0 vin vdd jtag output leakage current i lojtag -5 +5 ? a 0 vout vdd notes: 1. all voltages referenced to vss (gnd); all jt ag inputs and outputs are lvttl-compatible. 2. in ?extest? mode and ?sample? mode, v ddq is nominally 1.5 v. is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 25 jtag ac test conditions (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v) parameter symbol conditions units input pulse high level v ih1 1.3 v input pulse low level v il1 0.5 v input rise time t r1 1.0 ns input fall time t f1 1.0 ns input and output timing reference level 0.9 v jtag ac characteristics (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v) parameter symbol min max units tck cycle time t thth 50 ? ns tck high pulse width t thtl 20 ? ns tck low pulse width t tlth 20 ? ns tms setup t mvth 5 ? ns tms hold t thmx 5 ? ns tdi setup t dvth 5 ? ns tdi hold t thdx 5 ? ns tck low to valid data* t tlov ? 10 ns note: see ac test loading(c) jtag timing diagram is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 26 instruction set code instruction tdo output notes 000 extest boundary scan register 2, 6 001 idcode 32-bit identification register 010 sample-z boundary scan register 1, 2 011 private do not use 5 100 sample(/preload) boundary scan register 4 101 private do not use 5 110 private do not use 5 111 bypass bypass register 3 notes: 1. places qs in high-z in order to sample all input data, regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds the last serially loaded tdi when exiting the shift-dr state. 4. sample instruction does not place qs in high-z. 5. this instruction is reserved. invoking this instruction will cause improper sram functionality. 6. this extest is not ieee 1149.1-compliant. by de fault, it places q in high-z. if the inte rnal register on the scan chain is set high, q will be updated with information loaded via a previous sample instruction. the actual transfer occurs during the update ir state after extest is loaded. the value of the internal regist er can be changed during sample and extest only . id register definition revision number (32:29) part configuration (28:12) jedec code ( 11:1) start bit (0) 000 00def0wx01pqlb0s0 00011010101 1 part configuration definition: 1. def = 010 for 36mb 2. wx = 11 for x36, 10 for x18 3. p = 1 for ii+(quad-p/ddr- iip), 0 for ii(quad/ddr-ii) 4. q = 1 for quad, 0 for ddr-ii 5. l = 1 for rl=2.5, 0 for rl 2.5 6. b = 1 for burst of 4, 0 for burst of 2 7. s = 1 for separate i/o, 0 for common i/o list of ieee 1149.1 standard violations ? 7.2.1.b, e ? 7.7.1.a-f ? 10.1.1.b, e ? 10.7.1.a-d ? 6.1.1.d is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 27 boundary scan exit order order pin id order pin id order pin id 1 6r 37 10d 73 2c 2 6p 38 9e 74 3e 3 6n 39 10c 75 2d 4 7p 40 11d 76 2e 5 7n 41 9c 77 1e 6 7r 42 9d 78 2f 7 8r 43 11b 79 3f 8 8p 44 11c 80 1g 9 9r 45 9b 81 1f 10 11p 46 10b 82 3g 11 10p 47 11a 83 2g 12 10n 48 10a 84 1h 13 9p 49 9a 85 1j 14 10m 50 8b 86 2j 15 11n 51 7c 87 3k 16 9m 52 6c 88 3j 17 9n 53 8a 89 2k 18 11l 54 7a 90 1k 19 11m 55 7b 91 2l 20 9l 56 6b 92 3l 21 10l 57 6a 93 1m 22 11k 58 5b 94 1l 23 10k 59 5a 95 3n 24 9j 60 4a 96 3m 25 9k 61 5c 97 1n 26 10j 62 4b 98 2m 27 11j 63 3a 99 3p 28 11h 64 2a 100 2n 29 10g 65 1a 101 2p 30 9g 66 2b 102 1p 31 11f 67 3b 103 3r 32 11g 68 1c 104 4r 33 9f 69 1b 105 4p 34 10f 70 3d 106 5p 35 11e 71 3c 107 5n 36 10e 72 1d 108 5r 109 internal notes: 1. nc pins as defined on the fbga ball assignments are read as ?don?t cares?. 2. state of internal pin (#109) is loaded via jtag is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 28 ordering information commercial range: 0c to +70c speed order part no. organization package 450mhz is61ddpb21m36a-450m3 1mx36 165 fbga is61ddpb21m36a-450m3l 1mx36 166 fbga, lead free is61ddpb22m18a-450m3 2mx18 165 fbga is61ddpb22m18a-450m3l 2mx18 166 fbga, lead free 400mhz is61ddpb21m36a-400m3 1mx36 165 fbga is61ddpb21m36a-400m3l 1mx36 166 fbga, lead free is61ddpb22m18a-400m3 2mx18 165 fbga is61ddpb22m18a-400m3l 2mx18 166 fbga, lead free 333mhz is61ddpb21m36a-333m3 1mx36 165 fbga is61ddpb21m36a-333m3l 1mx36 166 fbga, lead free is61ddpb22m18a-333m3 2mx18 165 fbga is61ddpb22m18a-333m3l 2mx18 166 fbga, lead free 400mhz is61ddpb21m36a-300m3 1mx36 165 fbga is61ddpb21m36a-300m3l 1mx36 166 fbga, lead free is61ddpb22m18a-300m3 2mx18 165 fbga is61ddpb22m18a-300m3l 2mx18 166 fbga, lead free industrial range: -40c to +85c speed order part no. organization package 450mhz is61ddpb21m36a-450m3i 1mx36 165 fbga is61ddpb21m36a-450m3li 1mx36 166 fbga, lead free is61ddpb22m18a-450m3i 2mx18 165 fbga is61ddpb22m18a-450m3li 2mx18 166 fbga, lead free 400mhz is61ddpb21m36a-400m3i 1mx36 165 fbga is61ddpb21m36a-400m3li 1mx36 166 fbga, lead free is61ddpb22m18a-400m3i 2mx18 165 fbga is61ddpb22m18a-400m3li 2mx18 166 fbga, lead free 333mhz is61ddpb21m36a-333m3i 1mx36 165 fbga IS61DDPB21M36A-333M3LI 1mx36 166 fbga, lead free is61ddpb22m18a-333m3i 2mx18 165 fbga is61ddpb22m18a-333m3li 2mx18 166 fbga, lead free 300mhz is61ddpb21m36a-300m3i 1mx36 165 fbga is61ddpb21m36a-300m3li 1mx36 166 fbga, lead free is61ddpb22m18a-300m3i 2mx18 165 fbga is61ddpb22m18a-300m3li 2mx18 166 fbga, lead free is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 29 package drawing ? 15x17x1.2 bga note : 1. controlling dimension : mm package outline 12/10/2007 is61ddp2b22m18a is61ddp2b21m36a integrated silicon solution, inc.- www.issi.com rev. 00a 4/29/2010 30 package drawing ? 13x15x1.2 bga 1. controlling dimension : mm . note : pac k age outline 08/28/2008 |
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