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| ds557 november 19, 2009 www.xilinx.com product specification 1 ? copyright 2007?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. pci, pci express, pcie, and pci-x are trademarks of pci-sig. all other trademarks are the property of their re spective owners. module 1: introduction and ordering information ds557-1 (v3.2) november 19, 2009 ? introduction ? features ? architectural overview ? configuration overview ? in-system flash memory overview ? general i/o capabilities ? supported packages and package marking ? ordering information module 2: functional description ds557-2 (v3.2) november 19, 2009 the functionality of the spartan?-3an fpga family is described in the following documents: ? ug331 : spartan-3 generation fpga user guide - clocking resources - digital clock managers (dcms) - block ram - configurable logic blocks (clbs) distributed ram srl16 shift registers carry and arithmetic logic - i/o resources - embedded multiplier blocks - programmable interconnect - ise? design tools and ip cores - embedded processing and control solutions - pin types and package overview - package drawings - powering fpgas - power management ? ug332 : spartan-3 generation conf iguration user guide - configuration overview - configuration pins and behavior - bitstream sizes - detailed descriptions by mode self-contained in-system flash mode master serial mode using platform flash prom master spi mode using commodity serial flash master bpi mode using commodity parallel flash slave parallel (selectmap) using a processor slave serial using a processor jtag mode - ise impact programming examples - multiboot reconfiguration - design authentication using device dna ? ug333 : spartan-3an in-system flash user guide ? ug33 4 : spartan-3an starter kit user guide module 3: dc and swit ching characteristics ds557-3 (v3.2) november 19, 2009 ? dc electrical characteristics - absolute maximum ratings - supply voltage specifications - recommended operating conditions ? switching characteristics - i/o timing - configurable logic block (clb) timing - multiplier timing - block ram timing - digital clock manager (dcm) timing - suspend mode timing - device dna timing - configuration and jtag timing module 4: pinout descriptions ds557-4 (v3.2) november 19, 2009 ? pin descriptions ? package overview ?pinout tables ? footprint diagrams additional information on the spartan-3an family can be found at http://www.xilinx. com/products/spartan3a/3an.htm . 0 spartan-3an fpga family data sheet ds557 november 19, 2009 0 0 product specification r ta bl e 1 : production status of spartan-3an fpgas spartan-3an fpga status xc3s50an production xc3s200an production xc3s400an production xc3s700an production xc3s1400an production
www.xilinx.com ds557 november 19, 2009 2 product specification r ds557-1 (v3.2) november 19, 2009 www.xilinx.com product specification 3 ? copyright 2007?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. pci, pci express, pcie, and pci-x are trademarks of pci-sig. all other trademarks are the property of their re spective owners. introduction the spartan?-3an fpga family combines the best attributes of a leading edge, low cost fpga with nonvolatile technology across a broad range of densities. the family combines all the features of the spartan-3a fpga family plus leading technology in -system flash memory for configuration and nonvolatile data storage. the spartan-3an fpgas are part of the extended spartan-3a family, which also includes the spartan-3a fpgas and the higher density spartan-3a dsp fpgas. the spartan-3an fpga family is excellent for space-constrained applications such as blade servers, medical devices, automotive infotainment, telematics, gps, and other small consumer products. combining fpga and flash technology minimizes chip count, pcb traces and overall size while incr easing system reliability. the spartan-3an fpga internal configuration interface is completely self-contained, increasing design security. the family maintains full support fo r external configuration. the spartan-3an fpga is the world?s first nonvolatile fpga with multiboot, supporting two or more configuration files in one device, allowing alternative configurations for field upgrades, test modes, or multiple system configurations. features ? the new standard for low cost nonvolatile fpga solutions ? eliminates traditional nonvolatile fpga limitations with the advanced 90 nm spartan-3a device feature set ? memory, multipliers, dcms, selectio, hot swap, power management, etc. ? integrated robust configuration memory ? saves board space ? improves ease-of-use ? simplifies design ? reduces support issues ? plentiful amounts of nonvolatile memory available to the user ? up to 11+ mb available ? multiboot support ? embedded processing and code shadowing ? scratchpad memory ? robust 100k flash memory program/erase cycles ? 20 years flash memory data retention ? security features provide bitstream anti-cloning protection ? buried configuration interface ? unique device dna serial number in each device for design authentication to prevent unauthorized copying ? flash memory sector protection and lockdown ? configuration watchdog timer automatically recovers from configuration errors ? suspend mode reduces system power consumption ? retains all design state and fpga configuration data ? fast response time, typically less than 100 s ? full hot-swap compliance ? multi-voltage, multi-standa rd selectio? interface pins ? up to 502 i/o pins or 227 differential signal pairs ? lvcmos, lvttl, hstl, and sstl single-ended signal standards ? 3.3v, 2.5v, 1.8v, 1.5v, and 1.2v signaling ? up to 24 ma output drive ? 3.3v 10% compatibility and hot swap compliance ? 622+ mb/s data transfer rate per i/o ? ddr/ddr2 sdram support up to 400 mb/s ? lvds, rsds, mini-lvds, ppds, and hstl/sstl differential i/o ? abundant, flexible logic resources ? densities up to 25,344 logic cells ? optional shift register or distributed ram support ? enhanced 18 x 18 multipliers with optional pipeline ? hierarchical selectram? memory architecture ? up to 576 kbits of dedicated block ram ? up to 176 kbits of efficient distributed ram ? up to eight digital clock managers (dcms) ? eight global clocks and eight additional clocks per each half of device, plus abundant low-skew routing ? complete xilinx? ise ? and webpack ? software development system support ? microblaze ? and picoblaze ? embedded processor cores ? fully compliant 32-/64-bit 33 mhz pci? technology support ? low-cost qfp and bga pb-free (rohs) packaging options ? pin-compatible with the same packages in the spartan-3a fpga family < b l b spartan-3an fpga family: introduction and ordering information ds557-1 (v3.2) november 19, 2009 product specification r ta bl e 2 : summary of spartan-3an fpga attributes device system gates equivalent logic cells clbs slices distributed ram bits ( 1 ) block ram bits ( 1 ) dedicated multipliers dcms maximum user i/o maximum differential i/o pairs bitstream size ( 1 ) in-system flash bits xc3s50an 50k 1,584 176 704 11k 54k 3 2 108 50 427k 1m xc3s200an 200k 4,032 448 1792 28k 288k 16 4 195 90 1,168k 4m xc3s400an 400k 8,064 896 3,584 56k 360k 20 4 311 142 1,842k 4m xc3s700an 700k 13,248 1472 5,888 92k 360k 20 8 372 165 2,669k 8m xc3s1400an 1400k 25,344 2816 11,264 176k 576k 32 8 502 227 4,644k 16m notes: 1. by convention, one kb is equivalent to 1, 024 bits and one mb is equivalent to 1,024 kb. introduction and ordering information w ww.xilinx.com ds557-1 (v3.2) november 19, 2009 4 product specification r architectural overview the spartan-3an fpga architectu re is compatible with that of the spartan-3a fpga. the architecture consists of five fundamental programmable functional elements: ? configurable logic blocks (clbs) contain flexible look-up tables (luts) that implement logic plus storage elements used as flip-flops or latches. ? input/output blocks (iobs) control the flow of data between the i/o pins and the internal logic of the device. iobs support bidirectional data flow plus 3-state operation. they support a variety of signal standards, including several high-performance differential standards. double data-rate (ddr) registers are included. ? block ram provides data storage in the form of 18-kbit dual-port blocks. ? multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. ? digital clock manager (dcm) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. these elements are organized as shown in figure 1 . a dual ring of staggered iobs surrounds a regular array of clbs. each device has two columns of block ram except for the xc3s50an, which has one column. each ram column consists of several 18-kbit ram blocks. each block ram is associated with a dedicated multiplier. the dcms are positioned in the center with two at the top and two at the bottom of the device. the xc3s50an has dcms only at the top, while the xc3s700an and xc3s1400an add two dcms in the middle of the two columns of block ram and multipliers. the spartan-3an fpga features a rich network of traces that interconnect all five functional elements, transmitting signals among them. each functional element has an associated switch matrix that permits multiple connections to the routing. x-ref target - figure 1 figure 1: spartan-3an family architecture clb block ram multiplier dcm iobs iobs ds557-1_01_122006 iobs iobs dcm block ram / multiplier dcm clbs iobs ob s d c m notes: 1. the xc3s700an and xc3s1400an have two additional dcms on both the left and right sides as indicated by the dashed lines. the xc3s50an has only two dcms at the top and only one block ram/multiplier column. introduction and ordering information ds557-1 (v3.2) november 19, 2009 www.xilinx.com product specification 5 r configuration spartan-3an fpgas are programmed by loading configuration data into robust, reprogrammable, static cmos configuration latches (ccl s) that collectively control all functional elements and routing resources. the fpga?s configuration data is stored on-chip in nonvolatile flash memory, or externally in a prom or some other nonvolatile medium, either on or off the board. after applying power, the configuration data is written to the fpga using any of seven different modes: ? configure from internal spi flash memory ( figure 2 ) ? completely self-contained ? reduced board space ? easy-to-use config uration interface ? master serial from a x ilinx platform flash prom ? serial peripheral interface (spi) from an external industry-standard spi serial flash ? byte peripheral interface (bpi) up from an industry-standard x8 or x8/x16 parallel nor flash ? slave serial, typically downloaded from a processor ? slave parallel, typically downloaded from a processor ? boundary-scan (jtag), typically downloaded from a processor or system tester the multiboot feature stores mu ltiple configur ation files in the on-chip flash, providing extended life with field upgrades. multiboot also supports multiple system solutions with a single board to minimize inventory and simplify the addition of new features, even in the field. flexibility is maintained to do additional multiboot configurations via the external configuration method. the spartan-3an device authentication protocol prevents cloning. design cloning, unauthorized overbuilding, and complete reverse engineering have driven device security requirements to higher and higher levels. authentication moves the security from bitstream protection to the next generation of design-level security protecting both the design and embedded microcode. the authentication algorithm is entirely user defined, implemented using fpga logic. every product, generation, or design can have a different algorithm and functionality to enhance security. in-system flash memory each spartan-3an fpga contains abundant integrated spi serial flash memory, shown in ta b l e 3 , used primarily to store the fpga?s configuration bitstream. however, the flash memory array is large enough to store at least two multiboot fpga configuration bitstreams or nonvolatile data required by the fpga application, such as code-shadowed microblaze processor applications. after configuration, the fpga design has full access to the in-system flash memory via an internal spi interface; the control logic is implemented wi th fpga logic. additionally, the fpga application itself can store nonvolatile data or provide live, in-system flash updates. the spartan-3an device in-system flash memory supports leading-edge serial flash features. ? small page size (264 or 528 bytes) simplifies nonvolatile data storage ? randomly accessible, byte addressable ? up to 66 mhz serial data transfers ? sram page buffers ? read flash data while programming another flash page ? eeprom-like byte wr ite functionality ? two buffers in most devices, one in xc3s50an ? page, block, and sector erase ? sector-based data protection and security features x-ref target - figure 2 figure 2: spartan-3an fpga configuration interface from internal spi flash memory m2 m1 m0 vccaux init_b done s partan- 3 an fpga ?0 ? ?1 ? ?1 ? 3 . 3 v config u re from intern a l fl as h memory indic a te s when config u r a tion i s fini s hed d s 557-1_06_01 3 107 table 3: spartan-3an device in-system flash memory part number total flash memory (bits) fpga bitstream (bits) additional flash memory (bits) (1) xc3s50an 1,081,344 437,312 642,048 xc3s200an 4,325,376 1,196,128 3,127,872 xc3s400an 4,325,376 1,886,560 2,437,248 xc3s700an 8,650,752 2,732,640 5,917,824 xc3s1400an 17,301,504 4,755,296 12,545,280 1. aligned to next available page location. introduction and ordering information w ww.xilinx.com ds557-1 (v3.2) november 19, 2009 6 product specification r ? sector protect: write- and erase-protect a sector (changeable) ? sector lockdown: sector data is unchangeable (permanent) ? 128-byte security register ? separate from fpga?s unique device dna identifier ? 64-byte factory-programmed identifier unique to the in-system flash memory ? 64-byte one-time programmable, user-programmable field ? 100,000 program/erase cycles ? 20-year data retention ? comprehensive programming support ? in-system prototype programming via jtag using xilinx platform cable usb and impact software ? product programming support using bpm microsystems programmers with appropriate programming adapter ? design examples demonstrating in-system programming from a spartan-3an fpga application i/o capabilities the spartan-3an fpga selectio interface supports many popular single-ended and differential standards. ta bl e 4 shows the number of user i/os as well as the number of differential i/o pairs available for each device/package combination. some of the user i/os are unidirectional, input-only pins as indicated in ta bl e 4 . spartan-3an fpgas support the following single-ended standards: ? 3.3v low-voltage ttl (lvttl) ? low-voltage cmos (lvcmos) at 3.3v, 2.5v, 1.8v, 1.5v, or 1.2v ? 3.3v pci at 33 mhz or 66 mhz ? hstl i, ii, and iii at 1.5v and 1.8v, commonly used in memory applications ? sstl i and ii at 1.8v, 2.5v, and 3.3v, commonly used for memory applications spartan-3an fpgas support the following differential standards: ? lvds, mini-lvds, rsds, and ppds i/o at 2.5v or 3.3v ? bus lvds i/o at 2.5v ? tmds i/o at 3.3v ? differential hstl and sstl i/o ? lvpecl inputs at 2.5v or 3.3v ta bl e 4 : available user i/os and differential (diff) i/o pairs package tq144 tqg144 ft256 ftg256 fg400 fgg400 fg484 fgg484 fg676 fgg676 body size (mm) (4) 20 x 20 17 x 17 21 x 21 23 x 23 27 x 27 device user diff user diff user diff user diff user diff xc3s50an 108 (7) 50 (24) ? ? ? ? ? ? ? ? xc3s200an ? ? 195 (35) 90 (50) ? ? ? ? ? ? xc3s400an ? ? ? ? 311 (63) 142 (78) ? ? ? ? xc3s700an ? ? ? ? ? ? 372 (84) 165 (93) ? ? xc3s1400an ? ? ? ? ? ? ? ? 502 (94) 227 (131) notes: 1. the number shown in bold indicates the maximum number of i/o and input-only pins. the number shown in ( italics ) indicates the number of input-only pins. the diff input-only pin count includes dedicated inputs and differential pins on banks restricted to inputs . the differential (diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on i/o pins within i/o b anks that are restricted to differential inputs. 2. see "pb and pb-free packaging," page 8 for details on pb and pb-free packaging options. 3. each spartan-3an fpga has a pin-compatib le spartan-3a fpga equivalent, although spar tan-3a fpgas do not have internal spi fla sh and offer more part/package combinations. 4. the footprint for the tq(g)144 (22 mm x 22 mm) package is larger than the package body. introduction and ordering information ds557-1 (v3.2) november 19, 2009 www.xilinx.com product specification 7 r package marking figure 3 provides a top marking example for spartan-3an fpgas in the quad-flat packages. figure 4 shows the top marking for spartan-3an fpgas in bga packages. the markings for the bga packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball a1 indicator. the ? 5c ? and ? 4i ? speed grade/temperature range part combinations may be dual marked as ? 5c/4i ?. devices with the dual mark can be used as either -5c or -4i devices. devices with a single mark are only guaranteed for the marked speed grade and temperature range. x-ref target - figure 3 figure 3: spartan-3an fpga qfp package marking example date code mask revision code process technology xc3s50an tm tqg144 agq0725 d1234567a 4c spartan temperature range fabrication code pin p1 device type package speed grade r r ds557-1_02_080107 lot code x-ref target - figure 4 figure 4: spartan-3an fpga bga package marking example lot code date code xc3s200an tm 4c spartan device type bga ball a1 package speed grade temperature range r r ds557-1_03_080107 ftg256 a gq0725 d1234567a mask revision code process code fabrication code introduction and ordering information w ww.xilinx.com ds557-1 (v3.2) november 19, 2009 8 product specification r pb and pb-free packaging spartan-3an fpgas are available in both leaded (pb) and pb-free packaging options (see ta bl e 5 ). the pb-free packages are available for all devices and include a ? g? character in the ordering code. leaded (non-pb-free) packages are available for selected devices. these devices have no ? g? in the ordering code and have the same pin-out as pb-free packages. ordering information ta bl e 5 : pb and pb-free package options pins 144 256 400 484 676 type tqfp ftbga fbga fbga fbga material pb-free pb pb-free pb pb-free pb pb-free pb pb-free pb device speed range tqg144 tq144 ftg256 ft256 fgg400 fg400 fgg484 fg484 fgg676 fg676 xc3s50an -4 c, i ? scd4100 (1) -5 c ? (2) xc3s200an -4 c, i ?? -5 c ?? xc3s400an -4 c, i ?? -5 c ? (2) xc3s700an -4 c, i ?? -5 c ? (2) xc3s1400an -4 c, i ?? -5 c ? (2) notes: 1. to order a pb package for the xc3s50an -4 option, a ppend scd4100 to the part num ber (xc3s50an-4tq144c4100). 2. for pb packaging for these options, contact your xilinx sales representative. x-ref target - figure 5 figure 5: device numbering format xc 3s 50an -4 tqg144 c device type s peed gr a de temper a t u re r a nge: p a ck a ge type/n u m b er of pin s example: d s 557-1_05_101109 c = commerci a l (t j = 0 o c to 8 5 o c) i = ind us tri a l (t j = -40 o c to 100 o c) device speed grade package type / number of pins temperature range ( t j ) xc3s50an ?4 standard performance tq144/ tqg144 144-pin thin quad flat pack (tqfp) c commercial (0c to 85c) xc3s200an ?5 high performance (1) ft256/ ftg256 256-ball fine-pitch thin ball grid array (ftbga) i industrial (?40c to 100c) xc3s400an fg400/ fgg400 400-ball fine-pitch ball grid array (fbga) xc3s700an fg484/ fgg484 484-ball fine-pitch ball grid array (fbga) xc3s1400an fg676/ fgg676 676-ball fine-pitch ball grid array (fbga) notes: 1. the ?5 speed grade is exclusively available in the commercial temperature range. 2. see ta b l e 4 and ta bl e 5 for available package combinations. introduction and ordering information ds557-1 (v3.2) november 19, 2009 www.xilinx.com product specification 9 r revision history the following table shows the revision history for this document. notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all s pecifications are subject to change without notice. products are not designed or intended to be fail-saf e or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. date version revision 02/26/07 1.0 initial release. 08/16/07 2.0 updated for production release of initial device. 09/12/07 2.0.1 noted that only dual-mark devices are guaranteed for both -4i and -5c. 12/12/07 3.0 updated to production status with production release of final fa mily member, xc3s 50an. noted that non-pb-free packages may be available for selected devices. 06/02/08 3.1 minor updates. 11/19/09 3.2 updated document throughout to reflect availab ility of pb package options. added references to the extended spartan-3a family. removed table note 2 from ta bl e 2 . in ta b l e 4 , added pb packages, added table note 4, and updated table note 2. added ta b l e 5 . introduction and ordering information w ww.xilinx.com ds557-1 (v3.2) november 19, 2009 10 product specification r ds557-2 (v3.2) november 19, 2009 www.xilinx.com product specification 11 ? copyright 2007?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. spartan-3an fpga design documentation the functionality of the spartan?-3an fpga family is described in the following documents. the topics covered in each guide are listed below: ? ds706: extended spartan-3a family overview www.xilinx.com/support/documentation/ data_sheets/ds706.pdf ? ug331: spartan-3 generation fpga user guide http://www.xilinx.com/ support/documentation/ u ser _ guides/ug331.pdf ? clocking resources ? digital clock managers (dcms) ? block ram ? configurable logic blocks (clbs) - distributed ram - srl16 shift registers - carry and arithmetic logic ? i/o resources ? embedded multiplier blocks ? programmable interconnect ? ise ? design tools ? ip cores ? embedded processing and control solutions ? pin types and package overview ? package drawings ? powering fpgas ? power management ? ug332: spartan-3 generation configuration user guide http://www.xilinx.com/ support/documentation/ u ser _ guides/ug332.pdf ? configuration overview - configuration pins and behavior - bitstream sizes ? detailed descriptions by mode - master serial mode using xilinx? platform flash - master spi mode using spi serial flash prom - internal master spi mode - master bpi mode using parallel nor flash - slave parallel (selectmap) using a processor - slave serial using a processor - jtag mode ? ise impact programming examples ? multiboot reconfiguration ? design authentication using device dna ? ug333: spartan-3an fpga in-system flash user guide http://www.xilinx.com/ support/documentation/ u ser _ guides/ug333.pdf ? for fpga applications that write to or read from the in-system flash memory after configuration ? spi_access interface ? in-system flash memory architecture ? read, program, and erase commands ? status registers ? sector protection and sector lockdown features ? security register with unique identifier xilinx alerts create a xilinx mysupport user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated. sign up for alerts on xilinx mysupport http:// www.xilinx.com/ support/answers/1 938 0.htm spartan-3an fpga starter kit for specific hardware examples, please see the spartan-3an fpga starter kit board web page, which has links to various design examples and the user guide. ? spartan-3an fpga starter kit board page http://www.xilinx.com/s3a n starter ? ug334: spartan-3an fpga starter kit user guide http://www.xilinx.com/ support/documentation/ boards_and_kits/ ug33 4. pd f functional description w ww.xilinx.com ds557-2 (v3.2) november 19, 2009 12 product specification r related product families the spartan-3an fpga family is generally compatible with the spartan-3a fpga family. ? ds529: spartan-3a fpga family data sheet http://www.xilinx.com/ support/documentation/ data_sheets/ ds529.pdf create a xilinx? mysupport us er account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated. ? sign up for alerts on xilinx mysupport revision history the following table shows the revision history for this document. notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all s pecifications are subject to change without notice. products are not designed or intended to be fail-saf e or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. date version revision 02/26/07 1.0 initial release. 08/16/07 2.0 updated for production release of initial device. 09/12/07 2.0.1 minor updates to text. 09/24/07 2.1 added note that in-system flash commands we re not supported by simulation until ise 10.1 software. 12/12/07 3.0 updated to production status with production release of final fa mily member, xc3s 50an. noted that spi_access simulation is supported in ise 10.1 software. updated links. 06/02/08 3.1 minor updates. 11/19/09 3.2 in the "spartan-3an fpga design documentation" section, added link to ds706 , extended spartan-3a family overview and removed references to older software versions. ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 13 ? copyright 2007?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. pci, pci express, pcie, and pci-x are trademarks of pci-sig. all other trademarks are the property of their re spective owners. dc electrical characteristics in this section, specific ations can be designated as advance, preliminary, or production. these terms are defined as follows: advance: initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics of other fam ilies. values are subject to change. use as estimates, not for production. preliminary: based on characterization. further changes are not expected. production: these specifications are approved once the silicon has been characterized over numerous production lots. parameter values are considered stable with no future changes expected. all parameter limits are representative of worst-case supply voltage and junction temperature conditions. unless otherwise noted, the published parameter values apply to all spartan ? -3an devices. ac and dc characteristics are specified using the same numbers for both commercial and industrial grades. absolute maximum ratings stresses beyond those listed under ta bl e 6 : absolute maximum ratings might cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the recommended operating conditions is not implied. exposure to absolute maximum conditions for extended periods of time adverse ly affects device reliability. dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 14 product specification r power supply specifications ta bl e 7 : supply voltage thresholds for power-on reset symbol description min max units v ccintt threshold for the v ccint supply 0.4 1.0 v v ccauxt threshold for the v ccaux supply 1.0 2.0 v v cco2t threshold for the v cco bank 2 supply 1.0 2.0 v notes: 1. when configuring from the in-system flash, v ccaux must be in the recommended operating range; on power-up make sure v ccaux reaches at least 3.0v before init_b goes high to indicate the start of configuration. v ccint , v ccaux , and v cco supplies to the fpga can be applied in any order if this requirement is met. however, an external configuration source might have specific requirements. check the data sheet for the attached configuration source. apply v ccint last for lowest overall power consumption (see the chapter called ?powering spartan-3 generation fpgas? in ug331 for more information). 2. to ensure successful power-on, v ccint , v cco bank 2, and v ccaux supplies must rise through their respective threshold-voltage ranges with no dips at any point. ta bl e 8 : supply voltage ramp rate symbol description min max units v ccintr ramp rate from gnd to valid v ccint supply level 0.2 100 ms v ccauxr ramp rate from gnd to valid v ccaux supply level 0.2 100 ms v cco2r ramp rate from gnd to valid v cco bank 2 supply level 0.2 100 ms notes: 1. when configuring from the in-system flash, v ccaux must be in the recommended operating range; on power-up make sure v ccaux reaches at least 3.0v before init_b goes high to indicate the start of configuration. v ccint , v ccaux , and v cco supplies to the fpga can be applied in any order if this requirement is met. however, an external configuration source might have specific requirements. check the data sheet for the attached configuration source. apply v ccint last for lowest overall power consumption (see the chapter called ?powering spartan-3 generation fpgas? in ug331 for more information). 2. to ensure successful power-on, v ccint , v cco bank 2, and v ccaux supplies must rise through their respective threshold-voltage ranges with no dips at any point. ta bl e 9 : supply voltage levels necessary for preserving cmos configuration latch (ccl) contents and ram data symbol description min units v drint v ccint level required to retain cmos configuration latch (ccl) and ram data 1.0 v v draux v ccaux level required to retain cmos conf iguration latch (ccl) and ram data 2.0 v dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 15 r general recommended op erating conditions ta bl e 1 0 : general recommended operating conditions symbol description min nominal max units t j junction temperature commercial 0 -85 c industrial ?40 - 100 c v ccint internal supply voltage 1.14 1.20 1.26 v v cco (1) output driver supply voltage 1.10 -3.60v v ccaux auxiliary supply voltage v ccaux = 3.3v 3.00 3.30 3.60 v v in (2) input voltage pci? iostandard ?0.5 ?v cco +0.5 v all other iostandards ?0.5 ?4.10v t in input signal transition time (3) - - 500 ns notes: 1. this v cco range spans the lowest and highest operating voltages for all supported i/o standards. table 13 lists the recommended v cco range specific to each of the single-ended i/o standards, and table 15 lists that specific to the differential standards. 2. see xapp459 , ?eliminating i/o coupling effects when interfacing large-swing single-ended signals to user i/o pins. ? 3. measured between 10% and 90% v cco . follow signal integrity recommendations. dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 16 product specification r general dc characteristics for i/o pins ta bl e 1 1 : general dc characteristics of user i/o, dual-purpose, and dedicated pins symbol description test conditions min typ max units i l leakage current at user i/o, input-only, dual-purpose, and dedicated pins, fpga powered driver is in a high-impedance state, v in = 0v or v cco max, sample-tested ?10 ?+10 a i hs leakage current on pins during hot socketing, fpga unpowered all pins except init_b, prog_b, done, and jtag pins when pudc_b = 1. ?10 ?+10 a init_b, prog_b, done, and jtag pins or other pins when pudc_b = 0. add i hs + i rpu a i rpu (2) current through pull-up resistor at user i/o, dual-purpose, input-only, and dedicated pins. dedicated pins are powered by v ccaux . v in = gnd v cco or v ccaux = 3.0v to 3.6v ?151 ?315 ?710 a v cco = 2.3v to 2.7v ?82 ?182 ?437 a v cco = 1.7v to 1.9v ?36 ?88 ?226 a v cco = 1.4v to 1.6v ?22 ?56 ?148 a v cco = 1.14v to 1.26v ?11 ?31 ?83 a r pu (2) equivalent pull-up resistor value at user i/o, dual-purpose, input-only, and dedicated pins (based on i rpu per note 2) v in = gnd v cco = 3.0v to 3.6v 5.1 11.4 23.9 k v cco = 2.3v to 2.7v 6.2 14.8 33.1 k v cco = 1.7v to 1.9v 8.4 21.6 52.6 k v cco = 1.4v to 1.6v 10.8 28.4 74.0 k v cco = 1.14v to 1.26v 15.3 41.1 119.4 k i rpd (2) current through pull-down resistor at user i/o, dual-purpose, input-only, and dedicated pins v in = v cco v ccaux = 3.0v to 3.6v 167 346 659 a r pd (2) equivalent pull-down resistor value at user i/o, dual-purpose, input-only, and dedicated pins (based on i rpd per note 2) v ccaux = 3.0v to 3.6v v in = 3.0v to 3.6v 5.5 10.4 20.8 k v in = 2.3v to 2.7v 4.1 7.8 15.7 k v in = 1.7v to 1.9v 3.0 5.7 11.1 k v in = 1.4v to 1.6v 2.7 5.1 9.6 k v in = 1.14v to 1.26v 2.4 4.5 8.1 k i ref v ref current per pin all v cco levels ?10 ?+10 a c in input capacitance - ? ?10pf r dt resistance of optional differential termination circuit within a differential i/o pa ir. not available on input-only pairs. v cco = 3.3v 10% lvds_33, mini_lvds_33, rsds_33 90 100 115 v cco = 2.5v 10% lvds_25, mini_lvds_25, rsds_25 90 110 ? notes: 1. the numbers in this table are based on the conditions set forth in table 10 . 2. this parameter is based on characterization. the pull-up resistance r pu = v cco / i rpu . the pull-down resistance r pd = v in / i rpd . 3. v ccaux must be 3.3v on spartan-3an fpgas. v ccaux for spartan-3a fpgas can be either 3.3v or 2.5v. dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 17 r quiescent current requirements ta bl e 1 2 : spartan-3an fpga quiescent supply current characteristics symbol description device typical (2) commercial maximum (2) industrial maximum (2) units i ccintq quiescent v ccint supply current xc3s50an 2 20 30 ma xc3s200an 7 50 70 ma xc3s400an 10 85 125 ma xc3s700an 13 120 185 ma xc3s1400an 24 220 310 ma i ccoq quiescent v cco supply current xc3s50an 0.2 2 3 ma xc3s200an 0.2 2 3 ma xc3s400an 0.3 3 4 ma xc3s700an 0.3 3 4 ma xc3s1400an 0.3 3 4 ma i ccauxq quiescent v ccaux supply current xc3s50an 3.1 8.1 10.1 ma xc3s200an 5.1 12.1 15.1 ma xc3s400an 5.1 18.1 24.1 ma xc3s700an 6.1 28.1 34.1 ma xc3s1400an 10.1 50.1 58.1 ma notes: 1. the numbers in this table are based on the conditions set forth in table 10 . 2. quiescent supply current is measured with all i/o drivers in a high-impedance state and with all pull-up/pull-down resistors at the i/o pads disabled. the internal spi flash is deselected (csb = high); the internal spi flash current is consumed on the v ccaux supply rail. typical values are characterized using typical devices at room temperature (t j of 25c at v ccint = 1.2v, v cco = 3.3v, and v ccaux = 3.3v). the maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limit s with v ccint = 1.26v, v cco = 3.6v, and v ccaux = 3.6v. the fpga is programmed with a ?blank? configuration data file (that is, a design with no functional elements instantiated). for conditions other than those described above (for example, a design including functional elements), measured quiescent current levels will be different than the values in the table. 3. there are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) the spartan-3an fpga xpower estimator provides quick, approximate, typical estimates, and does not require a netlist of the design, and b) xpower analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. for more infor mation on power for the in-system flash memory, see the power management chapter of ug333 . 4. the maximum numbers in this table indicate the minimum current ea ch power rail requires in order for the fpga to power-on suc cessfully. 5. for information on the power-saving suspend mode, see xapp480 : using suspend mode in spartan-3 generation fpgas . suspend mode typically saves 40% total power consumption compared to quiescent current. dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 18 product specification r single-ended i/o standards ta bl e 1 3 : recommended operating conditions for user i/os using single-ended standards iostandard attribute v cco for drivers (2) v ref v il v ih min (v) nom (v) max (v) min (v) nom (v) max (v) max (v) min (v) lv t t l 3 . 0 3 . 3 3 . 6 v ref is not used for these i/o standards 0.8 2.0 lv c m o s 3 3 (4) 3.0 3.3 3.6 0.8 2.0 lv c m o s 2 5 (4,5) 2.3 2.5 2.7 0.7 1.7 lvcmos18 1.65 1.8 1.95 0.4 0.8 lvcmos15 1.4 1.5 1.6 0.4 0.8 lvcmos12 1.1 1.2 1.3 0.4 0.7 pci33_3 3.0 3.3 3.6 0.3 ? v cco 0.5 ? v cco pci66_3 3.0 3.3 3.6 0.3 ? v cco 0.5 ? v cco hstl_i 1.4 1.5 1.6 0.68 0.75 0.9 v ref - 0.1 v ref + 0.1 hstl_iii 1.4 1.5 1.6 ? 0.9 - v ref - 0.1 v ref + 0.1 hstl_i_18 1.7 1.8 1.9 0.8 0.9 1.1 v ref - 0.1 v ref + 0.1 hstl_ii_18 1.7 1.8 1.9 ? 0.9 ? v ref - 0.1 v ref + 0.1 hstl_iii_18 1.7 1.8 1.9 ? 1.1 ? v ref - 0.1 v ref + 0.1 sstl18_i 1.7 1.8 1.9 0.833 0.900 0.969 v ref - 0.125 v ref + 0.125 sstl18_ii 1.7 1.8 1.9 0.833 0.900 0.969 v ref - 0.125 v ref + 0.125 sstl2_i 2.3 2.5 2.7 1.13 1.25 1.38 v ref - 0.150 v ref + 0.150 sstl2_ii 2.3 2.5 2.7 1.13 1.25 1.38 v ref - 0.150 v ref + 0.150 sstl3_i 3.0 3.3 3.6 1.3 1.5 1.7 v ref - 0.2 v ref + 0.2 sstl3_ii 3.0 3.3 3.6 1.3 1.5 1.7 v ref - 0.2 v ref + 0.2 notes: 1. descriptions of the symbols used in this table are as follows: v cco ? the supply voltage for output drivers v ref ? the reference voltage for setting the input switching threshold v il ? the input voltage that indicates a low logic level v ih ? the input voltage that indicates a high logic level 2. in general, the v cco rails supply only output drivers, not input circuits. the exceptions are for lvcmos25 inputs and for pci? i/o standards. 3. for device operation, the maximum signal voltage (v ih max) can be as high as v in max. see ta b l e 6 . 4. there is approximately 100 mv of hysteresis on inputs using lvcmos33 and lvcmos25 i/o standards. 5. all dedicated pins (prog_b, done, suspend, tc k, tdi, tdo, and tms) draw power from the v ccaux rail and use the lvcmos33 standard. the dual-purpose configuration pins use the lvcmos standard before the user mode. when using these pins as part of a standard 2.5v configuration interface, apply 2.5v to the v cco lines of banks 0, 1, and 2 at power-on as well as throughout configuration. dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 19 r ta bl e 1 4 : dc characteristics of user i/os using single-ended standards iostandard attribute test conditions logic level characteristics i ol (ma) i oh (ma) v ol max (v) v oh min (v) lv t t l (3) 22?2 0.4 2.4 44?4 66?6 88?8 12 12 ?12 16 16 ?16 24 24 ?24 lv c m o s 3 3 (3) 22?2 0.4 v cco ? 0.4 44?4 66?6 88?8 12 12 ?12 16 16 ?16 24 (4) 24 ?24 lv c m o s 2 5 (3) 22?2 0.4 v cco ? 0.4 44?4 66?6 88?8 12 12 ?12 16 (4) 16 ?16 24 (4) 24 ?24 lv c m o s 1 8 (3) 22?2 0.4 v cco ? 0.4 44?4 66?6 88?8 12 (4) 12 ?12 16 (4) 16 ?16 lv c m o s 1 5 (3) 22?2 0.4 v cco ? 0.4 44?4 66?6 8 (4) 8?8 12 (4) 12 ?12 lv c m o s 1 2 (3) 22?2 0.4 v cco ? 0.4 4 (4) 4?4 6 (4) 6?6 pci33_3 (5) 1.5 ?0.5 10% v cco 90% v cco pci66_3 (5) 1.5 ?0.5 10% v cco 90% v cco hstl_i (4) 8?8 0.4 v cco - 0.4 hstl_iii (4) 24 ?8 0.4 v cco - 0.4 hstl_i_18 8 ?8 0.4 v cco - 0.4 hstl_ii_18 (4) 16 ?16 0.4 v cco - 0.4 hstl_iii_18 24 ?8 0.4 v cco - 0.4 sstl18_i 6.7 ?6.7 v tt ? 0.475 v tt + 0.475 sstl18_ii (4) 13.4 ?13.4 v tt ? 0.603 v tt + 0.603 sstl2_i 8.1 ?8.1 v tt ? 0.61 v tt + 0.61 sstl2_ii (4) 16.2 ?16.2 v tt ? 0.81 v tt + 0.81 sstl3_i 8 ?8 v tt ? 0.6 v tt + 0.6 sstl3_ii 16 ?16 v tt ? 0.8 v tt + 0.8 notes: 1. the numbers in this table are based on the conditions set forth in table 10 and table 13 . 2. descriptions of the symbols used in this table are as follows: i ol ? the output current condition under which v ol is tested i oh ? the output current condition under which v oh is tested v ol ? the output voltage that indicates a low logic level v oh ? the output voltage that indicates a high logic level v cco ? the supply voltage for output drivers v tt ? the voltage applied to a resistor termination 3. for the lvcmos and lvttl standards: the same v ol and v oh limits apply for the fast, slow and quietio slew attributes. 4. these higher-drive output standards are supported only on fpga banks 1 and 3. inputs are unrestricted. see the ? using i/o resources ? chapter in ug331 . 5. tested according to the relevant pci specifications. for information on pci ip solutions, see www.xilinx.com/products/ design_resources/conn_central/protocols/pci_pcix.htm . the pcix iostandard is available and has equivalent characteristics but no pci-x ip is supported. table 14: dc characteristics of user i/os using single-ended standards (continued) iostandard attribute test conditions logic level characteristics i ol (ma) i oh (ma) v ol max (v) v oh min (v) dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 20 product specification r differential i/o standards differential input pairs x-ref target - figure 6 figure 6: differential input voltages d s 529- 3 _10_012907 v inn v inp gnd level 50 % v icm v icm = inp u t common mode volt a ge = v id v inp intern a l logic differenti a l i/o p a ir pin s v inn n p 2 v inp + v inn v id = differenti a l inp u t volt a ge = v inp - v inn ta bl e 1 5 : recommended operating conditions for user i/ os using differential signal standards iostandard attribute v cco for drivers (1) v id v icm (2) min (v) nom (v) max (v) min (mv) nom (mv) max (mv) min (v) nom (v) max (v) lv d s _ 2 5 (3) 2.25 2.5 2.75 100 350 600 0.3 1.25 2.35 lv d s _ 3 3 (3) 3.0 3.3 3.6 100 350 600 0.3 1.25 2.35 blvds_25 (4) 2.25 2.5 2.75 100 300 ? 0.3 1.3 2.35 mini_lvds_25 (3) 2.25 2.5 2.75 200 ? 600 0.3 1.2 1.95 mini_lvds_33 (3) 3.0 3.3 3.6 200 ? 600 0.3 1.2 1.95 lvpecl_25 (5) inputs only 100 800 1000 0.3 1.2 1.95 lvpecl_33 (5) inputs only 100 800 1000 0.3 1.2 2.8 (6) rsds_25 (3) 2.25 2.5 2.75 100 200 ?0.31.21.5 rsds_33 (3) 3.0 3.3 3.6 100 200 ?0.31.21.5 tmds_33 (3, 4, 7) 3.14 3.3 3.47 150 ?12002.7 ?3.23 ppds_25 (3) 2.25 2.5 2.75 100 ? 400 0.2 ?2.3 ppds_33 (3) 3.0 3.3 3.6 100 ? 400 0.2 ?2.3 diff_hstl_i_18 1.7 1.8 1.9 100 ? ?0.8 ?1.1 diff_hstl_ii_18 (8) 1.7 1.8 1.9 100 ? ?0.8 ?1.1 diff_hstl_iii_18 1.7 1.8 1.9 100 ? ?0.8 ?1.1 diff_hstl_i 1.4 1.5 1.6 100 ? ?0.68 0.9 diff_hstl_iii 1.4 1.5 1.6 100 ? ? ?0.9 ? diff_sstl18_i 1.7 1.8 1.9 100 ? ?0.7 ?1.1 diff_sstl18_ii (8) 1.7 1.8 1.9 100 ? ?0.7 ?1.1 diff_sstl2_i 2.3 2.5 2.7 100 ? ?1.0 ?1.5 diff_sstl2_ii (8) 2.3 2.5 2.7 100 ? ?1.0 ?1.5 diff_sstl3_i 3.0 3.3 3.6 100 ? ?1.1 ?1.9 diff_sstl3_ii 3.0 3.3 3.6 100 ? ?1.1 ?1.9 notes: 1. the v cco rails supply only differential output drivers, not input circuits. 2. v icm must be less than v ccaux . 3. these true differential output standards are supported only on fpga banks 0 and 2. inputs are unrestricted. see the ?using i/ o resources? chapter in ug331 . 4. see "external termination requirements for differential i/o," page 22 . 5. lvpecl is supported on inputs only, not outputs. requires v ccaux = 3.3v 10%. 6. lvpecl_33 maximum v icm = v ccaux ? (v id / 2) 7. requires v ccaux = 3.3v 10% for inputs. (v ccaux ? 300 mv) v icm (v ccaux ? 37 mv) 8. these higher-drive output standards are supported only on fpga banks 1 and 3. inputs are unrestricted. see the ?using i/o res ources? chapter in ug331 . 9. v ref inputs are used for the diff_sstl and diff_hstl standards. the v ref settings are the same as for the single-ended versions in table 13 . other differential standards do not use v ref . dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 21 r differential output pairs x-ref target - figure 7 figure 7: differential output voltages ta bl e 1 6 : dc characteristics of user i/os using differential signal standards iostandard attribute v od v ocm v oh v ol min (mv) typ (mv) max (mv) min (v) typ (v) max (v) min (v) max (v) lvds_25 247 350 454 1.125 ?1.375 ? ? lvds_33 247 350 454 1.125 ?1.375 ? ? blvds_25 240 350 460 ?1.30 ? ? ? mini_lvds_25 300 ?600 1.0 ?1.4 ? ? mini_lvds_33 300 ?600 1.0 ?1.4 ? ? rsds_25 100 ?400 1.0 ?1.4 ? ? rsds_33 100 ?400 1.0 ?1.4 ? ? tmds_33 400 ?800v cco ? 0.405 ?v cco ? 0.190 ? ? ppds_25 100 ? 400 0.5 0.8 1.4 ? ? ppds_33 100 ? 400 0.5 0.8 1.4 ? ? diff_hstl_i_18 ? ? ? ? ? ?v cco ? 0.4 0.4 diff_hstl_ii_18 ? ? ? ? ? ?v cco ? 0.4 0.4 diff_hstl_iii_18 ? ? ? ? ? ?v cco ? 0.4 0.4 diff_hstl_i ? ? ? ? ? ? v cco ? 0.4 0.4 diff_hstl_iii ? ? ? ? ? ? v cco ? 0.4 0.4 diff_sstl18_i ? ? ? ? ? ?v tt + 0.475 v tt ? 0.475 diff_sstl18_ii ? ? ? ? ? ?v tt + 0.475 v tt ? 0.475 diff_sstl2_i ? ? ? ? ? ?v tt + 0.61 v tt ? 0.61 diff_sstl2_ii ? ? ? ? ? ?v tt + 0.81 v tt ? 0.81 diff_sstl3_i ? ? ? ? ? ?v tt + 0.6 v tt ? 0.6 diff_sstl3_ii ? ? ? ? ? ?v tt + 0.8 v tt ? 0.8 notes: 1. the numbers in this table are based on the conditions set forth in ta b l e 1 0 and ta b l e 1 5 . 2. see "external termination requirements for differential i/o," page 22 . 3. output voltage measurements fo r all differential standards are made with a termination resistor (r t ) of 100 across the n and p pins of the differential signal pair. 4. at any given time, no more than two of the following differen tial output standards can be assigned to an i/o bank: lvds_25, rsds_25, mini_lvds_25, ppds_25 when v cco =2.5v, or lvds_33, rsds_33, mi ni_lvds_33, tmds_33, ppds_33 when v cco = 3.3v v outn v outp gnd level 50% v ocm v ocm v od v ol v oh v outp internal logic v outn n p = output common mode voltage = 2 v outp +v outn v od = output differential voltage = v oh = output voltage indicating a high logic level v ol = output voltage indicating a low logic level v outp -v outn differential i/o pair pins d s 529- 3 _11_012907 dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 22 product specification r external termination requirements for differential i/o lvds, rsds, mini_lvds, and ppds i/o standards blvds_25 i/o standard tmds_33 i/o standard x-ref target - figure 8 figure 8: external input termination for lvds, rs ds, mini_lvds, and ppds i/o standards 100 ds529-3_09_080307 a) input-only differential pairs or pairs not using diff_term=yes constraint z 0 = 50 z 0 = 50 z 0 = 50 z 0 = 50 b) differential pairs using diff_term=yes constraint diff_term=no diff_term=yes lvds_33, mini_lvds_33, rsds_33, ppds_33 lvds_33, lvds_25, mini_lvds_33, mini_lvds_25, rsds_33, rsds_25, ppds_33, ppds_25 cat16-pt4f4 part number 1/4th of bourns v cco = 3.3v lvds_25, mini_lvds_25, rsds_25, ppds_25 v cco = 2.5v lvds_33, mini_lvds_33, rsds_33, ppds_33 v cco = 3.3v lvds_25, mini_lvds_25, rsds_25, ppds_25 v cco = 2.5v no v cco restrictions r lvds_33, mini_lvds_33, rsds_33, ppds_33 v cco = 3.3v lvds_25, mini_lvds_25, rsds_25, ppds_25 v cco = 2.5v dt bank 0 bank 2 bank 0 bank 2 bank 3 bank 1 bank 0 and 2 any bank x-ref target - figure 9 figure 9: external output and input termination resistors for blvds_25 i/o standard 140 165 165 100 v cco = 2.5v no v cco requirement ds529-3_07_080307 blvds_25 blvds_25 cat16-lv4f12 part number cat16-pt4f4 part number 1/4th of bourns 1/4th of bourns bank 0 bank 2 bank 3 bank 1 any bank bank 0 bank 2 bank 3 bank 1 any bank z 0 = 50 z 0 = 50 x-ref target - figure 10 figure 10: external input resistors required for tmds_33 i/o standard 50 v cco = 3 . 3 v v ccaux = 3 . 3 v d s 529- 3 _0 8 _020107 dvi/hdmi c ab le 50 3 . 3 v tmd s _ 33 tmd s _ 33 b a nk 0 b a nk 2 b a nk 0 a nd 2 b a nk 0 b a nk 2 b a nk 3 b a nk 1 any b a nk dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 23 r device dna read endurance in-system flash memory data retention, program/write endurance ta bl e 1 7 : device dna identifier memory characteristics symbol description minimum units dna_cycles number of read operations or jtag isc_dna read operations. unaffected by hold or shift operations 30,000,000 read cycles ta bl e 1 8 : in-system flash (isf) memory characteristics symbol description minimum (1) units isf_retention data retention 20 years isf_active time that the isf memory is selected and active. spi_access design primitive pins csb = low, clk toggling 2years isf_page_cycles number of program/erase cycles, per isf memory page 100,000 cycles isf_page_rewrite number of cumulative random (non-se quential) page erase/program operations within a sector before pages must be rewritten 10,000 cycles isf_spr_cycles number of program/erase cycles for sector protection register 10,000 cycles isf_sec_cycles number of program cycles for sector lockdown register per sector, user-programmable field in security register, and power-of-2 page size 1 cycle notes: 1. minimum value at which functionality is still guaranteed. do not exceed these values. dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 24 product specification r switching characteristics all spartan-3an fpgas ship in two speed grades: ?4 and the higher performance ?5. switching characteristics in this document are designated as preview, advance, preliminary, or production, as shown in table 19 . each category is defined as follows: preview : these specifications are based on estimates only and should not be used for timing analysis. advance : these specifications are based on simulations only and are typically available soon after establishing fpga specifications. although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. preliminary : these specifications are based on complete early silicon characterization . devices and speed grades with this designation are intended to give a better indication of the expected performanc e of production silicon. the probability of under-r eporting preliminary delays is greatly reduced compared to advance data. production : these specifications are approved once enough production s ilicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. software version requirements production-quality systems must use fpga designs compiled using a speed file designated as production status. fpga designs using a less mature speed file designation should only be used during system prototyping or pre-production qualification. fpga designs with speed files designated as preview, advance, or preliminary should not be used in a production-quality system. whenever a speed file designation changes, as a device matures toward production stat us, rerun the latest xilinx? ise? software on the fpga design to ensure that the fpga design incorporates the latest timing information and software updates. in some cases, a particular family member (and speed grade) is released to production at a different time than when the speed file is releas ed with the production label. any labeling discrepancies are corrected in subsequent speed file releases. see table 19 for devices that can be considered to have the production label. all parameter limits are representative of worst-case supply voltage and junction temperature conditions. unless otherwise noted, the published parameter values apply to all spartan-3an devices. ac and dc characteristics are specified using the same numbers for both commercial and industrial grades. to create a xilinx mysupport user account and sign up for automatic e-mail notification whenever this data sheet is updated: ? sign up for alerts on xilinx mysupport w ww.xilinx.com/ support/answers/1 9380 .htm timing parameters and their representative values are selected for inclusion either because they are important as general design requirements or they indicate fundamental device performance characteristics. the spartan-3an speed files (v1.41), part of th e xilinx development software, are the original source for many but not all of the values. the speed grade designations for these files are shown in table 19 . for more complete, more precise, and worst-case data, use the values reported by the xilinx static timing analyzer (trace in the xilin x development software) and back-annotated to the simulation netlist. table 20 provides the recent history of the spartan-3an speed files. table 19: spartan-3an family v1.41 speed grade designations device preview advance preliminary production xc3s50an ? 4, ? 5 xc3s200an ? 4, ? 5 xc3s400an ? 4, ? 5 xc3s700an ? 4, ? 5 xc3s1400an ? 4, ? 5 table 20: spartan-3an speed file version history version ise release description 1.41 ise 10.1.03 updated for spartan-3a family. no change to data for spartan-3an family. 1.40 ise 10.1.02 updated for spartan-3a family. no change to data for spartan-3an family. 1.39 ise 10.1 updated for spartan-3a family. no change to data for spartan-3an family. 1.38 ise 9.2.03i updated to production. no change to data. 1.37 ise 9.2.01i updated pin-to-pin setup and hold times, tmds output adjustment, multiplier setup/hold times, and block ram clock width. 1.36 ise 9.2i added -5 speed grade, updated to advance. 1.34 ise 9.1.03i updated pin-to-pin timing. 1.32 ise 9.1.01i preview speed files for -4 speed grade. dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 25 r i/o timing pin-to-pin clock-to-output times ta bl e 2 1 : pin-to-pin clock-to-output times for the iob output path symbol description conditions device speed grade units -5 -4 max max clock-to-output times t ickofdcm when reading from the output flip-flop (off), the time from the active transition on the global clock pin to data appearing at the output pin. the dcm is in use. lv c m o s 2 5 (2) , 12ma output drive, fast slew rate, with dcm (3) xc3s50an 3.18 3.42 ns xc3s200an 3.21 3.27 ns xc3s400an 2.97 3.33 ns xc3s700an 3.39 3.50 ns xc3s1400an 3.51 3.99 ns t ickof when reading from off, the time from the active transition on the global clock pin to data appearing at the output pin. the dcm is not in use. lv c m o s 2 5 (2) , 12ma output drive, fast slew rate, without dcm xc3s50an 4.59 5.02 ns xc3s200an 4.88 5.24 ns xc3s400an 4.68 5.12 ns xc3s700an 4.97 5.34 ns xc3s1400an 5.06 5.69 ns notes: 1. the numbers in this table are tested using the methodology presented in ta b l e 3 0 and are based on the operating conditions set forth in ta b l e 1 0 and table 13 . 2. this clock-to-output time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or a standard other than lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. if the former is true, add the appropriate input adjustment from table 26 . if the latter is true, add the appropriate output adjustment from table 29 . 3. dcm output jitter is included in all measurements. dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 26 product specification r pin-to-pin setup and hold times ta bl e 2 2 : pin-to-pin setup and hold times for the iob input path (system synchronous) symbol description conditions device speed grade units -5 -4 min min setup times t psdcm when writing to the input flip-flop (iff), th e time from the setup of data at the input pin to the active transition at a global clock pin. the dcm is in use. no input delay is programmed. lv c m o s 2 5 (2) , ifd_delay_value = 0, with dcm (4) xc3s50an 2.45 2.68 ns xc3s200an 2.59 2.84 ns xc3s400an 2.38 2.68 ns xc3s700an 2.38 2.57 ns xc3s1400an 1.91 2.17 ns t psfd when writing to iff, the time from the setup of data at the input pin to an active transition at the global clock pin. the dcm is not in use. the input delay is programmed. lv c m o s 2 5 (2) , ifd_delay_value = 5, without dcm xc3s50an 2.55 2.76 ns xc3s200an 2.32 2.76 ns xc3s400an 2.21 2.60 ns xc3s700an 2.28 2.63 ns xc3s1400an 2.33 2.41 ns hold times t phdcm when writing to iff, the time from the active transition at the global clock pin to the point when data must be held at the input pin. the dcm is in use. no input delay is programmed. lv c m o s 2 5 (3) , ifd_delay_value = 0, with dcm (4) xc3s50an -0.36 -0.36 ns xc3s200an -0.52 -0.52 ns xc3s400an -0.33 -0.29 ns xc3s700an -0.17 -0.12 ns xc3s1400an -0.07 0.00 ns t phfd when writing to iff, the time from the active transition at the global clock pin to the point when data must be held at the input pin. the dcm is not in use. the input delay is programmed. lv c m o s 2 5 (3) , ifd_delay_value = 5, without dcm xc3s50an -0.63 -0.58 ns xc3s200an -0.56 -0.56 ns xc3s400an -0.42 -0.42 ns xc3s700an -0.80 -0.75 ns xc3s1400an -0.69 -0.69 ns notes: 1. the numbers in this table are tested using the methodology presented in table 30 and are based on the operating conditions set forth in table 10 and table 13 . 2. this setup time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or t he data input. if this is true of the global clock input, subtract the appropriate adjustment from table 26 . if this is true of the data input, add the appropriate input adjustment from the same table. 3. this hold time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or th e data input. if this is true of the global clock input, add the appropriate input adjustment from table 26 . if this is true of the data input, subtract the appropriate input adjustment from the same table. when the hold time is negative, it is possible to change the data before the clock?s active edge. 4. dcm output jitter is included in all measurements. dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 27 r input setup and hold times ta bl e 2 3 : setup and hold times for the iob input path symbol description conditions ifd_ delay_ value device speed grade units -5 -4 min min setup times t iopick time from the setup of data at the input pin to the active transition at the iclk input of the i nput flip-flop (iff). no input delay is programmed. lv c m o s 2 5 (2) 0 xc3s50an 1.56 1.58 ns xc3s200an 1.71 1.81 ns xc3s400an 1.30 1.51 ns xc3s700an 1.34 1.51 ns xc3s1400an 1.36 1.74 ns t iopickd time from the setup of data at the input pin to the active transition at the iclk input of the i nput flip-flop (iff). the input delay is programmed. lv c m o s 2 5 (2) 1 xc3s50an 2.16 2.18 ns 23.103.12 ns 33.513.76 ns 44.044.32 ns 53.884.24 ns 64.725.09 ns 75.475.94 ns 85.976.52 ns 1 xc3s200an 2.05 2.20 ns 22.722.93 ns 33.383.78 ns 43.884.37 ns 53.694.20 ns 64.565.23 ns 75.346.11 ns 85.856.71 ns 1 xc3s400an 1.79 2.02 ns 22.432.67 ns 33.023.43 ns 43.493.96 ns 53.413.95 ns 64.204.81 ns 74.965.66 ns 85.446.19 ns dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 28 product specification r t iopickd time from the setup of data at the input pin to the active transition at the iclk input of the i nput flip-flop (iff). the input delay is programmed. lv c m o s 2 5 (2) 1 xc3s700an 1.82 1.95 ns 22.622.83 ns 33.323.72 ns 43.834.31 ns 53.694.14 ns 64.605.19 ns 75.396.10 ns 85.926.73 ns 1 xc3s1400an 1.79 2.17 ns 22.552.92 ns 33.383.76 ns 43.754.32 ns 53.814.19 ns 64.395.09 ns 75.165.98 ns 85.696.57 ns hold times t ioickp time from the active transition at the iclk input of the i nput flip-flop (iff) to the point where data must be held at the input pin. no input delay is programmed. lv c m o s 2 5 (3) 0 xc3s50an ?0.66 ?0.64 ns xc3s200an ?0.85 ?0.65 ns xc3s400an ?0.42 ?0.42 ns xc3s700an ?0.81 ?0.67 ns xc3s1400an ?0.71 ?0.71 ns t ioickpd time from the active transition at the iclk input of the i nput flip-flop (iff) to the point where data must be held at the input pin. the input delay is programmed. lv c m o s 2 5 (3) 1 xc3s50an ?0.88 ?0.88 ns 2 ?1.33 ?1.33 ns 3 ?2.05 ?2.05 ns 4 ?2.43 ?2.43 ns 5 ?2.34 ?2.34 ns 6 ?2.81 ?2.81 ns 7 ?3.03 ?3.03 ns 8 ?3.83 ?3.57 ns 1 xc3s200an ?1.51 ?1.51 ns 2 ?2.09 ?2.09 ns 3 ?2.40 ?2.40 ns 4 ?2.68 ?2.68 ns 5 ?2.56 ?2.56 ns 6 ?2.99 ?2.99 ns 7 ?3.29 ?3.29 ns 8 ?3.61 ?3.61 ns ta bl e 2 3 : setup and hold times for the iob input path (continued) symbol description conditions ifd_ delay_ value device speed grade units -5 -4 min min dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 29 r t ioickpd time from the active transition at the iclk input of the i nput flip-flop (iff) to the point where data must be held at the input pin. the input delay is programmed. lv c m o s 2 5 (3) 1 xc3s400an ?1.12 ?1.12 ns 2 ?1.70 ?1.70 ns 3 ?2.08 ?2.08 ns 4 ?2.38 ?2.38 ns 5 ?2.23 ?2.23 ns 6 ?2.69 ?2.69 ns 7 ?3.08 ?3.08 ns 8 ?3.35 ?3.35 ns 1 xc3s700an ?1.67 ?1.67 ns 2 ?2.27 ?2.27 ns 3 ?2.59 ?2.59 ns 4 ?2.92 ?2.92 ns 5 ?2.89 ?2.89 ns 6 ?3.22 ?3.22 ns 7 ?3.52 ?3.52 ns 8 ?3.81 ?3.81 ns 1 xc3s1400an ?1.60 ?1.60 ns 2 ?2.06 ?2.06 ns 3 ?2.46 ?2.46 ns 4 ?2.86 ?2.86 ns 5 ?2.88 ?2.88 ns 6 ?3.24 ?3.24 ns 7 ?3.55 ?3.55 ns 8 ?3.89 ?3.89 ns set/reset pulse width t rpw_iob minimum pulse width to sr control input on iob - - all 1.33 1.61 ns notes: 1. the numbers in this table are tested using the methodology presented in ta b l e 3 0 and are based on the operating conditions set forth in ta b l e 1 0 and table 13 . 2. this setup time requires adjustment whenever a signal standard ot her than lvcmos25 is assigned to the data input. if this is true, add the appropriate input adjustment from table 26 . 3. these hold times require adjustment whenever a signal standard ot her than lvcmos25 is assigned to the data input. if this is true, subtract the appropriate input adjustment from table 26 . when the hold time is negative, it is possible to change the data before the clock?s active edge. ta bl e 2 4 : sample window (source synchronous) symbol description max units t samp setup and hold capture window of an iob flip-flop. the input capture sample window value is highly specific to a particular application, device, package, i/o standard, i/o placement, dcm usag e, and clock buffer. please consult the appropriate xilinx answer record for application-specific values. ? answer record 30879 ps ta bl e 2 3 : setup and hold times for the iob input path (continued) symbol description conditions ifd_ delay_ value device speed grade units -5 -4 min min dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 30 product specification r input propagation times ta bl e 2 5 : propagation times for the iob input path symbol description conditions delay_value device speed grade units -5 -4 max max propagation times t iopi the time it takes for data to travel from the input pin to the i output with no input delay programmed lv c m o s 2 5 (2) ibuf_delay_value=0 xc3s50an 1.04 1.12 ns xc3s200an 0.87 0.87 ns xc3s400an 0.65 0.72 ns xc3s700an 0.92 0.92 ns xc3s1400an 0.96 1.21 ns t iopid the time it takes for data to travel from the input pin to the i output with the input delay programmed lv c m o s 2 5 (2) 1 xc3s50an 1.79 2.07 ns 2 2.13 2.46 ns 3 2.36 2.71 ns 4 2.88 3.21 ns 5 3.11 3.46 ns 6 3.45 3.84 ns 7 3.75 4.19 ns 8 4.00 4.47 ns 9 3.61 4.11 ns 10 3.95 4.50 ns 11 4.18 4.67 ns 12 4.75 5.20 ns 13 4.98 5.44 ns 14 5.31 5.95 ns 15 5.62 6.28 ns 16 5.86 6.57 ns 1 xc3s200an 1.57 1.65 ns 2 1.87 1.97 ns 3 2.16 2.33 ns 4 2.68 2.96 ns 5 2.87 3.19 ns 6 3.20 3.60 ns 7 3.57 4.02 ns 8 3.79 4.26 ns 9 3.42 3.86 ns 10 3.79 4.25 ns 11 4.02 4.55 ns 12 4.62 5.24 ns 13 4.86 5.53 ns 14 5.18 5.94 ns dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 31 r t iopid the time it takes for data to travel from the input pin to the i output with the input delay programmed lv c m o s 2 5 (2) 15 xc3s200an 5.43 6.24 ns 16 5.75 6.59 ns 1 xc3s400an 1.32 1.43 ns 2 1.67 1.83 ns 3 1.90 2.07 ns 4 2.33 2.52 ns 5 2.60 2.91 ns 6 2.94 3.20 ns 7 3.23 3.51 ns 8 3.50 3.85 ns 9 3.18 3.55 ns 10 3.53 3.95 ns 11 3.76 4.20 ns 12 4.26 4.67 ns 13 4.51 4.97 ns 14 4.85 5.32 ns 15 5.14 5.64 ns 16 5.40 5.95 ns 1 xc3s700an 1.84 1.87 ns 2 2.20 2.27 ns 3 2.46 2.60 ns 4 2.93 3.15 ns 5 3.21 3.45 ns 6 3.54 3.80 ns 7 3.86 4.16 ns 8 4.13 4.48 ns 9 3.82 4.19 ns 10 4.17 4.58 ns 11 4.43 4.89 ns 12 4.95 5.49 ns 13 5.22 5.83 ns 14 5.57 6.21 ns 15 5.89 6.55 ns 16 6.16 6.89 ns 1 xc3s1400an 1.95 2.18 ns 2 2.29 2.59 ns 3 2.54 2.84 ns 4 2.96 3.30 ns ta bl e 2 5 : propagation times for the iob input path (continued) symbol description conditions delay_value device speed grade units -5 -4 max max dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 32 product specification r t iopid the time it takes for data to travel from the input pin to the i output with the input delay programmed lv c m o s 2 5 (2) 5 xc3s1400an 3.17 3.52 ns 6 3.52 3.92 ns 7 3.82 4.18 ns 8 4.10 4.57 ns 9 3.84 4.31 ns 10 4.20 4.79 ns 11 4.46 5.06 ns 12 4.87 5.51 ns 13 5.07 5.73 ns 14 5.43 6.08 ns 15 5.73 6.33 ns 16 6.01 6.77 ns t iopli the time it takes for data to travel from the input pin through the iff latch to the i output with no input delay programmed lv c m o s 2 5 (2) ifd_delay_value=0 xc3s50an 1.70 1.81 ns xc3s200an 1.85 2.04 ns xc3s400an 1.44 1.74 ns xc3s700an 1.48 1.74 ns xc3s1400an 1.50 1.97 ns ta bl e 2 5 : propagation times for the iob input path (continued) symbol description conditions delay_value device speed grade units -5 -4 max max dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 33 r t ioplid the time it takes for data to travel from the input pin through the iff latch to the i output with the input delay programmed lv c m o s 2 5 (2 1 xc3s50an 2.30 2.41 ns 2 3.24 3.35 ns 3 3.65 3.98 ns 4 4.18 4.55 ns 5 4.02 4.47 ns 6 4.86 5.32 ns 7 5.61 6.17 ns 8 6.11 6.75 ns 1 xc3s200an 2.19 2.43 ns 2 2.86 3.16 ns 3 3.52 4.01 ns 4 4.02 4.60 ns 5 3.83 4.43 ns 6 4.70 5.46 ns 7 5.48 6.33 ns 8 5.99 6.94 ns 1 xc3s400an 1.93 2.25 ns 2 2.57 2.90 ns 3 3.16 3.66 ns 4 3.63 4.19 ns 5 3.55 4.18 ns 6 4.34 5.03 ns 7 5.09 5.88 ns 8 5.58 6.42 ns 1 xc3s700an 1.96 2.18 ns 2 2.76 3.06 ns 3 3.45 3.95 ns 4 3.97 4.54 ns 5 3.83 4.37 ns 6 4.74 5.42 ns 7 5.53 6.33 ns 8 6.06 6.96 ns ta bl e 2 5 : propagation times for the iob input path (continued) symbol description conditions delay_value device speed grade units -5 -4 max max dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 34 product specification r t ioplid the time it takes for data to travel from the input pin through the iff latch to the i output with the input delay programmed lv c m o s 2 5 (2 1 xc3s1400an 1.93 2.40 ns 2 2.69 3.15 ns 3 3.52 3.99 ns 4 3.89 4.55 ns 5 3.95 4.42 ns 6 4.53 5.32 ns 7 5.30 6.21 ns 8 5.83 6.80 ns notes: 1. the numbers in this table are tested using the methodology presented in ta b l e 3 0 and are based on the operating conditions set forth in ta b l e 1 0 and table 13 . 2. this propagation time requires adjustment whenever a signal st andard other than lvcmos25 is assigned to the data input. when this is true, add the appropriate input adjustment from ta bl e 2 6 . ta bl e 2 5 : propagation times for the iob input path (continued) symbol description conditions delay_value device speed grade units -5 -4 max max dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 35 r input timing adjustments ta bl e 2 6 : input timing adjustments by iostandard convert input time from lvcmos25 to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 single-ended standards lv t t l 0 . 6 2 0 . 6 2 n s lvcmos33 0.54 0.54 ns lvcmos25 0 0 ns lvcmos18 0.83 0.83 ns lvcmos15 0.60 0.60 ns lvcmos12 0.31 0.31 ns pci33_3 0.41 0.41 ns pci66_3 0.41 0.41 ns hstl_i 0.72 0.72 ns hstl_iii 0.77 0.77 ns hstl_i_18 0.69 0.69 ns hstl_ii_18 0.69 0.69 ns hstl_iii_18 0.79 0.79 ns sstl18_i 0.71 0.71 ns sstl18_ii 0.71 0.71 ns sstl2_i 0.68 0.68 ns sstl2_ii 0.68 0.68 ns sstl3_i 0.78 0.78 ns sstl3_ii 0.78 0.78 ns differential standards lv d s _ 2 5 0 . 7 6 0 . 7 6 n s lv d s _ 3 3 0 . 7 9 0 . 7 9 n s blvds_25 0.79 0.79 ns mini_lvds_25 0.78 0.78 ns mini_lvds_33 0.79 0.79 ns lvpecl_25 0.78 0.78 ns lvpecl_33 0.79 0.79 ns rsds_25 0.79 0.79 ns rsds_33 0.77 0.77 ns tmds_33 0.79 0.79 ns ppds_25 0.79 0.79 ns ppds_33 0.79 0.79 ns diff_hstl_i_18 0.74 0.74 ns diff_hstl_ii_18 0.72 0.72 ns diff_hstl_iii_18 1.05 1.05 ns diff_hstl_i 0.72 0.72 ns diff_hstl_iii 1.05 1.05 ns diff_sstl18_i 0.71 0.71 ns diff_sstl18_ii 0.71 0.71 ns diff_sstl2_i 0.74 0.74 ns diff_sstl2_ii 0.75 0.75 ns diff_sstl3_i 1.06 1.06 ns diff_sstl3_ii 1.06 1.06 ns notes: 1. the numbers in this table are tested using the methodology presented in table 30 and are based on the operating conditions set forth in table 10 , ta bl e 1 3 , and table 15 . 2. these adjustments are used to convert input path times originally specified for the lvcmos25 standard to times that correspond to other signal standards. table 26: input timing adjustments by iostandard convert input time from lvcmos25 to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 36 product specification r output propagation times ta bl e 2 7 : timing for the iob output path symbol description conditions device speed grade units -5 -4 max max clock-to-output times t iockp when reading from the output flip-flop (off), the time from the active transition at the oclk input to data appearing at the output pin lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate all 2.87 3.13 ns propagation times t ioop the time it takes for data to travel from the iob?s o input to the output pin lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate all 2.78 2.91 ns set/reset times t iosrp time from asserting the off?s sr input to setting/resetting data at the output pin lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate all 3.63 3.89 ns t iogsrq time from asserting the global set reset (gsr) input on the startup_spartan3a primitive to setting/resetting data at the output pin 8.62 9.65 ns notes: 1. the numbers in this table are tested using the methodology presented in ta b l e 3 0 and are based on the operating conditions set forth in ta b l e 1 0 and table 13 . 2. this time requires adjustment whenever a signal standard other than lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. when this is true, add the appropriate output adjustment from table 29 . dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 37 r three-state output propagation times ta bl e 2 8 : timing for the iob three-state path symbol description conditions device speed grade units -5 -4 max max synchronous output enable/disable times t iockhz time from the active transition at the otclk input of the three-state flip-flop (tff) to when the output pin enters the high-impedance state lvcmos25, 12 ma output drive, fast slew rate all 0.63 0.76 ns t iockon (2) time from the active transition at tff?s otclk input to when the output pin drives valid data all 2.80 3.06 ns asynchronous output enable/disable times t gts time from asserting the global three state (gts) input on the startup_spartan3a primitive to when the output pin enters the high-impedance state lvcmos25, 12 ma output drive, fast slew rate all 9.47 10.36 ns set/reset times t iosrhz time from asserting tff?s sr input to when the output pin enters a high-impedance state lvcmos25, 12 ma output drive, fast slew rate all 1.61 1.86 ns t iosron (2) time from asserting tff?s sr input at tff to when the output pin drives valid data all 3.57 3.82 ns notes: 1. the numbers in this table are tested using the methodology presented in table 30 and are based on the operating conditions set forth in table 10 and table 13 . 2. this time requires adjustment whenever a signal standard other th an lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. when this is true, add the appropriate output adjustment from table 29 . dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 38 product specification r output timing adjustments ta bl e 2 9 : output timing adjustments for iob convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 single-ended standards lvttl slow 2 ma 5.58 5.58 ns 4 ma 3.16 3.16 ns 6 ma 3.17 3.17 ns 8 ma 2.09 2.09 ns 12 ma 1.62 1.62 ns 16 ma 1.24 1.24 ns 24 ma 2.74 (3) 2.74 (3) ns fast 2 ma 3.03 3.03 ns 4 ma 1.71 1.71 ns 6 ma 1.71 1.71 ns 8 ma 0.53 0.53 ns 12 ma 0.53 0.53 ns 16 ma 0.59 0.59 ns 24 ma 0.60 0.60 ns quietio 2 ma 27.67 27.67 ns 4 ma 27.67 27.67 ns 6 ma 27.67 27.67 ns 8 ma 16.71 16.71 ns 12 ma 16.67 16.67 ns 16 ma 16.22 16.22 ns 24 ma 12.11 12.11 ns lvcmos33 slow 2 ma 5.58 5.58 ns 4 ma 3.17 3.17 ns 6 ma 3.17 3.17 ns 8 ma 2.09 2.09 ns 12 ma 1.24 1.24 ns 16 ma 1.15 1.15 ns 24 ma 2.55 (3) 2.55 (3) ns fast 2 ma 3.02 3.02 ns 4 ma 1.71 1.71 ns 6 ma 1.72 1.72 ns 8 ma 0.53 0.53 ns 12 ma 0.59 0.59 ns 16 ma 0.59 0.59 ns 24 ma 0.51 0.51 ns quietio 2 ma 27.67 27.67 ns 4 ma 27.67 27.67 ns 6 ma 27.67 27.67 ns 8 ma 16.71 16.71 ns 12 ma 16.29 16.29 ns 16 ma 16.18 16.18 ns 24 ma 12.11 12.11 ns table 29: output timing adjustments for iob (continued) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 39 r lvcmos25 slow 2 ma 5.33 5.33 ns 4 ma 2.81 2.81 ns 6 ma 2.82 2.82 ns 8 ma 1.14 1.14 ns 12 ma 1.10 1.10 ns 16 ma 0.83 0.83 ns 24 ma 2.26 (3) 2.26 (3) ns fast 2 ma 4.36 4.36 ns 4 ma 1.76 1.76 ns 6 ma 1.25 1.25 ns 8 ma 0.38 0.38 ns 12 ma 0 0 ns 16 ma 0.01 0.01 ns 24 ma 0.01 0.01 ns quietio 2 ma 25.92 25.92 ns 4 ma 25.92 25.92 ns 6 ma 25.92 25.92 ns 8 ma 15.57 15.57 ns 12 ma 15.59 15.59 ns 16 ma 14.27 14.27 ns 24 ma 11.37 11.37 ns lvcmos18 slow 2 ma 4.48 4.48 ns 4 ma 3.69 3.69 ns 6 ma 2.91 2.91 ns 8 ma 1.99 1.99 ns 12 ma 1.57 1.57 ns 16 ma 1.19 1.19 ns fast 2 ma 3.96 3.96 ns 4 ma 2.57 2.57 ns 6 ma 1.90 1.90 ns 8 ma 1.06 1.06 ns 12 ma 0.83 0.83 ns 16 ma 0.63 0.63 ns quietio 2 ma 24.97 24.97 ns 4 ma 24.97 24.97 ns 6 ma 24.08 24.08 ns 8 ma 16.43 16.43 ns 12 ma 14.52 14.52 ns 16 ma 13.41 13.41 ns ta bl e 2 9 : output timing adjustments for iob (continued) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 lvcmos15 slow 2 ma 5.82 5.82 ns 4 ma 3.97 3.97 ns 6 ma 3.21 3.21 ns 8 ma 2.53 2.53 ns 12 ma 2.06 2.06 ns fast 2 ma 5.23 5.23 ns 4 ma 3.05 3.05 ns 6 ma 1.95 1.95 ns 8 ma 1.60 1.60 ns 12 ma 1.30 1.30 ns quietio 2 ma 34.11 34.11 ns 4 ma 25.66 25.66 ns 6 ma 24.64 24.64 ns 8 ma 22.06 22.06 ns 12 ma 20.64 20.64 ns lvcmos12 slow 2 ma 7.14 7.14 ns 4 ma 4.87 4.87 ns 6 ma 5.67 5.67 ns fast 2 ma 6.77 6.77 ns 4 ma 5.02 5.02 ns 6 ma 4.09 4.09 ns quietio 2 ma 50.76 50.76 ns 4 ma 43.17 43.17 ns 6 ma 37.31 37.31 ns pci33_3 0.34 0.34 ns pci66_3 0.34 0.34 ns hstl_i 0.78 0.78 ns hstl_iii 1.16 1.16 ns hstl_i_18 0.35 0.35 ns hstl_ii_18 0.30 0.30 ns hstl_iii_18 0.47 0.47 ns sstl18_i 0.40 0.40 ns sstl18_ii 0.30 0.30 ns sstl2_i 0 0 ns sstl2_ii ? 0.05 ? 0.05 ns sstl3_i 0 0 ns sstl3_ii 0.17 0.17 ns table 29: output timing adjustments for iob (continued) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 40 product specification r differential standards lvds_25 1.16 1.16 ns lvds_33 0.46 0.46 ns blvds_25 0.11 0.11 ns mini_lvds_25 0.75 0.75 ns mini_lvds_33 0.40 0.40 ns lvpecl_25 input only lvpecl_33 rsds_25 1.42 1.42 ns rsds_33 0.58 0.58 ns tmds_33 0.46 0.46 ns ppds_25 1.07 1.07 ns ppds_33 0.63 0.63 ns diff_hstl_i_18 0.43 0.43 ns diff_hstl_ii_18 0.41 0.41 ns diff_hstl_iii_18 0.36 0.36 ns diff_hstl_i 1.01 1.01 ns diff_hstl_iii 0.54 0.54 ns diff_sstl18_i 0.49 0.49 ns diff_sstl18_ii 0.41 0.41 ns diff_sstl2_i 0.82 0.82 ns diff_sstl2_ii 0.09 0.09 ns diff_sstl3_i 1.16 1.16 ns diff_sstl3_ii 0.28 0.28 ns notes: 1. the numbers in this table are tested using the methodology presented in ta b l e 3 0 and are based on the operating conditions set forth in ta bl e 1 0 , table 13 , and table 15 . 2. these adjustments are used to convert output- and three-state-path times originally specified for the lvcmos25 standard with 12 ma drive and fast slew rate to times that correspond to other signal standards. do not adjust times that measure when outputs go into a high-impedance state. 3. note that 16 ma drive is faster than 24 ma drive for the slow slew rate. ta bl e 2 9 : output timing adjustments for iob (continued) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 41 r timing measurem ent methodology when measuring timing parameters at the programmable i/os, different signal standards call for different test conditions. ta b l e 3 0 lists the conditions to use for each standard. the method for measuring input timing is as follows: a signal that swings between a low logic level of v l and a high logic level of v h is applied to the input under test. some standards also require the application of a bias voltage to the v ref pins of a given bank to properly set the input-switching threshold. the measurement point of the input signal (v m ) is commonly located halfway between v l and v h . the output test setup is shown in figure 11 . a termination voltage v t is applied to the termination resistor r t , the other end of which is connected to the output. for each standard, r t and v t generally take on the standard values recommended for minimizing signal reflections. if the standard does not ordinarily use terminations (for example, lv c m o s, lv t t l ) , t h e n r t is set to 1m to indicate an open connection, and v t is set to zero. the same measurement point (v m ) that was used at the input is also used at the output. x-ref target - figure 11 figure 11: output test setup fpga output v t (v ref ) r t (r ref ) v m (v meas ) c l (c ref ) ds312-3_04_102406 notes: 1. the names shown in parentheses are used in the ibis file. ta bl e 3 0 : test methods for timing measurement at i/os signal standard (iostandard) inputs outputs inputs and outputs v ref (v) v l (v) v h (v) r t ( ) v t (v) v m (v) single-ended lv t t l - 0 3.3 1m 0 1.4 lv c m o s 3 3 - 0 3.3 1m 0 1.65 lv c m o s 2 5 - 0 2.5 1m 0 1.25 lv c m o s 1 8 - 0 1.8 1m 0 0.9 lv c m o s 1 5 - 0 1.5 1m 0 0.75 lv c m o s 1 2 - 0 1.2 1m 0 0.6 pci33_3 rising - note 3 note 3 25 0 0.94 falling 25 3.3 2.03 pci66_3 rising - note 3 note 3 25 0 0.94 falling 25 3.3 2.03 hstl_i 0.75 v ref ? 0.5 v ref + 0.5 50 0.75 v ref hstl_iii 0.9 v ref ? 0.5 v ref + 0.5 50 1.5 v ref hstl_i_18 0.9 v ref ? 0.5 v ref + 0.5 50 0.9 v ref hstl_ii_18 0.9 v ref ? 0.5 v ref + 0.5 25 0.9 v ref hstl_iii_18 1.1 v ref ? 0.5 v ref + 0.5 50 1.8 v ref sstl18_i 0.9 v ref ? 0.5 v ref + 0.5 50 0.9 v ref sstl18_ii 0.9 v ref ? 0.5 v ref + 0.5 25 0.9 v ref sstl2_i 1.25 v ref ? 0.75 v ref + 0.75 50 1.25 v ref sstl2_ii 1.25 v ref ? 0.75 v ref + 0.75 25 1.25 v ref sstl3_i 1.5 v ref ? 0.75 v ref + 0.75 50 1.5 v ref sstl3_ii 1.5 v ref ? 0.75 v ref + 0.75 25 1.5 v ref dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 42 product specification r the capacitive load (c l ) is connected between the output and gnd. the output timing for all standards, as published in the speed files and the data sheet, is always based on a c l value of zero. high-impedance probes (less than 1 pf) are used for all measurements. any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet. differential lvds_25 -v icm ? 0.125 v icm + 0.125 50 1.2 v icm lvds_33 -v icm ? 0.125 v icm + 0.125 50 1.2 v icm blvds_25 -v icm ? 0.125 v icm + 0.125 1m 0 v icm mini_lvds_25 -v icm ? 0.125 v icm + 0.125 50 1.2 v icm mini_lvds_33 -v icm ? 0.125 v icm + 0.125 50 1.2 v icm lvpecl_25 -v icm ? 0.3 v icm + 0.3 n/a n/a v icm lvpecl_33 -v icm ? 0.3 v icm + 0.3 n/a n/a v icm rsds_25 -v icm ? 0.1 v icm + 0.1 50 1.2 v icm rsds_33 -v icm ? 0.1 v icm + 0.1 50 1.2 v icm tmds_33 -v icm ? 0.1 v icm + 0.1 50 3.3 v icm ppds_25 -v icm ? 0.1 v icm + 0.1 50 0.8 v icm ppds_33 -v icm ? 0.1 v icm + 0.1 50 0.8 v icm diff_hstl_i -v icm ? 0.5 v icm + 0.5 50 0.75 v icm diff_hstl_iii -v icm ? 0.5 v icm + 0.5 50 1.5 v icm diff_hstl_i_18 -v icm ? 0.5 v icm + 0.5 50 0.9 v icm diff_hstl_ii_18 -v icm ? 0.5 v icm + 0.5 50 0.9 v icm diff_hstl_iii_18 -v icm ? 0.5 v icm + 0.5 50 1.8 v icm diff_sstl18_i -v icm ? 0.5 v icm + 0.5 50 0.9 v icm diff_sstl18_ii -v icm ? 0.5 v icm + 0.5 50 0.9 v icm diff_sstl2_i -v icm ? 0.5 v icm + 0.5 50 1.25 v icm diff_sstl2_ii -v icm ? 0.5 v icm + 0.5 50 1.25 v icm diff_sstl3_i -v icm ? 0.5 v icm + 0.5 50 1.5 v icm diff_sstl3_ii -v icm ? 0.5 v icm + 0.5 50 1.5 v icm notes: 1. descriptions of the relevant symbols are as follows: v ref ? the reference voltage for setting the input switching threshold v icm ? the common mode input voltage v m ? voltage of measurement point on signal transition v l ? low-level test voltage at input pin v h ? high-level test voltage at input pin r t ? effective termination resistance, which takes on a value of 1 m when no parallel termination is required v t ? termination voltage 2. the load capacitance (c l ) at the output pin is 0 pf for all signal standards. 3. according to the pci specification. for information on pci ip solutions, see www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm . the pcix iostandard is available and has equivalent characteristics but no pci-x ip is supported. ta bl e 3 0 : test methods for timing measurement at i/os (continued) signal standard (iostandard) inputs outputs inputs and outputs v ref (v) v l (v) v h (v) r t ( )v t (v) v m (v) dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 43 r using ibis models to simulate load conditions in application ibis models permit the most accurate prediction of timing delays for a given application. the parameters found in the ibis model (v ref , r ref , and v meas ) correspond directly with the parameters used in table 30 (v t , r t , and v m ). do not confuse v ref (the termination voltage) from the ibis model with v ref (the input-switching threshold) from the table. a fourth parameter, c ref , is always zero. the four parameters describe all relevant output test conditions. ibis models are found in the xilinx development software as well as at the following link: www.xilinx.com/support/download/index.htm delays for a given application are simulated according to its specific load conditions as follows: 1. simulate the desired signal standard with the output driver connected to the test setup shown in figure 11 . use parameter values v t , r t , and v m from ta bl e 3 0 . c ref is zero. 2. record the time to v m . 3. simulate the same signal standard with the output driver connected to the pcb trace with load. use the appropriate ibis model (including v ref , r ref , c ref , and v meas values) or capacitive value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. add (or subtract) the increase (or decrease) in delay to (or from) the appropriate output standard adjustment ( table 29 ) to yield the worst-case delay of the pcb trace. simultaneously switching output guidelines this section provides guidelines for the recommended maximum allowable number of simultaneous switching outputs (ssos). these guidelines describe the maximum number of user i/o pins of a given output signal standard that should simultaneously swit ch in the same direction, while maintaining a safe level of switching noise. meeting these guidelines for the stated test conditions ensures that the fpga operates free from the adverse effects of ground and power bounce. ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. the output drive transistors all conduct current to a common voltage rail. low-to-high tr ansitions conduct to the v cco rail; high-to-low transitions conduct to the gnd rail. the resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. the inductance is associated with bonding wires, the package lead frame, and any other signal routing inside the package. other variables contribute to sso noise levels, including stray inductance on the pcb as well as capacitive loading at receivers. any sso-induced voltage consequently affects internal switching noise margins and ultimately signal quality. table 31 and table 32 provide the essential sso guidelines. for each device/package combination, table 31 provides the number of equivalent v cco /gnd pairs. the equivalent number of pairs is based on characterization and may not match the physical number of pairs. for each output signal standard and drive strength, table 32 recommends the maximum number of ssos, switching in the same direction, allowed per v cco /gnd pair within an i/o bank. the guidelines in table 32 are categorized by package style, slew rate, and output drive current. furthermore, the number of ssos is specified by i/o bank. generally, the left and right i/o banks (banks 1 and 3) support higher output drive current. multiply the appropriate numbers from ta bl e 3 1 and table 32 to calculate the maximum number of ssos allowed within an i/o bank. exceeding these sso guidelines might result in increased power or ground bounce, degraded signal integrity, or increased system jitter. sso max /io bank = table 31 x table 32 the recommended maximum sso values assumes that the fpga is soldered on the printed circuit board and that the board uses sound design practices. the sso values do not apply for fpgas mounted in sockets, due to the lead inductance introduced by the socket. the number of ssos allowed for quad-flat packages (tq) is lower than for ball grid array packages (fg) due to the larger lead inductance of the quad-flat packages. ball grid array packages are recommended for applications with a large number of simultaneously switching outputs. table 31: equivalent v cco /gnd pairs per bank device package style tqg144 ftg256 fgg400 fgg484 fgg676 xc3s50an 2 ? ? ? ? xc3s200an ?4 ? ? ? xc3s400an ? ?5 ? ? xc3s700an ? ? ?5 ? xc3s1400an ? ? ? ?9 dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 44 product specification r ta bl e 3 2 : recommended number of simultaneously switching outputs per v cco -gnd pair signal standard (iostandard) package type tqg144 ftg256, fgg400, fgg484, fgg676 top, bottom (banks 0,2) left, right (banks 1,3) top, bottom (banks 0,2) left, right (banks 1,3) single-ended standards lvttl slow 2 20 20 60 60 410 10 41 41 610 10 29 29 86 6 22 22 12 6 6 13 13 16 5 5 11 11 24 4 4 9 9 fast 2 10 10 10 10 46 6 6 6 65 5 5 5 83 3 3 3 12 3 3 3 3 16 3 3 3 3 24 2 2 2 2 quietio 2 40 40 80 80 424 24 48 48 620 20 36 36 816 16 27 27 12 12 12 16 16 16 9 9 13 13 24 9 9 12 12 lv c m o s 3 3 s l o w 2 2 4 2 4 7 6 7 6 414 14 46 46 611 11 27 27 810 10 20 20 12 9 9 13 13 16 8 8 10 10 24 ?8 ?9 fast 2 10 10 10 10 48 8 8 8 65 5 5 5 84 4 4 4 12 4 4 4 4 16 2 2 2 2 24 ?2 ?2 quietio 2 36 36 76 76 432 32 46 46 624 24 32 32 816 16 26 26 12 16 16 18 18 16 12 12 14 14 24 ?10 ?10 table 32: recommended number of simultaneously switching outputs per v cco -gnd pair (continued) signal standard (iostandard) package type tqg144 ftg256, fgg400, fgg484, fgg676 top, bottom (banks 0,2) left, right (banks 1,3) top, bottom (banks 0,2) left, right (banks 1,3) dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 45 r lv c m o s 2 5 s l ow 2 1 6 1 6 7 6 7 6 410 10 46 46 68 8 33 33 87 7 24 24 12 6 6 18 18 16 ?6 ?11 24 ?5 ?7 fast 2 12 12 18 18 410 10 14 14 68 8 6 6 86 6 6 6 12 3 3 3 3 16 ?3 ?3 24 ?2 ?2 quietio 2 36 36 76 76 430 30 60 60 624 24 48 48 820 20 36 36 12 12 12 36 36 16 ?12 ?36 24 ?8 ?8 lv c m o s 1 8 s l ow 2 1 3 1 3 6 4 6 4 48 8 34 34 68 8 22 22 87 7 18 18 12 ?5 ?13 16 ?5 ?10 fast 2 13 13 18 18 48 8 9 9 67 7 7 7 84 4 4 4 12 ?4 ?4 16 ?3 ?3 quietio 2 30 30 64 64 424 24 64 64 620 20 48 48 816 16 36 36 12 ?12 ?36 16 ?12 ?24 ta bl e 3 2 : recommended number of simultaneously switching outputs per v cco -gnd pair (continued) signal standard (iostandard) package type tqg144 ftg256, fgg400, fgg484, fgg676 top, bottom (banks 0,2) left, right (banks 1,3) top, bottom (banks 0,2) left, right (banks 1,3) lv c m o s 1 5 s l o w 2 1 2 1 2 5 5 5 5 47 7 31 31 67 7 18 18 8 ?6 ?15 12 ?5 ?10 fast 2 10 10 25 25 47 7 10 10 66 6 6 6 8 ?4 ?4 12 ?3 ?3 quietio 2 30 30 70 70 421 21 40 40 618 18 31 31 8 ?12 ?31 12 ?12 ?20 lv c m o s 1 2 s l o w 2 1 7 1 7 4 0 4 0 4 ?13 ?25 6 ?10 ?18 fast 2 12 9 31 31 4 ?9 ?13 6 ?9 ?9 quietio 2 36 36 55 55 4 ?33 ?36 6 ?27 ?36 pci33_3 9 9 16 16 pci66_3 ?9 ?13 hstl_i ?11 ?20 hstl_iii ?7 ?8 hstl_i_18 13 13 17 17 hstl_ii_18 ?5 ?5 hstl_iii_18 8 8 10 8 sstl18_i 7 13 7 15 sstl18_ii ?9 ?9 sstl2_i 10 10 18 18 sstl2_ii ?6 ?9 sstl3_i 7 8 8 10 sstl3_ii 5 6 6 7 table 32: recommended number of simultaneously switching outputs per v cco -gnd pair (continued) signal standard (iostandard) package type tqg144 ftg256, fgg400, fgg484, fgg676 top, bottom (banks 0,2) left, right (banks 1,3) top, bottom (banks 0,2) left, right (banks 1,3) dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 46 product specification r differential standards (number of i/o pairs or channels) lv d s _ 2 5 8 ?22 ? lv d s _ 3 3 8 ?27 ? blvds_25 1 1 4 4 mini_lvds_25 8 ?22 ? mini_lvds_33 8 ?27 ? lvpecl_25 input only lvpecl_33 input only rsds_25 8 ?22 ? rsds_33 8 ?27 ? tmds_33 8 ?27 ? ppds_25 8 ?22 ? ppds_33 8 ?27 ? diff_hstl_i ?5 ?10 diff_hstl_iii ?3 ?4 diff_hstl_i_18 6 6 8 8 diff_hstl_ii_18 ?2 ?2 diff_hstl_iii_18 4 4 5 4 diff_sstl18_i 3 6 3 7 diff_sstl18_ii ?4 ?4 diff_sstl2_i 5 5 9 9 diff_sstl2_ii ?3 ?4 diff_sstl3_i 3 4 4 5 diff_sstl3_ii 2 3 3 3 notes: 1. not all i/o standards are supported on all i/o banks. the left and right banks (i/o banks 1 and 3) support higher output drive current than the top and bottom banks (i/o banks 0 and 2). similarly, true differential output standards, such as lvds, rsds, ppds, minilvds, and tmds, are only supported in top or bottom banks (i/o banks 0 and 2). refer to ug331 : spartan-3 generation fpga user guide for additional information. 2. the numbers in this table are recommendations that assume sound board lay out practice. test limits are the v il /v ih voltage limits for the respective i/o standard. 3. if more than one signal standard is assigned to the i/os of a given bank, refer to xapp689 : managing ground bounce in large fpgas for information on how to perform weighted average sso calculations. ta bl e 3 2 : recommended number of simultaneously switching outputs per v cco -gnd pair (continued) signal standard (iostandard) package type tqg144 ftg256, fgg400, fgg484, fgg676 top, bottom (banks 0,2) left, right (banks 1,3) top, bottom (banks 0,2) left, right (banks 1,3) dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 47 r configurable logic block (clb) timing ta bl e 3 3 : clb (slicem) timing symbol description speed grade units -5 -4 min max min max clock-to-output times t cko when reading from the ffx (ffy) flip-flop, the time from the active transition at the clk input to data appearing at the xq (yq) output ?0.60 ?0.68ns setup times t as time from the setup of data at the f or g input to the active transition at the clk input of the clb 0.18 ?0.36 ?ns t dick time from the setup of data at the bx or by input to the active transition at the clk input of the clb 1.58 ?1.88 ?ns hold times t ah time from the active transition at the clk input to the point where data is last held at the f or g input 0 ?0 ?ns t ckdi time from the active transition at the clk input to the point where data is last held at the bx or by input 0 ?0 ?ns clock timing t ch the high pulse width of the clb?s clk signal 0.63 ?0.75 ?ns t cl the low pulse width of the clk signal 0.63 ?0.75 ?ns f tog toggle frequency (for export control) 0 770 0 667 mhz propagation times t ilo the time it takes for data to travel from the clb?s f (g) input to the x (y) output ?0.62 ?0.71ns set/reset pulse width t rpw_clb the minimum allowable pulse width, high or low, to the clb?s sr input 1.33 ?1.61 ?ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 1 0 . dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 48 product specification r ta bl e 3 4 : clb distributed ram swit ching characteristics symbol description -5 -4 units min max min max clock-to-output times t shcko time from the active edge at the clk input to data appearing on the distributed ram output ?1.69 ?2.01ns setup times t ds setup time of data at the bx or by input before the active transition at the clk input of the distributed ram ?0.07 ? ?0.02 ?ns t as setup time of the f/g address inputs before the active transition at the clk input of the distributed ram 0.18 ?0.36 ?ns t ws setup time of the write enable input before the active transition at the clk input of the distributed ram 0.30 ?0.59 ?ns hold times t dh hold time of the bx and by data inputs after the active transition at the clk input of the distributed ram 0.13 ?0.13 ?ns t ah, t wh hold time of the f/g address inputs or the write enable input after the active transition at the clk input of the distributed ram 0.01 ?0.01 ?ns clock pulse width t wph , t wpl minimum high or low pulse width at clk input 0.88 ?1.01 ?ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 1 0 . ta bl e 3 5 : clb shift register swit ching characteristics symbol description -5 -4 units min max min max clock-to-output times t reg time from the active edge at the clk input to data appearing on the shift register output ?4.11 ?4.82ns setup times t srlds setup time of data at the bx or by input before the active transition at the clk input of the shift register 0.13 ?0.18 ?ns hold times t srldh hold time of the bx or by data input after the active transition at the clk input of the shift register 0.16 ?0.16 ?ns clock pulse width t wph , t wpl minimum high or low pulse width at clk input 0.90 ?1.01 ?ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 1 0 . dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 49 r clock buffer/multiplexer switching characteristics ta bl e 3 6 : clock distribution switching characteristics description symbol minimum maximum units speed grade -5 -4 global clock buffer (bufg, bufgmux, bufgce) i input to o-output delay t gio ?0.220.23ns global clock multiplexer (bufgmux) select s-input setup to i0 and i1 inputs. same as bufgce enable ce-input t gsi ?0.560.63ns frequency of signals distributed on global buffers (all sides) f bufg 0350334mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 1 0 . dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 50 product specification r 18 x 18 embedded multiplier timing ta bl e 3 7 : 18 x 18 embedded multiplier timing symbol description speed grade units -5 -4 min max min max combinatorial delay t mult combinational multiplier propagation delay from the a and b inputs to the p outputs, assuming 18-bi t inputs and a 36-bit product (areg, breg, and preg registers unused) ?4.36 ?4.88ns clock-to-output times t msckp_p clock-to-output delay from the active transition of the clk input to valid data appearing on the p outputs when using the preg register (2,3) ?0.84 ?1.30ns t msckp_a t msckp_b clock-to-output delay from the active transition of the clk input to valid data appearing on the p output s when using either the areg or breg register (2,4) ?4.44 ?4.97ns setup times t msdck_p data setup time at the a or b input before the active transition at the clk when using only the preg ou tput register (areg, breg registers unused) (3) 3.56 ?3.98 ?ns t msdck_a data setup time at the a input before the active transition at the clk when using the areg input register (4) 0.00 ?0.00 ?ns t msdck_b data setup time at the b input before the active transition at the clk when using the breg input register (4) 0.00 ?0.00 ?ns hold times t msckd_p data hold time at the a or b input after the active transition at the clk when using only the preg ou tput register (areg, breg registers unused) (3) 0.00 ?0.00 ?ns t msckd_a data hold time at the a input after the active transition at the clk when using the areg input register (4) 0.35 ?0.45 ?ns t msckd_b data hold time at the b input after the active transition at the clk when using the breg input register (4) 0.35 ?0.45 ?ns clock frequency f mult internal operating frequency for a two-stage 18x18 multiplier using the areg and breg input regi sters and the preg output register (1) 0 280 0 250 mhz notes: 1. combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits. 2. the preg register is typically used in both single-stage and two-stage pipelined multiplier implementations. 3. the preg register is typically used when inferring a single-stage multiplier. 4. input registers areg or breg are typically used when inferring a two-stage multiplier. 5. the numbers in this table are based on the operating conditions set forth in ta b l e 1 0 . dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 51 r block ram timing ta bl e 3 8 : block ram timing symbol description speed grade units -5 -4 minmaxminmax clock-to-output times t rcko when reading from block ram, the delay from the active transition at the clk input to data appearing at the dout output ?2.06 ?2.49ns setup times t rcck_addr setup time for the addr inputs before the active transition at the clk input of the block ram 0.32 ?0.36 ?ns t rdck_dib setup time for data at the din inputs before the active transition at the clk input of the block ram 0.28 ?0.31 ?ns t rcck_enb setup time for the en input before the active transition at the clk input of the block ram 0.69 ?0.77 ?ns t rcck_web setup time for the we input before the active transition at the clk input of the block ram 1.12 ?1.26 ?ns hold times t rckc_addr hold time on the addr inputs afte r the active transition at the clk input 0 ?0 ?ns t rckd_dib hold time on the din inputs afte r the active transition at the clk input 0 ?0 ?ns t rckc_enb hold time on the en input after the active transition at the clk input 0 ?0 ?ns t rckc_web hold time on the we input after the active transition at the clk input 0 ?0 ?ns clock timing t bpwh high pulse width of the clk signal 1.56 ?1.79 ?ns t bpwl low pulse width of the clk signal 1.56 ?1.79 ?ns clock frequency f bram block ram clock frequency 0 320 0 280 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 1 0 . dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 52 product specification r digital clock manager (dcm) timing for specification purposes, the dcm consists of three key components: the delay-locked loop (dll), the digital frequency synthesizer (dfs), and the phase shifter (ps). aspects of dll operation play a role in all dcm applications. all such applicat ions inevitably use the clkin and the clkfb inputs connected to either the clk0 or the clk2x feedback, respectively. thus, specifications in the dll tables ( table 39 and table 40 ) apply to any application that only employs the dll component. when the dfs and/or the ps components are used together with the dll, then the specifications listed in the dfs and ps tables ( ta bl e 4 1 through table 44 ) supersede any corresponding ones in the dll tables. dll specifications that do not change with the addition of dfs or ps functions are presented in table 39 and table 40 . period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. both specifications describe statistical variation from a mean value. period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples. in a histogram of period jitter, the mean value is the clock period. cycle-cycle jitter is the worst-ca se difference in clock period between adjacent clock cycles in the collection of clock periods sampled. in a histogram of cycle-cycle jitter, the mean value is zero. spread spectrum dcms accept typical spread spectrum clocks as long as they meet the input requir ements. the dll will track the frequency changes created by th e spread spectrum clock to drive the global clocks to the fpga logic. see xapp469 , spread-spectrum clocking reception for displays for details. delay-locked loop (dll) ta bl e 3 9 : recommended operating conditions for the dll symbol description speed grade units -5 -4 min max min max input frequency ranges f clkin clkin_freq_dll frequency of the clkin clock input 5 (2) 280 (3) 5 (2) 250 (3) mhz input pulse requirements clkin_pulse clkin pulse width as a percentage of the clkin period f clkin < 150 mhz 40% 60% 40% 60% - f clkin > 150 mhz 45% 55% 45% 55% - input clock jitter toleran ce and delay path variation (4) clkin_cyc_jitt_dll_lf cycle-to-cycle jitter at the clkin input f clkin < 150 mhz ?300 ?300ps clkin_cyc_jitt_dll_hf f clkin > 150 mhz ?150 ?150ps clkin_per_jitt_dll period jitter at the clkin input ?1 ?1ns clkfb_delay_var_ext allowable variation of off-chip feedback delay from the dcm output to the clkfb input ?1 ?1ns notes: 1. dll specifications apply when any of the dll outputs (clk0, cl k90, clk180, clk270, clk2x, clk2x180, or clkdv) are in use. 2. the dfs, when operating independently of the dll, supports lower fclkin frequencies. see ta bl e 4 1 . 3. the clkin_divide_by_2 attribute can be used to increase the effective input frequency range up to f bufg . when set to true, clkin_divide_by_2 divides the incoming clock frequency by two as it enters the dcm. 4. clkin input jitter beyond these limits might cause the dcm to lose lock. 5. the dcm specifications are guaranteed when both adjacent dcms are locked. dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 53 r ta bl e 4 0 : switching characteristics for the dll symbol description device speed grade units -5 -4 min max min max output frequency ranges clkout_freq_clk0 frequency for the clk0 and clk180 outputs all 5 280 5 250 mhz clkout_freq_clk90 frequency for the clk90 and clk270 outputs 5 200 5 200 mhz clkout_freq_2x frequency for the clk2x and clk2x180 outputs 10 334 10 334 mhz clkout_freq_dv frequency for the clkdv output 0.3125 186 0.3125 166 mhz output clock jitter (2,3,4) clkout_per_jitt_0 period jitter at the clk0 output all ? 100 ? 100 ps clkout_per_jitt_90 period jitter at the clk90 output ? 150 ? 150 ps clkout_per_jitt_180 period jitter at the clk180 output ? 150 ? 150 ps clkout_per_jitt_270 period jitter at the clk270 output ? 150 ? 150 ps clkout_per_jitt_2x period jitter at the clk2x and clk2x180 outputs ? [0.5% of clkin period + 100] ? [0.5% of clkin period + 100] ps clkout_per_jitt_dv1 period jitter at the clkdv output when performing integer division ? 150 ? 150 ps clkout_per_jitt_dv2 period jitter at the clkdv output when performing non-integer division ? [0.5% of clkin period + 100] ? [0.5% of clkin period + 100] ps duty cycle (4) clkout_duty_cycle_dll duty cycle variation for the clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv outputs, including the bufgmux and clock tree duty-cycle distortion all ? [1% of clkin period + 350] ? [1% of clkin period + 350] ps phase alignment (4) clkin_clkfb_phase phase offset between the clkin and clkfb inputs all ? 150 ? 150 ps clkout_phase_dll phase offset between dll outputs clk0 to clk2x (not clk2x180) ? [1% of clkin period + 100] ? [1% of clkin period + 100] ps all others ? [1% of clkin period + 150] ? [1% of clkin period + 150] ps lock time lock_dll (3) when using the dll alone: the time from deassertion at the dcm?s reset input to the rising transition at its locked output. when the dcm is locked, the clkin and clkfb signals are in phase 5 mhz < f clkin < 15 mhz all ? 5 ? 5ms f clkin > 15 mhz ? 600 ? 600 s delay lines dcm_delay_step (5) finest delay resolution, average over all taps all 15 35 15 35 ps notes: 1. the numbers in this table are based on the operating conditions set forth in table 10 and table 39 . 2. indicates the maximum amount of output jitter that the dcm adds to the jitter on the clkin input. 3. for optimal jitter tolerance and faster lock time, use the clkin_period attribute. 4. some jitter and duty-cycle specifications include 1% of input clock period or 0.01 ui. for example, the data sheet specifies a maximum jitter of ?[1% of clkin period + 150]?. assume the clkin frequency is 100 mhz. t he equivalent clkin period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. according to the data sheet, the maximum jitter is [100 ps + 150 ps] = 250 ps. 5. the typical delay step size is 23 ps. dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 54 product specification r digital frequency synthesizer (dfs) ta bl e 4 1 : recommended operating conditions for the dfs symbol description speed grade units -5 -4 min max min max input frequency ranges (2) f clkin clkin_freq_fx frequency for the clkin input 0.200 333 (4) 0.200 333 (4) mhz input clock jitter tolerance (3) clkin_cyc_jitt_fx_lf cycle-to- cycle jitter at the clkin input, based on clkfx output frequency f clkfx < 150 mhz ? 300 ? 300 ps clkin_cyc_jitt_fx_hf f clkfx > 150 mhz ? 150 ? 150 ps clkin_per_jitt_fx period jitter at the clkin input ? 1 ? 1 ns notes: 1. dfs specifications apply when either of th e dfs outputs (clkfx or clkfx180) are used. 2. if both dfs and dll outputs are used on the same dcm, follow the more restrictive clkin_freq_dll specifications in table 39 . 3. clkin input jitter beyond these limits may cause the dcm to lose lock. 4. to support double the maximum effective fclkin limit, set the clkin_divide_by_2 attribute to true. this attribute divides the incoming clock frequency by two as it enters the dcm. ta bl e 4 2 : switching characteristics for the dfs symbol description device speed grade units -5 -4 min max min max output frequency ranges clkout_freq_fx frequency for the clkfx and clkfx180 outputs all 5 350 5 320 mhz output clock jitter (2,3) clkout_per_jitt_fx period jitter at the clkfx and clkfx180 outputs. all typ max typ max clkin 20 mhz use the spartan-3a jitter calculator: www.xilinx.com/support/documentation /data_sheets/s3a_jitter_calc.zip ps clkin > 20 mhz [1% of clkfx period + 100] [1% of clkfx period + 200] [1% of clkfx period + 100] [1% of clkfx period + 200] ps duty cycle (4,5) clkout_duty_cycle_fx duty cycle precision for t he clkfx and clkfx180 outputs, including the bufgmux and cloc k tree duty-cycle distortion all ? [1% of clkfx period + 350] ? [1% of clkfx period + 350] ps phase alignment (5) clkout_phase_fx phase offset between the dfs clkfx output and the dll clk0 output when both the dfs and dll are used all ? 200 ? 200 ps clkout_phase_fx180 phase offset between the dfs clkfx180 output and the dll clk0 output when both the dfs and dll are used all ? [1% of clkfx period + 200] ? [1% of clkfx period + 200] ps dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 55 r lock time lock_fx (2) the time from deassertion at the dcm?s reset input to the rising transition at its locked output. the dfs asserts locked when the clkfx and clkfx180 signals are valid. if using both the dll and the dfs, use the longer locking time. 5 mhz < f clkin < 15 mhz all ? 5 ? 5ms f clkin > 15 mhz ? 450 ? 450 s notes: 1. the numbers in this table are based on the operating conditions set forth in table 10 and table 41 . 2. for optimal jitter tolerance and faster lock time, use the clkin_period attribute. 3. maximum output jitter is characterized within a reasonable noi se environment (40 ssos and 25% clb switching) on an xc3s1400a fpga. output jitter strongly depends on the environment, including the number of ssos, the output drive strength, clb utilization, cl b switching activities, switching frequency, power supply and pcb design. the actual maximum output jitter depends on the system applicatio n. 4. the clkfx and clkfx180 outputs always have an approximate 50% duty cycle. 5. some duty-cycle and alignment specifications include a percentage of the clkfx output period. for example, the data sheet spe cifies a maximum clkfx jitter of ?[1% of clkfx period + 200]?. assume the clkfx output frequency is 100 mhz. the equivalent clkfx perio d is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. according to the data sheet, the maximum jitter is [100 ps + 200 ps] = 300 ps. ta bl e 4 2 : switching characteristics for the dfs (continued) symbol description device speed grade units -5 -4 min max min max dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 56 product specification r phase shifter (ps) ta bl e 4 3 : recommended operating conditions for the ps in variable phase mode symbol description speed grade units -5 -4 min max min max operating frequency ranges psclk_freq (f psclk ) frequency for the psclk input 1 167 1 167 mhz input pulse requirements psclk_pulse psclk pulse width as a perc entage of the psclk period 40% 60% 40% 60% - ta bl e 4 4 : switching characteristics for the ps in variable phase mode symbol description phase shift amount units phase shifting range max_steps (2) maximum allowed number of dcm_delay_step steps for a given clkin clock period, where t = clkin clock period in ns. if using clkin_divide_by_2 = true, double the clock effective clock period. clkin < 60 mhz [integer(10 ? (t clkin ? 3 ns))] steps clkin 60 mhz [integer(15 ? (t clkin ? 3 ns))] fine_shift_range_min mini mum guaranteed delay for variable phase shifting [max_steps ? dcm_delay_step_min] ns fine_shift_range_max maximum guaranteed delay for variable phase shifting [max_steps ? dcm_delay_step_max] ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 1 0 and ta bl e 4 3 . 2. the maximum variable phase shift range, max_steps, is only valid when the dcm is has no initial fixed phase shifting, that is , the phase_shift attribute is set to 0. 3. the dcm_delay_step values are provided at the bottom of table 40 . dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 57 r miscellaneous dcm timing dna port timing internal spi access port timing ta bl e 4 5 : miscellaneous dcm timing symbol description min max units dcm_rst_pw_min minimum duration of a rst pulse width 3 ?clkin cycles dcm_rst_pw_max (2) maximum duration of a rst pulse width n/a n/a seconds n/a n/a seconds dcm_config_lag_time (3) maximum duration from v ccint applied to fpga configuration successfully co mpleted (done pin goes high) and clocks applied to dcm dll n/a n/a minutes n/a n/a minutes notes: 1. this limit only applies to applications that use the dcm dll outputs (clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv ). the dcm dfs outputs (clkfx, clkfx180) are unaffected. 2. this specification is equivalent to the virtex ? -4 dcm_reset specification. this specification does not apply for spartan-3an fpgas. 3. this specification is equivalent to the virtex-4 tconfig specification. this specification does not apply for spartan-3an fpg as. ta bl e 4 6 : dna_port interface timing symbol description min max units t dnassu setup time on shift before the rising edge of clk 1.0 ?ns t dnash hold time on shift after the rising edge of clk 0.5 ?ns t dnadsu setup time on din before the rising edge of clk 1.0 ?ns t dnadh hold time on din after the rising edge of clk 0.5 ?ns t dnarsu setup time on read before the rising edge of clk 5.0 10,000 ns t dnarh hold time on read after the rising edge of clk 0 ?ns t dnadcko clock-to-output delay on dout after rising edge of clk 0.5 1.5 ns t dnaclkf clk frequency 0 100 mhz t dnaclkl clk high time 1.0 ns t dnaclkh clk low time 1.0 ns notes: 1. the minimum read pulse width is 5 ns, the maximum read pulse width is 10 s . ta bl e 4 7 : spi_access interface timing symbol description speed grade units -5 -4 minmaxminmax t spicck_mosi setup time on mosi before the active edge of clk 4.47 ?5.0 ?ns t spickc_mosi hold time on mosi after th e active edge of clk 4.03 ?4.5 ?ns t csb csb high time 50 ?50 ?ns t spicck_csb setup time on csb before the active edge of clk 7.15 ?8.0 ?ns t spicck_csb hold time on csb after the active edge of clk 7.15 ?8.0 ?ns t spicko_miso clock-to-output delay on miso after active edge of clk ?14.3 ? 16.0 ns f spiclk clk frequency ?50 ?50mhz f spicar1 clk frequency for continuous array read command ?50 ?50mhz dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 58 product specification r in-system flash (isf) memory timing f spicar1 clk frequency for continuous array read command, reduced initial latency ?33 ?33mhz t spiclkl clk high time ? ? ns t spiclkh clk low time 6.8 6.8 ns notes: 1. for details on using spi_access and the in-system flash memory, see ug333 spartan-3an fpga in-system flash user guide . ta bl e 4 7 : spi_access interface timing (continued) symbol description speed grade units -5 -4 minmaxminmax ta bl e 4 8 : in-system flash (isf) memory operations symbol description device typical max units t xfer page to buffer transfer time all ?400 s t comp page to buffer compare time all ?400 s t pp page programming time xc3s50an xc3s200an xc3s400an 24ms xc3s700an xc3s1400an 36ms t pe page erase time xc3s50an xc3s200an xc3s400an 13 32 ms xc3s700an xc3s1400an 15 35 ms t pep page erase and programming time xc3s50an xc3s200an xc3s400an xc3s700an 14 35 ms xc3s1400an 17 40 ms t be block erase time xc3s50an 15 35 ms xc3s200an xc3s400an 30 75 ms xc3s700an xc3s1400an 45 100 ms t se sector erase time xc3s50an 0.8 2.5 s xc3s200an xc3s400an xc3s700an xc3s1400an 1.6 5 s dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 59 r suspend mode timing x-ref target - figure 12 figure 12: suspend mode timing ta bl e 4 9 : suspend mode timing parameters symbol description min typ max units entering suspend mode t suspendhigh_awake rising edge of suspend pin to falling edge of awake pin without glitch filter ( suspend_filter:no ) ?7 ?ns t suspendfilter adjustment to suspend pin rising edge parameters when glitch filter enabled ( suspend_filter:yes ) +160 +300 +600 ns t suspend_gwe rising edge of suspend pin until fpga output pins drive their defined suspend constraint behavior ?10 ?ns t suspend_gts rising edge of suspend pin to write-protect lock on all writable clocked elements ?<5 ?ns t suspend_disable rising edge of the suspend pin to fpga input pins and interconnect disabled ? 340 ?ns exiting suspend mode t suspendlow_awake falling edge of the suspend pin to rising edge of the awake pin does not include dcm lock time ? 4 to 108 ? s t suspend_enable falling edge of the suspend pin to fpga input pins and interconnect re-enabled ? 3.7 to 109 ? s t awake_gwe1 rising edge of the awake pin until write-pr otect lock released on all writable clocked elements, using sw_clk:internalclock and sw_gwe_cycle:1 ?67 ?ns t awake_gwe512 rising edge of the awake pin until write-pr otect lock released on all writable clocked elements, using sw_clk:internalclock and sw_gwe_cycle:512 ?14 ? s t awake_gts1 rising edge of the awake pin until outputs return to the behavior described in the fpga application, using sw_clk:internalclock and sw_gts_cycle:1 ?57 ?ns t awake_gts512 rising edge of the awake pin until outputs return to the behavior described in the fpga application, using sw_clk:internalclock and sw_gts_cycle:512 ?14 ? s notes: 1. these parameters based on characterization. 2. for information on using the spartan-3an suspend feature, see xapp480 : using suspend mode in spartan-3 generation fpgas . ds610-3_08_061207 blocked t suspend_disable t suspend_gwe t suspendhigh_awake t awake_gwe t awake_gts t suspend_gts suspend input awake output flip-flops, block ram, distributed ram fpga outputs fpga inputs, interconnect write protected defined by suspend constraint entering suspend mode exiting suspend mode sw_gts_cycle sw_gwe_cycle t suspend_enable t suspendlow_awake dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 60 product specification r configuration and jtag timing general configuration power-on/reconfigure timing x-ref target - figure 13 figure 13: waveforms for power-on and the beginning of configuration ta bl e 5 0 : power-on timing and the be ginning of configuration symbol description device all speed grades units min max t por (2) the time from the application of v ccint , v ccaux , and v cco bank 2 supply voltage ramps (whichever occurs last) to the rising transition of the init_b pin all -18ms t prog the width of the low-going pulse on the prog_b pin all 0.5 - s t pl (2) the time from the rising edge of the prog_b pin to the rising transition on the init_b pin xc3s50an -0.5ms xc3s200an -0.5ms xc3s400an -1ms xc3s700an -2ms xc3s1400an -2ms t init minimum low pulse width on init_b output all 250 -ns t icck (3) the time from the rising edge of the init_b pin to the generation of the configuration clock signal at the cclk output pin all 0.5 4 s notes: 1. the numbers in this table are based on the operating conditions set forth in table 10 . this means power must be applied to all v ccint , v cco , and v ccaux lines. 2. power-on reset and the clearing of configuration memory occurs during this period. 3. this specification applies only to the master serial, spi, and bpi modes. 4. for details on configuration, see ug332 spartan-3 generation configuration user guide . v ccint (supply) (supply) (supply) v ccaux v cco bank 2 prog_b (output) (open-drain) (input) init_b cclk ds557-3_01_052908 1.2v t icck t prog t pl t por 1.0v 2.0v 2.0v 3.3v 3.3v 2.5v or notes: 1. when configuring from the in-system flash, v ccaux must be in the recommended operating range; on power-up make sure v ccaux reaches at least 3.0v before init_b goes high to indicate the start of configuration. v ccint , v ccaux , and v cco supplies to the fpga can be applied in any order if this requirement is met. 2. the low-going pulse on prog_b is optional after power-on but necessary for reconfiguration without a power cycle. 3. the rising edge of init_b samples the voltage levels applied to the mode pins (m0 - m2). dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 61 r configuration clock (cclk) characteristics ta bl e 5 1 : master mode cclk output period by configrate option setting symbol description configrate setting temperature range minimum maximum units t cclk1 cclk clock period by configrate setting 1 (power-on value) commercial 1,254 2,500 ns industrial 1,180 ns t cclk3 3 commercial 413 833 ns industrial 390 ns t cclk6 6 ( default ) commercial 207 417 ns industrial 195 ns t cclk7 7 commercial 178 357 ns industrial 168 ns t cclk8 8 commercial 156 313 ns industrial 147 ns t cclk10 10 commercial 123 250 ns industrial 116 ns t cclk12 12 commercial 103 208 ns industrial 97 ns t cclk13 13 commercial 93 192 ns industrial 88 ns t cclk17 17 commercial 72 147 ns industrial 68 ns t cclk22 22 commercial 54 114 ns industrial 51 ns t cclk25 25 commercial 47 100 ns industrial 45 ns t cclk27 27 commercial 44 93 ns industrial 42 ns t cclk33 33 commercial 36 76 ns industrial 34 ns t cclk44 44 commercial 26 57 ns industrial 25 ns t cclk50 50 commercial 22 50 ns industrial 21 ns t cclk100 100 commercial 11.2 25 ns industrial 10.6 ns notes: 1. set the configrate option value when generating a configuration bitstream. dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 62 product specification r ta bl e 5 2 : master mode cclk output frequency by configrate option setting symbol description configrate setting temperature range minimum maximum units f cclk1 equivalent cclk clock frequency by configrate setting 1 (power-on value) commercial 0.400 0.797 mhz industrial 0.847 mhz f cclk3 3 commercial 1.20 2.42 mhz industrial 2.57 mhz f cclk6 6 ( default ) commercial 2.40 4.83 mhz industrial 5.13 mhz f cclk7 7 commercial 2.80 5.61 mhz industrial 5.96 mhz f cclk8 8 commercial 3.20 6.41 mhz industrial 6.81 mhz f cclk10 10 commercial 4.00 8.12 mhz industrial 8.63 mhz f cclk12 12 commercial 4.80 9.70 mhz industrial 10.31 mhz f cclk13 13 commercial 5.20 10.69 mhz industrial 11.37 mhz f cclk17 17 commercial 6.80 13.74 mhz industrial 14.61 mhz f cclk22 22 commercial 8.80 18.44 mhz industrial 19.61 mhz f cclk25 25 commercial 10.00 20.90 mhz industrial 22.23 mhz f cclk27 27 commercial 10.80 22.39 mhz industrial 23.81 mhz f cclk33 33 commercial 13.20 27.48 mhz industrial 29.23 mhz f cclk44 44 commercial 17.60 37.60 mhz industrial 40.00 mhz f cclk50 50 commercial 20.00 44.80 mhz industrial 47.66 mhz f cclk100 100 commercial 40.00 88.68 mhz industrial 94.34 mhz ta bl e 5 3 : master mode cclk output minimum low and high time symbol description configrate setting units 1 3 6 7 8 10 12 13 17 22 25 27 33 44 50 100 t mccl, t mcch master mode cclk minimum low and high time commercial 595 196 98.3 84.5 74.1 58.4 48.9 44.1 34.2 25.6 22.3 20.9 17.1 12.3 10.4 5.3 ns industrial 560 185 92.6 79.8 69.8 55.0 46.0 41.8 32.3 24.2 21.4 20.0 16.2 11.9 10.0 5.0 ns ta bl e 5 4 : slave mode cclk input low and high time symbol description min max units t sccl, t scch cclk low and high time 5 ns dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 63 r master serial and slave serial mode timing x-ref target - figure 14 figure 14: waveforms for master serial and slave serial configuration ta bl e 5 5 : timing for the master serial and slave serial configuration modes symbol description slave/ master all speed grades units min max clock-to-output times t cco the time from the falling transition on the cclk pin to data appearing at the dout pin both 1.5 10 ns setup times t dcc the time from the setup of data at the din pin to the rising transition at the cclk pin both 7 ?ns hold times t ccd the time from the rising transition at the cclk pin to the point when data is last held at the din pin master 0 ? ns slave 1.0 clock timing t cch high pulse width at the cclk input pin master see table 53 slave see table 54 t ccl low pulse width at the cclk input pin master see table 53 slave see table 54 f ccser frequency of the clock signal at the cclk input pin no bitstream compression slave 0 100 mhz with bitstream compression 0 100 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 1 0 . 2. for serial configuration with a daisy-chain of multiple fpgas, the maximum limit is 25 mhz. ds312-3_05_103105 bit 0 bit 1 bit n bit n+1 bit n-64 bit n-63 1/f ccser t sccl t dcc t ccd t scch t cco prog_b (input) din (input) dout (output) (open-drain) init_b (input/output) cclk t mccl t mcch dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 64 product specification r slave parallel mode timing x-ref target - figure 15 figure 15: waveforms for slave parallel configuration ta bl e 5 6 : timing for the slave parallel configuration mode symbol description all speed grades units min max setup times t smdcc the time from the setup of dat a at the d0-d7 pins to the rising transition at the cclk pin 7 -ns t smcscc setup time on the csi_b pin before the rising transition at the cclk pin 7 -ns t smccw (2) setup time on the rdwr_b pin before the rising transition at the cclk pin 15 -ns hold times t smccd the time from the rising transition at the ccl k pin to the point when data is last held at the d0-d7 pins 1.0 -ns t smcccs the time from the rising transition at the cclk pin to the point when a logic level is last held at the cso_b pin 0 -ns t smwcc the time from the rising transition at the cclk pin to the point when a logic level is last held at the rdwr_b pin 0 -ns clock timing t cch the high pulse width at the cclk input pin 5 -ns t ccl the low pulse width at the cclk input pin 5 -ns f ccpar frequency of the clock signal at the cclk input pin no bitstream compression 0 80 mhz with bitstream compression 0 80 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in table 10 . 2. some xilinx documents refer to parallel modes as ?selectmap? modes. d s 529- 3 _02_051607 byte 0 byte 1 byte n byte n+1 t s mwcc 1/f ccpar t s mccc s t s cch t s mccw t s mccd t s mc s cc t s mdcc prog_b (inp u t) (open-dr a in) init_b (inp u t) c s i_b rdwr_b (inp u t) (inp u t) cclk (inp u t s ) d0 - d7 t mcch t s ccl t mccl notes: 1. it is possible to abort configuration by pulling csi_b low in a given cclk cycle, then switching rdwr_b low or high in any su bsequent cycle for which csi_b remains low. the rdwr_b pin asynchronously co ntrols the driver impedance of the d0 - d7 bus. when rdwr_b switches high, be careful to avoid contention on the d0 - d7 bus. 2. to pause configuration, pause cclk instead of de-asserting csi_b. see ug332 chapter 7 section ?non-continuous selectmap data loading? for more details. dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 65 r external serial peripheral interface (spi) configuration timing x-ref target - figure 16 figure 16: waveforms for external serial periph eral interface (spi) configuration ta bl e 5 7 : timing for external serial peripheral interface (spi) configuration mode symbol description minimum maximum units t cclk1 initial cclk clock period see table 51 t cclk n cclk clock period after fpga loads configrate bitstream option setting see table 51 t minit setup time on vs[2:0] variant-select pi ns and m[2:0] mode pins before the rising edge of init_b 50 ?ns t initm hold time on vs[2:0] variant-select pins and m[2:0] m ode pins after the rising edge of init_b 0 ?ns t cco mosi output valid delay after cclk falling clock edge see table 55 t dcc setup time on the din data input before cclk rising clock edge see table 55 t ccd hold time on the din data input after cclk rising clock edge see table 55 t dh t dsu command (msb) t v t css <1:1:1> init_b m[2:0] t minit t initm din cclk (input) t cclk n t cclk1 vs[2:0] (input) new configrate active mode input pins m[2:0] and variant select input pins vs[2:0] are sampled when init_b goes high. after this point, input values do not matter until done goes high, at which point these pins become user-i/o pins. <0:0:1> pin initially pulled high by internal pull-up resistor if pudc_b input is low. pin initially high-impedance (hi-z) if pudc_b input is high. external pull-up resistor required on cso_b. t cclk1 t mccl n t mcch n (input) data data data data cso_b mosi t cco t mccl1 t mcch1 t dcc t ccd (input) prog_b pudc_b (input) pudc_b must be stable before init_b goes high and constant throughout the configuration process. ds529-3_06_102506 (open-drain) shaded values indicate specifications on attached spi flash prom. command (msb-1) dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 66 product specification r ta bl e 5 8 : configuration timing requirements for attached spi serial flash symbol description requirement units t ccs spi serial flash prom chip-select time ns t dsu spi serial flash prom data input setup time ns t dh spi serial flash prom data input hold time ns t v spi serial flash prom data clock-to-output time ns f c or f r maximum spi serial flash prom clock frequency (also depends on specific read command used) mhz notes: 1. these requirements are for successful fpga configuration in spi mode, where the fpga generates the cclk signal. the post-configuration timing can be different to support the specific needs of the application loaded into the fpga. 2. subtract additional printed circuit board routing delay as required by the application. t ccs t mccl 1 t cco ? t dsu t mccl 1 t cco ? t dh t mcch 1 t v t mccln t dcc ? f c 1 t cclkn min () --------------------------------- dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 67 r byte peripheral interface (bpi) configuration timing x-ref target - figure 17 figure 17: waveforms for byte-wide periphera l interface (bpi) configuration ta bl e 5 9 : timing for byte-wide peripheral inte rface (bpi) configuration mode symbol description minimum maximum units t cclk1 initial cclk clock period see table 51 t cclk n cclk clock period after fpga loads configrate setting see table 51 t minit setup time on m[2:0] mode pins be fore the rising edge of init_b 50 ?ns t initm hold time on m[2:0] mode pins after the rising edge of init_b 0 ?ns t initaddr minimum period of initial a[25:0] address cycle; ldc[ 2:0] and hdc are asserted and valid 55t cclk1 cycles t cco address a[25:0] outputs valid after cclk falling edge see table 55 t dcc setup time on d[7:0] data inputs before cclk rising edge see t smdcc in ta b l e 5 6 t ccd hold time on d[7:0] data inputs after cclk rising edge 0 ?ns (input) pudc_b must be stable before init_b goes high and constant throughout the configuration process. data data data address address data address byte 0 000_0000 init_b <0:1:0> m[2:0] t minit t initm ldc[2:0] hdc cso_b byte 1 000_0001 cclk a[25:0] d[7:0] t dcc t ccd t avqv t cclk1 (input) t initaddr t cclk n t cclk1 t cco pudc_b new configrate active pin initially pulled high by internal pull-up resistor if pudc_b input is low. pin initially high-impedance (hi-z) if pudc_b input is high. mode input pins m[2:0] are sampled when init_b goes high. after this point, input values do not matter until done goes high, at which point the mode pins become user-i/o pins. (input) prog_b (input) ds557-3_16_032009 (open-drain) shaded values indicate specifications on attached parallel nor flash prom. dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 68 product specification r ta bl e 6 0 : configuration timing requirements for attached parallel nor flash symbol description requirement units t ce (t elqv ) parallel nor flash prom chip-select time ns t oe (t glqv ) parallel nor flash prom output-enable time ns t acc (t avqv ) parallel nor flash prom read access time ns t byte (t flqv, t fhqv ) for x8/x16 proms only: byte# to output valid time (3) ns notes: 1. these requirements are for successful fpga configuration in bpi mode, where the fpga generates the cclk signal. the post-configuration timing can be different to support the specific needs of the application loaded into the fpga. 2. subtract additional printed circuit board routing delay as required by the application. 3. the initial byte# timing can be extended using an external, appr opriately sized pull-down resistor on the fpga?s ldc2 pin. th e resistor value also depends on whether the fpga?s pudc_b pin is high or low. t ce t initaddr t oe t initaddr t acc 0.5 t cclkn min () t cco t dcc pcb ? ? ? t byte t initaddr dc and switching characteristics ds557-3 (v3.2) november 19, 2009 www.xilinx.com product specification 69 r ieee 1149.1/1553 jtag test access port timing x-ref target - figure 18 figure 18: jtag waveforms tck t tmstck tms tdi tdo (input) (input) (input) (output) t tcktms t tcktdi t tcktdo t tditck ds557_13_032009 t cch t ccl 1/f tck ta bl e 6 1 : timing for the jtag test access port symbol description all speed grades units min max clock-to-output times t tcktdo the time from the falling transition on the tck pin to data appearing at the tdo pin 1.0 11.0 ns setup times t tditck the time from the se tup of data at the tdi pin to the rising transition at the tck pin all devices and functions e xcept those shown below 7.0 ?ns boundary-scan commands (intest, extest, sample) on xc3s700an and xc3s1400an fpgas 11.0 t tmstck the time from the setup of a logic level at the tm s pin to the rising transition at the tck pin 7.0 ?ns hold times t tcktdi the time from the rising transition at the tck pin to the point when data is last held at the tdi pin all functions except those shown below 0 ?ns configuration commands (cfg_in, isc_program) 2.0 t tcktms the time from the rising transition at the tck pin to the point when a logic level is last held at the tms pin 0 ?ns clock timing t cch the high pulse width at the tck pin a ll functions except isc_dna command 5 ?ns t ccl the low pulse width at the tck pin 5 ?ns t cchdna the high pulse width at the tck pi n during isc_dna command 10 10,000 ns t ccldna the low pulse width at the tck pin 10 10,000 ns f tck frequency of the tck signal all operations on xc3s50an, xc3s200an, and xc3s400an fpgas and for bypass or highz instructions on all fpgas 033mhz all operations on xc3s700an and xc3s1400an fpgas, except for bypass or highz instructions 20 notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 1 0 . 2. for details on jtag see chapter 9 ?jtag configuration mode and boundary-scan? in ug332 spartan-3 generation configuration user guide . dc and switching characteristics w ww.xilinx.com ds557-3 (v3.2) november 19, 2009 70 product specification r revision history the following table shows the revision history for this document. notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all s pecifications are subject to change without notice. products are not designed or intended to be fail-saf e or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. date version revision 02/26/07 1.0 initial release. 08/16/07 2.0 updated for production release of initial device (xc3s200an). timing specifications updated for v1.38 speed files. dc specifications updated with production values. other changes throughout. 08/31/07 2.0.1 updated for production re lease of xc3s1400an. improved t pep for xc3s700an in table 48 . 09/12/07 2.0.2 updated for production release of xc3s700an. 09/24/07 2.1 updated for production release of xc3s400an. updated software version requirements to note that production speed files are available as of service pack 3. removed pcix iostandard due to limited pcix interface support. added note that spi_access (in-system flash) is not currently supported in simulation. 12/12/07 3.0 updated to production status with production release of final fa mily member, xc3s 50an. noted that spi_access simulation is supported in ise 10.1 software. removed dna_retention limit of 10 years in table 17 since number of read cycles is the only unique limit. updated setup, hold, and propagation times for the iob input path to show values by device in table 23 and table 25 . increased sso recommendation for sstl18_ii in table 32 . updated figure 17 and table 59 to show bpi data synchronous to cclk rising edge. updated links. 06/02/08 3.1 improved v ccauxt and v cco2t por minimum in table 7 and updated v cco por levels in figure 13 . clarified power sequencing in note 1 of ta b l e 7 , ta bl e 8 , and figure 13 . added v in to recommended operating conditions in table 10 and added reference to xapp459 , ?eliminating i/o coupling effects when interfacing large-swing single-ended signals to user i/o pins.? reduced typical i ccintq and i ccauxq quiescent current values by 12%-58% in table 12 . noted latest speed f ile v1.39 in ise 10.1 software in ta bl e 1 9 . added reference to sample window in table 24 . changed internal spi interface max frequency to 50 mhz and updated other intern al spi timing parameters to match names and values from speed file in table 47 . restored units column to table 49 . updated cclk output maximum period in table 51 to match minimum frequency in table 52 . added references to user guides. 11/19/09 3.2 updated selected i/o standard dc characteri stics. changed typical quie scent current temperature from ambient to junction. removed references to older software versions. updated column 3 header of table 17 and table 18 . added table note to table 18 . added t iopi and t iopid propagation times in table 25 . updated t iockhz and t iockon synchronous output enable/disable times in table 28 . removed v ref requirements for differential hstl and differential sstl in table 30 . improved diff_sstl18_ii sso limits in table 32 . updated table note 3 in table 39 . removed references to old software versions from table 47 and table 48 . added description of spread spectrum in "spread spectrum" section. updated bpi configuration waveforms in figure 17 . updated t acc equation in table 60 . ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 71 ? copyright 2007?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. pci, pci express, pcie, and pci-x are trademarks of pci-sig. all other trademarks are the property of their re spective owners. introduction this section describes how the various pins on a spartan?-3an fpga connect within the supported component packages, and provides device-specific thermal characteristics. for general information on the pin functions and the package characteristics, see the packaging section of ug331: ? ug331: spartan-3 generation fpga user guide http://www.xilinx.com/ support/documentation/ u ser _ guides/ug331.pdf spartan-3an fpgas are available in pb-free, rohs packages, indicated by a ?g? in the middle of the package code. leaded (pb) packages are available for selected devices, with the same pinout and without the ? g? in the ordering code (see table 5, page 8 ). the pb-free package code can be selected in the software for the pb packages since the pinouts are identical. references to the pb-free package code in this document apply also to the pb package. pin types most pins on a spartan-3an fpga are general-purpose, user-defined i/o pins. there are, however, up to 12 different functional types of pins on spartan-3an fpga packages, as outlined in table 62 . in the package footprint drawings that follow, the individual pins are color-coded according to pin type as in the table. pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 72 product specification r package pins by type each package has three separate voltage supply inputs?vccint, vccaux, and vcco?and a common ground return, gnd. the numbers of pins dedicated to these functions vary by package, as shown in table 63 . a majority of package pins are user-defined i/o or input pins. however, the numbers and characteristics of these i/os depend on the device type and the package in which it is available, as shown in ta bl e 6 4 . the table shows the maximum number of single-ended i/o pins available, assuming that all i/o -, input -, dual -, vref -, and clk -type pins are used as general-purpose i/o. awake is counted here as a dual-purpose i/o pin. likewise, the table shows the maximum number of differential pin-pairs available on the package. finally, the table shows how the total maximum user-i/os are distributed by pin type, including the number of unconnected?n.c.?pins on the device. not all i/o standards are supported on all i/o banks. the left and right banks (i/o banks 1 and 3) support higher output drive current than the top and bottom banks (i/o banks 0 and 2). similarly, true differential output standards, such as lvds, rsds, ppds, minilvds, and tmds, are only supported in the top or bottom banks (i/o banks 0 and 2). inputs are unrestricted. for more details, see the ? using i/o resources ? chapter in ug331 . pwr mgmt control and status pins for the power-saving suspend mode. suspend is a dedicated pin and is powered by vccaux. awake is a dual-purpose pin. unless suspend mode is enabled in the application, awake is ava ilable as a user-i/o pin. suspend, awake jtag dedicated jtag pin - 4 per device. not available as a user-i/o pin. every package has four dedicated jtag pins. these pins are powered by vccaux. tdi, tms, tck, tdo gnd dedicated ground pin. the number of gnd pins depends on the package used. all must be connected. gnd vccaux dedicated auxiliary power supply pin. the number of vccaux pins depends on the package used. the in-system flash memory is powered by vccaux. all must be connected to +3.3v. vccaux vccint dedicated internal core logic power supply pin. the number of vccint pins depends on the package used. all must be connected to +1.2v. vccint vcco along with all the other vcco pins in the same bank, this pin supplies power to the output buffers within the i/o bank and sets the input thres hold voltage for some i/o standards. all must be connected. vcco_# n.c. this package pin is not connected in th is specific device/ package combination. n.c. notes: 1. # = i/o bank number, an integer between 0 and 3. ta bl e 6 2 : types of pins on spartan-3an fpgas (continued) type / color code description pin name(s) in type ta bl e 6 3 : power and ground supply pins by package package vccint vccaux vcco gnd tqg144 4 4 8 13 ftg256 6 4 16 28 fgg400 9 8 22 43 fgg484 15 10 24 53 fgg676 23 14 36 77 ta bl e 6 4 : maximum user i/o by package device package maximum user i/os and input-only maximum input- only maximum differential pairs all possible i/os by type i/o input dual vref clk n.c. xc3s50an tqg144 108 7 50 42 2 26 8 30 0 xc3s200an ftg256 195 35 90 69 21 52 21 32 0 xc3s400an fgg400 311 63 142 155 46 52 26 32 0 xc3s700an fgg484 372 84 165 194 61 52 33 32 3 xc3s1400an fgg676 502 94 227 313 67 52 38 32 17 notes: 1. some vrefs are on input pins. see pinout tables for details. pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 73 r electronic versions of the package pinout tables and foot- prints are available for down load from the xilinx website: http://www.xilinx.com/support/ documentation/data_sheets/ s3a_pin.zip using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. similarly, the ascii-text file is easily parsed by most scripting programs. package overview table 65 shows the five low-cost, space-saving production package styles for the spartan-3an family. each package style is available in an environmentally friendly lead-free (pb-free) option. the pb-free packages include an extra ? g? in the package style name. for example, the standard ?cs484? package becomes ?csg484? when ordered as the pb-free option. leaded (pb) packages are available for selected devices, with the same pinout and without the ? g? in the ordering code; see table 5, page 8 for more information. the mechanical dimensions of the pb and pb-free packages are similar, as shown in the mechanical drawings provided in ta b l e 6 6 . for additional package information, see ug112 : device package user guide . mechanical drawings detailed mechanical drawings for each package type are available from the xilinx websit e at the specified location in table 66 . material declaration data sheets (mdds) are also available on the xilinx web s ite for each package. ta bl e 6 5 : spartan-3an family package options package leads type maximum i/o lead pitch (mm) body area (mm) height (mm) mass (1) (g) tq144/tqg144 144 thin quad flat pa ck (tqfp) 108 0.5 20 x 20 1.60 1.4 ft256/ftg256 256 fine-pitch thin ball grid array (fbga) 195 1.0 17 x 17 1.55 0.9 fg400/fgg400 400 fine-pitch ball grid array (fbga) 311 1.0 21 x 21 2.43 2.2 fg484/fgg484 484 fine-pitch ball grid array (fbga) 372 1.0 23 x 23 2.60 2.2 fg676/fgg676 676 fine-pitch ball grid array (fbga) 502 1.0 27 x 27 2.60 3.4 notes: 1. package mass is 10%. ta b l e 6 6 : xilinx package documentation package drawing mdds tq144 package drawing pk169_tq144 tqg144 pk 126_tqg144 ft256 package drawing pk158_ft256 ftg256 pk 115_ftg256 fg400 package drawing pk182_fg400 fgg400 pk1 08_ fg g400 fg484 package drawing pk183_fg484 fgg484 pk1 10_ fg g484 fg676 package drawing pk155_fg676 fgg676 pk11 1_ fgg 676 pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 74 product specification r package thermal characteristics the power dissipated by an fpga application has implications on package selection and system design. the power consumed by a spartan-3an fpga is reported using either the xpower power estimator or the xpower analyzer calculator integrated in the xilinx? ise? development software. table 67 provides the thermal characteristics for the various spartan-3an fpga packages. this information is also available using the thermal query tool at: ( http://www.xilinx. com/cgi-bin/thermal/thermal.pl ). the junction-to-case thermal resistance ( jc ) indicates the difference between the temperature measured on the package body (case) and the junction temperature per watt of power consumption. the junction-to-board ( jb ) value similarly reports the difference between the board and junction temperature. the junction-to-ambient ( ja ) value reports the temperature difference between the ambient environment and the junction temperature. the ja value is reported at different air velocities, measured in linear feet per minute (lfm). the ?still ai r (0 lfm)? column shows the ja value in a system without a fan. the thermal resistance drops with increasing air flow. ta bl e 6 7 : spartan-3an fpga package thermal characteristics package device junction-to-case ( jc ) junction-to- board ( jb ) junction-to-ambient ( ja ) at different air flows units still air (0 lfm) 250 lfm 500 lfm 750 lfm tqg144 xc3s50an 13.4 32.8 38.9 32.8 32.5 31.7 c/watt ftg256 xc3s200an 7.4 23.3 29.0 23.8 23.0 22.3 c/watt fgg400 xc3s400an 6.2 12.9 22.5 16.7 15.6 15.0 c/watt fgg484 xc3s700an 5.3 11.5 19.4 15.0 13.9 13.4 c/watt fgg676 xc3s1400an 4.3 10.9 17.7 13.7 12.6 12.1 c/watt notes: 1. thermal characteristics are similar for leaded (non-pb-free) packages. pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 75 r tqg144: 144-lead thin quad flat package the xc3s50an is available in the 144-lead thin quad flat package, tqg144. table 68 lists all the package pins. they are sorted by bank number and then by pin name. pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. the xc3s50an does not support the address output pins for the byte-wide peripheral interface (bpi) configuration mode. an electronic version of this package pinout table and footprint diagram is available for download from the xilinx website at w ww.xilinx.com/ support/documentat ion/data_sheets/ s3a_pin.zip . pinout table ta bl e 6 8 : spartan-3an tqg144 pinout bank pin name pin type 0 io_0 p142 i/o 0 io_l01n_0 p111 i/o 0 io_l01p_0 p110 i/o 0 io_l02n_0 p113 i/o 0 io_l02p_0/vref_0 p112 vref 0 io_l03n_0 p117 i/o 0 io_l03p_0 p115 i/o 0 io_l04n_0 p116 i/o 0 io_l04p_0 p114 i/o 0 io_l05n_0 p121 i/o 0 io_l05p_0 p120 i/o 0 io_l06n_0/gclk5 p126 gclk 0 io_l06p_0/gclk4 p124 gclk 0 io_l07n_0/gclk7 p127 gclk 0 io_l07p_0/gclk6 p125 gclk 0 io_l08n_0/gclk9 p131 gclk 0 io_l08p_0/gclk8 p129 gclk 0 io_l09n_0/gclk11 p132 gclk 0 io_l09p_0/gclk10 p130 gclk 0 io_l10n_0 p135 i/o 0 io_l10p_0 p134 i/o 0 io_l11n_0 p139 i/o 0 io_l11p_0 p138 i/o 0 io_l12n_0/pudc_b p143 dual 0 io_l12p_0/vref_0 p141 vref 0 ip_0 p140 input 0 ip_0/vref_0 p123 vref 0 vcco_0 p119 vcco 0 vcco_0 p136 vcco 1io_1 p79 i/o 1 io_l01n_1/ldc2 p78 dual 1 io_l01p_1/hdc p76 dual 1 io_l02n_1/ldc0 p77 dual 1 io_l02p_1/ldc1 p75 dual 1 io_l03n_1 p84 i/o 1 io_l03p_1 p82 i/o 1 io_l04n_1/rhclk1 p85 rhclk 1 io_l04p_1/rhclk0 p83 rhclk 1 io_l05n_1/trdy1/rhclk3 p88 rhclk 1 io_l05p_1/rhclk2 p87 rhclk 1 io_l06n_1/rhclk5 p92 rhclk 1 io_l06p_1/rhclk4 p90 rhclk 1 io_l07n_1/rhclk7 p93 rhclk 1 io_l07p_1/irdy1/rhclk6 p91 rhclk 1 io_l08n_1 p98 i/o 1 io_l08p_1 p96 i/o 1 io_l09n_1 p101 i/o 1 io_l09p_1 p99 i/o 1 io_l10n_1 p104 i/o 1 io_l10p_1 p102 i/o 1 io_l11n_1 p105 i/o 1 io_l11p_1 p103 i/o 1 ip_1/vref_1 p80 vref 1 ip_1/vref_1 p97 vref 1 vcco_1 p86 vcco 1 vcco_1 p95 vcco 2 io_2/mosi/csi_b p62 dual 2 io_l01n_2/m0 p38 dual 2 io_l01p_2/m1 p37 dual 2 io_l02n_2/cso_b p41 dual 2 io_l02p_2/m2 p39 dual 2 io_l03n_2/vs1 p44 dual 2 io_l03p_2/rdwr_b p42 dual 2 io_l04n_2/vs0 p45 dual 2 io_l04p_2/vs2 p43 dual 2 io_l05n_2/d7 p48 dual ta b l e 6 8 : spartan-3an tqg144 pinout (continued) bank pin name pin type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 76 product specification r 2 io_l05p_2 p46 i/o 2 io_l06n_2/d6 p49 dual 2 io_l06p_2 p47 i/o 2 io_l07n_2/d4 p51 dual 2 io_l07p_2/d5 p50 dual 2 io_l08n_2/gclk15 p55 gclk 2 io_l08p_2/gclk14 p54 gclk 2 io_l09n_2/gclk1 p59 gclk 2 io_l09p_2/gclk0 p57 gclk 2 io_l10n_2/gclk3 p60 gclk 2 io_l10p_2/gclk2 p58 gclk 2 io_l11n_2/dout p64 dual 2 io_l11p_2/awake p63 pwr mgmt 2 io_l12n_2/d3 p68 dual 2 io_l12p_2/init_b p67 dual 2 io_l13n_2/d0/din/miso p71 dual 2 io_l13p_2/d2 p69 dual 2 io_l14n_2/cclk p72 dual 2 io_l14p_2/d1 p70 dual 2 ip_2/vref_2 p53 vref 2 vcco_2 p40 vcco 2 vcco_2 p61 vcco 3 io_l01n_3 p6 i/o 3 io_l01p_3 p4 i/o 3 io_l02n_3 p5 i/o 3 io_l02p_3 p3 i/o 3 io_l03n_3 p8 i/o 3 io_l03p_3 p7 i/o 3 io_l04n_3/vref_3 p11 vref 3 io_l04p_3 p10 i/o 3 io_l05n_3/lhclk1 p13 lhclk 3 io_l05p_3/lhclk0 p12 lhclk 3 io_l06n_3/irdy2/lhclk3 p16 lhclk 3 io_l06p_3/lhclk2 p15 lhclk 3 io_l07n_3/lhclk5 p20 lhclk 3 io_l07p_3/lhclk4 p18 lhclk 3 io_l08n_3/lhclk7 p21 lhclk 3 io_l08p_3/trdy2/lhclk6 p19 lhclk 3 io_l09n_3 p25 i/o 3 io_l09p_3 p24 i/o 3 io_l10n_3 p29 i/o ta bl e 6 8 : spartan-3an tqg144 pinout (continued) bank pin name pin type 3 io_l10p_3 p27 i/o 3 io_l11n_3 p30 i/o 3 io_l11p_3 p28 i/o 3 io_l12n_3 p32 i/o 3 io_l12p_3 p31 i/o 3 ip_l13n_3/vref_3 p35 vref 3 ip_l13p_3 p33 input 3 vcco_3 p14 vcco 3 vcco_3 p23 vcco gnd gnd p9 gnd gnd gnd p17 gnd gnd gnd p26 gnd gnd gnd p34 gnd gnd gnd p56 gnd gnd gnd p65 gnd gnd gnd p81 gnd gnd gnd p89 gnd gnd gnd p100 gnd gnd gnd p106 gnd gnd gnd p118 gnd gnd gnd p128 gnd gnd gnd p137 gnd vccaux suspend p74 pwr mgmt vccaux done p73 config vccaux prog_b p144 config vccaux tck p109 jtag vccaux tdi p2 jtag vccaux tdo p107 jtag vccaux tms p1 jtag vccaux vccaux p36 vccaux vccaux vccaux p66 vccaux vccaux vccaux p108 vccaux vccaux vccaux p133 vccaux vccint vccint p22 vccint vccint vccint p52 vccint vccint vccint p94 vccint vccint vccint p122 vccint ta b l e 6 8 : spartan-3an tqg144 pinout (continued) bank pin name pin type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 77 r user i/os by bank table 69 indicates how the 108 available user-i/o pins are distributed between the four i/o banks on the tqg144 package. the awake pin is counted as a dual-purpose i/o. footprint migration differences the xc3s50an fpga is the only spartan-3an device offered in the tqg144 package. the xc3s50an fpga is pin compatible with the spartan-3a xc3s50a fpga in the tq(g)144 package, although the spartan-3a fpga requires an external configuration source. ta bl e 6 9 : user i/os per bank for the xc3s50an in the tqg144 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref clk to p 0 27 14 1 1 3 8 right 1 25 11 0 4 2 8 bottom 2 30 2 0 21 1 6 left 3 26 15 1 0 2 8 total 108 42 2 26 8 30 pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 78 product specification r tqg144 footprint note pin 1 indicator in top-left corner and logo orientation. x-ref target - figure 19 figure 19: xc3s50an fpga in tqg144 package footprint (top view) prog_b io_l12n_0/pudc_b io_0 io_l12p_0/vref_0 ip_0 io_l11n_0 io_l11p_0 gnd vcco_0 io_l10n_0 io_l10p_0 vccaux io_l09n_0/gclk11 io_l0 8 n_0/gclk9 io_l09p_0/gclk10 io_l0 8 p_0/gclk 8 gnd io_l07n_0/gclk7 io_l06n_0/gclk5 io_l07p_0/gclk6 io_l06p_0/gclk4 ip_0/vref_0 vccint io_l05n_0 io_l05p_0 vcco_0 gnd io_l0 3 n_0 io_l04n_0 io_l0 3 p_0 io_l04p_0 io_l02n_0 io_l02p_0/vref_0 io_l01n_0 io_l01p_0 tck 144 14 3 142 141 140 1 3 9 1 38 1 3 7 1 3 6 1 3 5 1 3 4 1 33 1 3 2 1 3 1 1 3 0 129 12 8 127 126 125 124 12 3 122 121 120 119 11 8 117 116 115 114 11 3 112 111 110 109 tm s 1 10 8 vccaux tdi 2 107 td o io_l02p_ 33 x 106 gnd io_l01p_ 3 4 105 io_l11n_1 io_l02n_ 3 5 104 io_l10n_1 io_l01n_ 3 6 10 3 io_l11p_1 io_l0 3 p_ 3 7 102 io_l10p_1 io_l0 3 n_ 38 101 io_l09n_1 gnd 9 100 gnd io_l04p_ 3 10 99 io_l09p_1 io_l04n_ 3 /vref_ 3 11 9 8 io_l0 8 n_1 io_l05p_ 3 /lhclk 0 12 97 ip_1/vref_1 io_l05n_ 3 /lhclk1 1 3 96 io_l0 8 p_1 vcco_ 3 14 95 vcco_1 io_l06p_ 3 /lhclk2 15 94 vccint io_l06n_ 3 /lhclk 3 16 9 3 io_l07n_1/rhclk 7 gnd 17 92 io_l06n_1/rhclk 5 io_l07p_ 3 /lhclk 4 1 8 91 io_l07p_1/rhclk 6 io_l0 8 p_ 3 /lhclk 6 19 90 io_l06p_1/rhclk 4 io_l07n_ 3 /lhclk 5 20 8 9 gnd io_l0 8 n_ 3 /lhclk 7 21 88 io_l05n_1/rhclk 3 vccint 22 8 7 io_l05p_1/rhclk2 vcco_ 3 2 3 8 6 vcco_1 io_l09p_ 3 24 8 5 io_l04n_1/rhclk1 io_l09n_ 3 25 8 4 io_l0 3 n_1 gnd 26 83 io_l04p_1/rhclk 0 io_l10p_ 3 27 8 2 io_l0 3 p_1 io_l11p_ 3 2 8 8 1 gnd io_l10n_ 3 29 8 0 ip_1/vref_1 io_l11n_ 33 0 79 io_1 io_l12p_ 33 1 7 8 io_l01n_1/ldc2 io_l12n_ 33 2 77 io_l02n_1/ldc 0 ip_l1 3 p_ 333 76 i o _l01p_1 / hd c g nd 3 4 75 i o _l02p_1 / ld c 1 ip_l1 3 n_ 3 /vref_ 3 3 5 74 s u s pend v cc aux 3 6 7 3 done 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 49 50 51 52 5 3 54 55 56 57 5 8 59 60 61 62 6 3 64 65 66 67 6 8 69 70 71 72 io_l01p_2/m1 io_l01n_2/m0 io_l02p_2/m2 vcco_2 io_l02n_2/c s o_b io_l0 3 p_2/rdwr_b io_l04p_2/v s 2 io_l0 3 n_2/v s 1 io_l04n_2/v s 0 io_l05p_2 io_l06p_2 io_l05n_2/d7 io_l06n_2/d6 io_l07p_2/d5 io_l07n_2/d4 vccint ip_2/vref_2 io_l0 8 p_2/gclk14 io_l0 8 n_2/gclk15 gnd io_l09p_2/gclk0 io_l10p_2/gclk2 io_l09n_2/gclk1 io_l10n_2/gclk 3 vcco_2 io_2/mo s i/c s i_b io_l11p_2/awake io_l11n_2/dout gnd vccaux io_l12p_2/init_b io_l12n_2/d 3 io_l1 3 p_2/d2 io_l14p_2/d1 io_l1 3 n_2/d0/din/mi s o io_l14n_2/cclk bank 3 bank 1 bank 0 bank 2 d s 529-4_10_0 3 1207 42 i/o: unrestricted, general-purpose user i/o 25 dual: configuration pins, then possible user i/o 8 vref: user i/o or input voltage reference for bank 2 input: unrestricted, general-purpose input pin 30 clk: user i/o, input, or global buffer input 8 vcco: output voltage supply for bank 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 4 vccint: internal core supply voltage (+1.2v) 0 n.c.: not connected 13 gnd: ground 4 vccaux: auxiliary supply voltage 2 suspend: dedicated suspend and dual-purpose awake power management pins pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 79 r ftg256: 256-ball fine-pit ch, thin ball grid array the 256-ball fine-pitch, thin ball grid array package, ftg256, supports the xc3s200an fpgas. table 70 lists all the package pins. they are sorted by bank number and then by pin name of the largest device. pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. figure 20 shows the footprint for the xc3s200an. an electronic version of this package pinout table and footprint diagram is available for download from the xilinx website at www.xilinx.com/support/documentat ion/data_sheets/s3a_pin.zip . pinout table ta bl e 7 0 : spartan-3an ftg256 pinout bank pin name ft256 ball type 0 io_l01n_0 c13 i/o 0 io_l01p_0 d13 i/o 0 io_l02n_0 b14 i/o 0 io_l02p_0/vref_0 b15 vref 0 io_l03n_0 d11 i/o 0 io_l03p_0 c12 i/o 0 io_l04n_0 a13 i/o 0 io_l04p_0 a14 i/o 0 io_l05n_0 a12 i/o 0 io_l05p_0 b12 i/o 0 io_l06n_0/vref_0 e10 vref 0 io_l06p_0 d10 i/o 0 io_l07n_0 a11 i/o 0 io_l07p_0 c11 i/o 0 io_l08n_0 a10 i/o 0 io_l08p_0 b10 i/o 0 io_l09n_0/gclk5 d9 gclk 0 io_l09p_0/gclk4 c10 gclk 0 io_l10n_0/gclk7 a9 gclk 0 io_l10p_0/gclk6 c9 gclk 0 io_l11n_0/gclk9 d8 gclk 0 io_l11p_0/gclk8 c8 gclk 0 io_l12n_0/gclk11 b8 gclk 0 io_l12p_0/gclk10 a8 gclk 0 io_l13n_0 c7 i/o 0 io_l13p_0 a7 i/o 0 io_l14n_0/vref_0 e7 vref 0 io_l14p_0 f8 i/o 0 io_l15n_0 b6 i/o 0 io_l15p_0 a6 i/o 0 io_l16n_0 c6 i/o 0 io_l16p_0 d7 i/o 0 io_l17n_0 c5 i/o 0 io_l17p_0 a5 i/o 0 io_l18n_0 b4 i/o 0 io_l18p_0 a4 i/o 0 io_l19n_0 b3 i/o 0 io_l19p_0 a3 i/o 0 io_l20n_0/pudc_b d5 dual 0 io_l20p_0/vref_0 c4 vref 0 ip_0 d6 input 0 ip_0 d12 input 0 ip_0 e6 input 0 ip_0 f7 input 0 ip_0 f9 input 0 ip_0 f10 input 0 ip_0/vref_0 e9 vref 0 vcco_0 b5 vcco 0 vcco_0 b9 vcco 0 vcco_0 b13 vcco 0 vcco_0 e8 vcco 1 io_l01n_1/ldc2 n14 dual 1 io_l01p_1/hdc n13 dual 1 io_l02n_1/ldc0 p15 dual 1 io_l02p_1/ldc1 r15 dual 1 io_l03n_1/a1 n16 dual 1 io_l03p_1/a0 p16 dual 1 io_l05n_1/vref_1 m14 vref 1 io_l05p_1 m13 i/o 1 io_l06n_1/a3 k13 dual 1 io_l06p_1/a2 l13 dual 1 io_l07n_1/a5 m16 dual 1 io_l07p_1/a4 m15 dual 1 io_l08n_1/a7 l16 dual 1 io_l08p_1/a6 l14 dual 1 io_l10n_1/a9 j13 dual 1 io_l10p_1/a8 j12 dual 1 io_l11n_1/rhclk1 k14 rhclk 1 io_l11p_1/rhclk0 k15 rhclk 1 io_l12n_1/trdy1/rhclk3 j16 rhclk 1 io_l12p_1/rhclk2 k16 rhclk 1 io_l14n_1/rhclk5 h14 rhclk ta b l e 7 0 : spartan-3an ftg256 pinout (continued) bank pin name ft256 ball type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 80 product specification r 1 io_l14p_1/rhclk4 j14 rhclk 1 io_l15n_1/rhclk7 h16 rhclk 1 io_l15p_1/irdy1/rhclk6 h15 rhclk 1 io_l16n_1/a11 f16 dual 1 io_l16p_1/a10 g16 dual 1 io_l17n_1/a13 g14 dual 1 io_l17p_1/a12 h13 dual 1 io_l18n_1/a15 f15 dual 1 io_l18p_1/a14 e16 dual 1 io_l19n_1/a17 f14 dual 1 io_l19p_1/a16 g13 dual 1 io_l20n_1/a19 f13 dual 1 io_l20p_1/a18 e14 dual 1 io_l22n_1/a21 d15 dual 1 io_l22p_1/a20 d16 dual 1 io_l23n_1/a23 d14 dual 1 io_l23p_1/a22 e13 dual 1 io_l24n_1/a25 c15 dual 1 io_l24p_1/a24 c16 dual 1 ip_l04n_1/vref_1 k12 vref 1 ip_l04p_1 k11 input 1 ip_l09n_1 j11 input 1 ip_l09p_1/vref_1 j10 vref 1 ip_l13n_1 h11 input 1 ip_l13p_1 h10 input 1 ip_l21n_1 g11 input 1 ip_l21p_1/vref_1 g12 vref 1 ip_l25n_1 f11 input 1 ip_l25p_1/vref_1 f12 vref 1 vcco_1 e15 vcco 1 vcco_1 h12 vcco 1 vcco_1 j15 vcco 1 vcco_1 n15 vcco 2 io_l01n_2/m0 p4 dual 2 io_l01p_2/m1 n4 dual 2 io_l02n_2/cso_b t2 dual 2 io_l02p_2/m2 r2 dual 2 io_l03n_2/vs2 t3 dual 2 io_l03p_2/rdwr_b r3 dual 2 io_l04n_2/vs0 p5 dual 2 io_l04p_2/vs1 n6 dual 2 io_l05n_2 r5 i/o 2 io_l05p_2 t4 i/o 2 io_l06n_2/d6 t6 dual ta bl e 7 0 : spartan-3an ftg256 pinout (continued) bank pin name ft256 ball type 2 io_l06p_2/d7 t5 dual 2 io_l07n_2 p6 i/o 2 io_l07p_2 n7 i/o 2 io_l08n_2/d4 n8 dual 2 io_l08p_2/d5 p7 dual 2 io_l09n_2/gclk13 t7 gclk 2 io_l09p_2/gclk12 r7 gclk 2 io_l10n_2/gclk15 t8 gclk 2 io_l10p_2/gclk14 p8 gclk 2 io_l11n_2/gclk1 p9 gclk 2 io_l11p_2/gclk0 n9 gclk 2 io_l12n_2/gclk3 t9 gclk 2 io_l12p_2/gclk2 r9 gclk 2 io_l13n_2 m10 i/o 2 io_l13p_2 n10 i/o 2 io_l14n_2/mosi/csi_b p10 dual 2 io_l14p_2 t10 i/o 2 io_l15n_2/dout r11 dual 2 io_l15p_2/ awake t11 pwr mgmt 2 io_l16n_2 n11 i/o 2 io_l16p_2 p11 i/o 2 io_l17n_2/d3 p12 dual 2 io_l17p_2/init_b t12 dual 2 io_l18n_2/d1 r13 dual 2 io_l18p_2/d2 t13 dual 2 io_l19n_2 p13 i/o 2 io_l19p_2 n12 i/o 2 io_l20n_2/cclk r14 dual 2 io_l20p_2/d0/din/miso t14 dual 2 ip_2 l7 input 2 ip_2 l8 input 2 ip_2/vref_2 l9 vref 2 ip_2/vref_2 l10 vref 2 ip_2/vref_2 m7 vref 2 ip_2/vref_2 m8 vref 2 ip_2/vref_2 m11 vref 2 ip_2/vref_2 n5 vref 2 vcco_2 m9 vcco 2 vcco_2 r4 vcco 2 vcco_2 r8 vcco 2 vcco_2 r12 vcco 3 io_l01n_3 c1 i/o 3 io_l01p_3 c2 i/o ta b l e 7 0 : spartan-3an ftg256 pinout (continued) bank pin name ft256 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 81 r 3 io_l02n_3 d3 i/o 3 io_l02p_3 d4 i/o 3 io_l03n_3 e1 i/o 3 io_l03p_3 d1 i/o 3 io_l05n_3 e2 i/o 3 io_l05p_3 e3 i/o 3 io_l07n_3 g4 i/o 3 io_l07p_3 f3 i/o 3 io_l08n_3/vref_3 g1 vref 3 io_l08p_3 f1 i/o 3 io_l09n_3 h4 i/o 3 io_l09p_3 g3 i/o 3 io_l10n_3 h5 i/o 3 io_l10p_3 h6 i/o 3 io_l11n_3/lhclk1 h1 lhclk 3 io_l11p_3/lhclk0 g2 lhclk 3 io_l12n_3/irdy2/lhclk3 j3 lhclk 3 io_l12p_3/lhclk2 h3 lhclk 3 io_l14n_3/lhclk5 j1 lhclk 3 io_l14p_3/lhclk4 j2 lhclk 3 io_l15n_3/lhclk7 k1 lhclk 3 io_l15p_3/trdy2/lhclk6 k3 lhclk 3 io_l16n_3 l2 i/o 3 io_l16p_3/vref_3 l1 vref 3 io_l17n_3 j6 i/o 3 io_l17p_3 j4 i/o 3 io_l18n_3 l3 i/o 3 io_l18p_3 k4 i/o 3 io_l19n_3 l4 i/o 3 io_l19p_3 m3 i/o 3 io_l20n_3 n1 i/o 3 io_l20p_3 m1 i/o 3 io_l22n_3 p1 i/o 3 io_l22p_3 n2 i/o 3 io_l23n_3 p2 i/o 3 io_l23p_3 r1 i/o 3 io_l24n_3 m4 i/o 3 io_l24p_3 n3 i/o 3 ip_l04n_3/vref_3 f4 vref 3 ip_l04p_3 e4 input 3 ip_l06n_3/vref_3 g5 vref 3 ip_l06p_3 g6 input 3 ip_l13n_3 j7 input 3 ip_l13p_3 h7 input ta bl e 7 0 : spartan-3an ftg256 pinout (continued) bank pin name ft256 ball type 3 ip_l21n_3 k6 input 3 ip_l21p_3 k5 input 3 ip_l25n_3/vref_3 l6 vref 3 ip_l25p_3 l5 input 3 vcco_3 d2 vcco 3 vcco_3 h2 vcco 3 vcco_3 j5 vcco 3 vcco_3 m2 vcco gnd gnd a1 gnd gnd gnd a16 gnd gnd gnd b7 gnd gnd gnd b11 gnd gnd gnd c3 gnd gnd gnd c14 gnd gnd gnd e5 gnd gnd gnd e12 gnd gnd gnd f2 gnd gnd gnd f6 gnd gnd gnd g8 gnd gnd gnd g10 gnd gnd gnd g15 gnd gnd gnd h9 gnd gnd gnd j8 gnd gnd gnd k2 gnd gnd gnd k7 gnd gnd gnd k9 gnd gnd gnd l11 gnd gnd gnd l15 gnd gnd gnd m5 gnd gnd gnd m12 gnd gnd gnd p3 gnd gnd gnd p14 gnd gnd gnd r6 gnd gnd gnd r10 gnd gnd gnd t1 gnd gnd gnd t16 gnd vccaux suspend r16 pwr mgmt vccaux done t15 config vccaux prog_b a2 config vccaux tck a15 jtag vccaux tdi b1 jtag vccaux tdo b16 jtag vccaux tms b2 jtag ta b l e 7 0 : spartan-3an ftg256 pinout (continued) bank pin name ft256 ball type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 82 product specification r user i/os by bank table 71 indicates how the available user-i/o pins are distributed between the four i/o banks on the ftg256 package. the awake pin is counted as a dual-purpose i/o. footprint migration differences the xc3s200an fpga is the only spartan-3an device offered in the ftg256 package. the xc3s200an fpga is pin compatible with the spartan-3a xc3s200a fpga in the ft(g)256 package, although the spartan-3a fpga requires an external configuration source. vccaux vccaux e11 vccaux vccaux vccaux f5 vccaux vccaux vccaux l12 vccaux vccaux vccaux m6 vccaux vccint vccint g7 vccint vccint vccint g9 vccint vccint vccint h8 vccint vccint vccint j9 vccint vccint vccint k8 vccint vccint vccint k10 vccint ta bl e 7 0 : spartan-3an ftg256 pinout (continued) bank pin name ft256 ball type ta bl e 7 1 : user i/os per bank on xc3s200an in the ftg256 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref clk to p 0 47 27 6 1 5 8 right 1 50 1 6 30 5 8 bottom 2 48 11 2 21 6 8 left 3 50 30 7 0 5 8 total 195 69 21 52 21 32 pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 83 r ftg256 footprint (xc3s200an) x-ref target - figure 20 figure 20: xc3s200an fpga in ftg256 package footprint (top view) 12 3 4567 8 9 1011121 3 14 15 16 a gnd prog_b i/o l19p_0 i/o l1 8 p_0 i/o l17p_0 i/o l15p_0 i/o l1 3 p_0 i/o l12p_0 gclk10 i/o l10n_0 gclk7 i/o l0 8 n_0 i/o l07n_0 i/o l05n_0 i/o l04n_0 i/o l04p_0 tck gnd b tdi tm s i/o l19n_0 i/o l1 8 n_0 vcco_0 i/o l15n_0 gnd i/o l12n_0 gclk11 vcco_0 i/o l0 8 p_0 gnd i/o l05p_0 vcco_0 i/o l02n_0 i/o l02p_0 vref_0 tdo c i/o l01n_ 3 i/o l01p_ 3 gnd i/o l20p_0 vref_0 i/o l17n_0 i/o l16n_0 i/o l1 3 n_0 i/o l11p_0 gclk 8 i/o l10p_0 gclk6 i/o l09p_0 gclk4 i/o l07p_0 i/o l0 3 p_0 i/o l01n_0 gnd i/o l24n_1 a25 i/o l24p_1 a24 d i/o l0 3 p_ 3 vcco_ 3 i/o l02n_ 3 i/o l02p_ 3 i/o l20n_0 pudc_b input i/o l16p_0 i/o l11n_0 gclk9 i/o l09n_0 gclk5 i/o l06p_0 i/o l0 3 n_0 input i/o l01p_0 i/o l2 3 n_1 a2 3 i/o l22n_1 a21 i/o l22p_1 a20 e i/o l0 3 n_ 3 i/o l05n_ 3 i/o l05p_ 3 input l04p_ 3 gnd input i/o l14n_0 vref_0 vcco_0 input vref_0 i/o l06n_0 vref_0 vccaux gnd i/o l2 3 p_1 a22 i/o l20p_1 a1 8 vcco_1 i/o l1 8 p_1 a14 f i/o l0 8 p_ 3 gnd i/o l07p_ 3 input l04n_ 3 vref_ 3 vccaux gnd input i/o l14p_0 input input input l25n_1 input l25p_1 vref_1 i/o l20n_1 a19 i/o l19n_1 a17 i/o l1 8 n_1 a15 i/o l16n_1 a11 g i/o l0 8 n_ 3 vref_ 3 i/o l11p_ 3 lhclk0 i/o l09p_ 3 i/o l07n_ 3 input l06n_ 3 vref_ 3 input l06p_ 3 vccint gnd vccint gnd input l21n_1 input l21p_1 vref_1 i/o l19p_1 a16 i/o l17n_1 a1 3 gnd i/o l16p_1 a10 h i/o l11n_ 3 lhclk1 vcco_ 3 i/o l12p_ 3 lhclk2 i/o l09n_ 3 i/o l10n_ 3 i/o l10p_ 3 input l1 3 p_ 3 vccint gnd input l1 3 p_1 input l1 3 n_1 vcco_1 i/o l17p_1 a12 i/o l14n_1 rhclk5 i/o l15p_1 irdy1 rhclk6 i/o l15n_1 rhclk7 j i/o l14n_ 3 lhclk5 i/o l14p_ 3 lhclk4 i/o l12n_ 3 irdy2 lhclk 3 i/o l17p_ 3 vcco_ 3 i/o l17n_ 3 input l1 3 n_ 3 gnd vccint input l09p_1 vref_1 input l09n_1 i/o l10p_1 a 8 i/o l10n_1 a9 i/o l14p_1 rhclk4 vcco_1 i/o l12n_1 trdy1 rhclk 3 k i/o l15n_ 3 lhclk7 gnd i/o l15p_ 3 trdy2 lhclk6 i/o l1 8 p_ 3 input l21p_ 3 input l21n_ 3 gnd vccint gnd vccint input l04p_1 input l04n_1 vref_1 i/o l06n_1 a 3 i/o l11n_1 rhclk1 i/o l11p_1 rhclk0 i/o l12p_1 rhclk2 l i/o l16p_ 3 vref_ 3 i/o l16n_ 3 i/o l1 8 n_ 3 i/o l19n_ 3 input l25p_ 3 input l25n_ 3 vref_ 3 input input input vref_2 input vref_2 gnd vccaux i/o l06p_1 a2 i/o l0 8 p_1 a6 gnd i/o l0 8 n_1 a7 m i/o l20p_ 3 vcco_ 3 i/o l19p_ 3 i/o l24n_ 3 gnd vccaux input vref_2 input vref_2 vcco_2 i/o l1 3 n_2 input vref_2 gnd i/o l05p_1 i/o l05n_1 vref_1 i/o l07p_1 a4 i/o l07n_1 a5 n i/o l20n_ 3 i/o l22p_ 3 i/o l24p_ 3 i/o l01p_2 m1 input vref_2 i/o l04p_2 v s 1 i/o l07p_2 i/o l0 8 n_2 d4 i/o l11p_2 gclk0 i/o l1 3 p_2 i/o l16n_2 i/o l19p_2 i/o l01p_1 hdc i/o l01n_1 ldc2 vcco_1 i/o l0 3 n_1 a1 p i/o l22n_ 3 i/o l2 3 n_ 3 gnd i/o l01n_2 m0 i/o l04n_2 v s 0 i/o l07n_2 i/o l0 8 p_2 d5 i/o l10p_2 gclk14 i/o l11n_2 gclk1 i/o l14n_2 mo s i c s i_b i/o l16p_2 i/o l17n_2 d 3 i/o l19n_2 gnd i/o l02n_1 ldc0 i/o l0 3 p_1 a0 r i/o l2 3 p_ 3 i/o l02p_2 m2 i/o l0 3 p_2 rdwr_b vcco_2 i/o l05n_2 gnd i/o l09p_2 gclk12 vcco_2 i/o l12p_2 gclk2 gnd i/o l15n_2 dout vcco_2 i/o l1 8 n_2 d1 i/o l20n_2 cclk i/o l02p_1 ldc1 s u s pend t gnd i/o l02n_2 c s o_b i/o l0 3 n_2 v s 2 i/o l05p_2 i/o l06p_2 d7 i/o l06n_2 d6 i/o l09n_2 gclk1 3 i/o l10n_2 gclk15 i/o l12n_2 gclk 3 i/o l14p_2 i/o l15p_2 awake i/o l17p_2 init_b i/o l1 8 p_2 d2 i/o l20p_2 d0 din/mi s o done gnd bank 2 bank 3 bank 1 bank 0 d s 529-4_06_101106 69 i/o: unrestricted, general-purpose user i/o 51 dual: configuration pins, then possible user i/o 21 vref: user i/o or input voltage reference for bank 2 suspend: dedicated suspend and dual-purpose awake power management pins 21 input: unrestricted, general-purpose input pin 32 clk: user i/o, input, or global buffer input 16 vcco: output voltage supply for bank 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 6 vccint: internal core supply voltage (+1.2v) 0 n.c.: not connected 28 gnd: ground 4 vccaux: auxiliary supply voltage pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 84 product specification r fgg400: 400-ball fine-pitch ball grid array the 400-ball fine-pitch ball grid array, fgg400, supports the xc3s400an fpga as shown in table 72 and figure 21 . table 72 lists all the fgg400 package pins. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and footprint diagram is available for download from the xilinx website at www.xilinx.com/support/documentat ion/data_sheets/s3a_pin.zip . pinout table ta bl e 7 2 : spartan-3an fgg400 pinout bank pin name fg400 ball type 0 io_l01n_0 a18 i/o 0 io_l01p_0 b18 i/o 0 io_l02n_0 c17 i/o 0 io_l02p_0/vref_0 d17 vref 0 io_l03n_0 e15 i/o 0 io_l03p_0 d16 i/o 0 io_l04n_0 a17 i/o 0 io_l04p_0/vref_0 b17 vref 0 io_l05n_0 a16 i/o 0 io_l05p_0 c16 i/o 0 io_l06n_0 c15 i/o 0 io_l06p_0 d15 i/o 0 io_l07n_0 a14 i/o 0 io_l07p_0 c14 i/o 0 io_l08n_0 a15 i/o 0 io_l08p_0 b15 i/o 0 io_l09n_0 f13 i/o 0 io_l09p_0 e13 i/o 0 io_l10n_0/vref_0 c13 vref 0 io_l10p_0 d14 i/o 0 io_l11n_0 c12 i/o 0 io_l11p_0 b13 i/o 0 io_l12n_0 f12 i/o 0 io_l12p_0 d12 i/o 0 io_l13n_0 a12 i/o 0 io_l13p_0 b12 i/o 0 io_l14n_0 c11 i/o 0 io_l14p_0 b11 i/o 0 io_l15n_0/gclk5 e11 gclk 0 io_l15p_0/gclk4 d11 gclk 0 io_l16n_0/gclk7 c10 gclk 0 io_l16p_0/gclk6 a10 gclk 0 io_l17n_0/gclk9 e10 gclk 0 io_l17p_0/gclk8 d10 gclk 0 io_l18n_0/gclk11 a8 gclk 0 io_l18p_0/gclk10 a9 gclk 0 io_l19n_0 c9 i/o 0 io_l19p_0 b9 i/o 0 io_l20n_0 c8 i/o 0 io_l20p_0 b8 i/o 0 io_l21n_0 d8 i/o 0 io_l21p_0 c7 i/o 0 io_l22n_0/vref_0 f9 vref 0 io_l22p_0 e9 i/o 0 io_l23n_0 f8 i/o 0 io_l23p_0 e8 i/o 0 io_l24n_0 a7 i/o 0 io_l24p_0 b7 i/o 0 io_l25n_0 c6 i/o 0 io_l25p_0 a6 i/o 0 io_l26n_0 b5 i/o 0 io_l26p_0 a5 i/o 0 io_l27n_0 f7 i/o 0 io_l27p_0 e7 i/o 0 io_l28n_0 d6 i/o 0 io_l28p_0 c5 i/o 0 io_l29n_0 c4 i/o 0 io_l29p_0 a4 i/o 0 io_l30n_0 b3 i/o 0 io_l30p_0 a3 i/o 0 io_l31n_0 f6 i/o 0 io_l31p_0 e6 i/o 0 io_l32n_0/pudc_b b2 dual 0 io_l32p_0/vref_0 a2 vref 0 ip_0 e14 input ta b l e 7 2 : spartan-3an fgg400 pinout (continued) bank pin name fg400 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 85 r 0 ip_0 f11 input 0 ip_0 f14 input 0 ip_0 g8 input 0 ip_0 g9 input 0 ip_0 g10 input 0 ip_0 g12 input 0 ip_0 g13 input 0 ip_0 h9 input 0 ip_0 h10 input 0 ip_0 h11 input 0 ip_0 h12 input 0 ip_0/vref_0 g11 vref 0 vcco_0 b4 vcco 0 vcco_0 b10 vcco 0 vcco_0 b16 vcco 0 vcco_0 d7 vcco 0 vcco_0 d13 vcco 0 vcco_0 f10 vcco 1 io_l01n_1/ldc2 v20 dual 1 io_l01p_1/hdc w20 dual 1 io_l02n_1/ldc0 u18 dual 1 io_l02p_1/ldc1 v19 dual 1 io_l03n_1/a1 r16 dual 1 io_l03p_1/a0 t17 dual 1 io_l05n_1 t20 i/o 1 io_l05p_1 t18 i/o 1 io_l06n_1 u20 i/o 1 io_l06p_1 u19 i/o 1 io_l07n_1 p17 i/o 1 io_l07p_1 p16 i/o 1 io_l08n_1 r17 i/o 1 io_l08p_1 r18 i/o 1 io_l09n_1 r20 i/o 1 io_l09p_1 r19 i/o 1 io_l10n_1/vref_1 p20 vref 1 io_l10p_1 p18 i/o 1 io_l12n_1/a3 n17 dual 1 io_l12p_1/a2 n15 dual 1 io_l13n_1/a5 n19 dual 1 io_l13p_1/a4 n18 dual ta bl e 7 2 : spartan-3an fgg400 pinout (continued) bank pin name fg400 ball type 1 io_l14n_1/a7 m18 dual 1 io_l14p_1/a6 m17 dual 1 io_l16n_1/a9 l16 dual 1 io_l16p_1/a8 l15 dual 1 io_l17n_1/rhclk1 m20 rhclk 1 io_l17p_1/rhclk0 m19 rhclk 1 io_l18n_1/trdy1/rhclk3 l18 rhclk 1 io_l18p_1/rhclk2 l19 rhclk 1 io_l20n_1/rhclk5 l17 rhclk 1 io_l20p_1/rhclk4 k18 rhclk 1 io_l21n_1/rhclk7 j20 rhclk 1 io_l21p_1/irdy1/rhclk6 k20 rhclk 1 io_l22n_1/a11 j18 dual 1 io_l22p_1/a10 j19 dual 1 io_l24n_1 k16 i/o 1 io_l24p_1 j17 i/o 1 io_l25n_1/a13 h18 dual 1 io_l25p_1/a12 h19 dual 1 io_l26n_1/a15 g20 dual 1 io_l26p_1/a14 h20 dual 1 io_l28n_1 h17 i/o 1 io_l28p_1 g18 i/o 1 io_l29n_1/a17 f19 dual 1 io_l29p_1/a16 f20 dual 1 io_l30n_1/a19 f18 dual 1 io_l30p_1/a18 g17 dual 1 io_l32n_1 e19 i/o 1 io_l32p_1 e20 i/o 1 io_l33n_1 f17 i/o 1 io_l33p_1 e18 i/o 1 io_l34n_1 d18 i/o 1 io_l34p_1 d20 i/o 1 io_l36n_1/a21 f16 dual 1 io_l36p_1/a20 g16 dual 1 io_l37n_1/a23 c19 dual 1 io_l37p_1/a22 c20 dual 1 io_l38n_1/a25 b19 dual 1 io_l38p_1/a24 b20 dual 1 ip_1/vref_1 n14 vref 1 ip_l04n_1/vref_1 p15 vref ta b l e 7 2 : spartan-3an fgg400 pinout (continued) bank pin name fg400 ball type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 86 product specification r 1 ip_l04p_1 p14 input 1 ip_l11n_1/vref_1 m15 vref 1 ip_l11p_1 m16 input 1 ip_l15n_1 m13 input 1 ip_l15p_1/vref_1 m14 vref 1 ip_l19n_1 l13 input 1 ip_l19p_1 l14 input 1 ip_l23n_1 k14 input 1 ip_l23p_1/vref_1 k15 vref 1 ip_l27n_1 j15 input 1 ip_l27p_1 j16 input 1 ip_l31n_1 j13 input 1 ip_l31p_1/vref_1 j14 vref 1 ip_l35n_1 h14 input 1 ip_l35p_1 h15 input 1 ip_l39n_1 g14 input 1 ip_l39p_1/vref_1 g15 vref 1 vcco_1 d19 vcco 1 vcco_1 h16 vcco 1 vcco_1 k19 vcco 1 vcco_1 n16 vcco 1 vcco_1 t19 vcco 2 io_l01n_2/m0 v4 dual 2 io_l01p_2/m1 u4 dual 2 io_l02n_2/cso_b y2 dual 2 io_l02p_2/m2 w3 dual 2 io_l03n_2 w4 i/o 2 io_l03p_2 y3 i/o 2 io_l04n_2 r7 i/o 2 io_l04p_2 t6 i/o 2 io_l05n_2 u5 i/o 2 io_l05p_2 v5 i/o 2 io_l06n_2 u6 i/o 2 io_l06p_2 t7 i/o 2 io_l07n_2/vs2 u7 dual 2 io_l07p_2/rdwr_b t8 dual 2 io_l08n_2 y5 i/o 2 io_l08p_2 y4 i/o 2 io_l09n_2/vs0 w6 dual 2 io_l09p_2/vs1 v6 dual ta bl e 7 2 : spartan-3an fgg400 pinout (continued) bank pin name fg400 ball type 2 io_l10n_2 y7 i/o 2 io_l10p_2 y6 i/o 2 io_l11n_2 u9 i/o 2 io_l11p_2 t9 i/o 2 io_l12n_2/d6 w8 dual 2 io_l12p_2/d7 v7 dual 2 io_l13n_2 v9 i/o 2 io_l13p_2 v8 i/o 2 io_l14n_2/d4 t10 dual 2 io_l14p_2/d5 u10 dual 2 io_l15n_2/gclk13 y9 gclk 2 io_l15p_2/gclk12 w9 gclk 2 io_l16n_2/gclk15 w10 gclk 2 io_l16p_2/gclk14 v10 gclk 2 io_l17n_2/gclk1 v11 gclk 2 io_l17p_2/gclk0 y11 gclk 2 io_l18n_2/gclk3 v12 gclk 2 io_l18p_2/gclk2 u11 gclk 2 io_l19n_2 r12 i/o 2 io_l19p_2 t12 i/o 2 io_l20n_2/mosi/csi_b w12 dual 2 io_l20p_2 y12 i/o 2 io_l21n_2 w13 i/o 2 io_l21p_2 y13 i/o 2 io_l22n_2/dout v13 dual 2 io_l22p_2/awake u13 pwr mgmt 2 io_l23n_2 r13 i/o 2 io_l23p_2 t13 i/o 2 io_l24n_2/d3 w14 dual 2 io_l24p_2/init_b y14 dual 2 io_l25n_2 t14 i/o 2 io_l25p_2 v14 i/o 2 io_l26n_2/d1 v15 dual 2 io_l26p_2/d2 y15 dual 2 io_l27n_2 t15 i/o 2 io_l27p_2 u15 i/o 2 io_l28n_2 w16 i/o 2 io_l28p_2 y16 i/o 2 io_l29n_2 u16 i/o ta b l e 7 2 : spartan-3an fgg400 pinout (continued) bank pin name fg400 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 87 r 2 io_l29p_2 v16 i/o 2 io_l30n_2 y18 i/o 2 io_l30p_2 y17 i/o 2 io_l31n_2 u17 i/o 2 io_l31p_2 v17 i/o 2 io_l32n_2/cclk y19 dual 2 io_l32p_2/d0/din/miso w18 dual 2 ip_2 p9 input 2 ip_2 p12 input 2 ip_2 p13 input 2 ip_2 r8 input 2 ip_2 r10 input 2 ip_2 t11 input 2 ip_2/vref_2 n9 vref 2 ip_2/vref_2 n12 vref 2 ip_2/vref_2 p8 vref 2 ip_2/vref_2 p10 vref 2 ip_2/vref_2 p11 vref 2 ip_2/vref_2 r14 vref 2 vcco_2 r11 vcco 2 vcco_2 u8 vcco 2 vcco_2 u14 vcco 2 vcco_2 w5 vcco 2 vcco_2 w11 vcco 2 vcco_2 w17 vcco 3 io_l01n_3 d3 i/o 3 io_l01p_3 d4 i/o 3 io_l02n_3 c2 i/o 3 io_l02p_3 b1 i/o 3 io_l03n_3 d2 i/o 3 io_l03p_3 c1 i/o 3 io_l05n_3 e1 i/o 3 io_l05p_3 d1 i/o 3 io_l06n_3 g5 i/o 3 io_l06p_3 f4 i/o 3 io_l07n_3 j5 i/o 3 io_l07p_3 j6 i/o 3 io_l08n_3 h4 i/o 3 io_l08p_3 h6 i/o 3 io_l09n_3 g4 i/o ta bl e 7 2 : spartan-3an fgg400 pinout (continued) bank pin name fg400 ball type 3 io_l09p_3 f3 i/o 3 io_l10n_3 f2 i/o 3 io_l10p_3 e3 i/o 3 io_l12n_3 h2 i/o 3 io_l12p_3 g3 i/o 3 io_l13n_3/vref_3 g1 vref 3 io_l13p_3 f1 i/o 3 io_l14n_3 h3 i/o 3 io_l14p_3 j4 i/o 3 io_l16n_3 j2 i/o 3 io_l16p_3 j3 i/o 3 io_l17n_3/lhclk1 k2 lhclk 3 io_l17p_3/lhclk0 j1 lhclk 3 io_l18n_3/irdy2/lhclk3 l3 lhclk 3 io_l18p_3/lhclk2 k3 lhclk 3 io_l20n_3/lhclk5 l5 lhclk 3 io_l20p_3/lhclk4 k4 lhclk 3 io_l21n_3/lhclk7 m1 lhclk 3 io_l21p_3/trdy2/lhclk6 l1 lhclk 3 io_l22n_3 m3 i/o 3 io_l22p_3/vref_3 m2 vref 3 io_l24n_3 m5 i/o 3 io_l24p_3 m4 i/o 3 io_l25n_3 n2 i/o 3 io_l25p_3 n1 i/o 3 io_l26n_3 n4 i/o 3 io_l26p_3 n3 i/o 3 io_l28n_3 r1 i/o 3 io_l28p_3 p1 i/o 3 io_l29n_3 p4 i/o 3 io_l29p_3 p3 i/o 3 io_l30n_3 r3 i/o 3 io_l30p_3 r2 i/o 3 io_l32n_3 t2 i/o 3 io_l32p_3/vref_3 t1 vref 3 io_l33n_3 r4 i/o 3 io_l33p_3 t3 i/o 3 io_l34n_3 u3 i/o 3 io_l34p_3 u1 i/o 3 io_l36n_3 t4 i/o ta b l e 7 2 : spartan-3an fgg400 pinout (continued) bank pin name fg400 ball type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 88 product specification r 3 io_l36p_3 r5 i/o 3 io_l37n_3 v2 i/o 3 io_l37p_3 v1 i/o 3 io_l38n_3 w2 i/o 3 io_l38p_3 w1 i/o 3 ip_3 h7 input 3 ip_l04n_3/vref_3 g6 vref 3 ip_l04p_3 g7 input 3 ip_l11n_3/vref_3 j7 vref 3 ip_l11p_3 j8 input 3 ip_l15n_3 k7 input 3 ip_l15p_3 k8 input 3 ip_l19n_3 k5 input 3 ip_l19p_3 k6 input 3 ip_l23n_3 l6 input 3 ip_l23p_3 l7 input 3 ip_l27n_3 m7 input 3 ip_l27p_3 m8 input 3 ip_l31n_3 n7 input 3 ip_l31p_3 m6 input 3 ip_l35n_3 n6 input 3 ip_l35p_3 p5 input 3 ip_l39n_3/vref_3 p7 vref 3 ip_l39p_3 p6 input 3 vcco_3 e2 vcco 3 vcco_3 h5 vcco 3 vcco_3 l2 vcco 3 vcco_3 n5 vcco 3 vcco_3 u2 vcco gnd gnd a1 gnd gnd gnd a11 gnd gnd gnd a20 gnd gnd gnd b6 gnd gnd gnd b14 gnd gnd gnd c3 gnd gnd gnd c18 gnd gnd gnd d9 gnd gnd gnd e5 gnd gnd gnd e12 gnd gnd gnd f15 gnd ta bl e 7 2 : spartan-3an fgg400 pinout (continued) bank pin name fg400 ball type gnd gnd g2 gnd gnd gnd g19 gnd gnd gnd h8 gnd gnd gnd h13 gnd gnd gnd j9 gnd gnd gnd j11 gnd gnd gnd k1 gnd gnd gnd k10 gnd gnd gnd k12 gnd gnd gnd k17 gnd gnd gnd l4 gnd gnd gnd l9 gnd gnd gnd l11 gnd gnd gnd l20 gnd gnd gnd m10 gnd gnd gnd m12 gnd gnd gnd n8 gnd gnd gnd n11 gnd gnd gnd n13 gnd gnd gnd p2 gnd gnd gnd p19 gnd gnd gnd r6 gnd gnd gnd r9 gnd gnd gnd t16 gnd gnd gnd u12 gnd gnd gnd v3 gnd gnd gnd v18 gnd gnd gnd w7 gnd gnd gnd w15 gnd gnd gnd y1 gnd gnd gnd y10 gnd gnd gnd y20 gnd vccaux suspend r15 pwr mgmt vccaux done w19 config vccaux prog_b d5 config vccaux tck a19 jtag vccaux tdi f5 jtag vccaux tdo e17 jtag vccaux tms e4 jtag ta b l e 7 2 : spartan-3an fgg400 pinout (continued) bank pin name fg400 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 89 r user i/os by bank table 73 indicates how the 311 available user-i/o pins are distributed between the four i/o banks on the fgg400 package. the awake pin is counted as a dual-purpose i/o. footprint migration differences the xc3s400an is the only spartan-3an fpga offered in the fgg400 package. the xc3s400an fpga is pin compatible with the spartan-3a xc3s400a fpga in the fg(g)400 package, although the spartan-3a fpga requires an external configuration source. vccaux vccaux a13 vccaux vccaux vccaux e16 vccaux vccaux vccaux h1 vccaux vccaux vccaux k13 vccaux vccaux vccaux l8 vccaux vccaux vccaux n20 vccaux vccaux vccaux t5 vccaux vccaux vccaux y8 vccaux vccint vccint j10 vccint vccint vccint j12 vccint vccint vccint k9 vccint vccint vccint k11 vccint vccint vccint l10 vccint vccint vccint l12 vccint vccint vccint m9 vccint vccint vccint m11 vccint vccint vccint n10 vccint ta bl e 7 2 : spartan-3an fgg400 pinout (continued) bank pin name fg400 ball type ta bl e 7 3 : user i/os per bank for the xc3s400an in the fgg400 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref clk to p 0 77 50 12 1 6 8 right 1 79 21 12 30 8 8 bottom 2 76 35 6 21 6 8 left 3 79 49 16 0 6 8 total 311 155 46 52 26 32 pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 90 product specification r fg400 footprint x-ref target - figure 21 left half of fg400 package (top view) 155 i/o: unrestricted, general-purpose user i/o 46 input: unrestricted, general-purpose input pin 51 dual: configuration pins, then possible user i/o 26 vref: user i/o or input voltage reference for bank 32 clk: user i/o, input, or clock buffer input 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 2 suspend: dedicated suspend and dual-purpose awake power management pins 43 gnd: ground 22 vcco: output voltage supply for bank 9 vccint: internal core supply voltage (+1.2v) 8 vccaux: auxiliary supply voltage figure 21: fg400 package footprint (top view) 12 3 4567 8 910 a gnd i/o l 3 2p_0 vref_0 i/o l 3 0p_0 i/o l29p_0 i/o l26p_0 i/o l25p_0 i/o l24n_0 i/o l1 8 n_0 gclk11 i/o l1 8 p_0 gclk10 i/o l16p_0 gclk6 b i/o l02p_ 3 i/o l 3 2n_0 pudc_b i/o l 3 0n_0 vcco_0 i/o l26n_0 gnd i/o l24p_0 i/o l20p_0 i/o l19p_0 vcco_0 c i/o l0 3 p_ 3 i/o l02n_ 3 gnd i/o l29n_0 i/o l2 8 p_0 i/o l25n_0 i/o l21p_0 i/o l20n_0 i/o l19n_0 i/o l16n_0 gclk7 d i/o l05p_ 3 i/o l0 3 n_ 3 i/o l01n_ 3 i/o l01p_ 3 prog _b i/o l2 8 n_0 vcco_0 i/o l21n_0 gnd i/o l17p_0 gclk 8 e i/o l05n_ 3 vcco_ 3 i/o l10p_ 3 tm s gnd i/o l 3 1p_0 i/o l27p_0 i/o l2 3 p_0 i/o l22p_0 i/o l17n_0 gclk9 f i/o l1 3 p_ 3 i/o l10n_ 3 i/o l09p_ 3 i/o l06p_ 3 tdi i/o l 3 1n_0 i/o l27n_0 i/o l2 3 n_0 i/o l22n_0 vref_0 vcco_0 g i/o l1 3 n_ 3 vref_ 3 gnd i/o l12p_ 3 i/o l09n_ 3 i/o l06n_ 3 input l04n_ 3 vref_ 3 input l04p_ 3 input input input h vccaux i/o l12n_ 3 i/o l14n_ 3 i/o l0 8 n_ 3 vcco_ 3 i/o l0 8 p_ 3 input gnd input input j i/o l17p_ 3 lhclk0 i/o l16n_ 3 i/o l16p_ 3 i/o l14p_ 3 i/o l07n_ 3 i/o l07p_ 3 input l11n_ 3 vref_ 3 input l11p_ 3 gnd vccint k gnd i/o l17n_ 3 lhclk1 i/o l1 8 p_ 3 lhclk2 i/o l20p_ 3 lhclk4 input l19n_ 3 input l19p_ 3 input l15n_ 3 input l15p_ 3 vccint gnd l i/o l21p_ 3 trdy2 lhclk6 vcco_ 3 i/o l1 8 n_ 3 irdy2 lhclk 3 gnd i/o l20n_ 3 lhclk5 input l2 3 n_ 3 input l2 3 p_ 3 vccaux gnd vccint m i/o l21n_ 3 lhclk7 i/o l22p_ 3 vref_ 3 i/o l22n_ 3 i/o l24p_ 3 i/o l24n_ 3 input l 3 1p_ 3 input l27n_ 3 input l27p_ 3 vccint gnd n i/o l25p_ 3 i/o l25n_ 3 i/o l26p_ 3 i/o l26n_ 3 vcco_ 3 input l 3 5n_ 3 input l 3 1n_ 3 gnd input vref_2 vccint p i/o l2 8 p_ 3 gnd i/o l29p_ 3 i/o l29n_ 3 input l 3 5p_ 3 input l 3 9p_ 3 input l 3 9n_ 3 vref_ 3 input vref_2 input input vref_2 r i/o l2 8 n_ 3 i/o l 3 0p_ 3 i/o l 3 0n_ 3 i/o l 33 n_ 3 i/o l 3 6p_ 3 gnd i/o l04n_2 input gnd input t i/o l 3 2p_ 3 vref_ 3 i/o l 3 2n_ 3 i/o l 33 p_ 3 i/o l 3 6n_ 3 vccaux i/o l04p_2 i/o l06p_2 i/o l07p_2 rdwr_b i/o l11p_2 i/o l14n_2 d4 u i/o l 3 4p_ 3 vcco_ 3 i/o l 3 4n_ 3 i/o l01p_2 m1 i/o l05n_2 i/o l06n_2 i/o l07n_2 v s 2 vcco_2 i/o l11n_2 i/o l14p_2 d5 v i/o l 3 7p_ 3 i/o l 3 7n_ 3 gnd i/o l01n_2 m0 i/o l05p_2 i/o l09p_2 v s 1 i/o l12p_2 d7 i/o l1 3 p_2 i/o l1 3 n_2 i/o l16p_2 gclk14 w i/o l 38 p_ 3 i/o l 38 n_ 3 i/o l02p_2 m2 i/o l0 3 n_2 vcco_2 i/o l09n_2 v s 0 gnd i/o l12n_2 d6 i/o l15p_2 gclk12 i/o l16n_2 gclk15 y gnd i/o l02n_2 c s o_b i/o l0 3 p_2 i/o l0 8 p_2 i/o l0 8 n_2 i/o l10p_2 i/o l10n_2 vccaux i/o l15n_2 gclk1 3 gnd bank 2 bank 3 bank 0 d s 529-4_0 3 _101106 pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 91 r right half of fgg400 package (top view) 11 12 1 3 14 15 16 17 1 8 19 20 gnd i/o l1 3 n_0 vccaux i/o l07n_0 i/o l0 8 n_0 i/o l05n_0 i/o l04n_0 i/o l01n_0 tck gnd a i/o l14p_0 i/o l1 3 p_0 i/o l11p_0 gnd i/o l0 8 p_0 vcco_0 i/o l04p_0 vref_0 i/o l01p_0 i/o l 38 n_1 a25 i/o l 38 p_1 a24 b i/o l14n_0 i/o l11n_0 i/o l10n_0 vref_0 i/o l07p_0 i/o l06n_0 i/o l05p_0 i/o l02n_0 gnd i/o l 3 7n_1 a2 3 i/o l 3 7p_1 a22 c i/o l15p_0 gclk4 i/o l12p_0 vcco_0 i/o l10p_0 i/o l06p_0 i/o l0 3 p_0 i/o l02p_0 vref_0 i/o l 3 4n_1 vcco_1 i/o l 3 4p_1 d i/o l15n_0 gclk5 gnd i/o l09p_0 input i/o l0 3 n_0 vccaux tdo i/o l 33 p_1 i/o l 3 2n_1 i/o l 3 2p_1 e input i/o l12n_0 i/o l09n_0 input gnd i/o l 3 6n_1 a21 i/o l 33 n_1 i/o l 3 0n_1 a19 i/o l29n_1 a17 i/o l29p_1 a16 f input vref_0 input input input l 3 9n_1 input l 3 9p_1 vref_1 i/o l 3 6p_1 a20 i/o l 3 0p_1 a1 8 i/o l2 8 p_1 gnd i/o l26n_1 a15 g input input gnd input l 3 5n_1 input l 3 5p_1 vcco_1 i/o l2 8 n_1 i/o l25n_1 a1 3 i/o l25p_1 a12 i/o l26p_1 a14 h gnd vccint input l 3 1n_1 input l 3 1p_1 vref_1 input l27n_1 input l27p_1 i/o l24p_1 i/o l22n_1 a11 i/o l22p_1 a10 i/o l21n_1 rhclk7 j vccint gnd vccaux input l2 3 n_1 input l2 3 p_1 vref_1 i/o l24n_1 gnd i/o l20p_1 rhclk4 vcco_1 i/o l21p_1 irdy1 rhclk6 k gnd vccint input l19n_1 input l19p_1 i/o l16p_1 a 8 i/o l16n_1 a9 i/o l20n_1 rhclk5 i/o l1 8 n_1 trdy1 rhclk 3 i/o l1 8 p_1 rhclk2 gnd l vccint gnd input l15n_1 input l15p_1 vref_1 input l11n_1 vref_1 input l11p_1 i/o l14p_1 a6 i/o l14n_1 a7 i/o l17p_1 rhclk0 i/o l17n_1 rhclk1 m gnd input vref_2 gnd input vref_1 i/o l12p_1 a2 vcco_1 i/o l12n_1 a 3 i/o l1 3 p_1 a4 i/o l1 3 n_1 a5 vccaux n input vref_2 input input input l04p_1 input l04n_1 vref_1 i/o l07p_1 i/o l07n_1 i/o l10p_1 gnd i/o l10n_1 vref_1 p vcco_2 i/o l19n_2 i/o l2 3 n_2 input vref_2 s u s pend i/o l0 3 n_1 a1 i/o l0 8 n_1 i/o l0 8 p_1 i/o l09p_1 i/o l09n_1 r input i/o l19p_2 i/o l2 3 p_2 i/o l25n_2 i/o l27n_2 gnd i/o l0 3 p_1 a0 i/o l05p_1 vcco_1 i/o l05n_1 t i/o l1 8 p_2 gclk2 gnd i/o l22p_2 awake vcco_2 i/o l27p_2 i/o l29n_2 i/o l 3 1n_2 i/o l02n_1 ldc0 i/o l06p_1 i/o l06n_1 u i/o l17n_2 gclk1 i/o l1 8 n_2 gclk 3 i/o l22n_2 dout i/o l25p_2 i/o l26n_2 d1 i/o l29p_2 i/o l 3 1p_2 gnd i/o l02p_1 ldc1 i/o l01n_1 ldc2 v vcco_2 i/o l20n_2 mo s i c s i_b i/o l21n_2 i/o l24n_2 d 3 gnd i/o l2 8 n_2 vcco_2 i/o l 3 2p_2 d0 din/mi s o done i/o l01p_1 hdc w i/o l17p_2 gclk0 i/o l20p_2 i/o l21p_2 i/o l24p_2 init_b i/o l26p_2 d2 i/o l2 8 p_2 i/o l 3 0p_2 i/o l 3 0n_2 i/o l 3 2n_2 cclk gnd y bank 2 bank 1 bank 0 d s 529-4_04_101106 pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 92 product specification r fgg484: 484-ball fine-pitch ball grid array the 484-ball fine-pitch ball grid array, fgg484, supports the xc3s700an fpga, as described in table 74 . table 74 lists all the fgg484 package pins. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and footprint diagram is available for download from the xilinx website at www.xilinx.com/support/documentat ion/data_sheets/s3a_pin.zip . pinout table ta bl e 7 4 : spartan-3an fgg484 pinout bank pin name fg484 ball type 0 io_l01n_0 d18 i/o 0 io_l01p_0 e17 i/o 0 io_l02n_0 c19 i/o 0 io_l02p_0/vref_0 d19 vref 0 io_l03n_0 a20 i/o 0 io_l03p_0 b20 i/o 0 io_l04n_0 f15 i/o 0 io_l04p_0 e15 i/o 0 io_l05n_0 a18 i/o 0 io_l05p_0 c18 i/o 0 io_l06n_0 a19 i/o 0 io_l06p_0/vref_0 b19 vref 0 io_l07n_0 c17 i/o 0 io_l07p_0 d17 i/o 0 io_l08n_0 c16 i/o 0 io_l08p_0 d16 i/o 0 io_l09n_0 e14 i/o 0 io_l09p_0 c14 i/o 0 io_l10n_0 a17 i/o 0 io_l10p_0 b17 i/o 0 io_l11n_0 c15 i/o 0 io_l11p_0 d15 i/o 0 io_l12n_0/vref_0 a15 vref 0 io_l12p_0 a16 i/o 0 io_l13n_0 a14 i/o 0 io_l13p_0 b15 i/o 0 io_l14n_0 e13 i/o 0 io_l14p_0 f13 i/o 0 io_l15n_0 c13 i/o 0 io_l15p_0 d13 i/o 0 io_l16n_0 a13 i/o 0 io_l16p_0 b13 i/o 0 io_l17n_0/gclk5 e12 gclk 0 io_l17p_0/gclk4 c12 gclk 0 io_l18n_0/gclk7 a11 gclk 0 io_l18p_0/gclk6 a12 gclk 0 io_l19n_0/gclk9 c11 gclk 0 io_l19p_0/gclk8 b11 gclk 0 io_l20n_0/gclk11 e11 gclk 0 io_l20p_0/gclk10 d11 gclk 0 io_l21n_0 c10 i/o 0 io_l21p_0 a10 i/o 0 io_l22n_0 a8 i/o 0 io_l22p_0 a9 i/o 0 io_l23n_0 e10 i/o 0 io_l23p_0 d10 i/o 0 io_l24n_0/vref_0 c9 vref 0 io_l24p_0 b9 i/o 0 io_l25n_0 c8 i/o 0 io_l25p_0 b8 i/o 0 io_l26n_0 a6 i/o 0 io_l26p_0 a7 i/o 0 io_l27n_0 c7 i/o 0 io_l27p_0 d7 i/o 0 io_l28n_0 a5 i/o 0 io_l28p_0 b6 i/o 0 io_l29n_0 d6 i/o 0 io_l29p_0 c6 i/o 0 io_l30n_0 d8 i/o 0 io_l30p_0 e9 i/o 0 io_l31n_0 b4 i/o 0 io_l31p_0 a4 i/o 0 io_l32n_0 d5 i/o 0 io_l32p_0 c5 i/o 0 io_l33n_0 b3 i/o 0 io_l33p_0 a3 i/o 0 io_l34n_0 f8 i/o 0 io_l34p_0 e7 i/o 0 io_l35n_0 e6 i/o 0 io_l35p_0 f7 i/o 0 io_l36n_0/pudc_b a2 dual 0 io_l36p_0/vref_0 b2 vref 0 ip_0 e16 input 0 ip_0 e8 input 0 ip_0 f10 input 0 ip_0 f12 input 0 ip_0 f16 input 0 ip_0 g10 input 0 ip_0 g11 input ta b l e 7 4 : spartan-3an fgg484 pinout (continued) bank pin name fg484 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 93 r 0 ip_0 g12 input 0 ip_0 g13 input 0 ip_0 g14 input 0 ip_0 g15 input 0 ip_0 g16 input 0 ip_0 g7 input 0 ip_0 g9 input 0 ip_0 h10 input 0 ip_0 h13 input 0 ip_0 h14 input 0 ip_0/vref_0 g8 vref 0 ip_0/vref_0 h12 vref 0 ip_0/vref_0 h9 vref 0 vcco_0 b10 vcco 0 vcco_0 b14 vcco 0 vcco_0 b18 vcco 0 vcco_0 b5 vcco 0 vcco_0 f14 vcco 0 vcco_0 f9 vcco 1 io_l01n_1/ldc2 y21 dual 1 io_l01p_1/hdc aa22 dual 1 io_l02n_1/ldc0 w20 dual 1 io_l02p_1/ldc1 w19 dual 1 io_l03n_1/a1 t18 dual 1 io_l03p_1/a0 t17 dual 1 io_l05n_1 w21 i/o 1 io_l05p_1 y22 i/o 1 io_l06n_1 v20 i/o 1 io_l06p_1 v19 i/o 1 io_l07n_1 v22 i/o 1 io_l07p_1 w22 i/o 1 io_l09n_1 u21 i/o 1 io_l09p_1 u22 i/o 1 io_l10n_1 u19 i/o 1 io_l10p_1 u20 i/o 1 io_l11n_1 t22 i/o 1 io_l11p_1 t20 i/o 1 io_l13n_1 t19 i/o 1 io_l13p_1 r20 i/o 1 io_l14n_1 r22 i/o 1 io_l14p_1 r21 i/o 1 io_l15n_1/vref_1 p22 vref 1 io_l15p_1 p20 i/o 1 io_l17n_1/a3 p18 dual 1 io_l17p_1/a2 r19 dual 1 io_l18n_1/a5 n21 dual 1 io_l18p_1/a4 n22 dual 1 io_l19n_1/a7 n19 dual ta bl e 7 4 : spartan-3an fgg484 pinout (continued) bank pin name fg484 ball type 1 io_l19p_1/a6 n20 dual 1 io_l20n_1/a9 n17 dual 1 io_l20p_1/a8 n18 dual 1 io_l21n_1/rhclk1 l22 rhclk 1 io_l21p_1/rhclk0 m22 rhclk 1 io_l22n_1/trdy1/rhclk3 l20 rhclk 1 io_l22p_1/rhclk2 l21 rhclk 1 io_l24n_1/rhclk5 m20 rhclk 1 io_l24p_1/rhclk4 m18 rhclk 1 io_l25n_1/rhclk7 k19 rhclk 1 io_l25p_1/irdy1/rhclk6 k20 rhclk 1 io_l26n_1/a11 j22 dual 1 io_l26p_1/a10 k22 dual 1 io_l28n_1 l19 i/o 1 io_l28p_1 l18 i/o 1 io_l29n_1/a13 j20 dual 1 io_l29p_1/a12 j21 dual 1 io_l30n_1/a15 g22 dual 1 io_l30p_1/a14 h22 dual 1 io_l32n_1 k18 i/o 1 io_l32p_1 k17 i/o 1 io_l33n_1/a17 h20 dual 1 io_l33p_1/a16 h21 dual 1 io_l34n_1/a19 f21 dual 1 io_l34p_1/a18 f22 dual 1 io_l36n_1 g20 i/o 1 io_l36p_1 g19 i/o 1 io_l37n_1 h19 i/o 1 io_l37p_1 j18 i/o 1 io_l38n_1 f20 i/o 1 io_l38p_1 e20 i/o 1 io_l40n_1 f18 i/o 1 io_l40p_1 f19 i/o 1 io_l41n_1 d22 i/o 1 io_l41p_1 e22 i/o 1 io_l42n_1 d20 i/o 1 io_l42p_1 d21 i/o 1 io_l44n_1/a21 c21 dual 1 io_l44p_1/a20 c22 dual 1 io_l45n_1/a23 b21 dual 1 io_l45p_1/a22 b22 dual 1 io_l46n_1/a25 g17 dual 1 io_l46p_1/a24 g18 dual 1 ip_l04n_1/vref_1 r16 vref 1 ip_l04p_1 r15 input 1 ip_l08n_1 p16 input 1 ip_l08p_1 p15 input 1 ip_l12n_1/vref_1 r18 vref ta b l e 7 4 : spartan-3an fgg484 pinout (continued) bank pin name fg484 ball type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 94 product specification r 1 ip_l12p_1 r17 input 1 ip_l16n_1/vref_1 n16 vref 1 ip_l16p_1 n15 input 1 ip_l23n_1 m16 input 1 ip_l23p_1 m17 input 1 ip_l27n_1 l16 input 1 ip_l27p_1/vref_1 m15 vref 1 ip_l31n_1 k16 input 1 ip_l31p_1 l15 input 1 ip_l35n_1 k15 input 1 ip_l35p_1/vref_1 k14 vref 1 ip_l39n_1 h18 input 1 ip_l39p_1 h17 input 1 ip_l43n_1/vref_1 j15 vref 1 ip_l43p_1 j16 input 1 ip_l47n_1 h15 input 1 ip_l47p_1/vref_1 h16 vref 1 vcco_1 e21 vcco 1 vcco_1 j17 vcco 1 vcco_1 k21 vcco 1 vcco_1 p17 vcco 1 vcco_1 p21 vcco 1 vcco_1 v21 vcco 2 io_l01n_2/m0 w5 dual 2 io_l01p_2/m1 v6 dual 2 io_l02n_2/cso_b y4 dual 2 io_l02p_2/m2 w4 dual 2 io_l03n_2 aa3 i/o 2 io_l03p_2 ab2 i/o 2 io_l04n_2 aa4 i/o 2 io_l04p_2 ab3 i/o 2 io_l05n_2 y5 i/o 2 io_l05p_2 w6 i/o 2 io_l06n_2 ab5 i/o 2 io_l06p_2 ab4 i/o 2 io_l07n_2 y6 i/o 2 io_l07p_2 w7 i/o 2 io_l08n_2 ab6 i/o 2 io_l08p_2 aa6 i/o 2 io_l09n_2/vs2 w9 dual 2 io_l09p_2/rdwr_b v9 dual 2 io_l10n_2 ab7 i/o 2 io_l10p_2 y7 i/o 2 io_l11n_2/vs0 y8 dual 2 io_l11p_2/vs1 w8 dual 2 io_l12n_2 ab8 i/o 2 io_l12p_2 aa8 i/o 2 io_l13n_2 y10 i/o ta bl e 7 4 : spartan-3an fgg484 pinout (continued) bank pin name fg484 ball type 2 io_l13p_2 v10 i/o 2 io_l14n_2/d6 ab9 dual 2 io_l14p_2/d7 y9 dual 2 io_l15n_2 ab10 i/o 2 io_l15p_2 aa10 i/o 2 io_l16n_2/d4 ab11 dual 2 io_l16p_2/d5 y11 dual 2 io_l17n_2/gclk13 v11 gclk 2 io_l17p_2/gclk12 u11 gclk 2 io_l18n_2/gclk15 y12 gclk 2 io_l18p_2/gclk14 w12 gclk 2 io_l19n_2/gclk1 ab12 gclk 2 io_l19p_2/gclk0 aa12 gclk 2 io_l20n_2/gclk3 u12 gclk 2 io_l20p_2/gclk2 v12 gclk 2 io_l21n_2 y13 i/o 2 io_l21p_2 ab13 i/o 2 io_l22n_2/mosi/csi_b ab14 dual 2 io_l22p_2 aa14 i/o 2 io_l23n_2 y14 i/o 2 io_l23p_2 w13 i/o 2 io_l24n_2/ dout aa15 dual 2 io_l24p_2/awake ab15 pwr mgmt 2 io_l25n_2 y15 i/o 2 io_l25p_2 w15 i/o 2 io_l26n_2/d3 u13 dual 2 io_l26p_2/init_b v13 dual 2 io_l27n_2 y16 i/o 2 io_l27p_2 ab16 i/o 2 io_l28n_2/d1 y17 dual 2 io_l28p_2/d2 aa17 dual 2 io_l29n_2 ab18 i/o 2 io_l29p_2 ab17 i/o 2 io_l30n_2 v15 i/o 2 io_l30p_2 v14 i/o 2 io_l31n_2 v16 i/o 2 io_l31p_2 w16 i/o 2 io_l32n_2 aa19 i/o 2 io_l32p_2 ab19 i/o 2 io_l33n_2 v17 i/o 2 io_l33p_2 w18 i/o 2 io_l34n_2 w17 i/o 2 io_l34p_2 y18 i/o 2 io_l35n_2 aa21 i/o 2 io_l35p_2 ab21 i/o 2 io_l36n_2/cclk aa20 dual ta b l e 7 4 : spartan-3an fgg484 pinout (continued) bank pin name fg484 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 95 r 2 io_l36p_2/d0/din/miso ab20 dual 2 ip_2 p12 input 2 ip_2 r10 input 2 ip_2 r11 input 2 ip_2 r9 input 2 ip_2 t13 input 2 ip_2 t14 input 2 ip_2 t9 input 2 ip_2 u10 input 2 ip_2 u15 input 2 n.c. u16 n.c. 2 n.c. u7 n.c. 2 ip_2 u8 input 2 ip_2 v7 input 2 ip_2/vref_2 r12 vref 2 ip_2/vref_2 r13 vref 2 ip_2/vref_2 r14 vref 2 ip_2/vref_2 t10 vref 2 ip_2/vref_2 t11 vref 2 ip_2/vref_2 t15 vref 2 ip_2/vref_2 t16 vref 2 ip_2/vref_2 t7 vref 2 n.c. t8 n.c. 2 ip_2/vref_2 v8 vref 2 vcco_2 aa13 vcco 2 vcco_2 aa18 vcco 2 vcco_2 aa5 vcco 2 vcco_2 aa9 vcco 2 vcco_2 u14 vcco 2 vcco_2 u9 vcco 3 io_l01n_3 d2 i/o 3 io_l01p_3 c1 i/o 3 io_l02n_3 c2 i/o 3 io_l02p_3 b1 i/o 3 io_l03n_3 e4 i/o 3 io_l03p_3 d3 i/o 3 io_l05n_3 g5 i/o 3 io_l05p_3 g6 i/o 3 io_l06n_3 e1 i/o 3 io_l06p_3 d1 i/o 3 io_l07n_3 e3 i/o 3 io_l07p_3 f4 i/o 3 io_l08n_3 g4 i/o 3 io_l08p_3 f3 i/o 3 io_l09n_3 h6 i/o 3 io_l09p_3 h5 i/o 3 io_l10n_3 j5 i/o 3 io_l10p_3 k6 i/o ta bl e 7 4 : spartan-3an fgg484 pinout (continued) bank pin name fg484 ball type 3 io_l12n_3 f1 i/o 3 io_l12p_3 f2 i/o 3 io_l13n_3 g1 i/o 3 io_l13p_3 g3 i/o 3 io_l14n_3 h3 i/o 3 io_l14p_3 h4 i/o 3 io_l16n_3 h1 i/o 3 io_l16p_3 h2 i/o 3 io_l17n_3/vref_3 j1 vref 3 io_l17p_3 j3 i/o 3 io_l18n_3 k4 i/o 3 io_l18p_3 k5 i/o 3 io_l20n_3 k2 i/o 3 io_l20p_3 k3 i/o 3 io_l21n_3/lhclk1 l3 lhclk 3 io_l21p_3/lhclk0 l5 lhclk 3 io_l22n_3/irdy2/lhclk3 l1 lhclk 3 io_l22p_3/lhclk2 k1 lhclk 3 io_l24n_3/lhclk5 m2 lhclk 3 io_l24p_3/lhclk4 m1 lhclk 3 io_l25n_3/lhclk7 m4 lhclk 3 io_l25p_3/trdy2/lhclk6 m3 lhclk 3 io_l26n_3 n3 i/o 3 io_l26p_3/vref_3 n1 vref 3 io_l28n_3 p2 i/o 3 io_l28p_3 p1 i/o 3 io_l29n_3 p5 i/o 3 io_l29p_3 p3 i/o 3 io_l30n_3 n4 i/o 3 io_l30p_3 m5 i/o 3 io_l32n_3 r2 i/o 3 io_l32p_3 r1 i/o 3 io_l33n_3 r4 i/o 3 io_l33p_3 r3 i/o 3 io_l34n_3 t4 i/o 3 io_l34p_3 r5 i/o 3 io_l36n_3 t3 i/o 3 io_l36p_3/vref_3 t1 vref 3 io_l37n_3 u2 i/o 3 io_l37p_3 u1 i/o 3 io_l38n_3 v3 i/o 3 io_l38p_3 v1 i/o 3 io_l40n_3 u5 i/o 3 io_l40p_3 t5 i/o 3 io_l41n_3 u4 i/o 3 io_l41p_3 u3 i/o 3 io_l42n_3 w2 i/o 3 io_l42p_3 w1 i/o ta b l e 7 4 : spartan-3an fgg484 pinout (continued) bank pin name fg484 ball type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 96 product specification r 3 io_l43n_3 w3 i/o 3 io_l43p_3 v4 i/o 3 io_l44n_3 y2 i/o 3 io_l44p_3 y1 i/o 3 io_l45n_3 aa2 i/o 3 io_l45p_3 aa1 i/o 3 ip_3/vref_3 j8 vref 3 ip_3/vref_3 r6 vref 3 ip_l04n_3/vref_3 h7 vref 3 ip_l04p_3 h8 input 3 ip_l11n_3 k8 input 3 ip_l11p_3 j7 input 3 ip_l15n_3/vref_3 l8 vref 3 ip_l15p_3 k7 input 3 ip_l19n_3 m8 input 3 ip_l19p_3 l7 input 3 ip_l23n_3 m6 input 3 ip_l23p_3 m7 input 3 ip_l27n_3 n9 input 3 ip_l27p_3 n8 input 3 ip_l31n_3 n5 input 3 ip_l31p_3 n6 input 3 ip_l35n_3 p8 input 3 ip_l35p_3 n7 input 3 ip_l39n_3 r8 input 3 ip_l39p_3 p7 input 3 ip_l46n_3/vref_3 t6 vref 3 ip_l46p_3 r7 input 3 vcco_3 e2 vcco 3 vcco_3 j2 vcco 3 vcco_3 j6 vcco 3 vcco_3 n2 vcco 3 vcco_3 p6 vcco 3 vcco_3 v2 vcco gnd gnd a1 gnd gnd gnd a22 gnd gnd gnd aa11 gnd gnd gnd aa16 gnd gnd gnd aa7 gnd gnd gnd ab1 gnd gnd gnd ab22 gnd gnd gnd b12 gnd gnd gnd b16 gnd gnd gnd b7 gnd gnd gnd c20 gnd gnd gnd c3 gnd gnd gnd d14 gnd gnd gnd d9 gnd ta bl e 7 4 : spartan-3an fgg484 pinout (continued) bank pin name fg484 ball type gnd gnd f11 gnd gnd gnd f17 gnd gnd gnd f6 gnd gnd gnd g2 gnd gnd gnd g21 gnd gnd gnd j11 gnd gnd gnd j13 gnd gnd gnd j14 gnd gnd gnd j19 gnd gnd gnd j4 gnd gnd gnd j9 gnd gnd gnd k10 gnd gnd gnd k12 gnd gnd gnd l11 gnd gnd gnd l13 gnd gnd gnd l17 gnd gnd gnd l2 gnd gnd gnd l6 gnd gnd gnd l9 gnd gnd gnd m10 gnd gnd gnd m12 gnd gnd gnd m14 gnd gnd gnd m21 gnd gnd gnd n11 gnd gnd gnd n13 gnd gnd gnd p10 gnd gnd gnd p14 gnd gnd gnd p19 gnd gnd gnd p4 gnd gnd gnd p9 gnd gnd gnd t12 gnd gnd gnd t2 gnd gnd gnd t21 gnd gnd gnd u17 gnd gnd gnd u6 gnd gnd gnd w10 gnd gnd gnd w14 gnd gnd gnd y20 gnd gnd gnd y3 gnd vccaux suspend u18 pwr mgmt vccaux done y19 config vccaux prog_b c4 config vccaux tck a21 jtag vccaux tdi f5 jtag vccaux tdo e19 jtag vccaux tms d4 jtag vccaux vccaux d12 vccaux ta b l e 7 4 : spartan-3an fgg484 pinout (continued) bank pin name fg484 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 97 r user i/os by bank table 75 indicates how the user-i/o pins are distributed between the four i/o banks on the fgg484 package. the awake pin is counted as a dual-purpose i/o. footprint migration differences the xc3s700an is the only spartan-3an fpga offered in the fgg484 package. the xc3s700an fpga is pin compatible with the spartan-3a xc3s700a fpga in the fg(g)484 package, although the spartan-3a fpga requires an external configuration source. vccaux vccaux e18 vccaux vccaux vccaux e5 vccaux vccaux vccaux h11 vccaux vccaux vccaux l4 vccaux vccaux vccaux m19 vccaux vccaux vccaux p11 vccaux vccaux vccaux v18 vccaux vccaux vccaux v5 vccaux vccaux vccaux w11 vccaux vccint vccint j10 vccint vccint vccint j12 vccint vccint vccint k11 vccint vccint vccint k13 vccint vccint vccint k9 vccint vccint vccint l10 vccint vccint vccint l12 vccint vccint vccint l14 vccint vccint vccint m11 vccint vccint vccint m13 vccint vccint vccint m9 vccint vccint vccint n10 vccint vccint vccint n12 vccint vccint vccint n14 vccint vccint vccint p13 vccint ta bl e 7 4 : spartan-3an fgg484 pinout (continued) bank pin name fg484 ball type ta bl e 7 5 : user i/os per bank for the xc3s700an in the fgg484 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref clk to p 0 92 58 17 1 8 8 right 1 94 33 15 30 8 8 bottom 2 92 43 11 21 9 8 left 3 94 61 17 0 8 8 total 372 195 60 52 33 32 pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 98 product specification r fg484 footprint x-ref target - figure 22 left half of fg484 package (top view) 195 i/o: unrestricted, general-purpose user i/o 60 input: unrestricted, general-purpose input pin 51 dual: configuration pins, then possible user i/o 33 vref: user i/o or input voltage reference for bank 32 clk: user i/o, input, or clock buffer input 2 suspend: dedicated suspend and dual-purpose awake power management pins 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 53 gnd: ground 24 vcco: output voltage supply for bank 15 vccint: internal core supply voltage (+1.2v) 10 vccaux: auxiliary supply voltage (+3.3v) 3 n.c.: not connected figure 22: fg484 package footprint (top view) 1234567891011 a gnd i/o l36n_0 pudc_b i/o l33p_0 i/o l31p_0 i/o l28n_0 i/o l26n_0 i/o l26p_0 i/o l22n_0 i/o l22p_0 i/o l21p_0 i/o l18n_0 gclk7 b i/o l02p_3 i/o l36p_0 vref_0 i/o l33n_0 i/o l31n_0 vcco_0 i/o l28p_0 gnd i/o l25p_0 i/o l24p_0 vcco_0 i/o l19p_0 gclk8 c i/o l01p_3 i/o l02n_3 gnd prog_b i/o l32p_0 i/o l29p_0 i/o l27n_0 i/o l25n_0 i/o l24n_0 vref_0 i/o l21n_0 i/o l19n_0 gclk9 d i/o l06p_3 i/o l01n_3 i/o l03p_3 tms i/o l32n_0 i/o l29n_0 i/o l27p_0 i/o l30n_0 gnd i/o l23p_0 i/o l20p_0 gclk10 e i/o l06n_3 vcco_3 i/o l07n_3 i/o l03n_3 vccaux i/o l35n_0 i/o l34p_0 input i/o l30p_0 i/o l23n_0 i/o l20n_0 gclk11 f i/o l12n_3 i/o l12p_3 i/o l08p_3 i/o l07p_3 tdi gnd i/o l35p_0 i/o l34n_0 vcco_0 input gnd g i/o l13n_3 gnd i/o l13p_3 i/o l08n_3 i/o l05n_3 i/o l05p_3 input input vref_0 input input input h i/o l16n_3 i/o l16p_3 i/o l14n_3 i/o l14p_3 i/o l09p_3 i/o l09n_3 input l04n_3 vref_3 input l04p_3 input vref_0 input vccaux j i/o l17n_3 vref_3 vcco_3 i/o l17p_3 gnd i/o l10n_3 vcco_3 input l11p_3 input vref_3 gnd vccint gnd k i/o l22p_3 lhclk2 i/o l20n_3 i/o l20p_3 i/o l18n_3 i/o l18p_3 i/o l10p_3 input l15p_3 input l11n_3 vccint gnd vccint l i/o l22n_3 irdy2 lhclk3 gnd i/o l21n_3 lhclk1 vccaux i/o l21p_3 lhclk0 gnd input l19p_3 input l15n_3 vref_3 gnd vccint gnd m i/o l24p_3 lhclk4 i/o l24n_3 lhclk5 i/o l25p_3 trdy2 lhclk 6 i/o l25n_3 lhclk7 i/o l30p_3 input l23n_3 input l23p_3 input l19n_3 vccint gnd vccint n i/o l26p_3 vref_3 vcco_3 i/o l26n_3 i/o l30n_3 input l31n_3 input l31p_3 input l35p_3 input l27p_3 input l27n_3 vccint gnd p i/o l28p_3 i/o l28n_3 i/o l29p_3 gnd i/o l29n_3 vcco_3 input l39p_3 input l35n_3 gnd gnd vccaux r i/o l32p_3 i/o l32n_3 i/o l33p_3 i/o l33n_3 i/o l34p_3 input vref_3 input l46p_3 input l39n_3 input input input t i/o l36p_3 vref_3 gnd i/o l36n_3 i/o l34n_3 i/o l40p_3 input l46n_3 vref_3 input vref_2 n.c. input input vref_2 input vref_2 u i/o l37p_3 i/o l37n_3 i/o l41p_3 i/o l41n_3 i/o l40n_3 gnd n.c. input vcco_2 input i/o l17p_2 gclk12 v i/o l38p_3 vcco_3 i/o l38n_3 i/o l43p_3 vccaux i/o l01p_2 m1 input input vref_2 i/o l09p_2 rdwr_b i/o l13p_2 i/o l17n_2 gclk13 w i/o l42p_3 i/o l42n_3 i/o l43n_3 i/o l02p_2 m2 i/o l01n_2 m0 i/o l05p_2 i/o l07p_2 i/o l11p_2 vs1 i/o l09n_2 vs2 gnd vccaux y i/o l44p_3 i/o l44n_3 gnd i/o l02n_2 cso_b i/o l05n_2 i/o l07n_2 i/o l10p_2 i/o l11n_2 vs0 i/o l14p_2 d7 i/o l13n_2 i/o l16p_2 d5 a a i/o l45p_3 i/o l45n_3 i/o l03n_2 i/o l04n_2 vcco_2 i/o l08p_2 gnd i/o l12p_2 vcco_2 i/o l15p_2 gnd a b gnd i/o l03p_2 i/o l04p_2 i/o l06p_2 i/o l06n_2 i/o l08n_2 i/o l10n_2 i/o l12n_2 i/o l14n_2 d6 i/o l15n_2 i/o l16n_2 d4 bank 3 bank 2 bank 0 ds557-4_01_032709 pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 99 r right half of fgg484 package (top view) 12 13 14 15 16 17 18 19 20 21 22 i/o l18p_0 gclk6 i/o l16n_0 i/o l13n_0 i/o l12n_0 vref_0 i/o l12p_0 i/o l10n_0 i/o l05n_0 i/o l06n_0 i/o l03n_0 tck gnd a gnd i/o l16p_0 vcco_0 i/o l13p_0 gnd i/o l10p_0 vcco_0 i/o l06p_0 vref_0 i/o l03p_0 i/o l45n_1 a23 i/o l45p_1 a22 b i/o l17p_0 gclk4 i/o l15n_0 i/o l09p_0 i/o l11n_0 i/o l08n_0 i/o l07n_0 i/o l05p_0 i/o l02n_0 gnd i/o l44n_1 a21 i/o l44p_1 a20 c vccaux i/o l15p_0 gnd i/o l11p_0 i/o l08p_0 i/o l07p_0 i/o l01n_0 i/o l02p_0 vref_0 i/o l42n_1 i/o l42p_1 i/o l41n_1 d i/o l17n_0 gclk5 i/o l14n_0 i/o l09n_0 i/o l04p_0 input i/o l01p_0 vccaux tdo i/o l38p_1 vcco_1 i/o l41p_1 e input i/o l14p_0 vcco_0 i/o l04n_0 input gnd i/o l40n_1 i/o l40p_1 i/o l38n_1 i/o l34n_1 a19 i/o l34p_1 a18 f input input input input input i/o l46n_1 a25 i/o l46p_1 a24 i/o l36p_1 i/o l36n_1 gnd i/o l30n_1 a15 g input vref_0 input input input l47n_1 input l47p_1 vref_1 input l39p_1 input l39n_1 i/o l37n_1 i/o l33n_1 a17 i/o l33p_1 a16 i/o l30p_1 a14 h vccint gnd gnd input l43n_1 vref_1 input l43p_1 vcco_1 i/o l37p_1 gnd i/o l29n_1 a13 i/o l29p_1 a12 i/o l26n_1 a11 j gnd vccint input l35p_1 vref_1 input l35n_1 input l31n_1 i/o l32p_1 i/o l32n_1 i/o l25n_1 rhclk7 i/o l25p_1 irdy1 rhclk6 vcco_1 i/o l26p_1 a10 k vccint gnd vccint input l31p_1 input l27n_1 gnd i/o l28p_1 i/o l28n_1 i/o l22n_1 trdy1 rhclk3 i/o l22p_1 rhclk2 i/o l21n_1 rhclk1 l gnd vccint gnd input l27p_1 vref_1 input l23n_1 input l23p_1 i/o l24p_1 rhclk4 vccaux i/o l24n_1 rhclk5 gnd i/o l21p_1 rhclk0 m vccint gnd vccint input l16p_1 input l16n_1 vref_1 i/o l20n_1 a9 i/o l20p_1 a8 i/o l19n_1 a7 i/o l19p_1 a6 i/o l18n_1 a5 i/o l18p_1 a4 n input vccint gnd input l08p_1 input l08n_1 vcco_1 i/o l17n_1 a3 gnd i/o l15p_1 vcco_1 i/o l15n_1 vref_1 p input vref_2 input vref_2 input vref_2 input l04p_1 input l04n_1 vref_1 input l12p_1 input l12n_1 vref_1 i/o l17p_1 a2 i/o l13p_1 i/o l14p_1 i/o l14n_1 r gnd input input input vref_2 input vref_2 i/o l03p_1 a0 i/o l03n_1 a1 i/o l13n_1 i/o l11p_1 gnd i/o l11n_1 t i/o l20n_2 gclk3 i/o l26n_2 d3 vcco_2 input n.c. gnd suspend i/o l10n_1 i/o l10p_1 i/o l09n_1 i/o l09p_1 u i/o l20p_2 gclk2 i/o l26p_2 init_b i/o l30p_2 i/o l30n_2 i/o l31n_2 i/o l33n_2 vccaux i/o l06p_1 i/o l06n_1 vcco_1 i/o l07n_1 v i/o l18p_2 gclk14 i/o l23p_2 gnd i/o l25p_2 i/o l31p_2 i/o l34n_2 i/o l33p_2 i/o l02p_1 ldc1 i/o l02n_1 ldc0 i/o l05n_1 i/o l07p_1 w i/o l18n_2 gclk15 i/o l21n_2 i/o l23n_2 i/o l25n_2 i/o l27n_2 i/o l28n_2 d1 i/o l34p_2 done gnd i/o l01n_1 ldc2 i/o l05p_1 y i/o l19p_2 gclk0 vcco_2 i/o l22p_2 i/o l24n_2 dout gnd i/o l28p_2 d2 vcco_2 i/o l32n_2 i/o l36n_2 cclk i/o l35n_2 i/o l01p_1 hdc a a i/o l19n_2 gclk1 i/o l21p_2 i/o l22n_2 mosi csi _b i/o l24p_2 awake i/o l27p_2 i/o l29p_2 i/o l29n_2 i/o l32p_2 i/o l36p_2 d0 din/miso i/o l35p_2 gnd a b bank 1 bank 2 bank 0 ds557-4_02_032709 pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 100 product specification r fgg676: 676-ball fine-pitch ball grid array the 676-ball fine-pitch ball grid array, fgg676, supports the xc3s1400an fpga. table 76 lists all the fgg676 package pins. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and footprint diagram is available for download from the xilinx website at www.xilinx.com/support/documentat ion/data_sheets/s3a_pin.zip . pinout table ta bl e 7 6 : spartan-3an fgg676 pinout bank pin name fg676 ball type 0 io_l01n_0 f20 i/o 0 io_l01p_0 g20 i/o 0 io_l02n_0 f19 i/o 0 io_l02p_0/vref_0 g19 vref 0 io_l05n_0 c22 i/o 0 io_l05p_0 d22 i/o 0 io_l06n_0 c23 i/o 0 io_l06p_0 d23 i/o 0 io_l07n_0 a22 i/o 0 io_l07p_0 b23 i/o 0 io_l08n_0 g17 i/o 0 io_l08p_0 h17 i/o 0 io_l09n_0 b21 i/o 0 io_l09p_0 c21 i/o 0 io_l10n_0 d21 i/o 0 io_l10p_0 e21 i/o 0 io_l11n_0 c20 i/o 0 io_l11p_0 d20 i/o 0 io_l12n_0 k16 i/o 0 io_l12p_0 j16 i/o 0 io_l13n_0 e17 i/o 0 io_l13p_0 f17 i/o 0 io_l14n_0 a20 i/o 0 io_l14p_0/vref_0 b20 vref 0 io_l15n_0 a19 i/o 0 io_l15p_0 b19 i/o 0 io_l16n_0 h15 i/o 0 io_l16p_0 g15 i/o 0 io_l17n_0 c18 i/o 0 io_l17p_0 d18 i/o 0 io_l18n_0 a18 i/o 0 io_l18p_0 b18 i/o 0 io_l19n_0 b17 i/o 0 io_l19p_0 c17 i/o 0 io_l20n_0/vref_0 e15 vref 0 io_l20p_0 f15 i/o 0 io_l21n_0 c16 i/o 0 io_l21p_0 d17 i/o 0 io_l22n_0 c15 i/o 0 io_l22p_0 d16 i/o 0 io_l23n_0 a15 i/o 0 io_l23p_0 b15 i/o 0 io_l24n_0 f14 i/o 0 io_l24p_0 e14 i/o 0 io_l25n_0/gclk5 j14 gclk 0 io_l25p_0/gclk4 k14 gclk 0 io_l26n_0/gclk7 a14 gclk 0 io_l26p_0/gclk6 b14 gclk 0 io_l27n_0/gclk9 g13 gclk 0 io_l27p_0/gclk8 f13 gclk 0 io_l28n_0/gclk11 c13 gclk 0 io_l28p_0/gclk10 b13 gclk 0 io_l29n_0 b12 i/o 0 io_l29p_0 a12 i/o 0 io_l30n_0 c12 i/o 0 io_l30p_0 d13 i/o 0 io_l31n_0 f12 i/o 0 io_l31p_0 e12 i/o 0 io_l32n_0/vref_0 d11 vref 0 io_l32p_0 c11 i/o 0 io_l33n_0 b10 i/o 0 io_l33p_0 a10 i/o 0 io_l34n_0 d10 i/o 0 io_l34p_0 c10 i/o 0 io_l35n_0 h12 i/o 0 io_l35p_0 g12 i/o 0 io_l36n_0 b9 i/o 0 io_l36p_0 a9 i/o 0 io_l37n_0 d9 i/o 0 io_l37p_0 e10 i/o 0 io_l38n_0 b8 i/o 0 io_l38p_0 a8 i/o 0 io_l39n_0 k12 i/o ta b l e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 101 r 0 io_l39p_0 j12 i/o 0 io_l40n_0 d8 i/o 0 io_l40p_0 c8 i/o 0 io_l41n_0 c6 i/o 0 io_l41p_0 b6 i/o 0 io_l42n_0 c7 i/o 0 io_l42p_0 b7 i/o 0 io_l43n_0 k11 i/o 0 io_l43p_0 j11 i/o 0 io_l44n_0 d6 i/o 0 io_l44p_0 c5 i/o 0 io_l45n_0 b4 i/o 0 io_l45p_0 a4 i/o 0 io_l46n_0 h10 i/o 0 io_l46p_0 g10 i/o 0 io_l47n_0 h9 i/o 0 io_l47p_0 g9 i/o 0 io_l48n_0 e7 i/o 0 io_l48p_0 f7 i/o 0 io_l51n_0 b3 i/o 0 io_l51p_0 a3 i/o 0 io_l52n_0/pudc_b g8 dual 0 io_l52p_0/vref_0 f8 vref 0 ip_0 a5 input 0 ip_0 a7 input 0 ip_0 a13 input 0 ip_0 a17 input 0 ip_0 a23 input 0 ip_0 c4 input 0 ip_0 d12 input 0 ip_0 d15 input 0 ip_0 d19 input 0 ip_0 e11 input 0 ip_0 e18 input 0 ip_0 e20 input 0 ip_0 f10 input 0 ip_0 g14 input 0 ip_0 g16 input 0 ip_0 h13 input 0 ip_0 h18 input 0 ip_0 j10 input 0 ip_0 j13 input 0 ip_0 j15 input 0 ip_0/vref_0 d7 vref ta bl e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type 0 ip_0/vref_0 d14 vref 0 ip_0/vref_0 g11 vref 0 ip_0/vref_0 j17 vref 0 n.c. a24 n.c. 0 n.c. b24 n.c. 0 n.c. d5 n.c. 0 n.c. e9 n.c. 0 n.c. f18 n.c. 0 n.c. e6 n.c. 0 n.c. f9 n.c. 0 n.c. g18 n.c. 0 vcco_0 b5 vcco 0 vcco_0 b11 vcco 0 vcco_0 b16 vcco 0 vcco_0 b22 vcco 0 vcco_0 e8 vcco 0 vcco_0 e13 vcco 0 vcco_0 e19 vcco 0 vcco_0 h11 vcco 0 vcco_0 h16 vcco 1 io_l01n_1/ldc2 y21 dual 1 io_l01p_1/hdc y20 dual 1 io_l02n_1/ldc0 ad25 dual 1 io_l02p_1/ldc1 ae26 dual 1 io_l03n_1/a1 ac24 dual 1 io_l03p_1/a0 ac23 dual 1 io_l04n_1 w21 i/o 1 io_l04p_1 w20 i/o 1 io_l05n_1 ac25 i/o 1 io_l05p_1 ad26 i/o 1 io_l06n_1 ab26 i/o 1 io_l06p_1 ac26 i/o 1 io_l07n_1/vref_1 ab24 vref 1 io_l07p_1 ab23 i/o 1 io_l08n_1 v19 i/o 1 io_l08p_1 v18 i/o 1 io_l09n_1 aa23 i/o 1 io_l09p_1 aa22 i/o 1 io_l10n_1 u20 i/o 1 io_l10p_1 v21 i/o 1 io_l11n_1 aa25 i/o 1 io_l11p_1 aa24 i/o 1 io_l12n_1 u18 i/o 1 io_l12p_1 u19 i/o ta b l e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 102 product specification r 1 io_l13n_1 y23 i/o 1 io_l13p_1 y22 i/o 1 io_l14n_1 t20 i/o 1 io_l14p_1 u21 i/o 1 io_l15n_1 y25 i/o 1 io_l15p_1 y24 i/o 1 io_l17n_1 t17 i/o 1 io_l17p_1 t18 i/o 1 io_l18n_1 v22 i/o 1 io_l18p_1 w23 i/o 1 io_l19n_1 v25 i/o 1 io_l19p_1 v24 i/o 1 io_l21n_1 u22 i/o 1 io_l21p_1 v23 i/o 1 io_l22n_1 r20 i/o 1 io_l22p_1 r19 i/o 1 io_l23n_1/vref_1 u24 vref 1 io_l23p_1 u23 i/o 1 io_l25n_1/a3 r22 dual 1 io_l25p_1/a2 r21 dual 1 io_l26n_1/a5 t24 dual 1 io_l26p_1/a4 t23 dual 1 io_l27n_1/a7 r17 dual 1 io_l27p_1/a6 r18 dual 1 io_l29n_1/a9 r26 dual 1 io_l29p_1/a8 r25 dual 1 io_l30n_1/rhclk1 p20 rhclk 1 io_l30p_1/rhclk0 p21 rhclk 1 io_l31n_1/trdy1/rhclk3 p25 rhclk 1 io_l31p_1/rhclk2 p26 rhclk 1 io_l33n_1/rhclk5 n24 rhclk 1 io_l33p_1/rhclk4 p23 rhclk 1 io_l34n_1/rhclk7 n19 rhclk 1 io_l34p_1/irdy1/rhclk6 p18 rhclk 1 io_l35n_1/a11 m25 dual 1 io_l35p_1/a10 m26 dual 1 io_l37n_1 n21 i/o 1 io_l37p_1 p22 i/o 1 io_l38n_1/a13 m23 dual 1 io_l38p_1/a12 l24 dual 1 io_l39n_1/a15 n17 dual 1 io_l39p_1/a14 n18 dual 1 io_l41n_1 k26 i/o 1 io_l41p_1 k25 i/o ta bl e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type 1 io_l42n_1/a17 m20 dual 1 io_l42p_1/a16 n20 dual 1 io_l43n_1/a19 j25 dual 1 io_l43p_1/a18 j26 dual 1 io_l45n_1 m22 i/o 1 io_l45p_1 m21 i/o 1 io_l46n_1 k22 i/o 1 io_l46p_1 k23 i/o 1 io_l47n_1 m18 i/o 1 io_l47p_1 m19 i/o 1 io_l49n_1 j22 i/o 1 io_l49p_1 j23 i/o 1 io_l50n_1 k21 i/o 1 io_l50p_1 l22 i/o 1 io_l51n_1 g24 i/o 1 io_l51p_1 g23 i/o 1 io_l53n_1 k20 i/o 1 io_l53p_1 l20 i/o 1 io_l54n_1 f24 i/o 1 io_l54p_1 f25 i/o 1 io_l55n_1 l17 i/o 1 io_l55p_1 l18 i/o 1 io_l56n_1 f23 i/o 1 io_l56p_1 e24 i/o 1 io_l57n_1 k18 i/o 1 io_l57p_1 k19 i/o 1 io_l58n_1 g22 i/o 1 io_l58p_1/vref_1 f22 vref 1 io_l59n_1 j20 i/o 1 io_l59p_1 j19 i/o 1 io_l60n_1 d26 i/o 1 io_l60p_1 e26 i/o 1 io_l61n_1 d24 i/o 1 io_l61p_1 d25 i/o 1 io_l62n_1/a21 h21 dual 1 io_l62p_1/a20 j21 dual 1 io_l63n_1/a23 c25 dual 1 io_l63p_1/a22 c26 dual 1 io_l64n_1/a25 g21 dual 1 io_l64p_1/a24 h20 dual 1 ip_l16n_1 y26 input 1 ip_l16p_1 w25 input 1 ip_l20n_1/vref_1 v26 vref 1 ip_l20p_1 w26 input ta b l e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 103 r 1 ip_l24n_1/vref_1 u26 vref 1 ip_l24p_1 u25 input 1 ip_l28n_1 r24 input 1 ip_l28p_1/vref_1 r23 vref 1 ip_l32n_1 n25 input 1 ip_l32p_1 n26 input 1 ip_l36n_1 n23 input 1 ip_l36p_1/vref_1 m24 vref 1 ip_l40n_1 l23 input 1 ip_l40p_1 k24 input 1 ip_l44n_1 h25 input 1 ip_l44p_1/vref_1 h26 vref 1 ip_l48n_1 h24 input 1 ip_l48p_1 h23 input 1 ip_l52n_1/vref_1 g25 vref 1 ip_l52p_1 g26 input 1 ip_l65n_1 b25 input 1 ip_l65p_1/vref_1 b26 vref 1 vcco_1 ab25 vcco 1 vcco_1 e25 vcco 1 vcco_1 h22 vcco 1 vcco_1 l19 vcco 1 vcco_1 l25 vcco 1 vcco_1 n22 vcco 1 vcco_1 t19 vcco 1 vcco_1 t25 vcco 1 vcco_1 w22 vcco 2 io_l01n_2/m0 ad4 dual 2 io_l01p_2/m1 ac4 dual 2 io_l02n_2/cso_b aa7 dual 2 io_l02p_2/m2 y7 dual 2 io_l05n_2 y9 i/o 2 io_l05p_2 w9 i/o 2 io_l06n_2 af3 i/o 2 io_l06p_2 ae3 i/o 2 io_l07n_2 af4 i/o 2 io_l07p_2 ae4 i/o 2 io_l08n_2 ad6 i/o 2 io_l08p_2 ac6 i/o 2 io_l09n_2 w10 i/o 2 io_l09p_2 v10 i/o 2 io_l10n_2 ae6 i/o 2 io_l10p_2 af5 i/o 2 io_l11n_2 ae7 i/o ta bl e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type 2 io_l11p_2 ad7 i/o 2 io_l12n_2 aa10 i/o 2 io_l12p_2 y10 i/o 2 io_l13n_2 u11 i/o 2 io_l13p_2 v11 i/o 2 io_l14n_2 ab7 i/o 2 io_l14p_2 ac8 i/o 2 io_l15n_2 ac9 i/o 2 io_l15p_2 ab9 i/o 2 io_l16n_2 w12 i/o 2 io_l16p_2 v12 i/o 2 io_l17n_2/vs2 aa12 dual 2 io_l17p_2/rdwr_b y12 dual 2 io_l18n_2 af8 i/o 2 io_l18p_2 ae8 i/o 2 io_l19n_2/vs0 af9 dual 2 io_l19p_2/vs1 ae9 dual 2 io_l20n_2 w13 i/o 2 io_l20p_2 v13 i/o 2 io_l21n_2 ac12 i/o 2 io_l21p_2 ab12 i/o 2 io_l22n_2/d6 af10 dual 2 io_l22p_2/d7 ae10 dual 2 io_l23n_2 ac11 i/o 2 io_l23p_2 ad11 i/o 2 io_l24n_2/d4 ae12 dual 2 io_l24p_2/d5 af12 dual 2 io_l25n_2/gclk13 y13 gclk 2 io_l25p_2/gclk12 aa13 gclk 2 io_l26n_2/gclk15 ae13 gclk 2 io_l26p_2/gclk14 af13 gclk 2 io_l27n_2/gclk1 aa14 gclk 2 io_l27p_2/gclk0 y14 gclk 2 io_l28n_2/gclk3 ae14 gclk 2 io_l28p_2/gclk2 af14 gclk 2 io_l29n_2 ac14 i/o 2 io_l29p_2 ad14 i/o 2 io_l30n_2/mosi/csi_b ab15 dual 2 io_l30p_2 ac15 i/o 2 io_l31n_2 w15 i/o 2 io_l31p_2 v14 i/o 2 io_l32n_2/dout ae15 dual 2 io_l32p_2/awake ad15 pwr mgmt ta b l e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 104 product specification r 2 io_l33n_2 ad17 i/o 2 io_l33p_2 ae17 i/o 2 io_l34n_2/d3 y15 dual 2 io_l34p_2/init_b aa15 dual 2 io_l35n_2 u15 i/o 2 io_l35p_2 v15 i/o 2 io_l36n_2/d1 ae18 dual 2 io_l36p_2/d2 af18 dual 2 io_l37n_2 ae19 i/o 2 io_l37p_2 af19 i/o 2 io_l38n_2 ab16 i/o 2 io_l38p_2 ac16 i/o 2 io_l39n_2 ae20 i/o 2 io_l39p_2 af20 i/o 2 io_l40n_2 ac19 i/o 2 io_l40p_2 ad19 i/o 2 io_l41n_2 ac20 i/o 2 io_l41p_2 ad20 i/o 2 io_l42n_2 u16 i/o 2 io_l42p_2 v16 i/o 2 io_l43n_2 y17 i/o 2 io_l43p_2 aa17 i/o 2 io_l44n_2 ad21 i/o 2 io_l44p_2 ae21 i/o 2 io_l45n_2 ac21 i/o 2 io_l45p_2 ad22 i/o 2 io_l46n_2 v17 i/o 2 io_l46p_2 w17 i/o 2 io_l47n_2 aa18 i/o 2 io_l47p_2 ab18 i/o 2 io_l48n_2 ae23 i/o 2 io_l48p_2 af23 i/o 2 io_l51n_2 ae25 i/o 2 io_l51p_2 af25 i/o 2 io_l52n_2/cclk ae24 dual 2 io_l52p_2/d0/din/miso af24 dual 2 ip_2 aa19 input 2 ip_2 ab13 input 2 ip_2 ab17 input 2 ip_2 ab20 input 2 ip_2 ac7 input 2 ip_2 ac13 input 2 ip_2 ac17 input 2 ip_2 ac18 input ta bl e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type 2 ip_2 ad9 input 2 ip_2 ad10 input 2 ip_2 ad16 input 2 ip_2 af2 input 2 ip_2 af7 input 2 ip_2 y11 input 2 ip_2/vref_2 aa9 vref 2 ip_2/vref_2 aa20 vref 2 ip_2/vref_2 ab6 vref 2 ip_2/vref_2 ab10 vref 2 ip_2/vref_2 ac10 vref 2 ip_2/vref_2 ad12 vref 2 ip_2/vref_2 af15 vref 2 ip_2/vref_2 af17 vref 2 ip_2/vref_2 af22 vref 2 ip_2/vref_2 y16 vref 2 n.c. aa8 n.c. 2 n.c. ac5 n.c. 2 n.c. ac22 n.c. 2 n.c. ad5 n.c. 2 n.c. y18 n.c. 2 n.c. y19 n.c. 2 n.c. ad23 n.c. 2 n.c. w18 n.c. 2 n.c. y8 n.c. 2 vcco_2 ab8 vcco 2 vcco_2 ab14 vcco 2 vcco_2 ab19 vcco 2 vcco_2 ae5 vcco 2 vcco_2 ae11 vcco 2 vcco_2 ae16 vcco 2 vcco_2 ae22 vcco 2 vcco_2 w11 vcco 2 vcco_2 w16 vcco 3 io_l01n_3 j9 i/o 3 io_l01p_3 j8 i/o 3 io_l02n_3 b1 i/o 3 io_l02p_3 b2 i/o 3 io_l03n_3 h7 i/o 3 io_l03p_3 g6 i/o 3 io_l05n_3 k8 i/o 3 io_l05p_3 k9 i/o 3 io_l06n_3 e4 i/o 3 io_l06p_3 d3 i/o ta b l e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 105 r 3 io_l07n_3 f4 i/o 3 io_l07p_3 e3 i/o 3 io_l09n_3 g4 i/o 3 io_l09p_3 f5 i/o 3 io_l10n_3 h6 i/o 3 io_l10p_3 j7 i/o 3 io_l11n_3 f2 i/o 3 io_l11p_3 e1 i/o 3 io_l13n_3 j6 i/o 3 io_l13p_3 k7 i/o 3 io_l14n_3 f3 i/o 3 io_l14p_3 g3 i/o 3 io_l15n_3 l9 i/o 3 io_l15p_3 l10 i/o 3 io_l17n_3 h1 i/o 3 io_l17p_3 h2 i/o 3 io_l18n_3 l7 i/o 3 io_l18p_3 k6 i/o 3 io_l19n_3 j4 i/o 3 io_l19p_3 j5 i/o 3 io_l21n_3 m9 i/o 3 io_l21p_3 m10 i/o 3 io_l22n_3 k4 i/o 3 io_l22p_3 k5 i/o 3 io_l23n_3 k2 i/o 3 io_l23p_3 k3 i/o 3 io_l25n_3 l3 i/o 3 io_l25p_3 l4 i/o 3 io_l26n_3 m7 i/o 3 io_l26p_3 m8 i/o 3 io_l27n_3 m3 i/o 3 io_l27p_3 m4 i/o 3 io_l28n_3 m6 i/o 3 io_l28p_3 m5 i/o 3 io_l29n_3/vref_3 m1 vref 3 io_l29p_3 m2 i/o 3 io_l30n_3 n4 i/o 3 io_l30p_3 n5 i/o 3 io_l31n_3 n2 i/o 3 io_l31p_3 n1 i/o 3 io_l32n_3/lhclk1 n7 lhclk 3 io_l32p_3/lhclk0 n6 lhclk 3 io_l33n_3/irdy2/lhclk3 p2 lhclk 3 io_l33p_3/lhclk2 p1 lhclk ta bl e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type 3 io_l34n_3/lhclk5 p3 lhclk 3 io_l34p_3/lhclk4 p4 lhclk 3 io_l35n_3/lhclk7 p10 lhclk 3 io_l35p_3/trdy2/lhclk6 n9 lhclk 3 io_l36n_3 r2 i/o 3 io_l36p_3/vref_3 r1 vref 3 io_l37n_3 r4 i/o 3 io_l37p_3 r3 i/o 3 io_l38n_3 t4 i/o 3 io_l38p_3 t3 i/o 3 io_l39n_3 p6 i/o 3 io_l39p_3 p7 i/o 3 io_l40n_3 r6 i/o 3 io_l40p_3 r5 i/o 3 io_l41n_3 p9 i/o 3 io_l41p_3 p8 i/o 3 io_l42n_3 u4 i/o 3 io_l42p_3 t5 i/o 3 io_l43n_3 r9 i/o 3 io_l43p_3/vref_3 r10 vref 3 io_l44n_3 u2 i/o 3 io_l44p_3 u1 i/o 3 io_l45n_3 r7 i/o 3 io_l45p_3 r8 i/o 3 io_l47n_3 v2 i/o 3 io_l47p_3 v1 i/o 3 io_l48n_3 t9 i/o 3 io_l48p_3 t10 i/o 3 io_l49n_3 v5 i/o 3 io_l49p_3 u5 i/o 3 io_l51n_3 u6 i/o 3 io_l51p_3 t7 i/o 3 io_l52n_3 w4 i/o 3 io_l52p_3 w3 i/o 3 io_l53n_3 y2 i/o 3 io_l53p_3 y1 i/o 3 io_l55n_3 aa3 i/o 3 io_l55p_3 aa2 i/o 3 io_l56n_3 u8 i/o 3 io_l56p_3 u7 i/o 3 io_l57n_3 y6 i/o 3 io_l57p_3 y5 i/o 3 io_l59n_3 v6 i/o 3 io_l59p_3 v7 i/o ta b l e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 106 product specification r 3 io_l60n_3 ac1 i/o 3 io_l60p_3 ab1 i/o 3 io_l61n_3 v8 i/o 3 io_l61p_3 u9 i/o 3 io_l63n_3 w6 i/o 3 io_l63p_3 w7 i/o 3 io_l64n_3 ac3 i/o 3 io_l64p_3 ac2 i/o 3 io_l65n_3 ad2 i/o 3 io_l65p_3 ad1 i/o 3ip_l04n_3/vref_3 c1vref 3 ip_l04p_3 c2 input 3 ip_l08n_3 d1 input 3 ip_l08p_3 d2 input 3ip_l12n_3/vref_3 h4vref 3 ip_l12p_3 g5 input 3 ip_l16n_3 g1 input 3 ip_l16p_3 g2 input 3 ip_l20n_3/vref_3 j2 vref 3 ip_l20p_3 j3 input 3 ip_l24n_3 k1 input 3 ip_l24p_3 j1 input 3 ip_l46n_3 v4 input 3 ip_l46p_3 u3 input 3 ip_l50n_3/vref_3 w2 vref 3 ip_l50p_3 w1 input 3 ip_l54n_3 y4 input 3 ip_l54p_3 y3 input 3 ip_l58n_3/vref_3 aa5 vref 3 ip_l58p_3 aa4 input 3 ip_l62n_3 ab4 input 3 ip_l62p_3 ab3 input 3 ip_l66n_3/vref_3 ae2 vref 3 ip_l66p_3 ae1 input 3 vcco_3 ab2 vcco 3 vcco_3 e2 vcco 3 vcco_3 h5 vcco 3 vcco_3 l2 vcco 3 vcco_3 l8 vcco 3 vcco_3 p5 vcco 3 vcco_3 t2 vcco 3 vcco_3 t8 vcco 3 vcco_3 w5 vcco gnd gnd a1 gnd ta bl e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type gnd gnd a6 gnd gnd gnd a11 gnd gnd gnd a16 gnd gnd gnd a21 gnd gnd gnd a26 gnd gnd gnd aa1 gnd gnd gnd aa6 gnd gnd gnd aa11 gnd gnd gnd aa16 gnd gnd gnd aa21 gnd gnd gnd aa26 gnd gnd gnd ad3 gnd gnd gnd ad8 gnd gnd gnd ad13 gnd gnd gnd ad18 gnd gnd gnd ad24 gnd gnd gnd af1 gnd gnd gnd af6 gnd gnd gnd af11 gnd gnd gnd af16 gnd gnd gnd af21 gnd gnd gnd af26 gnd gnd gnd c3 gnd gnd gnd c9 gnd gnd gnd c14 gnd gnd gnd c19 gnd gnd gnd c24 gnd gnd gnd f1 gnd gnd gnd f6 gnd gnd gnd f11 gnd gnd gnd f16 gnd gnd gnd f21 gnd gnd gnd f26 gnd gnd gnd h3 gnd gnd gnd h8 gnd gnd gnd h14 gnd gnd gnd h19 gnd gnd gnd j24 gnd gnd gnd k10 gnd gnd gnd k17 gnd gnd gnd l1 gnd gnd gnd l6 gnd gnd gnd l11 gnd gnd gnd l13 gnd ta b l e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 107 r gnd gnd l15 gnd gnd gnd l21 gnd gnd gnd l26 gnd gnd gnd m12 gnd gnd gnd m14 gnd gnd gnd m16 gnd gnd gnd n3 gnd gnd gnd n8 gnd gnd gnd n11 gnd gnd gnd n15 gnd gnd gnd p12 gnd gnd gnd p16 gnd gnd gnd p19 gnd gnd gnd p24 gnd gnd gnd r11 gnd gnd gnd r13 gnd gnd gnd r15 gnd gnd gnd t1 gnd gnd gnd t6 gnd gnd gnd t12 gnd gnd gnd t14 gnd gnd gnd t16 gnd gnd gnd t21 gnd gnd gnd t26 gnd gnd gnd u10 gnd gnd gnd u13 gnd gnd gnd u17 gnd gnd gnd v3 gnd gnd gnd w8 gnd gnd gnd w14 gnd gnd gnd w19 gnd gnd gnd w24 gnd vccaux suspend v20 pwr mgmt vccaux done ab21 config vccaux prog_b a2 config vccaux tck a25 jtag vccaux tdi g7 jtag vccaux tdo e23 jtag vccaux tms d4 jtag vccaux vccaux ab5 vccaux vccaux vccaux ab11 vccaux vccaux vccaux ab22 vccaux vccaux vccaux e5 vccaux ta bl e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type vccaux vccaux e16 vccaux vccaux vccaux e22 vccaux vccaux vccaux j18 vccaux vccaux vccaux k13 vccaux vccaux vccaux l5 vccaux vccaux vccaux n10 vccaux vccaux vccaux p17 vccaux vccaux vccaux t22 vccaux vccaux vccaux u14 vccaux vccaux vccaux v9 vccaux vccint vccint k15 vccint vccint vccint l12 vccint vccint vccint l14 vccint vccint vccint l16 vccint vccint vccint m11 vccint vccint vccint m13 vccint vccint vccint m15 vccint vccint vccint m17 vccint vccint vccint n12 vccint vccint vccint n13 vccint vccint vccint n14 vccint vccint vccint n16 vccint vccint vccint p11 vccint vccint vccint p13 vccint vccint vccint p14 vccint vccint vccint p15 vccint vccint vccint r12 vccint vccint vccint r14 vccint vccint vccint r16 vccint vccint vccint t11 vccint vccint vccint t13 vccint vccint vccint t15 vccint vccint vccint u12 vccint ta b l e 7 6 : spartan-3an fgg676 pinout (continued) bank pin name fg676 ball type pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 108 product specification r user i/os by bank table 77 indicates how the 502 available user-i/o pins are distributed between the four i/o banks on the fgg676 package. the awake pin is counted as a dual-purpose i/o. footprint migration differences the xc3s1400an is the only spartan-3an fpga offered in the fgg676 package. the xc3s1400an fpga is pin compatible with the spartan-3a xc3s1400a fpga in the fg(g)676 package, although the spartan-3a fpga requires an external configuration source. ta bl e 7 7 : user i/os per bank for the xc3s1400an in the fgg676 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref clk to p 0 120 82 20 1 9 8 right 1 130 67 15 30 10 8 bottom 2 120 67 14 21 10 8 left 3 132 97 18 0 9 8 total 502 313 67 52 38 32 pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 109 r fg676 footprint x-ref target - figure 23 left half of fg676 package (top view) 313 i/o: unrestricted, general-purpose user i/o 67 input: unrestricted, general-purpose input pin 51 dual: configuration pins, then possible user i/o 2 suspend: dedicated suspend and dual-purpose awake power management pins 38 vref: user i/o or input voltage reference for bank 32 clk: user i/o, input, or clock buffer input 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 77 gnd: ground 36 vcco: output voltage supply for bank 23 vccint: internal core supply voltage (+1.2v) 14 vccaux: auxiliary supply voltage 17 n.c.: not connected figure 23: fg676 package footprint (top view) 12345678910111213 a gnd prog_b i/o l51p_0 i/o l45p_0 input gnd input i/o l38p_0 i/o l36p_0 i/o l33p_0 gnd i/o l29p_0 input b i/o l02n_3 i/o l02p_3 i/o l51n_0 i/o l45n_0 vcco_0 i/o l41p_0 i/o l42p_0 i/o l38n_0 i/o l36n_0 i/o l33n_0 vcco_0 i/o l29n_0 i/o l28p_0 gclk10 c input l04n_3 vref_3 input l04p_3 gnd input i/o l44p_0 i/o l41n_0 i/o l42n_0 i/o l40p_0 gnd i/o l34p_0 i/o l32p_0 i/o l30n_0 i/o l28n_0 gclk11 d input l08n_3 input l08p_3 i/o l06p_3 tms n.c. i/o l44n_0 input vref_0 i/o l40n_0 i/o l37n_0 i/o l34n_0 i/o l32n_0 vref_0 input i/o l30p_0 e i/o l11p_3 vcco_3 i/o l07p_3 i/o l06n_3 vccaux i/o l48n_0 vcco_0 n.c. i/o l37p_0 input i/o l31p_0 vcco_0 f gnd i/o l11n_3 i/o l14n_3 i/o l07n_3 i/o l09p_3 gnd i/o l48p_0 i/o l52p_0 vref_0 input gnd i/o l31n_0 i/o l27p_0 gclk8 g input l16n_3 input l16p_3 i/o l14p_3 i/o l09n_3 input l12p_3 i/o l03p_3 tdi i/o l52n_0 pudc_b i/o l47p_0 i/o l46p_0 input vref_0 i/o l35p_0 i/o l27n_0 gclk9 h i/o l17n_3 i/o l17p_3 gnd input l12n_3 vref_3 vcco_3 i/o l10n_3 i/o l03n_3 gnd i/o l47n_0 i/o l46n_0 vcco_0 i/o l35n_0 input j input l24p_3 input l20n_3 vref_3 input l20p_3 i/o l19n_3 i/o l19p_3 i/o l13n_3 i/o l10p_3 i/o l01p_3 i/o l01n_3 input i/o l43p_0 i/o l39p_0 input k input l24n_3 i/o l23n_3 i/o l23p_3 i/o l22n_3 i/o l22p_3 i/o l18p_3 i/o l13p_3 i/o l05n_3 i/o l05p_3 gnd i/o l43n_0 i/o l39n_0 vccaux l gnd vcco_3 i/o l25n_3 i/o l25p_3 vccaux gnd i/o l18n_3 vcco_3 i/o l15n_3 i/o l15p_3 gnd vccint gnd m i/o l29n_3 vref_3 i/o l29p_3 i/o l27n_3 i/o l27p_3 i/o l28p_3 i/o l28n_3 i/o l26n_3 i/o l26p_3 i/o l21n_3 i/o l21p_3 vccint gnd vccint n i/o l31p_3 i/o l31n_3 gnd i/o l30n_3 i/o l30p_3 i/o l32p_3 lhclk0 i/o l32n_3 lhclk1 gnd i/o l35p_3 trdy2 lhclk 6 vccaux gnd vccint vccint p i/o l33p_3 lhclk2 i/o l33n_3 irdy2 lhclk 3 i/o l34n_3 lhclk5 i/o l34p_3 lhclk4 vcco_3 i/o l39n_3 i/o l39p_3 i/o l41p_3 i/o l41n_3 i/o l35n_3 lhclk7 vccint gnd vccint r i/o l36p_3 vref_3 i/o l36n_3 i/o l37p_3 i/o l37n_3 i/o l40p_3 i/o l40n_3 i/o l45n_3 i/o l45p_3 i/o l43n_3 i/o l43p_3 vref_3 gnd vccint gnd t gnd vcco_3 i/o l38p_3 i/o l38n_3 i/o l42p_3 gnd i/o l51p_3 vcco_3 i/o l48n_3 i/o l48p_3 vccint gnd vccint u i/o l44p_3 i/o l44n_3 input l46p_3 i/o l42n_3 i/o l49p_3 i/o l51n_3 i/o l56p_3 i/o l56n_3 i/o l61p_3 gnd i/o l13n_2 vccint gnd v i/o l47p_3 i/o l47n_3 gnd input l46n_3 i/o l49n_3 i/o l59n_3 i/o l59p_3 i/o l61n_3 vccaux i/o l09p_2 i/o l13p_2 i/o l16p_2 i/o l20p_2 w input l50p_3 input l50n_3 vref_3 i/o l52p_3 i/o l52n_3 vcco_3 i/o l63n_3 i/o l63p_3 gnd i/o l05p_2 i/o l09n_2 vcco_2 i/o l16n_2 i/o l20n_2 y i/o l53p_3 i/o l53n_3 input l54p_3 input l54n_3 i/o l57p_3 i/o l57n_3 i/o l02p_2 m2 i/o l05n_2 i/o l12p_2 input i/o l17p_2 rdwr_b i/o l25n_2 gclk13 a a gnd i/o l55p_3 i/o l55n_3 input l58p_3 input l58n_3 vref_3 gnd i/o l02n_2 cso_b n.c. input vref_2 i/o l12n_2 gnd i/o l17n_2 vs2 i/o l25p_2 gclk12 a b i/o l60p_3 vcco_3 input l62p_3 input l62n_3 vccaux input vref_2 i/o l14n_2 vcco_2 i/o l15p_2 input vref_2 vccaux i/o l21p_2 input a c i/o l60n_3 i/o l64p_3 i/o l64n_3 i/o l01p_2 m1 n.c. i/o l08p_2 input i/o l14p_2 i/o l15n_2 input vref_2 i/o l23n_2 i/o l21n_2 input a d i/o l65p_3 i/o l65n_3 gnd i/o l01n_2 m0 n.c. i/o l08n_2 i/o l11p_2 gnd input input i/o l23p_2 input vref_2 gnd a e input l66p_3 input l66n_3 vref_3 i/o l06p_2 i/o l07p_2 vcco_2 i/o l10n_2 i/o l11n_2 i/o l18p_2 i/o l19p_2 vs1 i/o l22p_2 d7 vcco_2 i/o l24n_2 d4 i/o l26n_2 gclk15 a f gnd input i/o l06n_2 i/o l07n_2 i/o l10p_2 gnd input i/o l18n_2 i/o l19n_2 vs0 i/o l22n_2 d6 gnd i/o l24p_2 d5 i/o l26p_2 gclk14 bank 2 bank 0 bank 3 ds557-4_07_032309 n.c. n.c. n.c. pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 110 product specification r right half of fgg676 package (top view) 14 15 16 17 18 19 20 21 22 23 24 25 26 i/o l26n_0 gclk7 i/o l23n_0 gnd input i/o l18n_0 i/o l15n_0 i/o l14n_0 gnd i/o l07n_0 input n.c. tck gnd a i/o l26p_0 gclk6 i/o l23p_0 vcco_0 i/o l19n_0 i/o l18p_0 i/o l15p_0 i/o l14p_0 vref_0 i/o l09n_0 vcco_0 i/o l07p_0 n.c. input l65n_1 input l65p_1 vref_1 b gnd i/o l22n_0 i/o l21n_0 i/o l19p_0 i/o l17n_0 gnd i/o l11n_0 i/o l09p_0 i/o l05n_0 i/o l06n_0 gnd i/o l63n_1 a23 i/o l63p_1 a22 c input vref_0 input i/o l22p_0 i/o l21p_0 i/o l17p_0 input i/o l11p_0 i/o l10n_0 i/o l05p_0 i/o l06p_0 i/o l61n_1 i/o l61p_1 i/o l60n_1 d i/o l24p_0 i/o l20n_0 vref_0 vccaux i/o l13n_0 input vcco_0 input i/o l10p_0 vccaux tdo i/o l56p_1 vcco_1 i/o l60p_1 e i/o l24n_0 i/o l20p_0 gnd i/o l13p_0 n.c. i/o l02n_0 i/o l01n_0 gnd i/o l58p_1 vref_1 i/o l56n_1 i/o l54n_1 i/o l54p_1 gnd f input i/o l16p_0 input i/o l08n_0 i/o l02p_0 vref_0 i/o l01p_0 i/o l64n_1 a25 i/o l58n_1 i/o l51p_1 i/o l51n_1 input l52n_1 vref_1 input l52p_1 g gnd i/o l16n_0 vcco_0 i/o l08p_0 input gnd i/o l64p_1 a24 i/o l62n_1 a21 vcco_1 input l48p_1 input l48n_1 input l44n_1 input l44p_1 vref_1 h i/o l25n_0 gclk5 input i/o l12p_0 input vref_0 vccaux i/o l59p_1 i/o l59n_1 i/o l62p_1 a20 i/o l49n_1 i/o l49p_1 gnd i/o l43n_1 a19 i/o l43p_1 a18 j i/o l25p_0 gclk4 vccint i/o l12n_0 gnd i/o l57n_1 i/o l57p_1 i/o l53n_1 i/o l50n_1 i/o l46n_1 i/o l46p_1 input l40p_1 i/o l41p_1 i/o l41n_1 k vccint gnd vccint i/o l55n_1 i/o l55p_1 vcco_1 i/o l53p_1 gnd i/o l50p_1 input l40n_1 i/o l38p_1 a12 vcco_1 gnd l gnd vccint gnd vccint i/o l47n_1 i/o l47p_1 i/o l42n_1 a17 i/o l45p_1 i/o l45n_1 i/o l38n_1 a13 input l36p_1 vref_1 i/o l35n_1 a11 i/o l35p_1 a10 m vccint gnd vccint i/o l39n_1 a15 i/o l39p_1 a14 i/o l34n_1 rhclk7 i/o l42p_1 a16 i/o l37n_1 vcco_1 input l36n_1 i/o l33n_1 rhclk5 input l32n_1 input l32p_1 n vccint vccint gnd vccaux i/o l34p_1 irdy1 rhclk6 gnd i/o l30n_1 rhclk1 i/o l30p_1 rhclk0 i/o l37p_1 i/o l33p_1 rhclk4 gnd i/o l31n_1 trdy1 rhclk 3 i/o l31p_1 rhclk2 p vccint gnd vccint i/o l27n_1 a7 i/o l27p_1 a6 i/o l22p_1 i/o l22n_1 i/o l25p_1 a2 i/o l25n_1 a3 input l28p_1 vref_1 input l28n_1 i/o l29p_1 a8 i/o l29n_1 a9 r gnd vccint gnd i/o l17n_1 i/o l17p_1 vcco_1 i/o l14n_1 gnd vccaux i/o l26p_1 a4 i/o l26n_1 a5 vcco_1 gnd t vccaux i/o l35n_2 i/o l42n_2 gnd i/o l12n_1 i/o l12p_1 i/o l10n_1 i/o l14p_1 i/o l21n_1 i/o l23p_1 i/o l23n_1 vref_1 input l24p_1 input l24n_1 vref_1 u i/o l31p_2 i/o l35p_2 i/o l42p_2 i/o l46n_2 i/o l08p_1 i/o l08n_1 suspend i/o l10p_1 i/o l18n_1 i/o l21p_1 i/o l19p_1 i/o l19n_1 input l20n_1 vref_1 v gnd i/o l31n_2 vcco_2 i/o l46p_2 gnd i/o l04p_1 i/o l04n_1 vcco_1 i/o l18p_1 gnd input l16p_1 input l20p_1 w i/o l27p_2 gclk0 i/o l34n_2 d3 input vref_2 i/o l43n_2 n.c. n.c. i/o l01p_1 hdc i/o l01n_1 ldc2 i/o l13p_1 i/o l13n_1 i/o l15p_1 i/o l15n_1 input l16n_1 y i/o l27n_2 gclk1 i/o l34p_2 init_b gnd i/o l43p_2 i/o l47n_2 input input vref_2 gnd i/o l09p_1 i/o l09n_1 i/o l11p_1 i/o l11n_1 gnd a a vcco_2 i/o l30n_2 mosi csi_b i/o l38n_2 input i/o l47p_2 vcco_2 input done vccaux i/o l07p_1 i/o l07n_1 vref_1 vcco_1 i/o l06n_1 a b i/o l29n_2 i/o l30p_2 i/o l38p_2 input input i/o l40n_2 i/o l41n_2 i/o l45n_2 n.c. i/o l03p_1 a0 i/o l03n_1 a1 i/o l05n_1 i/o l06p_1 a c i/o l29p_2 i/o l32p_2 awake input i/o l33n_2 gnd i/o l40p_2 i/o l41p_2 i/o l44n_2 i/o l45p_2 gnd i/o l02n_1 ldc0 i/o l05p_1 a d i/o l28n_2 gclk3 i/o l32n_2 dout vcco_2 i/o l33p_2 i/o l36n_2 d1 i/o l37n_2 i/o l39n_2 i/o l44p_2 vcco_2 i/o l48n_2 i/o l52n_2 cclk i/o l51n_2 i/o l02p_1 ldc1 a e i/o l28p_2 gclk2 input vref_2 gnd input vref_2 i/o l36p_2 d2 i/o l37p_2 i/o l39p_2 gnd input vref_2 i/o l48p_2 i/o l52p_2 d0 din/miso i/o l51p_2 gnd a f bank 2 bank 0 bank 1 ds557-4_08_032709 n.c. n.c. n.c. pinout descriptions ds557-4 (v3.2) november 19, 2009 www.xilinx.com product specification 111 r revision history the following table shows the revision history for this document. notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all s pecifications are subject to change without notice. products are not designed or intended to be fail-saf e or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. date version revision 02/26/07 1.0 initial release. 08/16/07 2.0 updated for production release of initial device. noted that family is available in pb-free packages only. 09/12/07 2.0.1 minor updates to text. 09/24/07 2.1 update thermal characteristics in ta bl e 6 7 . 12/12/07 3.0 updated to production status with production release of final fa mily member, xc3s 50an. noted that non-pb-free packages may be available for selected devices. updated thermal characteristics in table 67 . updated links. 06/02/08 3.1 add "package overview" section. removed vref and input designations and diamond symbols on unconnected n.c. pins for xc3s700an fg484 in table 74 and figure 21 and for xc3s1400an fgg676 in table 76 and figure 22 . 11/19/09 3.2 renamed package ? footprint area? to ? body area? throughout document. noted in "introduction" that references to pb-free package code also apply to the pb package. added pb packages to table 65 and table 66 . changed body area of tq144/tqg144 packages in ta b l e 6 5 . corrected bank designation for suspend to vccaux. noted that non-pb-free (pb) packages are available for selected devices. updated ta b l e 7 5 and figure 21 for i/o vs. input pin counts. pinout descriptions w ww.xilinx.com ds557-4 (v3.2) november 19, 2009 112 product specification r |
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